Pulse neural network system based on mixing of resonant tunneling diode and memristor

Abstract

The invention discloses a pulse neural network system based on mixing of a resonant tunneling diode and a memristor, which belongs to the technical field of neuromorphic calculation and brain-like intelligent hardware and comprises an input module, a pulse shaping and issuing module and a feedback control module. The input module is used for weighting an input pulse signal through a memristor and generating a total post-synaptic potential on a node; the pulse shaping and issuing module performs threshold judgment on the potential and generates standardized pulse output; the feedback control module provides refractory recovery, lateral suppression, and synaptic modulation functions. The system utilizes the memristor to simulate synaptic plasticity and RTD to realize high-speed neuron distribution, has the characteristics of high integration level, low power consumption and fast response, and is suitable for the fields of edge calculation and brain-like intelligent hardware.

Description

Technical Field

[0001] This invention relates to the field of neuromorphic computing and brain-like intelligent hardware technology, specifically to a spiking neural network system based on a hybrid of resonant tunneling diodes and memristors. Background Technology

[0002] Artificial neural networks have made significant progress in recent years, but improved accuracy is often accompanied by a substantial increase in model size and complexity. For example, Google's CoAtNet7 improved accuracy by 0.43% compared to CoAtNet6, but the number of parameters increased by 970 million. The fundamental reason for this phenomenon is that modern processors generally adopt the von Neumann architecture, in which computation and storage units are separated, leading to high power consumption and long latency. Therefore, traditional neural network solutions are difficult to apply to edge devices with limited area and power consumption, urgently requiring the development of new basic devices and computing paradigms.

[0003] Spiking Neural Networks (SNNs), as a crucial component of neuromorphic computing, mimic the way the human brain processes information, possessing the unique advantage of integrating storage and computation. This feature effectively reduces the high energy consumption and high latency problems caused by separating storage and computation during information transmission, providing a new solution to overcome the bottlenecks of the traditional von Neumann architecture. At the hardware level, SNNs, by simulating the spiking mechanism between neurons, can achieve low-power and high-concurrency computing, optimizing the data processing process. This enables systems to perform data analysis and response quickly and efficiently in complex environments, thereby significantly improving the autonomy and real-time decision-making capabilities of unmanned systems. With the development of SNN technology, it has laid a solid foundation for the leapfrog development of intelligent unmanned systems and for breaking through the limitations of traditional computing architectures, which is of great significance.

[0004] SNN (Spiking Neural Network) construction technologies can be divided into two categories. One category involves innovative circuits, architectures, and algorithms designed based on traditional CMOS devices. In this type of technology, SNN implementation relies on the high integration of CMOS processes. Through innovative circuit design, hardware architecture, and algorithm optimization, efficient neural network computation can be achieved on a relatively small chip area. However, SRAM and DRAM suffer from volatility, which limits system reliability and efficiency, especially when maintaining state for extended periods. Therefore, additional storage modules are needed to ensure data persistence and stability. Furthermore, the introduction of SRAM also presents challenges in chip integration density. Because SRAM has relatively low storage density and requires a large area, this limits further development in high-density chip integration. Therefore, exploring more efficient storage solutions and more sophisticated circuit designs is crucial to overcoming these bottlenecks and promoting the wider application and development of spiking neural network hardware.

[0005] Another category is based on resistive switching devices (RSDs), which have a higher similarity to biological neurons and synapses. RSDs mainly include memristors and resonant tunneling diodes (RTDs). Current research primarily focuses on all-memristor spiking neural networks; hardware platforms for hybrid spiking neural networks combining memristors and RTDs have not yet been reported. However, all-memristor neural networks suffer from unclear memristor implementation mechanisms and limitations in neuron speed. Therefore, addressing these issues by starting from fundamental biological mechanisms, conducting in-depth research on memristor synaptic devices and RTD neurons, and constructing hybrid neural networks based on memristors and RTDs are of significant importance in overcoming existing technological bottlenecks and providing new solutions for high-speed, low-power intelligent computing. Summary of the Invention

[0006] In view of this, the present invention proposes a pulse neural network system based on a hybrid of resonant tunneling diodes and memristors, aiming to provide an innovative solution for an intelligent computing platform that is efficient, low-power and has high-performance computing capabilities, so as to meet its needs for efficient and low-power real-time processing of tiny targets in complex scenarios.

[0007] To achieve the above effects, the technical solution adopted by the present invention is as follows: A pulse neural network system based on a hybrid of resonant tunneling diodes and memristors includes an input module and a pulse shaping and discharging module; The input module includes at least one synaptic input port, and each synaptic input port is connected to the node through a corresponding memristor; during operation, the memristor devices weight their respective input pulse signals to generate a total postsynaptic potential at the node; The pulse shaping and firing module performs threshold judgment on the postsynaptic potential from the input module. When the voltage exceeds the threshold voltage of the input neuron device, the neuron generates a pulse signal to fire. Then, the firing event of the neuron is detected and standardized to ensure that the output pulse is consistent in amplitude, width and timing, and generates a regular square wave signal synchronized with the global clock to simulate the "all or none" law of biological neurons.

[0008] Furthermore, the memristor is a transition metal oxide-based memristor; it has a three-layer structure consisting of an upper metal layer, a middle insulator layer, and a lower metal layer; the upper and lower metal layers are Pt, and the middle insulator includes a TaO / HfO2 structure; The upper and lower metal layers simulate the preneuron and postneuron, respectively, while the middle insulator simulates the synapse. When current passes through the synapse, the resistance state of the memristor changes according to the intensity and direction of the current. By adjusting the current parameters, the information transmission and memory storage between the front and back ends of the synapse, similar to those in a biological synapse, can be simulated.

[0009] Furthermore, the pulse shaping and dispensing module includes a dispensing path and a pulse shaping path; The firing path includes a neuron device and a transistor B; the drain of the transistor B is connected to the output terminal of the neuron device, and the gate receives a fixed bias voltage V. B The source is grounded; the input terminal of the neuron device is connected to the node; when the input signal of the neuron device is greater than the decision threshold, it outputs a pulse signal, which is converted into a voltage signal by transistor B. The pulse shaping path includes latch A, latch B, and AND gate A; the data input port of latch A is connected to the output of the neuron device, the data input port of latch B is connected to the data output port of latch A, the data input port of AND gate A is connected to the data output port of latch B, and the data output port of AND gate A serves as the output of the neural network system; the clock input ports of latch A, latch B, and AND gate A are all used to receive the global clock signal CLK.

[0010] Furthermore, it also includes a feedback control module, which consists of a refractory period feedback path, a lateral inhibition output path, and a synaptic inhibition path; The main body of the refractory period feedback path is transistor A; the drain of transistor A is connected to the node, the gate is connected to the data output port of latch B, and the source is grounded. The main body of the lateral suppression output path is an OR gate; the two input ports of the OR gate are respectively connected to the data output port of latch A and the data output port of latch B; The synaptic suppression path includes AND gate B, transistor C, and a buffer; the two input ports of AND gate B are respectively connected to the data output port of latch A and the global clock signal CLK; the output port of AND gate B is connected to the gate of transistor C and one end of the buffer, the source of transistor C is connected to the other end of the buffer, and the drain is connected to the node.

[0011] Furthermore, each of the aforementioned neuronal devices includes two RTDs; Each RTD includes, from top to bottom, an emitter layer, an isolation layer A, a double-barrier quantum well active region, an isolation layer B, a collector layer, and a substrate layer; The neuron device consists of two RTDs: a load RTD and a driver RTD. The collector layer of the load RTD is connected to the node, and its emitter layer is connected to the collector layer of the driver RTD, serving as the output terminal of the neuron device. The driver RTD is a gate-controlled RTD with its emitter layer grounded and its gate, located on isolation layer A, receives the gate voltage V. G By modulating the current I in the driving RTD drive The threshold voltage is changed, and the threshold voltage is used to determine whether the neuron device should fire a pulse signal.

[0012] The beneficial effects of adopting the above-mentioned optimized technical solution are as follows: 1. This invention promotes the realization of in-memory computing and improves system integration: Combining the characteristics of memristors and RTD neuron devices, their application in brain-inspired intelligent systems will show great potential. Memristors can simulate synaptic plasticity, providing adaptive learning capabilities for neural networks, while RTD neuron devices can efficiently realize the dynamic behavior of spiking neurons. Only one memristor and two RTD devices are needed to simulate the function of one synapse and one neuron respectively, representing only 6%-15% of the number of traditional CMOS devices. The combination of the two can promote the realization of in-memory computing, thereby significantly improving system integration.

[0013] 2. Low power consumption and high speed: Neuronal firing behavior typically exhibits threshold characteristics, while RTDs possess high-speed, low-power threshold switching characteristics, making them ideal for simulating neuronal activity. Combined with the non-volatile storage of memristors, which reduces dynamic power consumption, this provides power support for spiking neurons, further reducing power consumption, increasing neuronal speed, and driving efficient computation in brain-inspired intelligent systems.

[0014] 3. Enhanced Adaptability and Flexibility: As an electronic component with a memory effect, the conductance of a memristor can be adjusted according to changes in historical current, simulating the plasticity of biological synapses. This allows memristors to dynamically adjust connection strength, thereby achieving adaptive changes in synaptic weights, similar to the long-term enhancement (LTP) and long-term inhibition (LTD) phenomena in biological neurons. Through the application of memristors, the learning and memory functions of neural networks can be realized, giving spiking neural networks greater adaptability and flexibility.

[0015] In summary, this invention fully leverages the respective advantages of memristors and RTD neural devices to achieve in-memory computing integration, significantly improving system efficiency and integration. It also possesses low power consumption and high speed characteristics. Compared to existing technologies, in edge device applications such as intelligent unmanned systems where area and power consumption are limited, it can significantly enhance the system's autonomy and real-time decision-making capabilities, providing strong support for the leapfrog development of brain-like intelligent systems. It demonstrates significant innovation and broad market application prospects. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a pulse neural network system architecture based on a hybrid of resonant tunneling diodes and memristors. Figure 2 This is a schematic diagram of the structure of a memristor provided in an embodiment of the present invention.

[0017] Figure 3 This is a schematic diagram of the structure of the RTD in an embodiment of the present invention.

[0018] Figure 4 This is a schematic diagram of the principle structure of the RTD constituting a neuron device according to an embodiment of the present invention.

[0019] Explanation of reference numerals in the attached diagram: 1. Upper metal layer, 2. Middle insulator layer, 3. Lower metal layer, 4. Emitter contact layer, 5. Collector contact layer, 6. Insulating layer. Detailed Implementation

[0020] The specific embodiments described below further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0021] Reference Figure 1 The pulse neural network system based on a hybrid of resonant tunneling diode and memristor disclosed in this embodiment includes multiple pulse neural network branches, each of which includes an input module, a pulse shaping and discharging module, and a feedback control module.

[0022] The input module includes at least one synaptic input port, each of which is connected to a node via a corresponding memristor. During operation, the memristor devices weight their respective input pulse signals to generate a total postsynaptic potential at the node.

[0023] Reference Figure 2 The memristor is a transition metal oxide-based memristor with a structure of a metal / insulator / metal "sandwich" stack. The metal is typically Pt, with the upper metal layer 1 and the lower metal layer 3 simulating the preneuron and postneuron, respectively. The middle insulator 2 includes, but is not limited to, a TaO / HfO2 structure, simulating the synapse. When current flows through the memristor, its resistance changes according to the intensity and direction of the current, thus simulating the information transmission and memory storage functions in biological synapses. Memristors can also be based on other transition metal oxides (such as WO3). x Other heterojunction designs include TiO2, doped modified structures (La / Al / Zr doped HfO2), and other heterojunction designs (metal / oxide / metal sandwich structures).

[0024] The pulse shaping and delivery module includes a delivery path and a pulse shaping path.

[0025] The firing pathway includes a neuron device and transistor B. The drain of transistor B is connected to the output terminal of the neuron device, and its gate receives a fixed bias voltage V. B V BThe voltage amplitude used to set the firing pulse of the neuron is grounded. The input terminal of the neuron device is connected to the node. When the input signal of the neuron device is greater than the decision threshold, it outputs a pulse signal, which is converted into a voltage signal by transistor B.

[0026] The pulse shaping path includes latch A, latch B, and AND gate A. The data input port of latch A is connected to the output of the neuron device, the data input port of latch B is connected to the data output port of latch A, and the data input port of AND gate A is connected to the data output port of latch B. The data output port of AND gate A serves as the output of the neural network. The clock input ports of latch A, latch B, and AND gate A are all used to receive the global clock signal CLK. This path is used to detect neuron firing events and generate standardized pulse signals synchronized with the global clock.

[0027] After the neuron device is activated, latch A outputs a high level. Latch B synchronizes and delays the output of latch A, controlling the timing of the feedback signal. AND gate A performs a logical AND operation between the output of latch B and the clock signal, generating a standardized output pulse with a fixed width and amplitude, simulating the "all-or-none" law of biological neurons.

[0028] Reference Figure 3 The neuron device consists of two resonant tunneling diodes (RTDs). The RTDs are based on III-V compound semiconductor heterojunctions. The specific structure, from top to bottom, consists of an epitaxial layer and a substrate layer. The substrate layer is made of InP. The epitaxial layer, from top to bottom, consists of an emitter layer, an isolation layer A, a double-barrier quantum well (DBQW) active region (containing a barrier layer and a well layer), an isolation layer B, and a collector layer. The RTDs also include other III-V material combinations (such as GaAs / AlAs, Si / SiGe, GaN / AlN, etc.), multi-quantum-well structures, and monolithic co-substrate integration schemes of memristor synapses and RTDs.

[0029] Reference Figure 4 The neuron device consists of two RTDs: a load RTD and a driver RTD. The collector layer of the load RTD is connected to the node, and its emitter layer is connected to the collector layer of the driver RTD, serving as the output terminal of the neuron device. The driver RTD is a gate-controlled RTD with its emitter layer grounded, and its gate, located on isolation layer A, receives the gate voltage V. G By modulating the current I in the driving RTD drive The threshold voltage is changed, and this threshold voltage is used to determine whether the neuron device should fire a pulse signal. The neuron device utilizes the negative differential resistance (NDR) characteristic of the RTD device, and loads the RTD's IV characteristic I. load Only when driving RTD IV feature I driveThe point where the positive resistance regions intersect represents a stable state. The stable state corresponding to a high voltage is the high state, denoted by "1"; the stable state corresponding to a low voltage is the low state, denoted by "0". When the negative resistance curves of the negative resistance RTD and the driving RTD intersect in the positive resistance region to form two stable points, I... drive >I load When the node potential decreases, the output is in a "0" state; when I drive <I load When the node potential rises, the output is in a "1" state, i.e., an output pulse signal. The threshold voltage is passed through the gate signal voltage V. G Modulation drive RTD current I drive The decision was made to achieve a rapid jump when the input voltage reaches a threshold, simulating the "trigger-fire" behavior of neurons.

[0030] For an RTD, the connection of its emitter layer is achieved through emitter contact layer 4; the connection of the collector layer is achieved through collector contact layer 5; collector contact layer 5 is in contact with the substrate layer, but is separated from other layers by insulating layer 6.

[0031] The feedback control module includes a refractory period feedback pathway, a lateral inhibition output pathway, and a synaptic inhibition pathway.

[0032] The main component of the refractory period feedback path is transistor A. The drain of transistor A is connected to the node, its gate is connected to the data output port of latch B, and its source is grounded. When latch B outputs a high level, transistor A turns on, pulling the node low to ground potential, providing a refractory period for the neuron device, allowing it to return to its initial state, and providing a large current path for the memristor with input pulses, reducing its resistance and achieving synaptic enhancement. The specific implementation logic is as follows: a) Providing a refractory period: Transistor A turns on, pulling the node low to a low potential, providing a refractory period for the neuron device to return to its initial state; b) Performing synaptic enhancement: When the node is low, a large current path is provided for the memristor synapse with input pulses, reducing its resistance.

[0033] The main component of the lateral inhibition output path is an OR gate. The two input ports of the OR gate are connected to the data output ports of latch A and latch B, respectively. When a neuron fires, latch A and latch B output a high level, and the OR gate outputs a high-level signal to the neuron devices (or nodes) of other spiking neural network branches, realizing a "winner-take-all" competitive mechanism.

[0034] The synaptic suppression path includes AND gate B, transistor C, and a buffer. The two inputs of AND gate B are connected to the data output of latch A and the global clock signal CLK, respectively. The output of AND gate B is connected to the gate of transistor C and one end of the buffer; the source of transistor C is connected to the other end of the buffer, and its drain is connected to the node. When latch B outputs a high level, the suppression module conducts, raising the node potential and applying a reverse voltage to the memristor (which has no input pulse), increasing its resistance and achieving synaptic suppression.

[0035] The technical solution of the present invention will be further described below with reference to specific embodiments and accompanying drawings. It should be noted that the specific embodiments described below are merely illustrative examples, and the scope of protection of the present invention is not limited thereto.

Claims

1. A pulse neural network system based on a hybrid of resonant tunneling diodes and memristors, comprising multiple pulse neural network branches, characterized in that, Each pulse neural network branch includes an input module and a pulse shaping and delivery module; The input module includes at least one synaptic input port, and each synaptic input port is connected to the node through a corresponding memristor; during operation, the memristor devices weight their respective input pulse signals to generate a total postsynaptic potential at the node; The pulse shaping and firing module performs threshold judgment on the postsynaptic potential from the input module. When the voltage exceeds the threshold voltage of the input neuron device, the neuron generates a pulse signal to fire. Then, the firing event of the neuron is detected and standardized to ensure that the output pulse is consistent in amplitude, width and timing, and to generate a regular square wave signal synchronized with the global clock.

2. The pulse neural network system based on a hybrid resonant tunneling diode and memristor according to claim 1, characterized in that, The memristor is a transition metal oxide-based memristor; it has a three-layer structure consisting of an upper metal layer (1), a middle insulator layer (2), and a lower metal layer (3); the upper metal layer (1) and the lower metal layer (3) are Pt, and the middle insulator layer (2) includes a TaO / HfO2 structure; The upper metal layer (1) and the lower metal layer (3) simulate the anterior neuron and the posterior neuron, respectively, and the middle insulator (2) simulates the synapse; When current passes through a synapse, the resistance state of the memristor changes according to the intensity and direction of the current. By adjusting the parameters of the current, the information transmission and memory storage between the front and back ends of a synapse, similar to those in a biological synapse, can be simulated.

3. The pulse neural network system based on a hybrid resonant tunneling diode and memristor according to claim 1, characterized in that, The pulse shaping and delivery module includes a delivery path and a pulse shaping path; The firing path includes a neuron device and a transistor B; the drain of the transistor B is connected to the output terminal of the neuron device, and the gate receives a fixed bias voltage V. B The source is grounded; the input terminal of the neuron device is connected to the node; when the input signal of the neuron device is greater than the decision threshold, it outputs a pulse signal, which is converted into a voltage signal by transistor B. The pulse shaping path includes latch A, latch B, and AND gate A; the data input port of latch A is connected to the output of the neuron device, the data input port of latch B is connected to the data output port of latch A, the data input port of AND gate A is connected to the data output port of latch B, and the data output port of AND gate A serves as the output of the neural network system; the clock input ports of latch A, latch B, and AND gate A are all used to receive the global clock signal CLK.

4. The pulse neural network system based on a hybrid resonant tunneling diode and memristor according to claim 3, characterized in that, The spiking neural network branch also includes a feedback control module, which consists of a refractory period feedback path, a lateral inhibition output path, and a synaptic inhibition path. The main body of the refractory period feedback path is transistor A; the drain of transistor A is connected to the node, the gate is connected to the data output port of latch B, and the source is grounded. The main body of the lateral suppression output path is an OR gate; the two input ports of the OR gate are respectively connected to the data output ports of latch A and latch B; the output ports of the OR gate are respectively connected to the nodes of other pulse neural network branches. The synaptic suppression path includes AND gate B, transistor C, and a buffer; the two input ports of AND gate B are respectively connected to the data output port of latch A and the global clock signal CLK; the output port of AND gate B is connected to the gate of transistor C and one end of the buffer, the source of transistor C is connected to the other end of the buffer, and the drain is connected to the node.

5. The pulse neural network system based on a hybrid resonant tunneling diode and memristor according to claim 3, characterized in that, Each of the neuronal devices includes two RTDs; Each RTD includes, from top to bottom, an emitter layer, an isolation layer A, a double-barrier quantum well active region, an isolation layer B, a collector layer, and a substrate layer; The neuron device consists of two RTDs: a load RTD and a driver RTD. The collector layer of the load RTD is connected to the node, and its emitter layer is connected to the collector layer of the driver RTD, serving as the output terminal of the neuron device. The driver RTD is a gate-controlled RTD with its emitter layer grounded and its gate, located on isolation layer A, receives the gate voltage V. G By modulating the current I in the driving RTD drive The threshold voltage is changed, and the threshold voltage is used to determine whether the neuron device should fire a pulse signal.

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