Three-dimensional schematic visualization

Abstract

The present invention relates to three-dimensional schematic visualization by schematic display of a design with a three-dimensional (3D) graphical user interface (GUI) via which a first plane extending along a first axis and a second axis different from the first axis is displayed, comprising displaying symbols corresponding to a set of first level components of a first level of the design disposed on the first plane; and a second plane extending along the first axis and the second axis, including displaying symbols corresponding to a first set of second level components of a second level of the design disposed on the second plane. The two planes are displayed at the same time and are respectively arranged at a first position and a second position along a third axis different from the first axis and the second axis. Each level of the design may correspond to a respective level of the layered structure of the design, a respective substrate on which the design is to be implemented, or a combination thereof.

Description

Technical Field

[0001] This invention relates to electronic design automation, and more particularly to a graphical user interface (GUI) for displaying and interacting with electronic designs having multiple levels (e.g., hierarchical levels in a design hierarchy or levels corresponding to multiple stacked substrates). Background Technology

[0002] Electronic Design Automation (EDA) systems can present designs (such as designs for electronic devices or circuits) as schematic diagrams to users (such as chip designers) in graphical form to improve the ease of understanding for the user and to analyze and / or modify the design when needed.

[0003] One strategy to improve the understandability and editability of a design is to organize it as a hierarchical structure of components. Furthermore, this makes it easier to reuse components within a design and across multiple designs. Components in this hierarchical structure can be organized hierarchically, where components at each level of the structure can include one or more sub-components corresponding to components at lower levels of the structure.

[0004] In existing EDA systems, some or all of the components (or blocks) of one level of the hierarchical structure, as well as the interconnections between these components (or blocks), can be displayed in a window. To view detailed information about one or more components at different levels of the hierarchical structure, the user must open additional windows. Therefore, the user may end up opening numerous windows, each displaying a schematic diagram of one or more components at one or more corresponding levels, without explicitly indicating how these components are related to or connected to each other.

[0005] Designs with a slightly deep hierarchical structure and / or numerous small components become more difficult and time-consuming to understand and analyze due to this highly fragmented representation. Furthermore, it can be more challenging to identify specific parts of interest. Additionally, such structures can confuse navigation. Designers may find themselves having to open many windows sequentially, potentially looping between them, which consumes additional time and can lead to confusion and errors. This is especially true when users are dealing with designs they were not the original designers of, as such users often lack prior knowledge of the design's structure.

[0006] Therefore, an interface and corresponding method are needed that overcomes these obstacles by providing enhanced and immediate visualization to offer a more comprehensive view of the overall hierarchical structure and a convenient way to navigate and access any sub-parts. Furthermore, such an interface and method needs to be able to flatten any part of interest from the design (where flattening makes these parts easier to understand, analyze, and / or manipulate). Summary of the Invention

[0007] Embodiments of the present invention relate to Electronic Design Automation (EDA) tools through which users can inspect and optionally interact with designs. In particular, embodiments relate to using a three-dimensional 3D representation of the design to facilitate understanding of the design, wherein one axis of the 3D representation corresponds to a hierarchy in the design, and wherein the hierarchy may be conceptual (e.g., in a layered design) or physical (e.g., in a stacked wafer design).

[0008] In one embodiment, a method for schematically displaying a design using a three-dimensional (3D) graphical user interface (GUI) of a computer system includes displaying the design via the 3D GUI by displaying a first plane extending along a first axis and a second axis different from the first axis, and displaying a second plane extending along the first axis and the second axis. The first plane and the second plane are displayed simultaneously and are respectively positioned at a first position and a second position different from the first position along a third axis different from the first axis and the second axis. Displaying the first plane includes displaying a first-level set of first-level components of the design disposed on the first plane, and displaying the second plane includes displaying a first set of second-level components of the design disposed on the second plane, and displaying each component of the first-level set of components and each component of the first-level set of second-level components using corresponding electronic symbols.

[0009] In one embodiment, a system for schematically displaying a design using a three-dimensional (3D) graphical user interface (GUI) includes a processor, and the steps configured to perform include: displaying the design via the 3D GUI by displaying a first plane extending along a first axis and a second axis different from the first axis, and displaying a second plane extending along the first axis and the second axis. The first plane and the second plane are displayed simultaneously and are respectively located at a first position and a second position different from the first position along a third axis different from the first axis and the second axis. Displaying the first plane includes displaying a set of first-level components of a first level of the design disposed on the first plane, and displaying the second plane includes displaying a first set of second-level components of a second level of the design disposed on the second plane, and displaying each component of the first set of first-level components and each component of the first set of second-level components using corresponding electronic schematic symbols.

[0010] In one embodiment, a non-transitory computer-readable medium includes computer programming instructions that, when executed by one or more processors of a system including a three-dimensional (3D) graphical user interface (GUI), cause the system to schematically display a design by performing steps including: displaying a first plane extending along a first axis and a second axis different from the first axis, and displaying a second plane extending along the first axis and the second axis, via the 3D GUI. The first plane and the second plane are displayed simultaneously and are respectively positioned at a first location and a second location different from the first location along a third axis different from the first axis and the second axis. Displaying the first plane includes displaying a set of first-level components of a first level of the design disposed on the first plane; displaying the second plane includes displaying a first set of second-level components of a second level of the design disposed on the second plane; and displaying each component of the set of first-level components and each component of the first set of second-level components using corresponding electronic schematic symbols.

[0011] In this embodiment, the design is a hierarchical design, and the first second-level component of the first group of second-level components is a sub-component of the first first-level component of the first group of first-level components.

[0012] In an embodiment, the first set of first-level components corresponds to components to be implemented on the first substrate, and the first set of second-level components corresponds to components to be implemented on a second substrate stacked with the first substrate.

[0013] In an embodiment, the method or steps further include receiving user input corresponding to a change in the design via the 3D GUI, and responding to the user input to change the design. Attached Figure Description

[0014] The accompanying drawings, which are included and constitute a part of this specification, illustrate various embodiments of the invention and, together with the foregoing general description of the invention and the following detailed description of these embodiments, serve to explain these embodiments of the invention. In these drawings, similar reference numerals denote similar features in different views.

[0015] Figure 1 This illustrates a system for designing automation based on one embodiment.

[0016] Figure 2 The design is shown, for example, by one embodiment.

[0017] Figure 3 The illustration shows an embodiment. Figure 2 The design.

[0018] Figure 4 The design is shown, for example, by one embodiment.

[0019] Figure 5 The illustration shows an embodiment. Figure 4 The design.

[0020] Figure 6 The illustration shows an embodiment. Figure 4 Design

[0021] Figure 7 The illustration shows an embodiment. Figure 4 The design.

[0022] Figure 8 The illustration shows an embodiment. Figure 4 The design.

[0023] Figure 9 The illustration shows an embodiment. Figure 4 The design.

[0024] Figure 10 The illustration shows an embodiment. Figure 4 The design.

[0025] Figure 11 This illustrates, for example, what can be produced by one embodiment. Figure 4 The design features a partially flattened layout.

[0026] Figure 12 A multi-substrate design is shown according to one embodiment.

[0027] Figure 13 A multi-substrate design is shown according to one embodiment, wherein one substrate includes a layered design.

[0028] Figure 14 This illustrates a process for providing a user interface for a layered and / or stacked design, according to one embodiment.

[0029] Figure 15 A system for providing an embodiment is shown. Detailed Implementation

[0030] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the features of the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the invention thorough and complete, and to fully convey the scope of the claims to those skilled in the art. In this invention, similar reference numerals denote similar parts in different figures and embodiments.

[0031] It should be understood that although the terms "first" and / or "second" may be used herein to describe different elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the invention. Similarly, the second element may be referred to as the first element. Moreover, in the following text, a "set" of items means one or more of the items, and a "multiple" of items means two or more of the items.

[0032] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated in order to clearly show the features of these embodiments.

[0033] Figure 1 A system 10 for electronic design according to one embodiment is shown. System 10 includes a design database 12, an EDA system 14, a hierarchical 3D visualization graphical user interface (GUI) subsystem 18 (hereinafter referred to as GUI subsystem 18), and a human interaction device (HID) 16.

[0034] GUI subsystem 18 includes one embodiment of the present invention. GUI subsystem 18 presents a design stored in design database 12 to a user via HID 16, allowing the user to examine, evaluate, and modify the design via facilities provided by EDA system 14. Although GUI subsystem 18 is shown as a component of EDA system 14, the embodiment is not limited thereto; rather, in the embodiment, GUI subsystem 118 may be a standalone front-end configured to operate in conjunction with the EDA system.

[0035] HID 16 can be any various user interface device capable of presenting images to a user and receiving input from the user. For example, HID 16 may include one or more of the group consisting of monitors, touch screen displays, mice, keyboards, trackpads, digitizer tablets, trackballs, keypads, speakers, microphones, gesture recognition subsystems, etc., but embodiments are not limited thereto.

[0036] In some embodiments, the GUI subsystem 18 may use HID 16 to render one or more 2D projections of a 3D image corresponding to the design. The 2D projection may be an isometric projection, a semi-oblique projection, a perspective projection, etc.

[0037] In other embodiments, HID 16 may include a virtual reality (VR) or augmented reality (AR) device capable of displaying stereoscopic 3D images, and GUI subsystem 18 may use HID 16 to provide users with stereoscopic 3D images corresponding to the design.

[0038] In other embodiments, HID 16 may include a computer-generated hologram, a volumetric display device, or some other type of 3D display.

[0039] Input from the user via HID 16 may include commands to zoom, rotate, or pan the 3D image, to change which parts of the design are displayed and how they are displayed, to perform the functions of EDA system 14 (such as performing analysis or modification functions) on all or selected parts of the design, etc.

[0040] Figure 2 A hierarchical design 20, for example, that can be processed using one embodiment, is shown. Design 20 is a simpler design and can be part of a larger and more complex design. The hierarchical structure of design 20 includes a first (top) level (L1) and second and third levels L2 and L3.

[0041] The first level L1 includes a first-level component: a ring oscillator 22. The second level L2 of this hierarchical structure includes three second-level components as sub-components of the ring oscillator 22: first, second, and third inverters 222A, 222B, and 222C.

[0042] The third level L3 of the hierarchical structure includes six third-level components, corresponding to two sub-components of each of the first, second, and third inverters 222A, 222B, and 222C: the first nMOSFET 2222A and the first pMOSFET 2224A of the first inverter 222A, the second nMOSFET 2222B and the second pMOSFET 2224B of the second inverter 222B, and the third nMOSFET 2222C and the third pMOSFET 2224C of the third inverter 2222C.

[0043] Figure 3 An example is shown. Figure 2 The design of 20 displays. Figure 3 The example shows all the hierarchical levels of Design 20 at the same time.

[0044] Design 20 is schematically shown; that is, it does not depend on the physical appearance of the implementation of the design and it is not necessary to indicate the absolute or relative dimensions or absolute or relative positions of the components of the design. Moreover, the components and blocks of Design 20 are shown using electronic schematic symbols, including pictographic symbols for electronic devices such as transistors, resistors, and capacitors; geometric shapes corresponding to sub-circuits; and pictographic wiring symbols corresponding to interconnects, contacts, and terminals. This contrasts with, for example, a layout display that directly corresponds to the physical implementation of the design. Figure 2 The first, second, and third levels L1, L2, and L3 of the design 20 are displayed on the first, second, and third planes 20L1, 20L2, and 20L3, respectively. The first, second, and third planes 20L1, 20L2, and 20L3 extend along the x and y axes, respectively, and are arranged in hierarchical order on the Z axis.

[0045] Figure 3 The following figures (showing the design) will be illustrated based on the obvious arrangement of the elements in three dimensions, regardless of whether the embodiment uses 2D projection, a pair of stereoscopic images, computer-generated holograms, volumetric display devices, or some other technology to display the elements.

[0046] exist Figure 2 In the example, the distance in the Z direction corresponds to the hierarchical level of the schematic diagram; however, the embodiment is not limited to this. In other embodiments, the hierarchical level may correspond to the distance in the X direction, the distance in the Y direction, or the distance along some other direction, and the plane used to show each level may extend along two axes orthogonal to the axis corresponding to the hierarchical level.

[0047] For the first level L1 of the design 20 shown, this embodiment schematically shows a ring oscillator 22 located on the first plane 20L1, without showing details of its internal structure.

[0048] For the second level L2 of the design 20 shown, this embodiment schematically shows the first, second and third inverters 222A, 222B and 222C constituting the ring oscillator 22 located on the second plane 20L2, and the first, second and third interconnections 224A, 224B and 224C between them.

[0049] For the third level L3 of the design 20 shown, this embodiment schematically shows the first, second, and third nMOSFETs 2222A, 2222B, and 2222C and the first, second, and third pMOSFETs 2224A, 2224B, and 2224C respectively, which constitute the first, second, and third inverters 222A, 222B, and 222C, located on the third plane 20L3, as well as the first, second, and third interconnections 224A, 224B, and 224C between the inverters and the internal interconnection 2226 within the inverters.

[0050] although Figure 3 The interconnections shown on the second plane 20L2 are also shown on the third plane 20L3, but the embodiments are not limited thereto, and in the embodiments, in the interconnections shown on one level, none or only some of them may be shown in the next lower level.

[0051] also, Figure 3 The dashed line 26, marked in the third level 20L3, indicates the location of a component that is a sub-component of the first inverter 222A shown on the second level 20L2. In embodiments, such dashed lines may be provided for some or all of the displayed components, or no such dashed lines may be provided for any of the displayed components.

[0052] For example, in an embodiment, such dashed lines may be displayed only for components that the user indicates interest in (e.g., by selecting the component, by placing the cursor over the component, by determining that the user is viewing the component by an eye-tracking device, or by placing the component in the center of the display, or by other means known in the prior art).

[0053] Figure 4 A layered design 40, for example, can be shown by one embodiment. Design 40 is... Figure 2 The design 20 is more complex and includes a first (top) level (L1), second and third levels L2 and L3, as well as additional levels omitted for simplicity.

[0054] The first level L1 of the hierarchical structure includes circuit 42. The second level L2 of the hierarchical structure includes elements that are sub-components of circuit 42: a low-dropout regulator (LDO) 422, a voltage-controlled oscillator (VCO) 424, and first and second buffers 426A and 426B.

[0055] The third level L3 of this hierarchical structure includes components that are components of the second level L2: a differential amplifier (DIFF) 4222, a pass transistor (PASST) 4224, a programmable voltage divider (PDIV) 4226, and a low-pass filter (FILT) 4228 constituting the LDO 422; an inductor bridge (INDB) 4242, a digitally-controlled tuning circuit (DTUNE) 4244, a voltage-controlled tuning circuit (VTUNE) 4246, and a differential circuit (DIFF) 4248 constituting the VCO 424; a first inverting buffer (IBUF) 4262A and a first non-inverting buffer (BUF) 4264A constituting the first buffer 426A; and a second IBUF constituting the second buffer 426B. 4262B and second BUF 4264B.

[0056] One or more components of each of the components in the third level L3 of this hierarchical structure may be located in the fourth or lower level of the hierarchical structure of design 40, but for the sake of simplicity, in Figure 4 These components are not shown in the diagram.

[0057] Figure 5-11 The illustration shows a design 40 according to an embodiment. Figure 5-11 This may correspond to more than one embodiment, but a single embodiment may be able to display, depending on the user's selections and the configuration options specified for that embodiment, as shown below. Figure 5-11 Design 40 is shown in the figure.

[0058] In the production Figure 5-11 In any or all of the embodiments shown, and in the generation of such Figure 13 and 14In the embodiment of the multi-substrate design shown, this embodiment allows the user to select and edit any displayed feature, regardless of the layer in which the feature is located. The selection of the component to be edited can be accomplished in any of the various methods known in the art, such as clicking on the component or selecting the component from a list.

[0059] The embodiment can then automatically update the display of the hierarchy containing the edited component, the hierarchy above the edited component, the hierarchy below the edited component, or a combination thereof, to reflect the result of the editing.

[0060] Figure 5 A display of a layered design 40 according to one embodiment is shown. Figure 5 In the middle, only the second plane 40L2 corresponding to the second level L2 of design 40 is displayed.

[0061] The embodiment of the second plane 40L2 includes an LDO 422, a VCO 424, and first and second buffers 426A and 426B, which constitute components of the circuit 42 and are collectively referred to below as second-level components. Furthermore, this embodiment shows interconnects 44 between these second-level components, input interconnects 46 providing input signals to the circuit 42, and output interconnects 48 by which the circuit 42 provides output signals.

[0062] Figure 6 Another display of the layered design 40 according to one embodiment is shown. Figure 6 In the middle, the second plane 40L2 is displayed, and the third level L3 portion of the design 40 is displayed on the third level portion plane 40L3p. The second plane 40L2 is as follows: Figure 5 As stated above.

[0063] The third-level partial plane 40L3p corresponds to LDO 422, and in Figure 6 In the diagram, the dashed line 62 indicates this correspondence. Accordingly, the third-level partial plane 40L3p shows DIFF 4222, PASST 4224, PDIV 4226, and FILT 4228, which constitute LDO 422.

[0064] In one embodiment, it can respond to the user's viewing of, such as Figure 5 The design shown in Figure 40 uses LDO 422 for more detailed display, which is generated in [the specified position]. Figure 6 The display shown is shown below.

[0065] In addition, the third-level partial plane 40L3p is also shown as interconnection 64 between components of LDO 422, interconnection 66 providing input to LDO 422, and interconnection 68 providing output from LDO 422.

[0066] Figure 7 Another display of the layered design 40 according to one embodiment is shown. Figure 7 The image shows the second plane 40L2 and the third plane 40L3 corresponding to the third level L3 of design 40. The second plane 40L2 is shown as... Figure 5 The display.

[0067] In one embodiment, it can respond to the user's viewing of, such as Figure 5 or Figure 6 The design shown in Figure 40 selects circuit 42 for more detailed display and generates the circuit. Figure 7 The display shown is shown below.

[0068] The third plane 40L3 includes sub-components that constitute LDO 422, LDO 422, VCO 424, and first and second buffers 426A and 426B (which constitute components of circuit 42), respectively. These sub-components are collectively referred to below as third-level components. Accordingly, the third plane 40L3 shows DIFF 4222, PASST 4224, PDIV 4226, and FILT 4228 constituting LDO 422; INDB 4242, DTUNE 4244, VTUNE 4246, and DIFF 4248 constituting VCO 424; first IBUF 4262A and first BUF 4264A constituting first buffer 426A; and second IBUF 4262B and second BUF 4264B constituting second buffer 426B.

[0069] exist Figure 7 In the third plane 40L3, this embodiment shows some of the interconnections 44 between the second-level components of the design 40, which are also shown in the second plane 40L2. Furthermore, this embodiment shows in the third plane 40L3 interconnections between the third-level components, interconnections to the third-level components, and interconnections from the third-level components (e.g., in…) Figure 6 Interconnections 64, 66, and 68 are shown.

[0070] Figure 8 Another display of the layered design 40 according to one embodiment is shown. Figure 8 The diagram shows the second plane 40L2, the third plane 40L3, the fourth plane 40L4 corresponding to the fourth layer of design 40, and the fifth plane 40L5p corresponding to a portion of the fifth layer of design 40. The second plane 40L2 is shown as... Figure 5 The display. Third plane 40L3, as for... Figure 7 The display.

[0071] In one embodiment, it can respond to the user's viewing of, such as Figure 5 , Figure 6 or Figure 7 The design shown in Figure 40 selects circuit 42 for more detailed display and generates [the circuit]. Figure 8 The display shown is shown below.

[0072] exist Figure 8 In this embodiment, the sub-components of the third-level component are displayed as components of the fourth-level component (hereinafter referred to as the fourth-level component) in a manner similar to how the components of the second-level component are displayed in the third plane 40L3. Furthermore, this embodiment displays some of the sub-components of the fourth-level component as components of the fifth-level partial plane 40L5p in a manner similar to how the components of the second-level component are displayed in the third plane 40L3. Accordingly, for the sake of brevity, details regarding how the components of the fourth plane 40L4 and the fifth-level partial plane 40L5p are displayed in this embodiment are omitted.

[0073] exist Figure 8 In this embodiment, interconnections within each of the multiple layers of the hierarchical structure (i.e., intralevel interconnects) can be displayed simultaneously. Some embodiments may display intralevel interconnections for all display layers or for selected layers based on user input, configuration options, or a combination thereof.

[0074] Figure 9 Another display of a layered design 40 according to one embodiment is shown, including information about... Figure 8 The aforementioned components. Accordingly, for the sake of brevity, details regarding [the components mentioned above] are omitted. Figure 8 The features shown are basically similar Figure 9 Description of its characteristics.

[0075] exist Figure 9 The display and Figure 8 The difference in the display lies in the repeating components in this design. Figure 8 The text details the repeating components, such as the first buffer 426A and the second buffer 426B. Figure 8 As shown in the image. In contrast, in Figure 9 The diagram shows a detailed example of each set of repeating components (here, the first buffer 426A, the first IBUF 42662A, the first BUF 4264A, and the fifth-level component 904A), while other instances of each set of repeating components (here, the second buffer 426B, the second IBUF 4262B, the second BUF 4264B, and the fifth-level components 904B and 904C) are labeled as repeats of the detailed example shown.

[0076] exist Figure 9 In this system, labels are associated with each group of repeating components and are displayed in, above, or near each member of that group of repeating components to indicate their membership in that group. For example, the first buffer 426A and the second buffer 426B are each labeled "C100" to indicate that they are the corresponding repeating components, the fifth-level components 904A, 904B, and 904C are each labeled "C3007" to indicate that they are the corresponding repeating components, and so on.

[0077] In an embodiment, the label associated with each repeating component may correspond to a cell name in the design or in a library of cells.

[0078] In an embodiment, the rendering of labels for instances of repeating components that are rendered in detail differs from the rendering of labels for instances of repeating components that are not rendered in detail. For example, in Figure 9 In this embodiment, the label for the first buffer 426A, which is presented in detail, is displayed as a closed square extending along the Z-axis from the edge of the first buffer 426A, while the label for the second buffer 426B, which is not presented in detail, is displayed as an italicized element embedded in the center of the second buffer 426B. However, the embodiment is not limited to this, and in other embodiments, the labels for detailed and non-detailed components can be distinguished by changing one or more of the following: font, font size, font type, color, background color, shape, border color, transparency, or any other visible attribute of the label.

[0079] exist Figure 9 Even though the details of the second buffer 426B are not shown in the third plane 40L3, the fourth-level components (second IBUF 4262B and second BUF 4264B) that constitute the second buffer 426B and are therefore repeats of the fourth-level components (first IBUF 42662A and first BUF 4264A) constituting the first buffer 426A are also shown in the fourth plane 40L4, but the embodiment is not limited thereto. In other embodiments, components constituting repeating components not shown in detail at one level of the layered structure are not shown at the next lower level of the layered structure.

[0080] Figure 10 Another display of a layered design 40 according to one embodiment is shown, including information about... Figure 8 The aforementioned components. Accordingly, for the sake of brevity, details regarding [the components mentioned above] are omitted. Figure 8 The features shown are basically similar Figure 10 Description of its characteristics.

[0081] exist Figure 10 The display and Figure 8The difference in the display is that, in Figure 10 In this embodiment, the interconnection 1002 between components on two different levels of the hierarchical structure is shown.

[0082] Especially, on Figure 8 In this embodiment, INDB 4242 (in VCO 424) is shown on the third plane 40L3 and also on the fourth plane 40L4, and interconnections to and from INDB 4242 are shown on the third plane 40L3. In contrast, in Figure 10 In this embodiment, INDB 4242 (in VCO 424) is shown on the third plane 40L3, but not on the fourth plane 40L4, and correspondingly, the interconnection between components on the fourth plane 40L4 is shown as inter-level interconnection 1002.

[0083] Therefore, in Figure 10 In this embodiment, all interconnections between levels, as well as interconnections within each level (i.e., intra-level interconnections), can be displayed simultaneously. In this embodiment, interconnections can be color-coded to distinguish intra-level interconnections from inter-level interconnections.

[0084] In one embodiment, the display of design 40 as shown may be determined based on configuration options, commands from the user, or both. Figure 8 As shown (some components are repeated between levels) or as... Figure 10 As shown (some components are not repeated between levels, but are connected using inter-level interconnects).

[0085] Figure 11 This illustrates, for example, what can be produced by one embodiment. Figure 4 The layered design uses a flattened display for 40% of the elements. For example... Figure 6 Like in the middle, in Figure 11 In this embodiment, a third-level partial plane 40L3p is shown, which includes a sub-component of LDO 422 shown in the partially flattened second plane 40L2PF. Figure 11 The shown with Figure 6 and 7 The same reference symbols in these figures denote the same components.

[0086] Unlike Figure 6 ,exist Figure 11 In Figure 6The first and second buffers 426A and 426B shown are flattened so that their sub-components—first and second IBUFs 4262A and 4262B and first and second BUFs 4264A and 4264B—and the interconnections to, from, and between these components are shown in the partially flattened second plane 40L2PF.

[0087] Figure 11 The first and second buffers 426A and 426B are shown to be flattened through a single layer (i.e., to show sub-components from the next level in the hierarchical structure), but the embodiments are not limited thereto, and in the embodiments, components may be flattened through more than one layer or through all layers in the design, depending on user input, configuration options, or a combination thereof.

[0088] Figure 11 Only some of the components of the second level L2 of design 40 are shown to be flattened, but the embodiment is not limited to this, and all components of the selected level can be flattened based on user input, configuration options, or a combination thereof.

[0089] Figure 11 The top of this hierarchical structure shows the components of the hierarchy (here, in...). Figure 6 The second level L2 of the design 40 shown on the second plane 40L2 (unflattened) is flattened, but the embodiments are not limited thereto. For example, in one embodiment, the components of the third level L2 of the design 40 may be flattened together with or instead of the components shown in the partially flattened second level 40L2PF.

[0090] Figure 12 This illustration shows a stacked multi-substrate design 120 according to one embodiment. The multi-substrate design 120 includes a first, second, and third substrate, in... Figure 12 In the diagram, these substrates are shown on first, second, and third planes 120L1, 120L2, and 120L3, respectively. As an illustrative example, the first substrate may be a first semiconductor die, the second substrate may be an interposer, and the third substrate may be a second semiconductor die, but the embodiments are not limited thereto.

[0091] The display of the first plane 120L1 includes a plurality of first substrate components, including a first component 1202 and a second component 1204.

[0092] The display of the second plane 120L2 may include a plurality of second substrate components, including a third component 1212, a fourth component 1214, and a fifth component 1216. Furthermore, the display of the second plane 120L2 may include intrasubstrate interconnects, such as second substrate interconnect 1218.

[0093] The display of the third plane 120L3 may include a plurality of third substrate components, including a sixth component 1222, a seventh component 1224, and an eighth component 1226. Furthermore, the display of the third plane 120L3 may include in-substrate interconnects, such as third substrate interconnects 1228.

[0094] The multi-substrate design 120 also includes inter-substrate interconnects, including a first inter-substrate interconnect 1232 (shown as a line between a location on the first plane 120L1 and a location on the second plane 120L2) between the first and second substrates, a second inter-substrate interconnect 1234 (shown as a line between locations on the second plane 120L2 and the third plane 120L3) between the second and third substrates, and a third inter-substrate interconnect 1236 (shown as a line between locations on the first plane 120L1 and the third plane 120L3) between the first and third substrates. Figure 12 The display shown here is schematic (as opposed to a layout display or other displays that more directly correspond to the physical implementation), and therefore the embodiment may not show the way in which the third substrate interconnect 1236 passes through the second plane 120L2. In the embodiment, whether such a way is shown can be controlled by user selection, configuration options, or a combination thereof.

[0095] Figure 13 The illustration shows a stacked multi-substrate design 130 according to one embodiment, wherein the stacked multi-substrate design includes a layered design. The stacked multi-substrate design 130 corresponds to using a design including... Figure 4 The layered design of the new first plane group 130LG replaces the 40. Figure 12 The first plane 120L1 of the stacked multi-substrate design 120.

[0096] exist Figure 13 and Figure 7 and 12 The common reference symbol between them corresponds to about Figure 7 and 12 The corresponding components are described above, and for the sake of brevity, repeated descriptions of them are omitted.

[0097] In the Figure 13 In the display produced by the embodiment shown, in Figure 7The first and second layer levels L2 and L3 of the layered design 40 shown in the second plane 40L2 and the third plane 40L3 are respectively shown as the first subplane 130L1 and the second subplane 130L2 of the first plane group 130LG, which corresponds to the elements of the design 130 to be implemented on the first substrate.

[0098] Furthermore, in addition to the second substrate interconnect 1234 between the second plane 120L2 and the third plane 120L3, this embodiment also shows the fourth inter-layer interconnect 1332 between the bottommost display layer (here, the second sub-plane 130L2) of the layered design included in the first plane group 130LG.

[0099] Figure 13 For example, in Figure 12 The stacked multi-substrate design shown in the illustration is, for example, in Figure 7 The layered design of the substrate shown is not limited to this embodiment. In the embodiment, the layered design of any one or all of the designed multiple substrates can be based on... Figures 6 to 11 Any one of them can be used to display the corresponding value.

[0100] Figure 14 The process 1400 for providing a user interface for a layered and / or stacked design is illustrated according to one embodiment.

[0101] In S1402, process 1400 receives a designation regarding the content and manner of displaying the design. This designation may be based on input from a user, which can be input via a 3D GUI. The designation may include a scope (indicating which components of the design are selected for display), an indication of which layers of the design are selected for display, and various options, such as whether to flatten some or all components, the amount of flattening to be performed for each or all flattened components, whether to display interlayer interconnections, etc.

[0102] In S1404, process 1400 generates one or more planes corresponding to one or more layers selected for display. These planes can be generated using information about the design obtained from a design database. Each layer may correspond to a specific layer in a layered design, a specific substrate in a stacked design, or a combination thereof.

[0103] Each plane includes a representation of a component of the design from the corresponding level. This representation of a component may include a symbolic representation (such as a label of a square or a shape indicating the type of the component), or the representation may include one or more representations of subcomponents of the component, wherein the subcomponents are components of a different (lower) level of the design.

[0104] Each plane may also include interconnections between components, the representation of which is included within the plane (i.e., intra-layer interconnections). The representation of the intra-layer interconnection may include lines, dots indicating contacts, terminal markings, and other such markings of interconnections known in the prior art.

[0105] In S1406, process 1400 sets the planes along an axis in three-dimensional space. Each plane is set at a different position along this axis. This axis is different from the axis along which the plane extends in the 3D space, and in an embodiment, it may be orthogonal to the axis along which the planes extend.

[0106] In S1408, process 1400 simultaneously displays these planes via the 3D GUI. These planes can be displayed as a 2D projection of the 3D space, or via the methods described above. Figure 1 The 3D display is shown.

[0107] In S1410, process 1400 determines whether to display a subcomponent relationship between a component on one plane and one or more components on another plane that are subcomponents of that component. This decision regarding the display of the subcomponent relationship can be made based on configuration options, which can be set by a user or an administrator, and can be global options, options specific to a component of the design, options specific to a layer of the design, or combinations thereof. In response to determining that the subcomponent relationship should be displayed, process 1400 proceeds to S1412; otherwise, process 1400 proceeds to S1414.

[0108] In S1412, process 1400 displays an indication of the sub-component relationship via the 3D GUI while displaying the planes. This indication of the sub-component relationship may include lines between areas corresponding to the component and its sub-components, color coding of the component, or other indications of the relationship known in the prior art.

[0109] In S1414, process 1400 determines whether to display interlayer interconnections between a component on one plane and one or more components on another plane that connect to that component. This decision regarding the display of the interlayer interconnection can be made based on configuration options, which can be set by a user or an administrator, and can be global options, options specific to a component of the design, options specific to a layer of the design, or combinations thereof. If the interlayer interconnection is determined to be displayed, process 1400 proceeds to S1416; otherwise, process 1400 proceeds to S1418.

[0110] In S1416, process 1400 displays a representation of the interlayer interconnection while displaying the planes. The representation of the interlayer interconnection may include lines, dots indicating contacts, terminal markings, and other such markings of interconnections known in the prior art. This representation of the interlayer interconnection may differ from the manner of the intralayer interconnection described above (e.g., by using different weights, different colors, different levels of transparency, dashed lines, or combinations thereof).

[0111] In S1418, process 1400 receives user input from the user via the 3D GUI. See above for reference. Figure 1 The user input is received.

[0112] In S1420, process 1400 processes the user input. Processing the user input may include changing the options used to display the design, such as specifying a different range, a different level, or different options (compared to those received in S1402 or the previous iteration in S1418); changing the design, for example, by sending a command to the design database; forming and / or displaying all or part of the analysis about the design, or a combination thereof. However, the embodiments are not limited thereto.

[0113] After processing the user input, process 1400 returns to S1404. In S1404, process 1400 may update the planes according to the changes specified by the user input, including updating a plane to reflect changes to that plane resulting from explicit changes to another plane or to the hierarchy of the design corresponding to that other plane, updating the plane according to changes to the display options for that other plane, or a combination thereof.

[0114] For example, deleting a component at a level may cause not only the plane corresponding to that level to be updated, but also another plane corresponding to the level that previously included the child components of the deleted component. As another example, flattening the representation of a first-level component may cause the component's child components to no longer be displayed on the plane corresponding to the second level that includes those child components.

[0115] Figure 15 A device 1500 for providing a layered 3D visualization UI is shown according to one embodiment. The device 1500 may be included in or used to provide... Figure 1 All or part of the EDA system 14.

[0116] Device 1500 includes a processor 1504, memory 1506, storage 1508, input / output (I / O) interface 1510, and network interface 1512. In some embodiments, in Figure 15One or more of the components shown may not be present in device 1500. In some embodiments, device 1500 also includes an accelerator 1514 for accelerating graphics operations, such as a graphics processing unit (GPU).

[0117] Memory 1506 and storage unit 1508 may each include a non-transitory computer-readable medium. Memory 1506 may include, for example, volatile memory (e.g., Dynamic Random Access Memory (DRAM)), non-volatile memory (e.g., flash memory), or combinations thereof, but embodiments are not limited thereto. Storage unit 1508 may include, for example, an optical disk, a hard disk drive, a solid-state drive, or combinations thereof, but embodiments are not limited thereto.

[0118] Processor 1504 may be configured to provide the layered 3D visualization UI described herein. In embodiments, processor 1504 executes computer programming instructions stored in memory 1506, memory 1508, or both; accelerator 1514 executes computer programming instructions stored in memory 1506, memory 1508, or both; or a combination thereof to perform processes for providing the layered 3D visualization UI.

[0119] In this embodiment, a user of device 1500 can view a display as described herein and can provide input and control as described herein via I / O interface 1510 or via a device connected to device 1500 through network interface 1512.

[0120] In an embodiment, it can be Figure 1 The design database 12 is stored in memory 1506, storage 1508, a device accessed via network interface 1512, a device accessed via I / O interface 1510, or a combination thereof.

[0121] As described above, the embodiments display schematic diagrams in a three-dimensional manner to represent the hierarchical structure, thereby allowing designers to view all hierarchical details within a single window, including all possible hierarchical levels and all interconnections, or to view selected hierarchical levels and selected interconnections as needed. This improves design quality and time-to-market by making the design easier for designers to understand and the impact of any changes to it.

[0122] The present invention has been described in conjunction with specific embodiments of the invention presented as examples. Various substitutions, modifications, and alterations may be made to the embodiments set forth herein without departing from the scope of the claims set forth below. Therefore, the embodiments set forth herein are intended to be illustrative and not limiting.

Claims

1. A method of schematically displaying a design with a three-dimensional (3D) graphical user interface (GUI) of a computer system, characterized by, The method comprises: displaying the design via the 3D GUI by: displaying a first plane extending along a first axis and a second axis different from the first axis, including displaying a first set of first-level components of a first level of the design disposed on the first plane; and displaying a second plane extending along the first axis and the second axis, including displaying a first set of second-level components of a second level of the design disposed on the second plane, wherein the first plane and the second plane are displayed simultaneously, wherein the first plane and the second plane are disposed at a first position and a second position different from the first position, respectively, along a third axis different from the first axis and the second axis, and wherein each component of the first set of first-level components and each component of the first set of second-level components are displayed using corresponding electronic symbols.

2. The method of claim 1, wherein: wherein the design is a hierarchical design, and wherein a first second-level component of the first set of second-level components is a sub-component of a first first-level component of the first set of first-level components.

3. The method of claim 2, wherein, Further comprising: displaying via the 3D GUI and indicating that the first second-level component is a sub-component of the first first-level component.

4. The method of claim 2, wherein, Displaying the first plane further comprises: displaying a second first-level component of the first set of first-level components on the first plane by displaying a second set of second second-level components corresponding to sub-components of the second first-level component on the first plane.

5. The method of claim 2, wherein, Further comprising: displaying the design via the 3D GUI by displaying a third plane extending along the first axis and the second axis, including displaying a set of third-level components of a third level of the design disposed on the third plane, wherein the first set of first-level components and the first set of second-level components correspond to components to be implemented on a first substrate, and wherein the set of third-level components correspond to components to be implemented on a second substrate stacked with the first substrate.

6. The method of claim 1, wherein, Further comprising displaying interconnections among the first set of first-level components on the first plane, interconnections among the first set of second-level components on the second plane, or both.

7. The method of claim 1, wherein, Further comprising displaying interconnections between components disposed on the first plane and components disposed on the second plane.

8. The method of claim 1, wherein, Further comprising: receiving user input via the 3D GUI; and altering the display of the design in response to the user input.

9. The method of claim 1, wherein, Further comprising: receiving user input corresponding to an alteration of the design via the 3D GUI; and causing the design to be altered in response to the user input.

10. The method of claim 9, wherein, The alteration of the design corresponds to an addition, deletion, or alteration of one or more components displayed on one of the first and second planes, and further comprising: updating the display of the first plane and the second plane in response to the alteration of the design.

11. The method of claim 1, wherein, Further comprising: receiving user input corresponding to an analysis of part or all of the design via the 3D GUI; and causing the analysis to be performed, causing a result of the analysis to be displayed, or both.

12. The method of claim 1, wherein: wherein the first set of first-level components correspond to components to be implemented on a first substrate, and the second set of second-level components correspond to components to be implemented on a second substrate stacked with the first substrate. wherein the first set of second-level components corresponds to components to be implemented on a second substrate stacked with the first substrate.

13. The method of claim 1, wherein, Also included are: generating a 3D model including the components of the first level located on the first plane and the components of the first level located on the second plane; generating a two-dimensional (2D) projection of the 3D model; and displaying the design by displaying the 2D projection.

14. The method of claim 1, wherein, Also included are: generating a 3D model including the components of the first level located on the first plane and the components of the first level located on the second plane; and displaying the design by displaying the 3D model on a stereoscopic display, a computer-generated holography device, or a volumetric display device.

15. A system for displaying a design with a three-dimensional (3D) graphical user interface (GUI), the system comprising: The system includes: a processor, wherein the system is configured to perform steps including: displaying the design via the 3D GUI by: displaying a first plane extending along a first axis and a second axis different from the first axis, including displaying a set of first-level components of a first level of the design disposed on the first plane; and displaying a second plane extending along the first axis and the second axis, including displaying a first set of second-level components of a second level of the design disposed on the second plane, wherein the first plane and the second plane are displayed simultaneously, wherein the first plane and the second plane are disposed at a first position and a second position different from the first position, respectively, along a third axis different from the first axis and the second axis, and wherein each component of the set of first-level components and each component of the first set of second-level components is displayed with a corresponding electronic schematic symbol.

16. A non-transitory computer-readable medium comprising computer programming instructions, wherein, The computer programming instructions, when executed by one or more processors of a system including a three-dimensional (3D) graphical user interface (GUI), cause the system to schematically display a design by performing steps including: displaying the design via the 3D GUI by: displaying a first plane extending along a first axis and a second axis different from the first axis, including displaying a set of first-level components of a first level of the design disposed on the first plane; and displaying a second plane extending along the first axis and the second axis, including displaying a first set of second-level components of a second level of the design disposed on the second plane, wherein the first plane and the second plane are displayed simultaneously, wherein the first plane and the second plane are disposed at a first position and a second position different from the first position, respectively, along a third axis different from the first axis and the second axis, and wherein each component of the set of first-level components and each component of the first set of second-level components is displayed with a corresponding electronic schematic symbol. ​

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