Secondary equipment debugging intelligent auxiliary method and system based on secondary logic model

Abstract

The invention provides a secondary equipment debugging intelligent auxiliary method and system based on a secondary logic model, and relates to the technical field of debugging assistance, and the method comprises the steps: collecting multi-source structured data related to secondary equipment; constructing a secondary logic model diagram for debugging assistance by taking the equipment nodes as objects and the communication relationship and the logic control relationship as connecting edges based on the multi-source structured data; obtaining a debugging task; mapping the debugging task to a corresponding node in the secondary logic model diagram through a semantic and configuration fusion matching mechanism; based on the secondary logic model diagram and the debugging task mapping result, generating a structured debugging operation template in a mode of combining template retrieval, state injection and logic verification; based on the structured debugging operation template, comparing and checking the running state data of the current debugging object equipment; and on the basis of the comparison check result and the structured debugging operation template, executing online monitoring of the link state, and assisting in realizing intelligent analysis of the debugging state.

Description

Technical Field

[0001] This invention relates to the field of debugging assistance technology, and in particular to an intelligent auxiliary method and system for debugging secondary equipment based on a secondary logic model. Background Technology

[0002] Secondary equipment in power systems serves as a core component for control, protection, measurement, and communication; its commissioning directly impacts the safe operation of primary equipment and the overall stability of the system. With the continuous improvement of automation and intelligence in power systems, the types and quantities of secondary equipment are constantly increasing, and their configuration methods and functional logic are becoming increasingly complex. Therefore, developing an intelligent method that can assist the commissioning process, reduce error rates, and improve work efficiency has significant practical and technical value.

[0003] Currently, secondary equipment commissioning mainly relies on the following methods: first, manual point-to-point and functional verification based on preset logical flows; second, interface testing and functional simulation using general or special commissioning software; and third, manual verification of logic configuration files (such as relay protection configuration files, communication protocols, etc.) based on engineering experience. These methods have certain practicality in traditional engineering, but as system structures become increasingly complex, their limitations become more and more apparent. Some research has begun to introduce expert systems, rule engines, or machine learning methods to partially optimize the commissioning process, such as using static rule bases to perform consistency verification of configuration logic, or using historical data to mine potential fault modes.

[0004] However, existing technologies generally lack a unified logical modeling framework, resulting in a lack of structured technical support for the debugging process of secondary equipment. Communication relationships and control logic between different devices are difficult to model and analyze collaboratively from a global perspective, thus limiting the reusability of debugging rules and the system's scalability. Furthermore, existing debugging methods rely on limited logical judgment tools, primarily static rules or manual configuration, making it difficult to effectively handle complex dynamic logic scenarios such as multi-condition triggering and multi-state switching, significantly impacting the accuracy and intelligence level of the debugging process. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide an intelligent auxiliary method for secondary equipment debugging based on a secondary logic model. This method addresses the common lack of a unified logic modeling framework in existing technologies, which leads to a lack of structured technical support for the secondary equipment debugging process. Furthermore, it makes it difficult to collaboratively model and comprehensively analyze the communication relationships and control logic between different devices from a global perspective, thus limiting the reusability of debugging rules and the system's scalability. Simultaneously, existing debugging methods rely on limited logical judgment methods, primarily static rules or manual configuration, making it difficult to effectively handle complex dynamic logic scenarios such as multi-condition triggering and multi-state switching, significantly impacting the accuracy and intelligence level of the debugging process.

[0006] A first aspect of this invention proposes an intelligent auxiliary method for debugging secondary devices based on a quadratic logic model, comprising: S1: Collect multi-source structured data related to secondary equipment; S2: Based on the multi-source structured data, using device nodes as objects and communication and logical control relationships as connecting edges, construct a secondary logic model diagram for debugging assistance; S3: Obtain debug tasks; S4: Through the semantic and configuration fusion matching mechanism, the debugging task is mapped to the corresponding node in the secondary logic model diagram; S5: Based on the aforementioned secondary logic model diagram and debugging task mapping results, a structured debugging operation template is generated through a combination of template retrieval, state injection, and logic verification. S6: Based on the structured debugging operation template, compare and verify the operating status data of the current debugging target device; S7: Based on the comparison and verification results and the structured debugging operation template, perform online monitoring of the link status to assist in the intelligent analysis of the debugging status.

[0007] A second aspect of this invention provides an intelligent auxiliary system for debugging secondary devices based on a quadratic logic model, comprising: a processor and a memory; The memory stores programs or instructions that can run on the processor, and when the program or instructions are executed by the processor, they implement the steps of the intelligent auxiliary method for debugging secondary devices based on a secondary logic model as described in the first aspect.

[0008] A third aspect of the present invention provides a readable storage medium storing a program or instructions, which, when executed by a processor, implements the steps of the intelligent auxiliary method for debugging secondary devices based on a secondary logic model as described in the first aspect.

[0009] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following: In this embodiment of the invention, by collecting multi-source structured data related to secondary equipment and constructing a secondary logic model diagram with equipment nodes as the core and integrating communication relationships and control logic, unified modeling and structured expression of relationships between equipment are achieved, providing a global perspective and scalable model support for the debugging process. Simultaneously, through a task mapping mechanism that integrates semantics and configuration, and by combining template retrieval, state injection, logic verification, and link monitoring, the dynamic adaptability and logical analysis depth of debugging tasks are enhanced, significantly improving the ability to handle complex logic scenarios such as multi-condition triggering and multi-state transitions, thereby effectively improving the intelligence level and accuracy of the debugging process. Attached Figure Description

[0010] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0011] Figure 1 This is a flowchart illustrating an intelligent auxiliary method for debugging secondary devices based on a secondary logic model, provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of an intelligent auxiliary system for debugging secondary equipment based on a secondary logic model, provided in an embodiment of the present invention. Detailed Implementation

[0012] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0013] The intelligent auxiliary method for debugging secondary devices based on a secondary logic model, provided by the present invention, will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0014] Reference manual attached Figure 1 The diagram illustrates a flowchart of an intelligent auxiliary method for debugging secondary devices based on a secondary logic model, provided by an embodiment of the present invention.

[0015] This invention provides an intelligent auxiliary method for debugging secondary devices based on a quadratic logic model, which may include the following steps: S1: Collect multi-source structured data related to secondary equipment.

[0016] In one possible implementation, the multi-source structured data specifically includes: configuration file data, physical connection data, state data, rule knowledge base, and semantic mapping data.

[0017] The configuration file data includes a full-site SCD file consisting of logical nodes, datasets, and control block structure information defined in the IED device.

[0018] Among them, IED (Intelligent Electronic Device) is a key secondary device in intelligent substations, which has multiple functions such as collecting status information of primary equipment, logic control, protection actions, signal transmission and communication interaction.

[0019] The SCD file (Substation Configuration Description) is the core file in the IEC 61850 standard used to describe the configuration of the entire substation secondary system. It comprehensively defines the logical node structure, dataset, control block (such as GOOSE, SV, Report) configuration, and communication connection relationships between various IED devices.

[0020] Physical connection data includes fiber optic link tables, port definition files, and physical channel directions.

[0021] Status data includes IED operating status, message transmission and reception status, optical power data, and CRC check value.

[0022] The rule knowledge base includes a logic control dependency rule base, a misoperation prevention locking rule base, and an operation safety template base.

[0023] The logic control dependency rule base defines the triggering conditions and linkage logic for node relationships. The anti-misoperation interlocking rule base includes equipment interlocking conditions, operational constraint logic, and anti-misoperation points. The operation safety template base consists of operation procedure templates categorized by voltage level, equipment type, and operation type.

[0024] Semantic mapping data includes a functional dictionary, a manufacturer terminology mapping table, and spelling correction rules.

[0025] It should be noted that, in order to address the problems of invisible logical structure, disconnect between physical connections and virtual configuration, and difficulty in modeling control dependencies in traditional secondary equipment debugging, this invention innovatively proposes a method for constructing a secondary logical model graph that integrates virtual and physical topology and control dependencies. This method constructs a virtual communication structure graph between devices based on SCD files and introduces field fiber optic links and port information to accurately map logical links to physical links. In particular, it breaks through the challenge of identifying and labeling multiple logical links multiplexing a single physical channel. Based on this, combined with the device operating status and predefined control rules, a set of control dependency edges is dynamically generated, ultimately forming a unified model graph integrating logical functions, physical connections, and control relationships. This provides crucial support for intelligent matching of debugging tasks and generation of operation templates.

[0026] S2: Based on multi-source structured data, using device nodes as objects and communication and logical control relationships as connecting edges, construct a secondary logic model diagram for debugging assistance.

[0027] The secondary logic model diagram is the core data structure for the commissioning and monitoring of secondary systems in smart substations. It is constructed based on SCD files, equipment status information, and on-site physical connection data. The diagram uses secondary devices such as IEDs, merging units, and smart terminals as nodes, and communication links (such as GOOSE and SV) and logical control relationships (such as protection activation and pressure plate linkage) as edges. It integrates the mapping relationship between virtual communication structures and physical fiber optic paths, forming a network topology diagram that combines virtual and physical elements, provides a visual display, and is dynamically updated.

[0028] In one possible implementation, S2 specifically includes: S201: Parse the full-site SCD file in multi-source structured data to extract the logical nodes, datasets, control block structure information, and corresponding published data path information defined in each IED device.

[0029] S202: Based on the published data path information, identify the subscription relationship of each IED device to the external data source, and parse the corresponding Inputs block and virtual terminal subscription reference relationship to generate a preliminary virtual communication structure diagram.

[0030] The Inputs block is a configuration area used to define the reference relationships of the virtual terminals it subscribes to, and is used to establish functional communication connections between devices.

[0031] Specifically, the system extracts the SCD configuration file from the structured data collected, and automatically parses it to obtain information such as logical nodes, datasets, and control block definitions. In particular, it extracts the Inputs block of each IED device and the configuration items of its receiving virtual terminals to identify the functional logical connections and message subscription / publishing relationships between IED devices. The parsing results form a preliminary virtual communication structure diagram, serving as the foundational data for subsequent communication path mapping.

[0032] It should be noted that the preliminary virtual communication structure diagram is generated purely based on virtual configuration and does not contain any on-site physical connection information. It can preliminarily describe the functional communication structure relationship between secondary devices.

[0033] S203: Based on the control block structure information and the subscription reference relationship between the Inputs block and the virtual terminal, analyze the logical connection path between each IED device, and combine it with the preliminary virtual communication structure diagram to construct the logical communication topology diagram inside the device system.

[0034] The logical communication topology diagram is a graphical model that describes the virtual communication structure formed between various IED devices in a smart substation based on message mechanisms such as GOOSE and SV. Its nodes are functional units (such as IED, merging unit, and smart terminal), and the edges represent the data interaction relationship between them for publishing and subscribing.

[0035] S204: Collect on-site physical connection information, including equipment optical port and fiber optic link information, and fuse the logical communication topology diagram with the equipment optical port and fiber optic link information to form a virtual-real mapping model.

[0036] The virtual-physical mapping model is a structured model that associates and integrates the virtual logical communication structure built with SCD files in a smart substation with the real physical connection information on site (such as fiber optic links, port numbers, and channel directions), aiming to establish a one-to-one mapping relationship between "logical links and physical paths".

[0037] In one possible implementation, S204 specifically includes: S2041: Obtain and parse the field fiber optic link table, and extract the first physical link data including the device optical port number, fiber optic tag, and fiber optic channel direction.

[0038] S2042: Read the backplane port definition file of the IED device to determine the second physical link data, which includes the physical number, port type, and physical location of each communication port.

[0039] S2043: Determine if multiple logical links reuse the same physical optical fiber. If yes, proceed to S2044. Otherwise, combine the logical communication topology diagram, the first physical link data, and the second physical link data to perform a mapping operation from logical link to physical link, forming a mapping relationship from logical link to optical fiber link, and proceed to S2045.

[0040] S2044: By analyzing the virtual channel identifier, timestamp, and VLAN characteristics of the logical link, the multiplexing relationship is distinguished, a one-to-many logical-to-physical mapping relationship is established, and the multiplexing attribute is marked in the logical-to-physical mapping relationship. Cross-validation is performed using the physical number, port location, and type information contained in the IED device's port definition file, combined with the on-site fiber optic tag information, to complete the standardized mapping of optical port naming, proceeding to S2045.

[0041] In this embodiment of the invention, by taking into account the engineering practice of multiple logical links reusing the same physical optical fiber, features such as VLAN, timestamp, and virtual channel number are used to distinguish logical flows, supporting one-to-many mapping and multiplexing attribute marking, ensuring that the model still has good representation capabilities under complex configurations such as optical splitting, link aggregation, and ring network redundancy.

[0042] S2045: The standardized mapping of logical links to optical fiber links and optical port naming is integrated to form a virtual-real mapping model that serves as the basic supporting structure of the secondary logical model diagram.

[0043] Specifically, the virtual logical terminals are matched with their corresponding IED communication interfaces (such as "Protection Device A-Optical Port 6-3"), and a one-to-one mapping relationship between "logical communication links and physical fiber optic paths" is established based on the fiber optic link table. Furthermore, the system supports handling special cases such as multiplexed fibers and port aggregation, ensuring the accuracy and completeness of the mapping. Ultimately, a virtual-physical integrated network topology table is formed, recording the actual physical link information carried by each logical communication link, including the field optical port number, device location, and fiber optic tag.

[0044] In this embodiment of the invention, the final virtual-real mapping model serves as the physical carrier layer of the "secondary logic model diagram," supporting the intuitive labeling of information such as link status, message direction, and optical power alarms in the diagram. It also serves as the input basis for key modules such as status comparison, link monitoring, and control path availability assessment, providing a guarantee for the debugging auxiliary system to achieve closed-loop analysis and dynamic control.

[0045] S205: Based on the virtual-real mapping model, it calls the predefined logical control rule library and combines the operating status and pressure plate configuration of each IED device to construct a set of logical control dependency edges between devices.

[0046] It should be noted that the predefined logic control rule base includes state association rules between primary and secondary equipment obtained from human experience or literature summary (such as the logical relationship between circuit breaker status and pressure plate activation), as well as the activation condition logic of common protection actions (such as differential protection and interlocking function).

[0047] Specifically, firstly, these unstructured or semi-structured logical experiences are itemized and unified into a structured rule expression format. Then, logical expressions are used to define the triggering mechanism of control edges, such as "when the differential protection soft pressure plate is engaged, the intelligent terminal hard pressure plate is engaged, and the circuit breaker is in operation, then a logical control edge from the protection device to the intelligent terminal is generated." Rules are further divided into protection, remote control, and interlocking categories based on their function, and each control rule has clear triggering conditions, allowed scope of affected devices, and influence paths, ultimately forming a structured logical control rule library. Finally, by combining the logical control rule library with the operating status and pressure plate configuration of each device, a set of logical control dependency edges between devices is constructed.

[0048] S206: Integrate the logical communication topology diagram, the virtual-real mapping model, and the set of logical control dependency edges to construct a secondary logical model diagram for debugging assistance.

[0049] Specifically, firstly, the system uses devices such as IEDs, merging units, and smart terminals as nodes in the graph. Each node has attributes such as device type, assigned interval, IP address, and physical location information. Next, based on the virtual and physical link information provided in the previous steps, communication edges are generated, including data such as GOOSE or SV type, APPID, link direction, and control block ID. The communication edges are also associated with real-time link status, and their colors are dynamically updated based on link CRC check results, optical power, and cable connection status. Simultaneously, the system calls the rule base built in the previous steps to generate logical control edges representing "control influence relationships," such as "protection device A locks smart terminal B," and labels the edges with specific triggering conditions (such as "pressure plate engaged," "primary disconnector in position," etc.). The status of the logical edges is also updated in real-time according to the on-site operating status, displayed as "activated" or "inactive" labels. The final output is a dynamic secondary logic model graph that supports visual operation, path tracing, and device linkage query.

[0050] In this embodiment of the invention, by introducing a logic control rule base and constructing a set of control dependency edges between devices, device status, pressure plate configuration, and control logic can be further integrated into the virtual communication structure, achieving a semantic leap from "communication connection" to "functional linkage," significantly enhancing the expressive depth and debugging guidance capabilities of the secondary logic model diagram. This mechanism not only systematizes human experience and engineering rules into a structured logical expression, supporting dynamic matching and visualization, but also endows the model with "perception + reasoning + monitoring" capabilities through real-time updates of control edge states, providing precise path tracing, causal analysis, and operational verification basis for debugging tasks, thereby improving the accuracy of intelligent debugging.

[0051] S3: Get debug tasks.

[0052] S4: Through the semantic and configuration fusion matching mechanism, the debugging task is mapped to the corresponding node in the secondary logic model diagram.

[0053] Among them, the semantic and configuration fusion matching mechanism is a key technical means to automatically associate the natural language description in the debugging task with the secondary device configuration structure. It aims to solve the matching problems between task semantics and system configuration, such as inconsistent terminology, diverse naming, and spelling differences.

[0054] In one possible implementation, S4 specifically includes: S401: Perform semantic analysis on the debugging task to extract key elements, including device type, device identifier, operation type, and function object.

[0055] S402: Compares key elements with the built-in standard semantic dictionary and outputs a structured task feature vector.

[0056] It should be noted that the structured task feature vector is a task semantic structure obtained by extracting, standardizing and vectorizing the semantics of natural language debugging tasks. It is used to support key intermediate results for intelligent debugging operations such as device identification, node localization and graph model matching.

[0057] For example, the structured task feature vector is as follows: {"Equipment Type" is "Protective Device", "Equipment Identifier" is "P1", "Operation Type" is "Pressure Plate Engagement", "Function Object" is "Differential Protection", "Task Level" is "Equipment Level", "Task Intent" is "Function Activation", "Semantic Keywords" are ["Differential", "Pressure Plate", "Engagement", "P1", "Protective Device"], "Standard Mapping" is {"Function Alias" is "87", "Standard Number of Differential Protection", "Standard Code of Operation Action" is "IN", "Standard Code Representing the "Engagement" Action", "Target Logic Node Type" is "PTOC", which may be mapped to an overcurrent / differential logic node}.

[0058] S403: Based on the structured task feature vector, load the full-site SCD file, and parse the IED model structure and communication relationship in the full-site SCD file to locate the target device.

[0059] S404: Based on the functional object, identify the logical node in the target device, and filter out the key virtual terminals associated with the logical node to obtain the target IED node and the set of virtual terminals related to the function of the target IED node.

[0060] S405: Extract the semantic query input required to match the node information in the secondary logic model diagram during the debugging task. The semantic query input includes the function name, terminal alias, and operation target.

[0061] S406: Perform a matching and verification operation between the semantic query input and the corresponding nodes in the secondary logic model diagram to determine if there are any differences in semantic description, spelling discrepancies, or inconsistencies in manufacturer terminology. If so, correct the inconsistencies using string edit distance and proceed to S407. Otherwise, proceed directly to S407.

[0062] Edit distance is a common method for measuring the similarity between two strings, representing the minimum number of editing operations required to convert one string into another. Common editing operations include inserting a character, deleting a character, or replacing a character. It can effectively identify and correct string deviations caused by typing errors, inconsistent terminology, or differences in vendor naming, thereby achieving fuzzy matching and verification between semantic input and standard model data in debugging tasks.

[0063] Optionally, the dynamic programming formula for calculating the string edit distance is as follows:

[0064] in, D Indicates the minimum edit distance. Represents the original string. Represents the target string. Indicates the beginning of the original string u The number of characters transposes the target character before the target character. v The minimum edit distance required for each character, min This indicates taking the minimum value. Indicates the beginning of the original string u -1 character count, transpose the target character before... v The minimum edit distance required for each character, Indicates the beginning of the original string u The number of characters transposes the target character before the target character. v-Minimum edit distance required for 1 character Indicates the beginning of the original string u -1 character count, transpose the target character before... v -Minimum edit distance required for 1 character This represents the cost of the deletion operation. This represents the cost of the insertion operation. This indicates the cost of the replacement operation.

[0065] For example, if a user misspells "TRIP" as "TRUP," this can be judged as an acceptable deviation using a substitution operation (U→I). The difference between "OPEN_CB" and "CB_OPEN" named by different vendors is quantified through an insertion and substitution operation. Cross-platform terminology is inconsistent; for example, "BlkTrip" and "BlockTrip" are used. The system automatically assesses the degree of similarity and selects the most similar node for matching.

[0066] In this embodiment of the invention, by introducing a standard semantic dictionary, function alias mapping, action code unification, and string edit distance correction, the system can effectively handle issues such as terminology ambiguity, naming differences, and spelling deviations in task expression by different manufacturers and different debugging personnel, and achieve cross-system and cross-version universal semantic matching capability, thereby improving the system's compatibility and stability in complex engineering environments.

[0067] S407: Based on the matching verification results and combined with the virtual terminal set, locate the communication control block involved in the debugging task and map the debugging task to the corresponding node in the secondary logic model diagram.

[0068] Specifically, the system first performs semantic analysis on the natural language description of the debugging task to extract key elements, including device type, device identifier, operation type, and functional object. Then, the extracted key elements are compared with a built-in standard semantic dictionary to standardize word meanings and output a structured task feature vector as the basis for subsequent matching. Next, the system loads the full-site SCD file, parses the IED model structure and communication relationships within it, and locates the target device based on the key element information. Based on the functional object, the system further identifies logical nodes in the target device and filters out key virtual terminals associated with those logical nodes, thus obtaining the target IED node and its related set of virtual terminals. On this basis, the system extracts the semantic query inputs that need to be matched with nodes in the secondary logic model diagram in the debugging task. These semantic query inputs include information such as function name, terminal alias, and operation target. The system then performs a matching verification operation in the model diagram based on this information. If differences in semantic description, spelling discrepancies, or inconsistencies in manufacturer terminology are identified, the inconsistencies are corrected using a string edit distance algorithm. Otherwise, the system proceeds directly to the next step. Finally, based on the verification results, the system accurately maps the debugging task to the corresponding node in the secondary logic model diagram, achieving automatic alignment between semantic tasks and device structure.

[0069] In this embodiment of the invention, by constructing structured task feature vectors, problems such as inconsistent terminology, naming ambiguity, and vendor differences in on-site task descriptions are resolved. Furthermore, through algorithms such as semantic dictionaries, standard mappings, and edit distance, accurate identification of IED devices, logical nodes, and virtual terminals is achieved. Simultaneously, by combining the virtual terminal set, communication control blocks or data paths are further locked, ensuring that debugging tasks can be accurately positioned in the secondary logic model diagram. This not only improves the automation level of debugging and positioning but also provides reusable and structured semantic support for subsequent core functions such as operation template generation, state comparison, and link verification, thereby enhancing the adaptability of the entire system in complex scenarios.

[0070] It should be noted that although the previous step has achieved semantic matching and logical node localization for the debugging task, this only means that the operational target can be identified in terms of functional logic. It does not mean that the field equipment has physical link connectivity and operability in the current state. Therefore, after completing the debugging semantic recognition, a dual check is added to verify the physical feasibility of the control path and the logical execution conditions to prevent the hidden danger of accurate semantic recognition but unreachable execution path or unmet state requirements.

[0071] Optionally, after completing the semantic matching of the debugging task, by introducing a control path parsing and state awareness mechanism, the system can further determine whether the operation path is truly reachable in the current running state. Subsequently, based on the accuracy of semantic matching and the reliability of path state, the system jointly evaluates the execution credibility, effectively preventing the risk of misoperation caused by link interruption, state abnormality, or semantic ambiguity, and enhancing the intelligent decision-making and security protection capabilities of the debugging process.

[0072] S5: Based on the secondary logic model diagram and the debugging task mapping results, a structured debugging operation template is generated through a combination of template retrieval, state injection and logic verification.

[0073] Among them, the structured debugging operation template is a standardized operation process document that is automatically generated based on the semantics of the debugging task, the configuration of the target device and the current system status, and has execution constraints and verification mechanisms. Its core consists of task identifier, operation step sequence, device object information, state dependency conditions and error prevention logic verification points.

[0074] In one possible implementation, S5 specifically includes: S501: Based on the target logical node and physical terminal, and combined with the debugging task type, perform semantic parsing on the debugging task, extract the operation type and the target object, and associate it with the attribute information of the target logical node to construct a set of debugging operation primitives.

[0075] Among them, the set of debugging operation primitives refers to the set of the smallest executable operation units extracted by the system based on the operation intent, functional objects and logical node attributes after parsing the semantics of the debugging task and the configuration of the target device.

[0076] S502: Call the preset safety measure template library, using voltage level, equipment type and task type as index conditions, and combine the action type and target object in the debugging operation primitive set to match and retrieve the corresponding standard operation template, and extract the standardized operation process containing pre-check items, operation sequence and post-check items.

[0077] S503: Based on real-time status data in the secondary logic model diagram and combined with the current status of the target device, the standardized operation process is dynamically adjusted. If the status of the object being debugged does not meet expectations, state-dependent operations are injected. If a physical layer anomaly exists, anti-misoperation prompts and blocking instructions are inserted to form an operation sequence with state constraints.

[0078] Among them, the state-constrained operation sequence refers to a set of operation steps organized in a certain execution order within a structured debugging operation template, based on the debugging task intent and equipment configuration logic. Each operation step corresponds to a specific debugging action. The operation sequence not only includes the execution object, physical interface, and location information of each step, but also embeds state dependency conditions, anti-misoperation interlocking logic, and real-time verification points, enabling dynamic adjustment and risk control.

[0079] S504: Combining the anti-misoperation interlocking rule base, it performs logical verification on the operation sequence and matches the corresponding interlocking logic according to the debugging task type to achieve dynamic anti-misoperation verification control.

[0080] S505: Sort the operation sequence according to the operation logic priority, and supplement the device object, physical location and interface label information of each operation item to generate a structured debugging operation template including task identifier, operation step list, execution constraints and verification conditions.

[0081] Specifically, firstly, the system extracts the operation type (e.g., "exit" or "engage") and corresponding functional object (e.g., "differential protection" or "remote signaling plate") of the task based on the identified target logical nodes and corresponding physical terminal information, combined with the semantic content of the debugging task. Simultaneously, it associates the functional attributes of the target device nodes to construct a set of operation units representing the basic operation meaning. Next, the system calls a preset safety measure template library, using the voltage level, device type, and operation category in the debugging task as search criteria to find matching standard operation templates and extract standard operation procedures, including pre-task checks, the operation steps themselves, and post-operation confirmation. Then, the system introduces real-time status information to check the current status of relevant nodes in the model diagram. If the target device does not currently meet the initial conditions required in the template (e.g., the plate is not engaged or the device is not exited), the system automatically inserts some state-dependent transition operations. If an anomaly is detected at the physical layer (e.g., fiber optic link interruption or signal anomaly), a false alarm prompt is inserted or the operation is directly blocked to ensure the safety and reliability of the entire process. Next, the entire operation sequence is dynamically validated based on the anti-misoperation interlocking rule base. This includes checking for violations of interlocking logic and potential malfunctions in the operation sequence. Real-time validation points are inserted at critical steps, and error triggering conditions and prompts are set to achieve dynamic anti-misoperation control during operation. Finally, the entire sequence is sorted according to the logical priority of the operation steps, and necessary execution information is added to each step, such as device name, physical location, interface number, and port label. This results in a structured debugging operation template containing a task identifier, a complete list of operation steps, execution constraints for each step, and validation mechanisms. This template facilitates direct execution by debugging personnel or use by automated testing systems.

[0082] In this embodiment of the invention, by integrating debugging task semantics, target device configuration, and real-time status information, and combining safety rules and logical verification, the system can generate a structured debugging operation template with execution constraints and error prevention mechanisms, significantly improving the standardization, accuracy, and intelligence of the debugging process. Simultaneously, the system automatically verifies the operation logic through an error prevention interlocking rule base and sets real-time trigger points to ensure that critical operations are executed under safe conditions. The final output structured template not only includes complete task identifiers, device information, and operation steps, but also embeds physical locations, interface identifiers, and logical verification points, which can serve as direct execution input for on-site debugging or automated testing, thereby achieving standardization of the debugging process.

[0083] S6: Based on the structured debugging operation template, compare and verify the operating status data of the current debugging target device.

[0084] In one possible implementation, S6 specifically includes: S601: Parse the structured debugging operation template, extract the expected state information of each operation step in the structured debugging operation template, and associate it with the state type of the corresponding device to obtain the expected state set. Among them, the state types include fiber optic link state and message state.

[0085] S602: Integrates the soft pressure plate status and device parameters of the protection device read through the MMS service, the optical intensity and link status obtained by parsing the message, and the real-time optical power collected by the physical port through the optical power meter interface to form a real-time status snapshot of the device.

[0086] S603: Based on the expected state set and real-time state snapshot, compare the actual state of the device with the expected state item by item, and record the abnormal items with inconsistent states, so as to compare and verify the operating status data of the device currently being debugged.

[0087] Specifically, we designed a debugging and verification mechanism based on comparing expected and real-time states. The aim is to automatically detect device anomalies during debugging, preventing misoperations due to inconsistent states. The specific process is as follows: The system parses the previously generated structured debugging operation template, extracting the expected device state information for each operation step. These expected states are then mapped one-to-one with the specific device state type, resulting in a complete set of expected states. Next, the system enters the field data acquisition phase. It reads the soft pressure plate status and device parameter information of the protection device in real time through the MMS communication service, while simultaneously parsing device messages to obtain the current link's optical intensity and communication status. Furthermore, the system can directly collect the optical power of the physical port through the optical power meter interface, thus constructing a "snapshot" of the device's current actual operating state. Finally, this real-time state snapshot is compared item by item with the previously extracted set of expected states, such as whether a pressure plate is truly "in operation," whether the fiber optic link is unobstructed, and whether the CRC value is consistent. If any state is found to be inconsistent with expectations during the comparison process, such as message interruption, link anomaly, or pressure plate not being in operation, the system records these anomalies for subsequent operation procedures.

[0088] In this embodiment of the invention, a refined and automated status verification mechanism is constructed by comparing the expected states defined in the structured debugging operation template with the current operating state of the device item by item, effectively improving the accuracy and safety assurance capabilities of the debugging process. Simultaneously, by comparing the one-to-one correspondence between the expected and actual states, issues such as inconsistencies in states, link anomalies, or configuration deviations can be detected in a timely manner and recorded as anomalies, providing crucial support for subsequent steps, thereby achieving closed-loop status verification and risk control before debugging operations.

[0089] S7: Based on the comparison and verification results and the structured debugging operation template, perform online monitoring of the execution link status and assist in the intelligent analysis of the debugging status.

[0090] In one possible implementation, S7 specifically includes: S701: Sort anomalies by severity and generate a structured verification report based on the fault location logic.

[0091] S702: Based on the structured verification report, mark the abnormal variables and physical slot locations in the secondary logic model diagram and output them as visual prompts.

[0092] S703: Based on visual prompts and combined with the operation sequence and expected state requirements defined in the structured debugging operation template, the abnormal variables are correlated and matched and temporal logic is deduced to assist in the intelligent analysis of the debugging state.

[0093] In one possible implementation, the correlation matching and temporal logic deduction of the abnormal variables in S703 specifically includes: S7031: Use principal component analysis to analyze each outlier variable and calculate the outlier score for each outlier variable:

[0094] in, Indicates abnormal scores. X Represents a data matrix. T To represent the transpose of a matrix, PC Represents the principal component matrix. Describes the covariance matrix of the principal components. This represents the inverse of the covariance matrix.

[0095] S7032: Select all abnormal variables whose abnormal scores are greater than the preset abnormal scores. Construct a first candidate variable set and calculate the abnormal contribution rate of each abnormal variable in the first candidate variable set.

[0096]

[0097] in, Indicates the first i In the nth sample j Abnormal contribution rate of each variable, Indicates the first i In the nth sample j The absolute outlier contribution rate of each variable, Indicates the first The sum of the outliers of all variables in a sample.

[0098] S7033: Construct a time series model based on a long short-term memory autoencoder. Through the time series model, calculate the reconstruction error of each abnormal variable, and select abnormal variables whose reconstruction error is greater than the preset reconstruction error to construct a second candidate variable set.

[0099] S7034: Take the intersection of the first candidate variable set and the second candidate variable set to form the final candidate variable set.

[0100] S7035: Calculate the transition entropy and lag step of each outlier variable in the final candidate variable set to quantify the direction of information flow between variables and form a causal relationship graph:

[0101] in, Indicates from variable x arrive y The transfer entropy, Represents the Digamma function. k Represents the nearest neighbor parameter.N This represents the total number of data samples. Indicates inclusion j Variables of a historical sample y The past state window, Indicates inclusion l Variables of a historical sample x The past state window, Representing variables y In the future h The state vector with lag step size Indicates that in the inclusion j Variables of a historical sample The first in the past state window i The number of neighbors of each point Indicates that in the inclusion j Variables of a historical sample y and contain j Variables of a historical sample x The first joint past state window i The number of neighbors of each point This indicates the number of nearest neighbor samples in the joint window.

[0102] In this embodiment of the invention, by introducing a calculation method based on transfer entropy and lag step size, the invention can accurately quantify the information flow direction and causal influence relationship between multiple abnormal variables without relying on prior models, thereby constructing a causal relationship graph that reflects the actual state evolution logic. This approach not only effectively captures nonlinear, temporal variable dependency structures but also possesses directionality and dynamism, helping to eliminate spurious causal or synchronization misjudgment problems that may occur in traditional correlation analysis. The construction of the causal graph provides a solid logical foundation for subsequent fault path tracing and root cause identification, significantly improving the intelligence level and diagnostic accuracy of the debugging assistance system in the anomaly analysis stage.

[0103] S7036: Select the leaf node variable with the highest anomaly contribution rate from the causal relationship graph as the starting point of the fault path, and pass it up along the edge of the causal relationship graph in sequence. Prioritize the parent node variable with the largest transfer entropy value, and backtrack layer by layer until there is no parent node or a causal loop occurs, thus forming a fault propagation path.

[0104] Optionally, the leaf node variable with the highest anomaly contribution rate is:

[0105] in, The variable representing the starting node of the fault path. This represents the set of all leaf nodes in the causal graph. This represents the variable that maximizes the abnormal contribution rate. Represents a node Abnormal contribution rate.

[0106] The parent node variable for the maximum transition entropy value is specifically:

[0107] in, Indicates the first fault in the fault path i 1 node Indicates the current node The set of all parent nodes, This represents the transition entropy from the parent node to the current node.

[0108] The specific fault propagation path is as follows:

[0109] in, P This indicates the path of fault propagation.

[0110] It should be noted that, compared with diagnostic methods based solely on static topology or rule bases, the path construction mechanism of this invention has the advantages of being data-driven, adaptive, and interpretable, which can effectively avoid misdiagnosis or missed diagnosis and improve the root cause tracing ability and decision intelligence level of the debugging assistance system in complex scenarios.

[0111] S7037: If the endpoint of the fault propagation path is the root node variable, then the current node variable is taken as the root cause variable. If there is a loop in the fault propagation path, then the variable with the largest lag step in the loop is selected as the root cause variable, forming the fault propagation chain and the root cause identification result.

[0112] Root dependent variable identification specifically involves:

[0113] in, This represents the root cause variable in the fault propagation path. In a causal relationship graph, nodes represent... To the node The causal edge, This indicates the lag step size of the causal edge.

[0114] The specific fault propagation path and root cause identification results are as follows:

[0115] In this embodiment of the invention, a fault propagation path reconstruction and root variable identification based on a structured causal graph are achieved through leaf node screening guided by anomaly contribution rates and a layer-by-layer backtracking process of the maximum transfer entropy path. Compared with traditional diagnostic methods based on rules or static topology, this invention has stronger adaptability and interpretability in handling complex scenarios involving multivariate interactions, asynchronous fluctuations, and causal loops.

[0116] For example, when debugging differential protection, the operation template requires first engaging the control panel and then checking if the GOOSE message is sent normally. However, in actual execution, the control panel is engaged, but the GOOSE message is not sent. The system will automatically match these two states and perform logical reasoning based on the operation sequence: since the control panel is engaged but the message is not sent, it indicates that there may be problems such as an inactive control block, link anomaly, or missing configuration. In this way, the system not only detects anomalies but also intelligently analyzes their possible causes, providing clues for troubleshooting.

[0117] In this embodiment of the invention, by combining operational semantics, execution status, and link information into a model during the analysis process, the inefficient process of relying on manual experience to check each item is avoided. This is particularly suitable for smart substation scenarios with a large number of devices and complex logical relationships. Maintenance personnel do not need to check the link status one by one or manually check whether the pressure plates, control blocks, and links are consistent. The system can generate analysis conclusions with logical explanations, which greatly reduces the time for manual intervention and the error rate.

[0118] Reference manual attached Figure 2 The diagram shows a schematic representation of the structure of an intelligent auxiliary system for debugging secondary equipment based on a secondary logic model, provided in an embodiment of the present invention.

[0119] This invention provides an intelligent auxiliary system 20 for debugging secondary equipment based on a secondary logic model, comprising: a processor 201 and a memory 202; The memory 202 stores programs or instructions that can run on the processor 201. When the program or instructions are executed by the processor 201, they implement the steps of the above-mentioned intelligent auxiliary method for debugging secondary devices based on a secondary logic model and achieve the same technical effect. To avoid repetition, the present invention will not elaborate further.

[0120] It should be understood that the processor 201 in this embodiment of the invention may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0121] It should also be understood that the memory 202 in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0122] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0123] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0124] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0125] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0126] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0127] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0128] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0129] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0130] This invention provides a readable storage medium comprising: storing a program or instructions on the readable storage medium, wherein when the program or instructions are executed by a processor, the program or instructions implement the steps of the above-described intelligent auxiliary method for debugging secondary devices based on a secondary logic model, and can achieve the same technical effect. To avoid repetition, this invention will not elaborate further.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A quadratic device commissioning intelligent assistance method based on a quadratic logic model, characterized in that, The method comprises the following steps: S1: collecting multi-source structured data related to secondary equipment; S2: constructing a secondary logic model graph for debugging assistance based on the multi-source structured data, taking device nodes as objects, and taking communication relationships and logical control relationships as connection edges; S3: obtaining a debugging task; S4: mapping the debugging task to a corresponding node in the secondary logic model graph through a semantic and configuration fusion matching mechanism; S5: generating a structured debugging operation template based on the secondary logic model graph and the debugging task mapping result through a combination of template retrieval, state injection, and logical verification; S6: comparing and checking the running state data of the current debugging object device based on the structured debugging operation template; S7: performing online monitoring of link state based on the comparison and checking result and the structured debugging operation template to assist in intelligent analysis of the debugging state. 2.The secondary device commissioning intelligent assistance method based on a secondary logic model of claim 1, wherein, The S2 specifically comprises the following steps: S201: analyzing the full station level SCD file in the multi-source structured data, extracting the logical node, data set, control block structure information defined in each IED device, and the corresponding publishing data path information; S202: identifying the subscription relationship of each IED device to external data sources based on the publishing data path information, and analyzing the subscription reference relationship of the corresponding Inputs block and virtual terminal, to generate a preliminary virtual communication structure graph; S203: analyzing the logical connection path between each IED device based on the control block structure information and the subscription reference relationship of the Inputs block and the virtual terminal, and combining the preliminary virtual communication structure graph to construct a logical communication topology graph inside the device system; S204: collecting field physical connection information including device optical port and optical fiber link information, and fusing the logical communication topology graph with the device optical port and the optical fiber link information to form a virtual-real mapping model; S205: based on the virtual-real mapping model, calling a pre-defined logical control rule library and combining the running state and backplane configuration of each IED device to construct a logical control dependent edge set between devices; S206: integrating the logical communication topology graph, the virtual-real mapping model, and the logical control dependent edge set to construct the secondary logic model graph for debugging assistance. 3.The secondary device commissioning intelligent assistance method based on a secondary logic model of claim 2, wherein, The S204 specifically comprises the following steps: S2041: obtaining and analyzing the field optical fiber link table to extract first physical link data including device optical port number, optical fiber label, and optical fiber channel direction; S2042: reading the backplane port definition file of the IED device to determine second physical link data including the physical number, port type, and physical location of each communication port; S2043: determining whether multiple logical links are multiplexed on the same physical optical fiber; if yes, proceeding to S2044; otherwise, combining the logical communication topology graph, the first physical link data, and the second physical link data to perform logical link to physical link mapping operation to form a logical link to optical fiber link mapping relationship, and proceeding to S2045; S2044: distinguishing multiplexing relationship by analyzing virtual channel identification, timestamp and VLAN features of the logical link, establishing one-to-many logical-to-physical mapping relationship and marking multiplexing attribute in the logical-to-physical mapping relationship; completing standardized mapping of optical port naming by cross-checking through physical number, port position and type information contained in the port definition file of the IED device, combining with on-site fiber label information, and entering S2045; S2045: fusing mapping relationship of the logical path to the fiber link and standardized mapping of the optical port naming to form a virtual-real mapping model as a basic support structure of the secondary logical model graph. 4.The secondary device commissioning intelligent assistance method based on a secondary logic model of claim 1, wherein, The S4 specifically comprises: S401: performing semantic analysis on the commissioning task to extract key elements, wherein the key elements include device type, device identification, operation type and function object; S402: comparing the key elements with a built-in standard semantic dictionary to output a structured task feature vector; S403: based on the structured task feature vector, loading a total station SCD file and analyzing IED model structure and communication relationship in the total station SCD file to locate a target device; S404: identifying a logical node in the target device according to the function object and screening out key virtual terminals associated with the logical node to obtain a target IED node and a virtual terminal set functionally related to the target IED node; S405: extracting semantic query input required for matching node information in the secondary logical model graph in the commissioning task, wherein the semantic query input includes function name, terminal alias and operation target; S406: performing matching and checking operation on the semantic query input and corresponding nodes in the secondary logical model graph to determine whether there is a semantic description difference, spelling deviation or manufacturer terminology inconsistency; if yes, correcting inconsistent items by using string edit distance, and entering S407; otherwise, directly entering S407; S407: based on the matching and checking result, locating a communication control block involved in the commissioning task in combination with the virtual terminal set, and mapping the commissioning task to the corresponding node in the secondary logical model graph.

5. The method of claim 1, wherein, The S5 specifically comprises: S501: based on a target logical node and a physical terminal, combining a commissioning task type to perform semantic analysis on the commissioning task, extracting operation type and action object, and associating with attribute information of the target logical node to construct a commissioning operation primitive set; S502: calling a preset safety measure template library, taking voltage level, device type and task type as index conditions, combining action type and target object in the commissioning operation primitive set to match and search a corresponding standard operation template, and extracting a standardized operation process including pre-check items, operation sequence and post-check items; S503: Based on the real-time state data in the secondary logic model graph, the standardized operation process is dynamically adjusted in combination with the current state of the target device. If the state of the debugging object does not meet the expectation, a state-dependent operation is injected. If there is a physical layer exception, a false operation prevention and blocking instruction is inserted to form an operation sequence with state constraints; S504: In combination with the false operation prevention and locking rule library, the operation sequence is logically checked, and corresponding locking logic is matched according to the debugging task type to realize dynamic false operation prevention and checking control; S505: The operation sequence is sorted according to the operation logic priority, and the device object, physical position and interface label information of each operation item are supplemented to generate the structured debugging operation template including task identification, operation step list, execution constraints and checking conditions.

6. The method of claim 1, wherein, The S6 specifically includes: S601: The structured debugging operation template is parsed, the expected state information of each operation step in the structured debugging operation template is extracted, and the state type of the corresponding device is associated to obtain an expected state set; wherein the state type includes a fiber link state and a message state; S602: The real-time state snapshot of the device is formed by integrating the soft pressure plate state and device parameters of the protection device read through the MMS service, the light intensity and fiber link state obtained by analyzing the message, and the real-time optical power collected through the optical power meter interface of the physical port; S603: Based on the expected state set and the real-time state snapshot, the actual state and the expected state of the device are compared item by item, and the abnormal items with inconsistent states are recorded to compare and verify the running state data of the current debugging object device.

7. The method of claim 1, wherein the method further comprises: The S7 specifically includes: S701: The abnormal items are sorted according to the severity, and a structured verification report is generated in combination with the fault positioning logic; S702: Based on the structured verification report, the abnormal variables and physical slot positions are marked in the secondary logic model graph, and output as visual prompt information; S703: Based on the visual prompt information, the abnormal variables are associated, matched and time sequence logic deduced in combination with the operation sequence and expected state requirement defined in the structured debugging operation template to assist in realizing intelligent analysis of the debugging state.

8. The method of claim 7, wherein the method further comprises: The S703 includes: S7031: Using principal component analysis, each of the abnormal variables is analyzed, and the abnormal score of each of the abnormal variables is calculated; S7032: Selecting the abnormal variables with abnormal scores greater than a preset abnormal score; forming a first candidate variable set, and calculating the abnormal contribution rate of each of the abnormal variables in the first candidate variable set; S7033: Based on a long short-term memory autoencoder, a time sequence model is constructed, the reconstruction error of each of the abnormal variables is calculated through the time sequence model, and the abnormal variables with reconstruction errors greater than a preset reconstruction error are selected to construct a second candidate variable set; S7034: Taking the intersection of the first candidate variable set and the second candidate variable set, a final candidate variable set is formed; S7035: Calculate the transition entropy and the lag step of each abnormal variable in the final candidate variable set to quantify the information flow direction between variables and form a causal relationship graph; S7036: Select the leaf node variable with the highest abnormal contribution rate from the causal relationship graph as the starting point of the fault path, sequentially transmit along the edges of the causal relationship graph, preferentially select the parent node variable with the largest transition entropy value, and backtrack layer by layer until there is no parent node or a causal loop occurs to form a fault propagation path; S7037: If the end point of the fault propagation path is a root node variable, the current node variable is taken as a root cause variable; if there is a loop in the fault propagation path, the variable with the largest lag step in the loop is selected as the root cause variable to form a fault propagation chain and a root cause identification result.

9. A secondary device commissioning intelligent assistant system based on a quadratic logic model, characterized in that, Comprise: a processor and a memory; The memory stores programs or instructions that can be run on the processor, and the programs or instructions are executed by the processor to realize the steps of the secondary equipment debugging intelligent auxiliary method based on the secondary logic model according to any one of claims 1 to 8.

10. A readable storage medium, characterized by, The readable storage medium stores programs or instructions, and the programs or instructions are executed by the processor to realize the steps of the secondary equipment debugging intelligent auxiliary method based on the secondary logic model according to any one of claims 1 to 8.

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