A tamperproof device for traffic sign systems

Abstract

The application discloses an instruction tamper-proofing device for a traffic information board system, relates to the field of traffic information security, and solves the three technical problems of key clonable risk, high algorithm dependence and poor environmental adaptability existing in traditional encryption schemes. A tamper-proofing system is constructed through a triple synergy mechanism: unique unclonable physical characteristics are extracted based on a physically unclonable circuit, efficient integrity verification is realized through a segmented cascading parity check circuit, and time stamps are accurately compared in combination with a temperature compensation clock; and multi-dimensional features are fused and integrated, tamper identification is performed through feature comparison, irreversible hardware failure is formed to trigger tamper identification, and ultimate protection is formed. The device achieves a pure hardware millisecond-level response, completely eliminates software dependence, maintains a zero false rejection rate in extreme environments, ensures the safety of the whole life cycle of the instruction through physical-level protection, and provides uncopyable security protection for the information board system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of traffic information safety, more particularly, it relates to a command tamper-proof device for a traffic information board system. BACKGROUND

[0002] The traffic information board system is a LED induction screen product erected on the expressway, urban expressway, main traffic node, widely used in urban roads and other related traffic infrastructure, connected with the related system of traffic management unit, providing visible traffic induction information display, used for indicating the traffic condition, sudden road condition, road condition, safety warning, weather information and construction information in front of the driver, and has become one of the important information systems supporting the normal operation of current traffic. The command information of the traffic information board is sent by the traffic monitoring center, transmitted to the information board controller through the gateway, but the traditional gateway lacks anti-tampering ability, and the attacker can tamper with the gateway hardware or firmware to fake the command such as traffic induction command, resulting in a major safety accident.

[0003] The prior art highly depends on software encryption algorithms such as SHA-256 hash check, RSA digital signature, or traditional hardware encryption modules such as TPM security chip, eFuse key storage to ensure the safety of command transmission, but these technologies have the following significant defects:

[0004] 1) Algorithm crackability: software encryption algorithms rely on mathematical problems and are easy to be reverse-engineered and cracked, and the key storage module has physical vulnerabilities that may be physically extracted or cloned; the residual charge of flash memory storage data at low temperature can be recovered by electron microscope scanning, resulting in key cloning risk; 2) Large resource consumption: encryption algorithms require high computing power support, resulting in high power consumption and response delay in resource-limited information board controllers, thus causing algorithm failure; 3) Poor environmental adaptability: hardware encryption modules such as TPM are sensitive to temperature and voltage fluctuations, and the misjudgment rate increases in extreme environments.

[0005] Therefore, how to research and design a command tamper-proof device for a traffic information board system that can overcome the above defects is a problem we need to solve urgently. SUMMARY

[0006] In order to solve the problems in the prior art, the technical problem to be solved by the present application is to provide an instruction tamper-proofing device for a traffic information board system, which constructs a triple tamper-proofing mechanism under the condition of completely avoiding the use of traditional encryption algorithms through the synergistic effect of a physical feature extraction module, a data feature extraction module and a timing feature extraction module, effectively solving the inherent defects of the prior art, such as the risk of key cloning, high algorithm dependence and poor environmental adaptability; the system uses pure hardware circuit to realize the feature extraction, fusion and comparison process, significantly reducing power consumption and response delay, and at the same time, combining a fuse protection mechanism to form an irreversible physical protection layer, fundamentally eliminating replay attacks and persistent hardware tampering behaviors, and ensuring the whole life cycle safety of traffic information board instruction transmission.

[0007] The above technical problem of the present application is solved by the following technical scheme:

[0008] An instruction tamper-proofing device for a traffic information board system is provided, comprising:

[0009] A monitoring center for generating an instruction signal and attaching a time stamp;

[0010] A security gateway connected to the monitoring center for receiving the instruction signal and forwarding to an information board controller;

[0011] An information board controller deployed at an information board terminal, comprising:

[0012] A physical feature extraction module for extracting noise from the instruction signal based on a physically unclonable function to generate a physical feature value;

[0013] A data feature extraction module for calculating a check code by block using a segmented parity check algorithm to generate a data feature value;

[0014] A timing feature extraction module for analyzing the time stamp in the instruction signal and comparing with a local clock to generate a standard timing difference to generate a timing feature value;

[0015] A multi-dimensional feature fusion module for fusing the physical feature value, the data feature value and the timing feature value into a feature vector of the current instruction;

[0016] A feature comparison module for calculating the similarity of the feature vector with a feature vector of a stored last legal instruction, and determining that the instruction is tampered if the similarity is lower than a preset threshold.

[0017] Further, the physical feature extraction module comprises a physically unclonable circuit and a noise quantization circuit, wherein:

[0018] The physical unclonable circuit includes an SRAM memory array and a latch flip-flop, and a physical entropy source signal is generated based on the instruction signal using a power-on transient transistor threshold voltage difference;

[0019] The noise quantization circuit includes a high-pass filter, a wideband amplifier, and a peak detector, and a physical feature value is obtained by filtering and noise extraction based on the physical entropy source signal.

[0020] Further, the data feature extraction module includes a data block circuit and a cascade check circuit, wherein:

[0021] The data block circuit includes a shift register and a zero value filler, divides the instruction signal into data blocks, and obtains data segments after zero padding at the end;

[0022] The cascade check circuit includes a longitudinal XOR gate array, a transverse shift XOR chain, and a compressor, receives the data segments, calculates the longitudinal parity bits in parallel, iteratively calculates the transverse parity chain by shifting, and finally outputs the data feature value after compression.

[0023] Further, the timing feature extraction module includes a timestamp analysis circuit, a local clock circuit, and a timing difference calculation circuit, wherein:

[0024] The timestamp analysis circuit includes a packet header decoder and a data latch, and is used for extracting and latching the timestamp in the instruction information;

[0025] The local clock circuit includes a temperature-compensated crystal oscillator and a binary counter, and is used for generating a high-precision local time;

[0026] The timing difference calculation circuit includes a subtractor and an absolute value comparator, and is used for receiving the timestamp and the local time, calculating the absolute value of their difference, and outputting the timing feature value.

[0027] Further, the multi-dimensional feature fusion module includes a bit splicing circuit, which is used for combining the physical feature value, the data feature value, and the timing feature value into a feature vector.

[0028] Further, the feature comparison module includes a Hamming distance calculation circuit and a threshold comparison circuit, wherein:

[0029] The Hamming distance calculation circuit includes an XOR gate array and an addition tree, and is used for receiving the current and historical feature vectors, calculating the bit difference in parallel, and accumulating the Hamming distance;

[0030] The threshold comparison circuit includes a voltage comparator and a dial switch, and is used for setting a threshold voltage, comparing the Hamming distance signal with the threshold voltage, and outputting a tamper judgment signal.

[0031] Further, tampering response unit is further included, be provided with passage cutout circuit, alarm signal circuit and event record circuit, wherein:

[0032] The passage cutout circuit is used for receiving the tampering judgment signal and cutting off the instruction passage when tampering is judged.

[0033] The alarm signal circuit is used for receiving the tampering judgment signal and generating and sending an alarm signal when tampering is judged.

[0034] The event record circuit is used for receiving the tampering judgment signal and recording event information when tampering is judged.

[0035] Further, the tampering response unit further includes a fuse protection circuit provided with a nichrome fuse and a fuse trigger, for permanently disconnecting the power supply when the number of tampering events reaches a set threshold.

[0036] Further, a physical protection structure is further included, provided with an electromagnetic shield, a heat-conducting substrate and a serpentine wiring circuit, for blocking electromagnetic interference and maintaining signal synchronization.

[0037] Further, the electromagnetic shield of the physical protection structure covers the passage cutout circuit and the fuse protection circuit of the tampering response unit, the heat-conducting substrate is in heat-conducting connection with the nichrome fuse of the fuse protection circuit, and the serpentine wiring circuit is arranged at the input end of the Hamming distance calculation circuit.

[0038] Compared with the prior art, the present application has the following beneficial effects:

[0039] 1. The present application constructs a triple tamper-proofing mechanism through the synergistic effect of the physical feature extraction module, the data feature extraction module and the timing feature extraction module, completely avoids the use of traditional encryption algorithms, effectively solves the inherent defects of the prior art such as key cloning risk, high algorithm dependence and poor environmental adaptability, the system realizes the feature extraction, fusion and comparison process by using pure hardware circuit, significantly reduces power consumption and response delay, and forms an irreversible physical protection layer by combining a fuse protection mechanism, fundamentally eliminates replay attacks and persistent hardware tampering behavior, and ensures the whole life cycle safety of traffic information board instruction transmission.

[0040] 2. The feature extraction, fusion and comparison process of the present application are realized by hardware circuit. This pure hardware implementation significantly reduces the power consumption and instruction response delay of the system, solves the problem of dependence on high algorithm of software encryption. At the same time, the hardware circuit has stronger adaptability to environmental factors such as temperature and voltage fluctuation, improves the reliability of the system in extreme environment, and avoids the problem of increased misjudgment rate of traditional hardware encryption modules in extreme environment.

[0041] 3, The application innovatively combines a fuse protection mechanism such as a fuse protection circuit and a fuse trigger, which can permanently disconnect the power supply when the number of tampering events detected reaches a set threshold. This irreversible protection at the physical level fundamentally eliminates replay attacks and persistent hardware tampering behavior, providing full-life-cycle security for traffic information board command transmission, which is difficult to achieve with traditional software or resettable hardware protection measures. BRIEF DESCRIPTION OF DRAWINGS

[0042] The drawings described herein are intended to provide further understanding of the embodiments of the application, form a part of the application, and do not constitute a limitation on the embodiments of the application. In the drawings:

[0043] Figure 1 The structure diagram in the embodiments of the application is shown.

[0044] Figure 2 The feature comparison module flow chart in the embodiments of the application is shown. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical scheme and advantages of the application more clear and obvious, the application is further described in detail below in combination with embodiments and drawings. The illustrative embodiments of the application and their descriptions are only used to explain the application and do not constitute a limitation on the application.

[0046] Embodiment: An instruction tamper-proofing device for a traffic information board system, as shown in Figure 1 , comprising:

[0047] A monitoring center for generating an original instruction signal and attaching a time stamp. A security gateway connected to the monitoring center for receiving the instruction signal and forwarding it to the information board controller. The information board controller deployed at the information board terminal, comprising: a physical feature extraction module for extracting noise from the received instruction signal based on a physically unclonable function to generate a physical feature value; a data feature extraction module for calculating a check code by block using a segmented parity check algorithm to generate a data feature value; a time sequence feature extraction module for analyzing the time stamp in the instruction signal and comparing it with the local clock to generate a standard time sequence difference to generate a time sequence feature value; a multi-dimensional feature fusion module for fusing the physical feature value, the data feature value and the time sequence feature value into a feature vector of the current instruction; a feature comparison module for calculating the similarity between the feature vector of the current instruction and the feature vector of the stored last legal instruction, and determining that the instruction is tampered if the similarity is lower than a preset threshold.

[0048] The system comprises a monitoring center, a security gateway and an intelligence board controller to form a closed loop tamper-proof link. The monitoring center generates original instructions with time stamps, which are transmitted to the intelligence board controller through the security gateway. The controller generates a feature vector through a triple feature extraction module and compares it with the historical legal instruction features to determine tampering. The following describes the structure and principles of each module:

[0049] The physical feature extraction module is based on the physical unclonable function (PUF) technology and includes a physical unclonable circuit and a noise quantization circuit. Considering that software encryption algorithms are easy to be reverse-engineered and broken, and hardware encryption modules have the risk of cloning keys, the PUF uses the random differences in transistor threshold voltages in semiconductor manufacturing processes to generate a physical fingerprint that cannot be replicated, and attackers cannot clone it. Therefore, the physical feature extraction module of the present application is designed based on the physical unclonable function and extracts noise from the received instruction signals.

[0050] The physical unclonable circuit is composed of an SRAM memory array and a latch trigger. The instruction signal is input to the latch trigger, which triggers the SRAM memory array to power on. At the moment of power-on, the SRAM unit enters a metastable state due to the random differences in transistor threshold voltages, generating a native random state sequence and forming a physical entropy source signal (micro-volt level analog signal). This process utilizes the intrinsic randomness of silicon wafer manufacturing to ensure that the output of different chips is unique and cannot be replicated.

[0051] The noise quantization circuit processes the physical entropy source signal. First, a high-pass filter filters the physical entropy source signal to filter out low-frequency environmental interference and retain high-frequency components to isolate pure noise features, obtaining a high-frequency noise signal. A wideband amplifier amplifies the micro-volt level high-frequency noise signal to a detectable range, enhancing the signal-to-noise ratio, and obtaining an amplified noise signal. Finally, a peak detector captures the pulse amplitude of the amplified noise signal and outputs it as a physical feature value.

[0052] It should be noted that the physical unclonable circuit (PUF) generates a physical entropy source signal based on the uniqueness of the controller hardware (such as the difference in SRAM threshold voltage). When the instruction signal is forwarded to the controller through the security gateway, the PUF will extract noise from the instruction to generate a physical feature value. This means that the same instruction will generate different physical feature values on different controllers, thereby indirectly identifying the transmission path and controller identity of the instruction. The physical feature module does not directly identify the instruction, but ensures the trusted execution of the instruction on a specific controller through hardware uniqueness. Attackers cannot clone the controller hardware, so they cannot fake the physical features of the instruction.

[0053] The physical feature extraction process of the application realizes millisecond-level response at the pure hardware level, avoids software dependence, ensures that the feature fluctuation rate of the physical feature is low under temperature fluctuation of-40 DEG C to 85 DEG C, the misjudgment rate of the traditional hardware encryption module is low, the key copying is eliminated from the physical layer, the anti-cloning and environmental robustness are ensured, and thus an irreversible trust foundation for instruction tamper-proofing is provided.

[0054] The data feature extraction module adopts a segmented parity check algorithm to calculate a check code for the instruction signal in blocks, generates a data feature value, and comprises a data block circuit and a cascade check circuit. Because the existing software encryption algorithm consumes a large amount of resources, leads to high power consumption and response delay in high-resource-limited environments such as intelligence board controllers, and the hardware encryption module is sensitive to temperature fluctuation, the misjudgment rate is high in extreme environments. Therefore, the application discards the traditional encryption method, realizes dynamic block cascade parity check through a pure hardware circuit, and constructs an integrity protection barrier for instruction data with extremely low resource consumption.

[0055] The data block circuit comprises a shift register and a zero value filler, the instruction signal is divided into data segments of a fixed bit through the shift register, and the zero value filler is used for zero filling operation at the end of the segment to ensure data integrity.

[0056] The cascade check circuit comprises a longitudinal XOR gate array, a horizontal shift XOR chain and a compressor; receives the data segment, calculates the parity bit in the segment in parallel through the longitudinal XOR gate array, obtains the parity value of each segment, iteratively generates a multi-stage parity chain through the horizontal shift XOR chain, and finally outputs the data feature value by the compressor.

[0057] It should be noted that this module is not a simple error check, but generates a dynamic feature value through a segmented parity check algorithm for tamper detection. The purpose of calculating the similarity is to detect whether the instruction is tampered with (for example, a replay attack will cause the data feature value to be abnormal), and the similarity comparison of different instructions can identify minor changes, rather than testing transmission errors.

[0058] The application only needs a few logic gates to perform data verification, reduces power consumption and improves response speed, and the cascade structure automatically adapts to changes in instruction length, eliminates the grouping padding delay of software verification, and improves environmental adaptability, thereby constructing an efficient and low-power tamper-proofing barrier to support real-time traffic instruction processing requirements while avoiding the risk of key cloning.

[0059] In view of the problem that the traditional hardware encryption module is sensitive to clock drift and leads to high misjudgment rate, the application selects a local high-precision clock and instruction timestamp direct comparison scheme, and the technical principle is to generate an absolute time reference by using the microsecond-level stability of a temperature-compensated crystal oscillator, and capture a replay attack by calculating the time difference of instruction transmission in real time. The time sequence feature extraction module comprises a timestamp analysis circuit, a local clock circuit and a time sequence difference calculation circuit.

[0060] The time stamp analysis circuit comprises a header decoder and a data latch, and first receives the instruction signal, the header decoder identifies the time stamp field, and the data latch latches the multi-bit time stamp data at the clock rising edge.

[0061] The local clock circuit adopts a temperature-compensated crystal oscillator and a binary counter architecture, the crystal oscillator outputs a stable frequency signal, and the counter divides the frequency to generate an accurate local time.

[0062] The time difference calculation circuit comprises a subtractor and an absolute value comparator, the subtractor performs a binary subtraction operation on the time stamp and the local time, and the absolute value comparator converts the difference into an unsigned time feature value.

[0063] The time feature extraction module analyzes the instruction time stamp and compares it with the local temperature-compensated clock to generate a time feature value. If the attacker modifies the time stamp, the time difference calculation circuit will detect an abnormal deviation from the local time (such as the delay of a replay attack), thereby triggering the tampering judgment. This module ensures the effectiveness of the time stamp verification through the non-tamperable nature of the hardware clock (the attacker cannot modify the local clock of the controller), without the need for decryption algorithms.

[0064] The crystal oscillator frequency drift maintains a very low level throughout the process, the time difference resolution reaches a high precision standard, ensures effective interception of malicious delayed instructions in long-distance transmission scenarios, the time error rate tends to zero in a wide temperature range, and the replay attack interception rate is significantly improved, while the power consumption is reduced compared with traditional schemes.

[0065] To meet the millisecond-level response requirement of traffic instructions, the multi-dimensional feature fusion module of the application adopts a hardware bit splicing architecture. The traditional software fusion scheme has scheduling and memory access delay, which cannot meet the real-time requirement; the dynamic weighting circuit is easily affected by temperature drift in extreme environments and has high resource consumption, therefore, the architecture realizes direct alignment and compression of features through physical circuits, integrates multi-dimensional features into hierarchical vectors in a single clock cycle, and completely avoids software processing delay.

[0066] The module comprises a bit splicing circuit, the core of the bit splicing circuit comprises a bit width matching circuit, a shift register and an output latch, first receives physical feature values, data feature values and time feature values, uniformly expands the feature values to a preset bit width through the bit width matching circuit to eliminate the bit width difference; the feature value signals of the uniform bit width are input into the shift register and spliced in the order of physical high bit, data middle bit and time low bit, the spliced parallel signals are latched through the output latch to obtain a complete feature vector.

[0067] The multi-dimensional feature fusion module realizes nanosecond-level feature fusion through hardware bit splicing, completely eliminates software scheduling delay and memory access overhead; synchronous control ensures accurate alignment of multiple signal phases, avoiding temperature drift error; the physical solidification splicing structure forms an unalterable hierarchical protection barrier, maintains high reliability in extreme environments, and provides zero-error input for real-time anti-tampering decision.

[0068] Considering the software similarity algorithm delay bottleneck, the feature comparison module adopts a pure hardware Hamming distance real-time comparison architecture based on parallel computing and threshold comparison of feature vector bit differences, as shown in Figure 2 .

[0069] The Hamming distance calculation circuit includes an XOR gate array and an addition tree. First, the current and historical feature vectors are received, the XOR gate array performs full-bit-width parallel computation of bit differences, generates a difference vector, and inputs the multi-level addition tree structure for step-by-step compression, and finally outputs the Hamming distance value.

[0070] Among them, the Hamming distance is a core measurement index in information theory and coding theory, used to quantify the difference between two equal-length strings. In view of the real-time response and computing power demand of the traffic information board, with the advantages of hardware friendliness, environmental strong robustness, cost and power consumption, it becomes the core algorithm to realize the protection demand of the present application; its bit-level difference quantization characteristic fundamentally avoids the dependence on computing power and the risk of key storage of traditional encryption algorithms, providing a hardware-level security foundation for subsequent comparison of the present application.

[0071] The threshold comparison circuit adopts a voltage comparison mechanism, and the dial switch sets multiple protection thresholds. The Hamming distance value is compared with the threshold voltage after conversion. If tampering is judged, a tampering judgment level signal is output to the tampering response unit. If no tampering is judged, it is output to the information board terminal for instruction display.

[0072] It should be noted that the feature comparison module is not directly comparing the instruction signal, but comparing the feature vector fused by physical, data, and timing features. The multi-dimensional feature fusion module combines the three types of feature values into a feature vector through the bit splicing circuit. The feature comparison module (Hamming distance calculation circuit and threshold comparison circuit) calculates the Hamming distance between the current and historical feature vectors. If the similarity is lower than the threshold, it indicates that the instruction may be tampered with. The similarity calculation is based on multi-dimensional features such as physical uniqueness, data integrity, and timing consistency to achieve comprehensive detection of various tampering behaviors such as cloning, data modification, and replay attacks.

[0073] The threshold comparison of the application is in the order of sub-microsecond, the Hamming distance is triggered when it exceeds the threshold, the single-bit tampering detection rate is close to absolute coverage, the replay attack recognition rate reaches complete protection, the power consumption and circuit area are exponentially optimized compared with the digital processing scheme, and the full-time protection demand of the resource-limited scene is met.

[0074] The tamper response unit receives the tamper judgment signal of the feature comparison module for circuit protection, and is provided with a path cutting circuit, an alarm signal circuit, an event recording circuit and a fuse protection circuit.

[0075] The path cutting circuit is composed of a high-speed relay and an optical coupling isolator, receives the tamper judgment signal output by the feature comparison module, cuts off the instruction transmission path when tampering is judged, and blocks the downward penetration of malicious instructions.

[0076] The alarm signal circuit includes a multi-vibrator and a wireless transmission module, activates the oscillation circuit after receiving the tamper judgment signal, generates a pulse of a specific frequency, and drives the wireless transmission module to send an encrypted alarm signal to the monitoring center.

[0077] The event recording circuit uses a non-volatile FRAM memory in linkage with a real-time clock chip, and automatically records the event timestamp, Hamming distance value and original instruction feature value when a tampering event occurs.

[0078] The fuse protection circuit is provided with a nichrome fuse and a fuse trigger for replay attacks and persistent hardware tampering behaviors, and when the number of tampering events counted by the event recording circuit reaches a set threshold, the fuse trigger drives the circuit to make the nichrome fuse fuse, permanently disconnecting the controller power supply and forming irreversible physical protection.

[0079] The tamper response unit of the application realizes protection upgrade through a four-stage hardware linkage mechanism, the path cutting realizes nanosecond-level attack blocking, the alarm system uses a physical oscillation circuit to ensure that power failure can still alarm, and the fuse mechanism completely eliminates persistent attacks through irreversible physical damage, thereby improving security.

[0080] The application also includes a physical protection structure, which adopts a three-layer composite protection architecture to solve the problem of extreme electromagnetic environment interference and hardware tampering risk.

[0081] The electromagnetic shield cover is made of permalloy and covers the path cutting circuit and the fuse protection circuit of the tamper response unit, provides shielding effectiveness in the high frequency band, and blocks external electromagnetic injection attacks.

[0082] The heat-conducting substrate is directly connected to the nichrome fuse of the fuse protection circuit through a copper-embedded ceramic substrate, has a high thermal conductivity, ensures rapid heat dissipation when the fuse is working, and avoids false fusing.

[0083] The serpentine wiring circuit is arranged at the input end of the Hamming distance calculation circuit of the feature comparison module, the length of the wiring is accurately matched with the clock period, the phase difference of the signals is eliminated through delay superposition, and the synchronization precision of the bit comparison is maintained.

[0084] The physical protection structure of the application innovatively integrates electromagnetic shielding, thermal management and signal synchronization technology, reduces the electromagnetic interference false triggering rate through the permalloy shield, controls the smooth fluctuation of the fuse working temperature using the ceramic heat-conducting substrate, and reduces the Hamming distance calculation signal offset using the serpentine wiring circuit, so that the triple protection ensures that the system has near-zero failure in the-40℃~125℃ and strong electromagnetic environment.

[0085] Working principle: The monitoring center generates original instructions with time stamps, which are transmitted to the intelligence board controller through the security gateway. The controller extracts physical features based on transistor threshold differences using the physical feature extraction module, generates data features through segmented parity check using the data feature extraction module, and generates timing features by comparing time stamps using the timing feature extraction module. After the multi-dimensional feature fusion module integrates the feature vectors, the feature comparison module calculates the Hamming distance and compares it with the threshold value to determine tampering. If tampering is detected, the tampering response unit immediately cuts off the path, sends an alarm and records the event, and the fuse protection mechanism permanently disconnects the power supply after multiple events. The entire process is implemented at the pure hardware level, without the need for software encryption, significantly reducing power consumption and delay, and ensuring the safety of the entire life cycle of instruction transmission.

[0086] Those skilled in the art will appreciate that embodiments of the application can be provided as methods, systems, or computer program products. Accordingly, the application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage, etc.) containing computer usable program code.

[0087] The application is described with reference to flowcharts and / or block diagrams according to the method, device (system) and computer program product of the embodiments of the application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of the flows and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device that implements the functions specified in the flowchart and / or block diagram. Figure 1 The device that implements the functions specified in one flow or multiple flows and / or blocks Figure 1 The device that implements the functions specified in one flow or multiple flows and / or blocks

[0088] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the flow Figure 1 one or more flow or block Figure 1 one or more flow or block

[0089] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions that are executed on the computer or other programmable apparatus provide steps for implementing the flow Figure 1 one or more flow or block Figure 1 one or more flow or block

[0090] The above detailed description merely describes a specific implementation of the application, and the specific implementation does not limit the scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application should be included in the protection scope of the application.

Claims

1. A device for preventing tampering of instructions in a traffic information sign system, characterized in that, include: The monitoring center is used to generate command signals and attach timestamps; A security gateway, connected to the monitoring center, is used to receive the instruction signals and forward them to the information board controller; The information board controller, deployed at the information board terminal, includes: The physical feature extraction module performs noise extraction on the command signal based on the physically non-clonable function to generate physical feature values; The data feature extraction module uses a segmented parity check algorithm to calculate check codes in blocks of the instruction signal and generate data feature values. The timing feature extraction module parses the timestamp in the instruction signal, compares it with the local clock to generate a standard timing difference, and generates timing feature values. The multi-dimensional feature fusion module fuses the physical feature values, the data feature values, and the temporal feature values ​​into a feature vector for the current instruction. The feature comparison module calculates the similarity between the feature vector and the feature vector of the previous legal instruction stored in the database. If the similarity is lower than a preset threshold, the instruction is determined to have been tampered with. The data feature extraction module includes a data segmentation circuit and a cascaded verification circuit, wherein: The data segmentation circuit includes a shift register and a zero filler, which divides the instruction signal into data blocks and fills the end segments with zeros to obtain data segments. The cascaded verification circuit includes a vertical XOR gate array, a horizontal shift XOR chain, and a compressor. It receives the data segment, calculates the vertical parity bits of each segment in parallel, iteratively calculates the horizontal parity chain, and finally compresses and outputs the data feature value.

2. The command anti-tampering device for a traffic information board system according to claim 1, characterized in that, The physical feature extraction module includes a physically unclonable circuit and a noise quantization circuit, wherein: The physically unclonable circuit includes an SRAM memory array and a latching flip-flop, and generates a physical entropy source signal based on the instruction signal by utilizing the difference in transistor threshold voltage at the moment of power-on. The noise quantization circuit includes a high-pass filter, a broadband amplifier, and a peak detector, used to filter and extract noise from the physical entropy source signal to obtain physical feature values.

3. The command anti-tampering device for a traffic information board system according to claim 1, characterized in that, The timing feature extraction module includes a timestamp parsing circuit, a local clock circuit, and a timing difference calculation circuit, wherein: The timestamp parsing circuit includes a packet header decoder and a data latch, used to extract and latch the timestamp in the instruction signal; The local clock circuit includes a temperature-compensated crystal oscillator and a binary counter for generating high-precision local time. The timing difference calculation circuit includes a subtractor and an absolute value comparator, used to receive the timestamp and the local time, calculate the absolute value of their difference and output it as the timing feature value.

4. The command anti-tampering device for a traffic information board system according to claim 1, characterized in that, The multi-dimensional feature fusion module includes a bit splicing circuit, which is used to combine physical feature values, data feature values, and time series feature values ​​into a feature vector.

5. The command anti-tampering device for a traffic information board system according to claim 1, characterized in that, The feature comparison module includes a Hamming distance calculation circuit and a threshold comparison circuit, wherein: The Hamming distance calculation circuit includes an XOR gate array and an addition tree, used to receive current and historical feature vectors, perform parallel XOR calculation of bit differences, and accumulate and output the Hamming distance; The threshold comparison circuit includes a voltage comparator and a DIP switch, used to set a threshold voltage, compare it with the Hamming distance signal, and output a tampering determination signal.

6. The command anti-tampering device for a traffic information board system according to claim 5, characterized in that, It also includes a tamper response unit, which is equipped with a path disconnection circuit, an alarm signal circuit, and an event recording circuit, wherein: The path cutting-off circuit is used to receive the tampering determination signal and cut off the instruction path when tampering is determined. The alarm signal circuit is used to receive the tampering determination signal and generate and send an alarm signal when tampering is determined. The event recording circuit is used to receive the tampering determination signal and record event information when tampering is determined.

7. The command anti-tampering device for a traffic information board system according to claim 6, characterized in that, The tamper response unit also includes a fuse protection circuit, which is equipped with a nickel-chromium fuse and a fuse trigger, used to permanently disconnect the power supply when the number of tampering events reaches a set threshold.

8. A device for preventing tampering of instructions in a traffic information board system according to claim 6, characterized in that, It also includes a physical protection structure, which is equipped with an electromagnetic shield, a heat-conducting substrate and a serpentine circuit, to block electromagnetic interference and maintain signal synchronization.

9. A device for preventing tampering of instructions in a traffic information sign system according to claim 8, characterized in that, The electromagnetic shield of the physical protection structure covers the path cutting-off circuit and the fuse protection circuit of the tamper response unit. The thermally conductive substrate is thermally connected to the nickel-chromium fuse of the fuse protection circuit. The serpentine wiring circuit is arranged at the input terminal of the Hamming distance calculation circuit.

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