Configuration structure, method and equipment of graphics processor, storage medium and program product

Abstract

The invention relates to a configuration structure and method of a graphics processor, equipment, a storage medium and a program product. The method comprises the following steps: a configuration structure of the graphics processor comprises a coprocessor, a network-on-chip and a broadcast module; the coprocessor is used for receiving a first configuration instruction sent by the central processor; in response to the first configuration instruction, sending configuration information to the network-on-chip; wherein the first configuration instruction is used for indicating to send configuration information to the image processor, and the configuration information is used for configuring hardware resources of the image processor during operation; the network-on-chip is connected with the coprocessor and is used for sending the configuration information to the broadcast module under the condition that the type of the configuration information is broadcast configuration; the broadcasting module is connected with the network-on-chip; and the broadcasting module comprises a plurality of broadcasting channels and is used for broadcasting and sending the configuration information to the plurality of graphics processors through the broadcasting channels. By adopting the method, the configuration concurrency capability of the graphics processor can be improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a configuration structure, method, apparatus, storage medium, and program product of a graphics processor. Background Technology

[0002] With the increasing prevalence of applications such as artificial intelligence, massively parallel computing, and high-resolution graphics processing, graphics processing units (GPUs) have evolved from fixed rendering units into high-performance accelerators supporting general-purpose parallel computing. To meet the ever-growing computing demands, GPUs have gradually evolved into multi-core designs.

[0003] In related technologies, resource allocation and task scheduling in multi-core graphics processing units (GPUs) typically rely on the central processing unit (CPU). However, with the rapid increase in the number of GPU cores in multi-core GPUs, the CPU-based allocation method faces the problem of insufficient concurrency. Summary of the Invention

[0004] Based on this, a configuration structure, method, device, storage medium, and program product for a graphics processor that can improve the configuration concurrency capability of a graphics processor are provided.

[0005] In a first aspect, this application provides a configuration structure for a graphics processor, the configuration structure of which includes a coprocessor, an on-chip network, and a broadcast module;

[0006] The coprocessor is configured to receive a first configuration instruction sent by the central processing unit; and in response to the first configuration instruction, send configuration information to the on-chip network; wherein the first configuration instruction is configured to instruct the image processor to send configuration information, and the configuration information is configured to configure the hardware resources of the image processor during operation;

[0007] The on-chip network, connected to the coprocessor, is used to send the configuration information to the broadcast module when the type of the configuration information is broadcast configuration;

[0008] The broadcast module is connected to the on-chip network; the broadcast module includes multiple broadcast channels for broadcasting the configuration information to multiple graphics processors through the broadcast channels.

[0009] In one embodiment, the coprocessor includes multiple configuration channels for caching the configuration information.

[0010] In one embodiment, the on-chip network includes multiple Advanced Scalable AXI interfaces, each AXI interface being connected to a graphics processor. The AXI interface is used to send configuration information output by the configuration structure of the graphics processor to the graphics processor connected to the AXI interface.

[0011] In one embodiment, the configuration information includes a sideband signal, which is used to indicate the configuration information in the configuration channel where the coprocessor cache is located;

[0012] The broadcast module is further configured to determine the graphics processor to receive the configuration information based on the configuration information indicated by the sideband signal in the configuration channel where the coprocessor cache is located, and the mapping relationship between the configuration channel and the transmission address information.

[0013] In one embodiment, the broadcast module is further configured to broadcast the configuration information to the graphics processor receiving the configuration information via an AXI interface connected to the graphics processor receiving the configuration information in the on-chip network.

[0014] In one embodiment, the on-chip network is further configured to send the configuration information to the target graphics processor through the AXI interface corresponding to the target graphics processor when the type of the configuration information is unicast configuration, wherein the target graphics processor is the graphics processor corresponding to the transmission address information of the configuration information.

[0015] In one embodiment, the broadcast module is further configured to broadcast the configuration information to multiple graphics processors via the broadcast channel.

[0016] In one embodiment, the coprocessor is further configured to receive a second configuration instruction sent by the central processing unit, the second configuration instruction including identification information of the graphics processor to which the configuration information is to be received; and to convert the identification information of the graphics processor to which the configuration information is to be received into transmission address information of the configuration information.

[0017] In one embodiment, the graphics processor includes a graphics processor in a first chip or a graphics processor in a second chip;

[0018] Wherein, the first core is the core in which the configuration structure of the graphics processor is located, and the second core is another core besides the first core.

[0019] Secondly, this application provides a method for configuring a graphics processor, the method comprising:

[0020] The system receives a first configuration instruction sent by the central processing unit, wherein the first configuration instruction is used to instruct the image processor to send configuration information, the configuration information being used to configure the hardware resources of the image processor during operation;

[0021] When the configuration information is of type broadcast configuration, the configuration information is sent to the broadcast module, which includes multiple broadcast channels for broadcasting the configuration information to multiple graphics processors through the broadcast channels.

[0022] In one embodiment, the configuration information includes a sideband signal, which is used to indicate the configuration information in the configuration channel where the coprocessor cache is located;

[0023] The method further includes: determining the graphics processor to receive the configuration information based on the configuration information indicated by the sideband signal in the configuration channel where the coprocessor cache is located, and the mapping relationship between the configuration channel and the transmission address information.

[0024] In one embodiment, when the configuration information is of unicast type, the configuration information is sent to the target graphics processor through the AXI interface corresponding to the target graphics processor, where the target graphics processor is the graphics processor corresponding to the transmission address information of the configuration information.

[0025] In one embodiment, the broadcast module is further configured to interleave the configuration information to multiple graphics processors via the broadcast channel, wherein the interleaving transmission is a method in which the broadcast channel inserts and transmits configuration information cached by different configuration channels during idle transmission gaps.

[0026] In one embodiment, the method further includes:

[0027] Receive a second configuration instruction sent by the central processing unit, wherein the second configuration instruction includes identification information of the graphics processor to which the configuration information is to be received;

[0028] The identification information of the graphics processor to receive the configuration information is converted into the transmission address information of the configuration information.

[0029] In one embodiment, the graphics processor includes a graphics processor in a first chip or a graphics processor in a second chip;

[0030] Wherein, the first core is the core in which the configuration structure of the graphics processor is located, and the second core is another core besides the first core.

[0031] Thirdly, this application also provides a configuration device for a graphics processor, the device comprising:

[0032] The instruction receiving module is used to receive a first configuration instruction sent by the central processing unit, wherein the first configuration instruction is used to instruct the image processor to send configuration information, and the configuration information is used to configure the hardware resources of the image processor during operation;

[0033] A transmission module is used to send the configuration information to a broadcast module when the type of the configuration information is broadcast configuration. The broadcast module includes multiple broadcast channels for broadcasting the configuration information to multiple graphics processors through the broadcast channels.

[0034] Fourthly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the configuration method of the graphics processor described in the second aspect.

[0035] Fifthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the configuration method of the graphics processor described in the second aspect.

[0036] Sixthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the configuration method of the graphics processor described in the second aspect above.

[0037] The aforementioned graphics processor configuration structure, method, device, storage medium, and program product include a graphics processor configuration structure comprising a coprocessor, an on-chip network, and a broadcast module. The coprocessor receives a first configuration instruction from the central processing unit (CPU) and, in response to the first configuration instruction, sends configuration information to the on-chip network. The first configuration instruction instructs the sending of configuration information to the graphics processor, which configures the hardware resources of the graphics processor during runtime. The on-chip network, connected to the coprocessor, sends the configuration information to the broadcast module when the configuration information is of broadcast configuration type. The broadcast module, connected to the on-chip network, includes multiple broadcast channels for broadcasting the configuration information to multiple graphics processors. Because the configuration information is broadcast configuration, and the multiple broadcast channels of the broadcast module broadcast the configuration information to multiple graphics processors, the broadcast configuration does not consume a large amount of concurrency, thereby improving the configuration concurrency capability of the graphics processor. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram illustrating a configuration method for a multi-core graphics processor in related technologies.

[0040] Figure 2 A structural block diagram illustrating the configuration structure of a graphics processor provided in an embodiment of this application;

[0041] Figure 3 A flowchart illustrating a method for configuring a graphics processor according to an embodiment of this application;

[0042] Figure 4 A structural block diagram of a graphics processor configuration device provided in an embodiment of this application;

[0043] Figure 5 This is an internal structural diagram of a computer device provided in an embodiment of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0045] The relevant technologies will be explained below.

[0046] With the increasing prevalence of applications such as artificial intelligence, massively parallel computing, and high-resolution graphics processing, graphics processing units (GPUs) have evolved from fixed rendering units into high-performance accelerators supporting general-purpose parallel computing. To meet the growing computing demands, GPUs have gradually evolved into multi-core designs. By integrating a large number of parallel computing cores into the same chip or multiple chips, overall computing power and throughput can be significantly improved.

[0047] In related technologies, resource allocation and task scheduling in multi-core graphics processors typically rely on the central processing unit (CPU) within the multi-core graphics processor. Figure 1 This is a schematic diagram illustrating a configuration method for a multi-core graphics processor in related technologies, such as... Figure 1As shown, the multi-core graphics processing unit (GPU) includes four GPU cores: GPU 0, GPU 1, GPU 2, and GPU 3. GPU 0 is designated as the configuration core and includes a CPU for configuration. The configuration interface of the CPU in GPU 0 includes one Advanced Dextensible Interface (AXI) host interface and one AXI slave interface. The registers of the four GPU cores in the multi-core GPU can be configured through the AXI host interface corresponding to the CPU in GPU 0.

[0048] For example, when a broadcast configuration needs to be sent, the CPU in GPU 0 can convert the broadcast configuration from parallel to serial before sending it to the corresponding AXI host interface. Since each GPU can potentially become a configuration core, and each GPU can access other cores while being accessed by other cores, to avoid the deadlock problem of a single-ring on-chip network, such as... Figure 1 As shown, a dual-ring on-chip network can be used in a multi-core graphics processor.

[0049] However, because related technologies convert broadcast configurations into serial configuration streams for transmission, the concurrent processing capacity of configuration cores is heavily consumed by broadcast configurations as the number of GPU cores in multi-core GPUs rapidly increases and broadcast configuration scenarios become more frequent. Furthermore, multi-core GPUs are limited by on-chip networking, restricting their maximum concurrency to 256; as the number of cores increases, the number of configurations each GPU can receive decreases linearly. Therefore, CPU-based configuration methods in related technologies face the problem of insufficient concurrency.

[0050] Furthermore, in related technologies, the graphics processor (GPU) only has one set of AXI host interfaces when used as the configuration core, resulting in a theoretical upper limit to the configuration bandwidth. Therefore, as the number of GPU cores in a multi-core GPU increases, the configuration bandwidth received by each GPU decreases linearly. In addition, the configuration core in these technologies only utilizes the AXI protocol for handshaking, lacking scalability and the ability to perform any performance optimizations tailored to configuration characteristics.

[0051] To address the aforementioned issues, embodiments of this application provide a configuration structure, method, device, storage medium, and program product for a graphics processor. When the configuration information is broadcast configuration, the configuration information is broadcast to multiple graphics processors through multiple broadcast channels of the broadcast module, thereby preventing the broadcast configuration from consuming a large number of concurrent connections and thus improving the configuration concurrency capability of the graphics processor.

[0052] It should be understood that the above-mentioned graphics processor configuration can be any multi-core graphics processor, or any device including a multi-core graphics processor, and this application does not limit this.

[0053] In one exemplary embodiment, such as Figure 2 As shown, a configuration structure for a graphics processor is provided, which includes a coprocessor, an on-chip network, and a broadcast module.

[0054] The coprocessor receives a first configuration instruction from the central processing unit (CPU) and, in response to the first configuration instruction, sends configuration information to the on-chip network (ISP). The ISP, connected to the coprocessor, sends the configuration information to the broadcast module when the configuration information is a broadcast configuration. The broadcast module, connected to the ISP, broadcasts the configuration information to multiple graphics processors via a broadcast channel.

[0055] The first configuration instruction is used to instruct the transmission of configuration information, which is used to configure the hardware resources of the graphics processor during runtime. This configuration information can be the configuration information of any one or more graphics processors.

[0056] The coprocessor will be explained first.

[0057] In some embodiments, the coprocessor includes multiple configuration channels for caching configuration information.

[0058] For example, a coprocessor can instantiate multiple configuration channels, and each configuration channel can cache multiple configuration information. It should be understood that this application embodiment does not limit the number of configuration channels in the coprocessor, and can be specifically set according to actual conditions. For example, a coprocessor can instantiate 32 configuration channels, and each configuration channel can cache 32 bits * 64 pieces of configuration information.

[0059] In some embodiments, the configuration information in the coprocessor's configuration channel can be controlled by instructions sent from an external central processing unit (CPU) to perform various operations, including sending, responding, and address updating. Depending on the characteristics of different configuration information, corresponding methods can be employed through instructions sent from the CPU to improve performance.

[0060] For example, the instructions sent by the central processing unit include the aforementioned first configuration instruction, thereby causing the central processing unit to instruct the coprocessor to send the configuration information to the on-chip network by sending the first configuration instruction to the coprocessor, and then the on-chip network to send the configuration information to the broadcast module, and the broadcast module to broadcast the configuration information to multiple graphics processors through multiple broadcast channels.

[0061] In some embodiments, the first configuration instruction may further include identification information of the configuration channel and identification information of the configuration information, so that the coprocessor can determine the target configuration channel for which the configuration information to be sent is cached from multiple configuration channels based on the identification information of the configuration channel, and determine the configuration information to be sent from multiple configuration information cached in the target configuration channel based on the identification information of the configuration information.

[0062] The identification information of the configuration channel may include the configuration channel number, and the identification information of the configuration information may include the configuration information number.

[0063] In some embodiments, the instructions sent by the central processing unit may further include a second configuration instruction. Correspondingly, the coprocessor is further configured to receive the second configuration instruction sent by the central processing unit, the second configuration instruction including identification information of the graphics processor receiving configuration information. Subsequently, the coprocessor converts the identification information of the graphics processor to which the configuration information is to be received into transmission address information for the configuration information.

[0064] The identification information of the graphics processor may include the graphics processor's serial number. The transfer address information may include the field segment information of the register corresponding to the graphics processor.

[0065] For example, the coprocessor may include an address translation subunit, which may store the identification information of the graphics processor and the transport address information of the graphics processor. Accordingly, when the coprocessor receives the second configuration instruction sent by the central processing unit, it can map the corresponding transport address information through the identification information of the graphics processor in the second configuration instruction, thereby determining the transport address information to which the configuration information should be sent.

[0066] For example, if a multi-core graphics processing unit (GPU) includes two cores, and each core includes four GPUs, then there can be eight GPUs numbered 0-7. Correspondingly, the coprocessor can store the register segment information corresponding to GPUs 0-7. When the second configuration instruction includes the number of GPU 0, the register segment information corresponding to GPU 0 can be directly mapped as the transmission address information for the configuration information.

[0067] In some embodiments, if the identification information of the graphics processor in the second configuration instruction does not belong to the chip in which the configuration structure of the graphics processor is located, the transmission address information of the configuration information can be mapped to the domain segment corresponding to cross-chip transmission in the on-chip network.

[0068] In this application, by converting the identification information of the graphics processor into the transmission address information of the configuration information, the central processing unit does not need to distinguish the specific distribution of the graphics processor, and can quickly and easily indicate the transmission address of the configuration information.

[0069] In this embodiment, the coprocessor unit enables support for various configuration instructions of the central processing unit, making the configuration of multi-core graphics processors more flexible and allowing performance optimization for different configuration characteristics. Simultaneously, the graphics processor configuration structure provided in this embodiment also supports multi-core design. The coprocessor automatically converts the identification information of the graphics processor in the core into transmission address information, and then performs broadcast configuration and forwarding of cross-core configurations based on the transmission address information.

[0070] The following section explains on-chip networks.

[0071] In some embodiments, the on-chip network can identify the received configuration information and determine whether the configuration information is a broadcast configuration. If the configuration information is a broadcast configuration, the configuration information is sent to the broadcast module.

[0072] It should be understood that the embodiments of this application do not limit how to determine whether the configuration information is a broadcast configuration. In some embodiments, the on-chip network can read the header control field of the configuration data packet and determine whether the configuration information is a broadcast configuration by the value of the broadcast flag bit in the header control field. For example, when the broadcast flag bit in the header control field is 0, the on-chip network can determine that the configuration information is not a broadcast configuration (unicast configuration); when the broadcast flag bit in the header control field is 1, the on-chip network can determine that the configuration information is a broadcast configuration.

[0073] In this embodiment of the application, when the configuration information is a broadcast configuration, the configuration information can be routed to the broadcast module by the on-chip network. Due to the single-interface concurrency capability of the broadcast module, for example, it is increased to 1024, so that in a quad-core scenario, each graphics processor can also be configured using a concurrency of 256.

[0074] In other embodiments, when the configuration information is unicast, the on-chip network can send the configuration information to the target graphics processor through the AXI interface corresponding to the target graphics processor, where the target graphics processor is the graphics processor corresponding to the transmission address information of the configuration information.

[0075] For example, the on-chip network includes multiple AXI interfaces, each connected to a graphics processor (GPU). The AXI interface is used to send configuration information output from the GPU's configuration structure to the GPU connected to that AXI interface. That is, when the configuration information is unicast, the on-chip network can directly determine the target GPU to which the configuration information is to be transmitted through the transmission address information of the configuration information, and then use the AXI interface corresponding to the target GPU to send the configuration information to the target GPU.

[0076] It should be understood that the transmission address information of the above configuration information can be read by the on-chip network from the configuration channel corresponding to the coprocessor, or the configuration information sent by the coprocessor to the on-chip network can also include the transmission address information of the configuration information. This application embodiment does not limit this.

[0077] The target graphics processor can be a graphics processor in a first chip or a graphics processor in a second chip. The first chip is the chip containing the configuration structure of the graphics processor, and the second chip is another chip besides the first chip. That is, when the configuration information is a unicast configuration, it can be sent directly to the graphics processor in this chip through the AXI interface in the on-chip network, or it can be transmitted across chips to the graphics processors in other chips through the AXI interface in the on-chip network.

[0078] In this embodiment, the on-chip network instantiates a corresponding number of AXI interfaces based on the number of graphics processors, so that each graphics processor can have a corresponding AXI interface, which can be configured with the maximum theoretical bandwidth of the AXI interface and will not decrease as the number of cores increases.

[0079] The configuration structure of the graphics processor provided in this application embodiment can improve the overall and individual graphics processor configuration concurrency capabilities through the on-chip network described above.

[0080] The broadcast module will be explained below.

[0081] In some embodiments, when the configuration information is broadcast, the on-chip network can send the configuration information to the broadcast module. Subsequently, the broadcast module can interleave the configuration information and send it to multiple graphics processors through multiple broadcast channels.

[0082] The graphics processor includes either a graphics processor in a first chip or a graphics processor in a second chip, wherein the first chip is the chip in which the configuration structure of the graphics processor is located, and the second chip is another chip besides the first chip.

[0083] For example, the broadcast module may include multiple broadcast channels, each of which can be used to send configuration information to the graphics processor. This application embodiment does not limit the number of broadcast channels in the broadcast module; for example, the number of broadcast channels in the broadcast module may be the same as the number of configuration channels in the coprocessor, both being 32.

[0084] Interleaved transmission is a method in which the broadcast channel inserts and transmits configuration information cached by different configuration channels during idle transmission gaps.

[0085] It should be understood that the configuration information among the 32 broadcast channels in this embodiment can be interleaved for transmission, thereby improving bandwidth utilization. That is, the 32 broadcast channels and the 32 configuration channels are not in one-to-one correspondence; configuration information in any configuration channel can be sent to multiple graphics processors through the 32 broadcast channels.

[0086] For example, after arbitration, the configuration information cached in configuration channel 1 will occupy broadcast channel 1 for transmission. If there is an idle transmission gap (bubble) between multiple configuration information in configuration channel 1, broadcast channel 1 can insert and send configuration information cached in other configuration channels such as configuration channel 2 and configuration channel 3 during the idle transmission gap.

[0087] Once a channel wins arbitration, its configurations will occupy the broadcast channel indefinitely. However, if there are gaps between its multiple configurations, it will cause a loss of bus bandwidth utilization. This solution aims to allow other channels to insert into the transmission gaps, thereby improving bus bandwidth utilization.

[0088] For example, to achieve interleaved transmission, the coprocessor can pass-through sideband signals from the configuration information to the broadcast module. These sideband signals indicate the configuration channel in the coprocessor's cache where the configuration information resides. The broadcast module then determines the graphics processor to receive the configuration information based on the configuration channel indicated by the sideband signals and the mapping relationship between the configuration channel and the transmission address information.

[0089] For example, the mapping relationship between configuration channels and transmission address information may include transmission address information corresponding to configuration channel 0 including graphics processors 0 to 2, and transmission address information corresponding to configuration channel 1 including graphics processors 3 to 5. Accordingly, after the configuration information corresponding to configuration channel 0 is sent to the broadcast module, the broadcast module can obtain the sideband signal, and then use the sideband signal to determine the configuration channel 0 corresponding to the received configuration information, thereby using the mapping relationship to determine that the configuration information is to be sent to graphics processors 0 to 2.

[0090] In some embodiments, the broadcast module is further configured to broadcast configuration information to the graphics processor receiving the configuration information via an AXI interface connected to the graphics processor receiving the configuration information in the on-chip network.

[0091] For example, after the broadcast module determines the multiple graphics processors to which the configuration information is to be sent, it can interleave the configuration information and send it to the corresponding AXI interfaces of the multiple graphics processors through multiple broadcast channels, thereby inputting the configuration information to the multiple graphics processors through the AXI interfaces.

[0092] In other embodiments, the broadcast module can also transmit configuration information across cores.

[0093] The graphics processor configuration structure provided in this application embodiment can improve the overall bandwidth through the aforementioned broadcast module, and the multi-broadcast channel and multi-channel interleaving configuration in the broadcast module can improve bandwidth utilization.

[0094] The graphics processor (GPU) configuration structure provided in this application includes a coprocessor, an on-chip network (CNB), and a broadcast module. The coprocessor receives a first configuration instruction from the central processing unit (CPU) and, in response to the first configuration instruction, sends configuration information to the CNB. The first configuration instruction instructs the sending of configuration information to the GPU, which configures the GPU's hardware resources during runtime. The CNB, connected to the coprocessor, sends the configuration information to the broadcast module when the configuration information is of broadcast configuration type. The broadcast module, connected to the CNB, includes multiple broadcast channels for broadcasting the configuration information to multiple GPUs. Because the configuration information is broadcast to multiple GPUs through the multiple broadcast channels of the broadcast module when it is broadcast configuration, the broadcast configuration does not consume a large amount of concurrent connections, thereby improving the GPU's configuration concurrency capability.

[0095] Figure 3 This is a flowchart illustrating a method for configuring a graphics processor according to an embodiment of this application, applied to... Figure 2 The configuration structure of the graphics processor in the image is illustrated using S201 to S202 as an example. Wherein:

[0096] S201. Receive a first configuration instruction sent by the central processing unit, wherein the first configuration instruction is used to instruct the image processor to send configuration information, and the configuration information is used to configure the hardware resources of the image processor during operation.

[0097] In one embodiment, a second configuration instruction sent by the central processing unit can also be received, the second configuration instruction including the identification information of the graphics processor to which the configuration information is to be received; subsequently, the identification information of the graphics processor to which the configuration information is to be received is converted into the transmission address information of the configuration information.

[0098] In one embodiment, the graphics processor includes a graphics processor in a first chip or a graphics processor in a second chip;

[0099] The first core is the core containing the configuration structure of the graphics processor, and the second core is any other core besides the first core.

[0100] S202. If the configuration information type is broadcast configuration, send the configuration information to the broadcast module.

[0101] The broadcast module includes multiple broadcast channels, which are used to interleave configuration information to multiple graphics processors. Interleaving is a method in which the broadcast channels insert and send the configuration information cached by different configuration channels during idle transmission gaps.

[0102] In one embodiment, the configuration information includes a sideband signal, which is used to indicate the configuration channel in which the configuration information is located in the coprocessor cache;

[0103] The method also includes: determining the graphics processor to receive the configuration information based on the configuration channel where the configuration information indicated by the sideband signal is located in the coprocessor cache, and the mapping relationship between the configuration channel and the transmission address information.

[0104] In one embodiment, when the configuration information is of unicast type, the configuration information is sent to the target graphics processor through the AXI interface corresponding to the target graphics processor, where the target graphics processor is the graphics processor corresponding to the transmission address information of the configuration information.

[0105] In one embodiment, the broadcast module is further configured to broadcast configuration information to multiple graphics processors via a broadcast channel.

[0106] The graphics processor configuration method provided in this application embodiment receives a first configuration instruction sent by a central processing unit (CPU). The first configuration instruction instructs the sending of configuration information to the graphics processor, which is used to configure the hardware resources of the graphics processor during runtime. When the configuration information is of the broadcast configuration type, the configuration information is sent to a broadcast module. The broadcast module includes multiple broadcast channels for broadcasting the configuration information to multiple graphics processors via these channels. Because the configuration information is broadcast to multiple graphics processors via multiple broadcast channels in the case of broadcast configuration, the broadcast configuration does not consume a large amount of concurrent connections, thereby improving the configuration concurrency capability of the graphics processor.

[0107] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0108] Based on the same inventive concept, this application also provides a configuration structure for a graphics processor to implement the above-described configuration method. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations of one or more graphics processor configuration structure embodiments provided below can be found in the limitations of the graphics processor configuration method described above, and will not be repeated here.

[0109] In one exemplary embodiment, such as Figure 4 As shown, a graphics processor configuration device 300 is provided, including: an instruction receiving module 301 and a transmission module 302, wherein:

[0110] The instruction receiving module 301 is used to receive a first configuration instruction sent by the central processing unit, wherein the first configuration instruction is used to instruct the image processor to send configuration information, and the configuration information is used to configure the hardware resources of the image processor during operation.

[0111] The transmission module 302 is used to send the configuration information to the broadcast module when the configuration information type is broadcast configuration. The broadcast module includes multiple broadcast channels and is used to broadcast the configuration information to multiple graphics processors through the broadcast channels.

[0112] In one embodiment, the instruction receiving module 301 is used to receive a second configuration instruction sent by the central processing unit, the second configuration instruction including the identification information of the graphics processor to which configuration information is to be received; and to convert the identification information of the graphics processor to which configuration information is to be received into the transmission address information of the configuration information.

[0113] In one embodiment, the graphics processor includes a graphics processor in a first chip or a graphics processor in a second chip;

[0114] The first core is the core containing the configuration structure of the graphics processor, and the second core is any other core besides the first core.

[0115] In one embodiment, the configuration information includes a sideband signal, which is used to indicate the configuration channel in which the configuration information is located in the coprocessor cache;

[0116] The transmission module 302 is also used to determine the graphics processor to receive the configuration information based on the configuration information indicated by the sideband signal in the configuration channel where the coprocessor cache is located, and the mapping relationship between the configuration channel and the transmission address information.

[0117] In one embodiment, the transmission module 302 is further configured to send the configuration information to the target graphics processor through the AXI interface corresponding to the target graphics processor when the type of the configuration information is unicast configuration, wherein the target graphics processor is the graphics processor corresponding to the transmission address information of the configuration information.

[0118] In one embodiment, the broadcast module is further configured to interleave configuration information to multiple graphics processors via a broadcast channel. Interleaving refers to a method in which the broadcast channel inserts and transmits configuration information cached by different configuration channels during idle transmission gaps.

[0119] The modules in the above-described graphics processor configuration can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0120] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 5As shown, the computer device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage medium. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When executed by the processor, the computer program implements a configuration method for a graphics processor.

[0121] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0122] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described configuration method of a graphics processor.

[0123] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the above-described configuration method for a graphics processor.

[0124] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described configuration method for a graphics processor.

[0125] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0126] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0127] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0128] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A configuration structure of a graphics processor, characterized by, The configuration structure of the graphics processor includes a coprocessor, an on-chip network, and a broadcast module; The coprocessor is configured to receive a first configuration instruction sent by the central processing unit; and in response to the first configuration instruction, send configuration information to the on-chip network; wherein the first configuration instruction is configured to instruct the image processor to send configuration information, and the configuration information is configured to configure the hardware resources of the image processor during operation; The on-chip network, connected to the coprocessor, is used to send the configuration information to the broadcast module when the type of the configuration information is broadcast configuration; The broadcast module is connected to the on-chip network; the broadcast module includes multiple broadcast channels for broadcasting the configuration information to multiple graphics processors through the broadcast channels.

2. The configuration structure according to claim 1, characterized in that, The coprocessor includes multiple configuration channels, which are used to cache the configuration information.

3. The configuration structure according to claim 1, characterized in that, The on-chip network includes multiple Advanced Scalable AXI interfaces, each of which is connected to a graphics processor. The AXI interface is used to send the configuration information output by the configuration structure of the graphics processor to the graphics processor connected to the AXI interface.

4. The configuration structure according to claim 3, characterized in that The configuration information includes a sideband signal, which is used to indicate the configuration information in the configuration channel where the coprocessor cache is located; The broadcast module is further configured to determine the graphics processor to receive the configuration information based on the configuration information indicated by the sideband signal in the configuration channel where the coprocessor cache is located, and the mapping relationship between the configuration channel and the transmission address information.

5. The configuration structure according to claim 4, characterized in that The broadcast module is further configured to broadcast the configuration information to the graphics processor receiving the configuration information via an AXI interface connected to the graphics processor receiving the configuration information in the on-chip network.

6. The configuration structure according to claim 3, characterized in that, The on-chip network is further configured to send the configuration information to the target graphics processor through the AXI interface corresponding to the target graphics processor when the type of the configuration information is unicast configuration, wherein the target graphics processor is the graphics processor corresponding to the transmission address information of the configuration information.

7. The configuration structure according to claim 1, characterized in that, The broadcast module is also used to interleave the configuration information to multiple graphics processors through the broadcast channel. The interleaving transmission is a method in which the broadcast channel inserts and transmits the configuration information cached by different configuration channels during idle transmission gaps.

8. The configuration structure according to claim 1, characterized in that, The coprocessor is further configured to receive a second configuration instruction sent by the central processing unit, the second configuration instruction including identification information of the graphics processor to which the configuration information is to be received; and to convert the identification information of the graphics processor to which the configuration information is to be received into transmission address information of the configuration information.

9. The configuration structure according to claim 1, characterized in that, The graphics processor includes a graphics processor in a first chip or a graphics processor in a second chip; Wherein, the first core is the core in which the configuration structure of the graphics processor is located, and the second core is another core besides the first core.

10. A method for configuring a graphics processor, characterized in that, The method includes: The system receives a first configuration instruction sent by the central processing unit, wherein the first configuration instruction is used to instruct the image processor to send configuration information, the configuration information being used to configure the hardware resources of the image processor during operation; When the configuration information is of type broadcast configuration, the configuration information is sent to the broadcast module, which includes multiple broadcast channels for broadcasting the configuration information to multiple graphics processors through the broadcast channels.

11. A configuration device for a graphics processor, characterized in that, The device includes: The instruction receiving module is used to receive a first configuration instruction sent by the central processing unit, wherein the first configuration instruction is used to instruct the image processor to send configuration information, and the configuration information is used to configure the hardware resources of the image processor during operation; A transmission module is used to send the configuration information to a broadcast module when the type of the configuration information is broadcast configuration. The broadcast module includes multiple broadcast channels for broadcasting the configuration information to multiple graphics processors through the broadcast channels.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 10.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 10.

14. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 10.

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