Voltage discharge circuits and display driver chips suitable for positive and negative voltage output VCOM

Abstract

This application provides a voltage discharge circuit and display driver chip suitable for positive and negative voltage output VCOM. The voltage discharge circuit includes: a discharge unit connected between the VCOM output terminal and a reference ground, used to discharge the positive or negative voltage of the VCOM output terminal to the reference ground in discharge mode; and a control unit connected to the control terminal of the discharge unit, used to adaptively generate a gate control voltage according to the voltage polarity of the VCOM output terminal in discharge mode to control the discharge unit to conduct. The discharge unit is in a turned-off state during normal operation and conducts in response to the gate control voltage in discharge mode, achieving adaptive discharge of positive or negative voltage. The voltage discharge circuit of this application is low in cost, can quickly and safely discharge output voltage, protect device safety, and can be widely used in various liquid crystal display driver chips, possessing high industrial practical value.

Description

Technical Field

[0001] This application relates to the field of liquid crystal display driving technology, specifically to a voltage discharge circuit and display driver chip suitable for positive and negative voltage output VCOM. Background Technology

[0002] The VCOM (Common Electrode Voltage) circuit is widely used in liquid crystal display technology to provide a reference voltage for the LCD panel, determining the brightness of each pixel. Depending on the requirements of the display panel, the output voltage of the VCOM may be positive or negative.

[0003] When the VCOM circuit is off or disabled, residual charge accumulates on the output pins. If not discharged promptly, residual positive voltage may cause inaccurate pixel charging upon the next power-on, while residual negative voltage may cause latch-up or damage the driver IC. Therefore, it is necessary to quickly and safely discharge the output voltage when the VCOM is turned off.

[0004] In existing technologies, the bleeder circuits for positive voltage output and negative voltage output are usually designed separately. When it is necessary to support both positive and negative voltage outputs simultaneously, two independent bleeder circuits are often required, leading to increased chip area, more complex control logic, and higher costs. In addition, existing solutions lack a simple circuit structure that can adaptively adjust the bleeder path according to the polarity of the output voltage.

[0005] Therefore, there is an urgent need for a VCOM voltage discharge circuit that can adaptively output positive and negative voltages to simplify the circuit structure, reduce costs, and improve reliability.

[0006] The foregoing statements are for informational purposes only and are not intended to provide background information in connection with this application. Unless otherwise stated herein, the content described in this section is not prior art to the rest of this application. Summary of the Invention

[0007] The present invention aims to solve the problem that the existing VCOM circuit requires two independent discharge circuits when outputting positive and negative voltages. It provides a voltage discharge circuit and display driver chip that can adapt to positive and negative voltage outputs. When the VCOM is turned off, it automatically conducts the discharge path according to the polarity of the output voltage to discharge the residual voltage to ground.

[0008] According to a first aspect of the embodiments of this application, a voltage discharge circuit suitable for positive and negative voltage output VCOM is provided, comprising:

[0009] The bleed unit is connected between the VCOM output terminal and the reference ground, and is used to bleed the positive or negative pressure of the VCOM output terminal to the reference ground in bleed mode;

[0010] The control unit, connected to the control terminal of the bleeder unit, is used to adaptively generate a gate control voltage according to the voltage polarity of the VCOM output terminal in bleeder mode to control the bleeder unit to conduct.

[0011] The discharge unit is in the off state during normal operation, and turns on in response to the gate control voltage in discharge mode to achieve adaptive discharge of positive or negative voltage.

[0012] In some embodiments of this application, the discharge unit includes a first discharge NMOS transistor M1 and a second discharge NMOS transistor M2;

[0013] The drain of the first bleeder NMOS transistor M1 is connected to the VCOM output terminal; the drain of the second bleeder NMOS transistor M2 is connected to the reference ground.

[0014] The source of the first bleeder NMOS transistor M1 is connected to the source of the second bleeder NMOS transistor M2 to form a common node OUT_DIS; the gate of the first bleeder NMOS transistor M1 and the gate of the second bleeder NMOS transistor M2 are connected together to form the control terminal of the bleeder unit, which receives the gate control voltage.

[0015] In some embodiments of this application, the control unit includes a polarity detection terminal, a gate voltage control unit, and a gate control voltage output terminal:

[0016] The gate voltage control unit is connected to the common node OUT_DIS formed by the first discharge NMOS transistor M1 and the second discharge NMOS transistor M2 in the discharge unit through the polarity detection terminal;

[0017] When the VCOM output is positive, the gate control unit raises the gate control voltage to the first potential; when the VCOM output is negative, the gate control voltage raises the gate control voltage to the second potential.

[0018] The gate voltage control unit is connected to the control terminal VGATE of the bleeder unit through the gate control voltage output terminal to ensure that the bleeder unit is turned on.

[0019] In some embodiments of this application, the gate voltage control unit includes an input positive voltage, a current mirror structure, and a voltage divider resistor network; specifically:

[0020] The input positive voltage VIN is connected to one end of the second resistor, and the other end of the second resistor is connected to the source of the first switching NMOS transistor P1; the gate of the first switching NMOS transistor P1 is connected to the enable signal, and the drain of the first switching NMOS transistor P1 is connected to the gate of the first current mirror NMOS transistor N1, the gate and drain of the second current mirror NMOS transistor N2, and the connection node forms the gate control voltage output terminal.

[0021] The drain of the first current mirror NMOS transistor N1 is connected to one end of the first resistor, and the other end of the first resistor is grounded; the source of the first current mirror NMOS transistor N1 is connected to the first end of the third resistor, and the other end of the third resistor is connected to the common node OUT_DIS of the bleeder unit.

[0022] The source of the second current mirror NMOS transistor N2 is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the drain of the fourth NMOS transistor N4; the source of the fourth NMOS transistor N4 is grounded, and the gate of the fourth NMOS transistor N4 is connected to the first end of the third resistor.

[0023] In some embodiments of this application, the gate voltage control unit further includes:

[0024] The voltage regulator capacitor C1 is connected between the control terminal VGATE of the discharge unit and the common node OUT_DIS;

[0025] Clamping diode D1 has its anode connected to the common node OUT_DIS and its cathode connected to the control terminal VGATE.

[0026] In some embodiments of this application, when in the discharge mode and the VCOM output is positive, the first switching NMOS transistor P1 is turned on, raising the gate control voltage output to the input positive voltage VIN; thereby causing the gate-source voltages of the first discharge NMOS transistor M1 and the second discharge NMOS transistor M2 to be greater than their respective threshold voltages, turning on the discharge unit, and discharging the VCOM output to the reference ground through the first discharge NMOS transistor M1 and the second discharge NMOS transistor M2.

[0027] In some embodiments of this application, when in the discharge mode and the VCOM output is negative, the second resistor R2 generates a voltage difference and current. The first current mirror NMOS transistor N1 and the second current mirror NMOS transistor N2 form a current mirror structure, generating a voltage drop across the third resistor R3 and the fourth resistor R4, causing the fourth NMOS transistor N4 to conduct.

[0028] This raises the gate control voltage output to a second potential higher than the common node OUT_DIS. The gate-source voltages of the first bleeder NMOS transistor M1 and the second bleeder NMOS transistor M2 are both greater than their respective threshold voltages, causing the bleeder unit to conduct. The VCOM output is then bleed to the reference ground through the first bleeder NMOS transistor M1 and the second bleeder NMOS transistor M2.

[0029] In some embodiments of this application, the circuit further includes an enabling unit;

[0030] The enabling unit connects to the control unit and the discharge unit;

[0031] The enable unit is used to receive external enable signals, forcibly shut down the discharge unit during normal operation and when the discharge mode is off; and enable the control unit to turn on to conduct the discharge unit when the discharge mode is on.

[0032] In some embodiments of this application, the enabling unit includes a second switching NMOS transistor P2, which is used to receive an enabling signal and ensure that the bleedering unit is completely turned off when the bleedering mode is off.

[0033] According to a second aspect of the embodiments of this application, a display driver chip is provided, which integrates the voltage discharge circuit of any of the above claims.

[0034] This application discloses a voltage discharge circuit and display driver chip suitable for positive and negative voltage output VCOM. The voltage discharge circuit includes: a discharge unit connected between the VCOM output terminal and a reference ground, used to discharge the positive or negative voltage of the VCOM output terminal to the reference ground in discharge mode; and a control unit connected to the control terminal of the discharge unit, used to adaptively generate a gate control voltage according to the voltage polarity of the VCOM output terminal in discharge mode to control the discharge unit to conduct; wherein, the discharge unit is in the off state during normal operation, and conducts in response to the gate control voltage in discharge mode to achieve adaptive discharge of positive or negative voltage.

[0035] In other aspects, two NMOS transistors are connected in a source-to-source structure to form a bleeder unit with an intermediate voltage of OUT_DIS, achieving adaptive bleedering under both positive and negative voltages. The control unit dynamically generates the gate control voltage based on the output voltage polarity, ensuring that the bleeder MOS transistor can conduct under both positive and negative voltages. The enable unit completely shuts off the bleedering path in the non-bleedering state to prevent leakage. When bleedering is required, it does not affect the operation of the control unit. Furthermore, a current mirror, resistor voltage divider, capacitor voltage regulator, and clamping diode are incorporated to achieve stable gate voltage control and MOS transistor protection.

[0036] The voltage discharge circuit of this application is low-cost and suitable for integrated design; it can quickly and safely discharge the output voltage when the power is off or VCOM is disabled, protecting the device. Through the enable unit and voltage regulation design, it avoids device damage caused by leakage and voltage surges; it can be widely used in various liquid crystal display driver chips, especially suitable for display panels that require positive and negative VCOM output, and has high industrial practical value. Attached Figure Description

[0037] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0038] Figure 1This is a schematic diagram of a voltage discharge circuit provided in an embodiment of this application;

[0039] Figure 2 A circuit structure diagram of a voltage discharge circuit provided in an embodiment of this application;

[0040] Figure 3 This is a schematic diagram of the structure of a display driver chip 400 provided in an embodiment of this application. Detailed Implementation

[0041] Regarding this application, considering that currently only discharge circuits specifically designed for positive or negative output voltages exist on the market, there is no mature and simple circuit structure that can simultaneously satisfy both positive and negative voltage discharge functions and adaptively discharge the output voltage for a complete circuit.

[0042] This application aims to solve the problem that the existing VCOM circuit requires two independent discharge circuits when outputting positive and negative voltages. It provides a voltage discharge circuit that can adapt to positive and negative voltage outputs. When the VCOM is turned off, it automatically conducts the discharge path according to the polarity of the output voltage to discharge the residual voltage to ground.

[0043] To achieve the above objectives, the present invention provides the following technical solution:

[0044] A voltage bleeder circuit suitable for positive and negative voltage output VCOM includes a bleeder unit connected between the VCOM output terminal and a reference ground, used to bleed the positive or negative voltage of the VCOM output terminal to the reference ground in bleeder mode; and a control unit connected to the control terminal of the bleeder unit, used to adaptively generate a gate control voltage according to the voltage polarity of the VCOM output terminal in bleeder mode to control the bleeder unit to conduct; wherein, the bleeder unit is in the off state during normal operation, and conducts in response to the gate control voltage in bleeder mode to achieve adaptive bleedering of positive or negative voltage.

[0045] In addition, an enable unit is provided to connect to the control unit and the discharge unit to receive external enable signals, including the discharge enable signal En_dis, the operation enable signal en, and the inverted signal enb of the discharge enable signal. During normal operation, the control node VGATE is pulled to the same potential as the common node OUT_DIS to turn off the discharge unit. In discharge mode, the control unit is enabled to turn on the discharge unit.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] Adaptive positive and negative voltage discharge: Through a pair of source-connected NMOS transistors and a control unit, the polarity of the VCOM output voltage can be automatically identified, and the discharge path can be turned on under both positive and negative voltage conditions, so that a single circuit structure can support both positive and negative voltage discharge at the same time.

[0048] The circuit structure is simple: it does not require two independent discharge circuits, and only a small number of MOSFETs, resistors and capacitors are needed, which helps to reduce chip area and cost.

[0049] Reliable shutdown: The enable unit ensures that the discharge unit is completely shut off during normal operation to avoid leakage; in discharge mode, the discharge path is quickly opened to ensure that residual voltage is discharged in a timely manner.

[0050] Comprehensive protection: The gate control voltage is stabilized by the voltage regulator capacitor C1 to prevent voltage surges; the gate-source voltage is limited by the clamping diode D1 to prevent overvoltage damage to the MOSFET and improve circuit reliability.

[0051] Clear logic control: Through the coordination of the three enable signals En_dis, en, and enb, the precise switching between normal operation mode and discharge mode is achieved, avoiding mode conflicts.

[0052] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0053] Example 1

[0054] Figure 1 The diagram shows a schematic of a voltage discharge circuit according to an embodiment of this application.

[0055] like Figure 1 As shown, an embodiment of this application provides a voltage discharge circuit suitable for positive and negative voltage output VCOM, comprising:

[0056] The venting unit 10 is connected between the VCOM output terminal and the reference ground, and is used to vent the positive or negative pressure of the VCOM output terminal to the reference ground in venting mode;

[0057] The control unit 20 is connected to the control terminal of the bleeder unit and is used to adaptively generate a gate control voltage according to the voltage polarity of the VCOM output terminal in the bleeder mode to control the bleeder unit to be turned on.

[0058] The discharge unit 10 is in the off state during normal operation, and turns on in response to the gate control voltage in discharge mode to achieve adaptive discharge of positive or negative voltage.

[0059] This enables the residual voltage to be discharged to ground automatically by following the discharge path based on the output voltage polarity when VCOM is turned off.

[0060] In another preferred embodiment, the circuit further includes an enabling unit; the enabling unit is connected to the control unit and the discharge unit.

[0061] The enable unit is used to receive external enable signals, forcibly shut down the discharge unit during normal operation and when the discharge mode is off; and enable the control unit to turn on to conduct the discharge unit when the discharge mode is on.

[0062] Figure 2 The diagram shows a circuit structure diagram of a voltage discharge circuit according to an embodiment of this application.

[0063] like Figure 2 As shown, the discharge unit 10 includes a first discharge NMOS transistor M1 and a second discharge NMOS transistor M2.

[0064] The drain of the first bleeder NMOS transistor M1 is connected to the VCOM output terminal; the drain of the second bleeder NMOS transistor M2 is connected to the reference ground; the source of the first bleeder NMOS transistor M1 and the source of the second bleeder NMOS transistor M2 are connected to form a common node OUT_DIS; the gate of the first bleeder NMOS transistor M1 and the gate of the second bleeder NMOS transistor M2 are connected together to form the control terminal of the bleeder unit, which receives the gate control voltage.

[0065] Further described, the control unit 20 includes a polarity detection terminal, a gate voltage control unit, and a gate control voltage output terminal.

[0066] The gate voltage control unit is connected to the common node OUT_DIS formed by the first discharge NMOS transistor M1 and the second discharge NMOS transistor M2 in the discharge unit via a polarity detection terminal. When the VCOM output terminal is positive, the gate voltage control unit raises the gate control voltage to a first potential; when the VCOM output terminal is negative, the gate control voltage raises the gate control voltage to a second potential. The gate voltage control unit is connected to the control terminal of the discharge unit via the gate control voltage output terminal to ensure that the discharge unit is turned on.

[0067] like Figure 2 As shown, the gate voltage control unit includes an input positive voltage VIN, a current mirror structure, and a voltage divider resistor network; specifically:

[0068] The input positive voltage VIN is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the source of the first switching NMOS transistor P1; the gate of the first switching NMOS transistor P1 is connected to the enable signal enb (i.e., the inverted signal enb of the discharge enable signal En_dis); the drain of the first switching NMOS transistor P1 is connected to the gate of the first current mirror NMOS transistor N1, the gate and drain of the second current mirror NMOS transistor N2, and the connection node forms the gate control voltage output terminal VC;

[0069] The drain of the first current mirror NMOS transistor N1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded; the source of the first current mirror NMOS transistor N1 is connected to the first end of the third resistor R3, and the other end of the third resistor R3 is connected to the common node OUT_DIS of the bleeder unit.

[0070] The source of the second current mirror NMOS transistor N2 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the drain of the fourth NMOS transistor N4; the source of the fourth NMOS transistor N4 is grounded, and the gate of the fourth NMOS transistor N4 is connected to the first end of the third resistor R3.

[0071] Furthermore, the gate voltage control unit also includes:

[0072] Zener capacitor C1 is connected between the control terminal VGATE of the bleeder unit and the common node OUT_DIS; clamping diode D1 has its anode connected to the common node OUT_DIS and its cathode connected to the control terminal VGATE.

[0073] A voltage-stabilizing capacitor is connected between the control terminal of the bleeder unit and the common node to stabilize the gate control voltage and prevent sudden changes in the gate-source voltage of the first bleeder NMOS transistor M1 and the second bleeder NMOS transistor M2.

[0074] The clamping diode is connected between the control terminal of the bleeder unit and the common node to limit the gate-source voltage of the first bleeder NMOS transistor M1 and the second bleeder NMOS transistor M2 from exceeding their withstand voltage values.

[0075] Reference Figure 2 When in bleed mode and the VCOM output is positive, the first switching NMOS transistor P1 is turned on, raising the gate control voltage output VC to the input positive voltage VIN; thus, the gate-source voltage of the first bleed NMOS transistor M1 and the second bleed NMOS transistor M2 is greater than their threshold voltage, causing the bleed unit to turn on, and the VCOM output is bleed to the reference ground through the first bleed NMOS transistor M1 and the second bleed NMOS transistor M2.

[0076] When in bleed mode and the VCOM output is negative, the second resistor R2 generates a voltage difference and current. The first current mirror NMOS transistor N1 and the second current mirror NMOS transistor N2 mirror the current detection, generating a voltage drop across the third resistor R3 and the fourth resistor R4, causing the fourth NMOS transistor N4 to conduct.

[0077] This raises the gate control voltage output terminal VC to a second potential higher than the common node OUT_DIS. The gate-source voltage of the first bleeder NMOS transistor M1 and the second bleeder NMOS transistor M2 is greater than their threshold voltage, causing the bleeder unit to be turned on. The VCOM output terminal is then bleed to the reference ground through the first bleeder NMOS transistor M1 and the second bleeder NMOS transistor M2.

[0078] The enable unit includes a second switch NMOS transistor P2, which is used to receive an enable signal and ensure that the discharge unit is completely turned off when the discharge mode is off.

[0079] Reference Figure 2 The enable unit is used to receive external enable signals En_dis, en, and enb. During normal operation, it pulls the control node VGATE to the same potential as the common node OUT_DIS to turn off the discharge unit. In discharge mode, it enables the control unit to turn on the discharge unit.

[0080] The enabling unit specifically includes: a second NMOS transistor P2, the source of which is connected to the drain of a third NMOS transistor P3, and the source of the third NMOS transistor P3 is connected to the input positive voltage VIN; the gate of the second NMOS transistor P2 receives the enable signal en (i.e., the inverted signal enb of the discharge enable signal En_dis); the drain of the second NMOS transistor P2 serves as control node V1, connected to one end of the fifth resistor R5, and the other end of the fifth resistor is connected to the common node OUT_DIS of the discharge unit; control node V1 is also connected in series with a capacitor and then connected to the common node OUT_DIS. Control node V1 is also connected to the gate of the fifth NMOS transistor P5, the drain of the fifth NMOS transistor P5 is connected to the control terminal VGATE of the discharge unit 10, and the source of the fifth NMOS transistor P5 is connected to the common node OUT_DIS.

[0081] Next, the gate of the third NMOS transistor P3 is connected to the gate of the fourth NMOS transistor P4 and then grounded; the drain of the fourth NMOS transistor P4 is also grounded, and its source is connected to the input positive voltage VIN.

[0082] Regarding the logical relationship of the enable signals, the external enable signals include the discharge enable signal En_dis, the working enable signal en, and the inverted signal enb of the discharge enable signal;

[0083] When the discharge enable signal En_dis is high, the working enable signal en is high and the inverted signal enb of the discharge enable signal is low, the control unit is working and the discharge unit is in discharge mode.

[0084] When the discharge enable signal En_dis is low, the working enable signal en is low, the inverted signal enb of the discharge enable signal is high, the control unit is turned off, and the discharge unit is in the off state.

[0085] That is, the external enable signal satisfies the following logical relationship:

[0086] In normal operating mode, the discharge enable signal En_dis is low, the operating enable signal en is low, and the inverted signal enb of the discharge enable signal is high.

[0087] In bleed mode, the bleed enable signal En_dis is high, the working enable signal en is high, and the inverted signal enb of the bleed enable signal is low.

[0088] The circuit is further explained below:

[0089] Reference Figure 1 , Figure 2 The circuit is divided into three units according to function. The discharge unit consists of two NMOS transistors, M1 and M2, which form a back-to-back common-source structure with an intermediate voltage of OUT_DIS. It is responsible for discharging the positive or negative output voltage to ground. The control unit 20 is responsible for generating the gate control voltage VC of M1 and M2 to ensure that the two NMOS transistors (M1, M2) can be switched. The enable unit is responsible for closing M1 and M2 when the discharge function is off to ensure that no leakage occurs, and for not affecting the generation of the gate voltage when the discharge function needs to be turned on.

[0090] When the circuit is operating normally, the discharge function is off, and the control unit and discharge unit are in the off state. In the external enable signals, the discharge enable signal En_dis=0 and the operation enable signal en=0. At this time, P2 is turned on, the current in the current mirror flows through R5, causing V1 to pull high, and N3's VGATE to pull high, N3 is turned on, VGATE=OUT_DIS, and the gate-source voltages of M1 and M2 are respectively at VM. GS =0, M1 and M2 do not discharge the output voltage.

[0091] When the circuit is off, En_dis=1, en=1, enb=0, P2 is off. Since no current flows into resistor R5, the voltage at point V1 will be pulled low to VOUT_DIS, and the gate-source voltage VN of N3 will also be low. GS3 =0, N3 is off. At the same time, P1 is on, and the control unit starts working.

[0092] If the output voltage VOUT is negative, then the voltage OUT_DIS between M1 and M2 is close to 0V between 0 and VOUT, which is also negative. When P1 is on, the voltage at the lower end of R2 is negative, and the voltage at the upper end is VIN, resulting in a voltage difference. Current is generated in the path containing R2. N1 and N2 form a current mirror structure, and current is also generated in the N1 path, resulting in the gate-source voltage VN of N4 across R3. GS4 At this time, the VGATE voltage is the voltage across R3 plus the gate-source voltage VN of N1. GS1 ,Right now: Therefore, the gate-source voltages of M1 and M2 M1 and M2 are connected, and VOUT is discharged to ground.

[0093] If the output voltage VOUT is positive, then the voltage OUT_DIS between M1 and M2 is close to 0V between 0 and VOUT, which is also positive. Therefore, the upper end of R3 is also positive because the drain voltage V of N1 is... DN1 =0V, the source voltage V of N1 SN1 Since the voltage is >0V, no current can be generated from the drain (D) to the source (S) (current direction is from high voltage to low voltage), so N1 cannot conduct; the gate voltage of N4 cannot be greater than the source voltage, so N4 also cannot conduct. At the same time, because the conduction of P1 will directly charge VIN with the VGATE voltage, OUT_DIS is close to 0V. The voltage difference between VGATE and OUT_DIS causes M1 and M2 to turn on, and VOUT is discharged to ground.

[0094] Capacitor C1 regulates VGATE, ensuring that the voltage across its plates does not change abruptly, thus maintaining a stable VGS for M1 and M2. Clamping diode D1 protects the gate-source voltage VM of M1 and M2. GS The voltage will not exceed the withstand voltage value, which would damage the MOSFET.

[0095] In practice, the timing relationship of the external enable signals En_dis, en, and enb is as follows:

[0096] During normal operation: En_dis = 0, en = 0, enb = 1. The circuit is in normal operating condition, and the discharge unit is turned off.

[0097] During the bleedering mode: En_dis = 1, en = 1, enb = 0. The circuit enters bleedering mode, and the control unit adaptively generates the gate voltage according to the polarity of VOUT, turning on the bleedering unit.

[0098] The three signals switch synchronously to ensure a smooth transition of the circuit between the two modes and avoid malfunctions caused by intermediate states.

[0099] Regarding the selection of component parameters, those skilled in the art can choose appropriate component parameters according to actual application requirements. The following is a set of example parameters:

[0100] Input positive voltage VIN: 3.3V;

[0101] R2: 10kΩ ~ 100kΩ (pull-up resistor);

[0102] R4: 1kΩ ~ 10kΩ (select according to detection sensitivity);

[0103] R1, R3: 10kΩ ~ 50kΩ (determines the current mirror output voltage swing);

[0104] Zener capacitor C1: 10pF ~ 100pF (stabilizes gate voltage and filters out high-frequency noise);

[0105] NMOS transistors M1 and M2: Select NMOS transistors with low on-resistance and sufficient withstand voltage to ensure discharge capability;

[0106] Current mirror NMOS transistors N1 and N2: The width-to-length ratio can be adjusted according to the required mirror ratio. They are usually set to the same size to achieve a 1:1 mirror.

[0107] This invention uses a back-to-back structure of two NMOS transistors combined with a control circuit to ensure that regardless of whether the output voltage VOUT is positive or negative, when the output voltage needs to be discharged, the voltage VGS of the two discharge MOS transistors can be kept greater than 0, thus maintaining the on state and adapting to the output voltage to perform the discharge function, ensuring the safety of the device.

[0108] The voltage bleedering circuit applicable to positive and negative voltage output VCOM using this application includes: a bleedering unit connected between the VCOM output terminal and a reference ground, used to bleed the positive or negative voltage of the VCOM output terminal to the reference ground in bleedering mode; and a control unit connected to the control terminal of the bleedering unit, used to adaptively generate a gate control voltage according to the voltage polarity of the VCOM output terminal in bleedering mode to control the bleedering unit to conduct; wherein, the bleedering unit is in the off state during normal operation, and conducts in response to the gate control voltage in bleedering mode to achieve adaptive bleedering of positive or negative voltage.

[0109] In addition, two NMOS transistors are connected in a source-to-source configuration to form a bleeder unit with an intermediate voltage of OUT_DIS, enabling adaptive bleedering under both positive and negative voltages. The control unit dynamically generates the gate control voltage based on the output voltage polarity, ensuring that the bleeder MOS transistor can conduct under both positive and negative voltages. The enable unit completely shuts off the bleedering path in the non-bleedering state to prevent leakage. When bleedering is required, it does not affect the operation of the control unit. Furthermore, a current mirror, resistor voltage divider, capacitor voltage regulator, and clamping diode are incorporated to achieve stable gate voltage control and MOS transistor protection.

[0110] The voltage discharge circuit of this application is low-cost and suitable for integrated design; it can quickly and safely discharge the output voltage when the power is off or VCOM is disabled, protecting the device. Through the enable unit and voltage regulation design, it avoids device damage caused by leakage and voltage surges; it can be widely used in various liquid crystal display driver chips, especially suitable for display panels that require positive and negative VCOM output, and has high industrial practical value.

[0111] Example 2

[0112] This application also provides a display driver chip that integrates the voltage discharge circuit of Embodiment 1. For details not disclosed in the display driver chip of this embodiment, please refer to the specific implementation of the voltage discharge circuit in other embodiments.

[0113] Figure 3 The diagram shows a schematic of the structure of a display driver chip 400 provided according to an embodiment of this application.

[0114] like Figure 3 As shown, the display driver chip 400 integrates the voltage discharge circuit of Embodiment 1.

[0115] The voltage discharge circuit of this invention can be integrated into a display driver chip as part of the VCOM output stage. During chip design, the enable signals En_dis, en, and enb can be connected to the chip's control register, allowing system software or hardware logic to control the activation and deactivation of the discharge function.

[0116] Those skilled in the art will understand that the schematic diagrams of the embodiments of this application are merely examples and do not constitute a limitation on the display driver chip 400. It may include more or fewer components than shown, or combine certain components, or different components. For example, the display driver chip 400 may also include input / output devices, network access devices, buses, etc.

[0117] If the unit integrated in the display driver chip 400 is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by instructing related hardware through computer-readable instructions. The computer-readable instructions can be stored in a computer-readable storage medium, and when executed by a processor, the computer-readable instructions can implement the steps of the various method embodiments described above.

[0118] Those skilled in the art will understand that the terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular forms “a,” “the,” and “the” as used in this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0119] It should be understood that although the terms first, second, third, etc., may be used in this invention to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first information may also be referred to as second information without departing from the scope of this invention, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0120] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0121] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A voltage discharge circuit suitable for positive and negative voltage output VCOM, characterized in that, include: A venting unit is connected between the VCOM output terminal and the reference ground, and is used to vent the positive or negative pressure of the VCOM output terminal to the reference ground in venting mode; A control unit, connected to the control terminal of the bleeder unit, is used to adaptively generate a gate control voltage according to the voltage polarity of the VCOM output terminal in bleeder mode, so as to control the bleeder unit to be turned on. The discharge unit is in the off state during normal operation, and turns on in response to the gate control voltage in discharge mode to achieve adaptive discharge of positive or negative voltage. The discharge unit includes a first discharge NMOS transistor (M1) and a second discharge NMOS transistor (M2); The drain of the first bleeder NMOS transistor (M1) is connected to the VCOM output terminal; the drain of the second bleeder NMOS transistor (M2) is connected to the reference ground; The source of the first bleeder NMOS transistor (M1) is connected to the source of the second bleeder NMOS transistor (M2) to form a common node (OUT_DIS); the gate of the first bleeder NMOS transistor (M1) and the gate of the second bleeder NMOS transistor (M2) are connected together to form the control terminal of the bleeder unit, which receives the gate control voltage; The control unit includes a polarity detection terminal, a gate voltage control unit, and a gate control voltage output terminal. The gate voltage control unit is connected to the common node (OUT_DIS) formed by connecting the first discharge NMOS transistor (M1) and the second discharge NMOS transistor (M2) in the discharge unit through the polarity detection terminal. When the VCOM output is positive, the gate control unit raises the gate control voltage to a first potential; when the VCOM output is negative, the gate control voltage raises the gate control voltage to a second potential. The gate voltage control unit is connected to the control terminal (VGATE) of the bleeder unit through the gate control voltage output terminal to ensure that the bleeder unit is turned on.

2. The voltage discharge circuit according to claim 1, characterized in that, The gate voltage control unit includes an input positive voltage, a current mirror structure, and a voltage divider resistor network; A positive input voltage (VIN) is connected to one end of a second resistor, and the other end of the second resistor is connected to the source of a first switching NMOS transistor (P1). An enable signal is connected to the gate of the first switching NMOS transistor (P1), and the drain of the first switching NMOS transistor (P1) is connected to the gate of the first current mirror NMOS transistor (N1), the gate of the second current mirror NMOS transistor (N2), and the connection node forms the gate control voltage output terminal. The drain of the first current mirror NMOS transistor (N1) is connected to one end of the first resistor, and the other end of the first resistor is grounded; the source of the first current mirror NMOS transistor (N1) is connected to the first end of the third resistor, and the other end of the third resistor is connected to the common node (OUT_DIS) of the discharge unit. The source of the second current mirror NMOS transistor (N2) is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the drain of the fourth NMOS transistor (N4); the source of the fourth NMOS transistor (N4) is grounded, and the gate of the fourth NMOS transistor (N4) is connected to the first end of the third resistor.

3. The voltage discharge circuit according to claim 2, characterized in that, The gate voltage control unit further includes: A voltage regulator capacitor (C1) is connected between the control terminal (VGATE) of the discharge unit and the common node (OUT_DIS); The clamping diode (D1) has its anode connected to the common node (OUT_DIS) and its cathode connected to the control terminal (VGATE).

4. The voltage discharge circuit according to claim 2, characterized in that, When in bleed mode and the VCOM output is positive, the first switching NMOS transistor (P1) is turned on, raising the gate control voltage output to the input positive voltage (VIN); thus, the gate-source voltages of the first bleed NMOS transistor (M1) and the second bleed NMOS transistor (M2) are both greater than their respective threshold voltages, turning on the bleed unit, and the VCOM output is bleed to the reference ground through the first bleed NMOS transistor (M1) and the second bleed NMOS transistor (M2).

5. The voltage discharge circuit according to claim 2, characterized in that, When in the discharge mode and the VCOM output is negative, the second resistor (R2) generates a voltage difference and current. The first current mirror NMOS transistor (N1) and the second current mirror NMOS transistor (N2) form a current mirror structure, generating a voltage drop across the third resistor (R3) and the fourth resistor (R4), which turns on the fourth NMOS transistor (N4). The gate control voltage output terminal is raised to a second potential higher than the common node (OUT_DIS). The gate-source voltages of the first bleeder NMOS transistor (M1) and the second bleeder NMOS transistor (M2) are both greater than their respective threshold voltages, so that the bleeder unit is turned on. The VCOM output terminal is bleed to the reference ground through the first bleeder NMOS transistor (M1) and the second bleeder NMOS transistor (M2).

6. The voltage discharge circuit according to claim 1, characterized in that, It also includes an enabling unit; The enabling unit is connected to the control unit and the discharge unit; The enabling unit is used to receive an external enabling signal and to forcibly shut down the bleeding unit when the bleeding mode is off, and to enable the control unit when the bleeding mode is on.

7. The voltage discharge circuit according to claim 6, characterized in that, The enabling unit includes a second switching NMOS transistor (P2), which is used to receive an enabling signal and ensure that the bleedering unit is completely turned off when the bleedering mode is off.

8. A display driver chip, characterized in that, It integrates the voltage discharge circuit according to any one of claims 1 to 7.

Images