FPGA-based programmable periodic pulse signal generation method and application thereof

By employing a three-tiered cascaded architecture of LUT coarse delay, coarse CARRY8 medium delay, and fine CARRY8 fine delay, along with an initial phase parameter pre-biasing algorithm, the problem of generating periodic pulse signals with large dynamic range and picosecond-level high resolution, which is difficult to achieve in existing technologies, is solved. This achieves a balance between high resolution and large dynamic range, supports independent configuration of multiple channels and extremely low jitter, and is suitable for high-precision testing and measurement.

CN121957280BActive Publication Date: 2026-07-07HANGZHOU CORE MOMENT TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
HANGZHOU CORE MOMENT TECH CO LTD
Filing Date
2026-04-01
Publication Date
2026-07-07

AI Technical Summary

Technical Problem

Existing technologies struggle to generate periodic pulse signals with a large dynamic range and picosecond-level high resolution without relying on scarce hard core resources (such as PLLs). Furthermore, additional hardware resources are required for phase compensation during multi-channel synchronization.

Method used

A three-stage cascaded architecture of LUT coarse delay + coarse CARRY8 medium delay + fine CARRY8 fine delay is adopted, combined with the initial phase parameter (M1/S1) pre-bias algorithm, to achieve full-cycle coverage and multi-channel phase alignment with picosecond accuracy.

Benefits of technology

It achieves a balance between high resolution and large dynamic range, reduces system complexity, supports independent configuration of multiple channels, and has extremely low jitter characteristics, making it suitable for high-precision testing and measurement.

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Abstract

The application provides a programmable period pulse signal generation method based on FPGA and application thereof, and belongs to the technical field of electronic measurement. In view of the problems that the prior art is difficult to balance a large dynamic range and high resolution, and a plurality of channel synchronization consumes hardware resources, the method utilizes FPGA system clock counting to realize coarse delay, and utilizes a residual decimal part to accumulate and calculate pulse parameters in the next time; a three-stage cascade architecture composed of a lookup table, a coarse carry chain and a fine carry chain is constructed to realize fine delay in picoseconds; rising edges and falling edges are independently generated and then are XORed to synthesize a waveform. In addition, transmission delay differences among channels are compensated by modifying initial calculation parameters. The application can realize generation of a plurality of channel pulse signals with high precision, low jitter and strictly aligned phases by only utilizing pure logic resources of FPGA.
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Citation Information

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