Single-chip based multi-service requirement adaptation method and device, equipment and medium

Abstract

A single-chip-based multi-service requirement adaptation method, device, equipment and medium. The method comprises: dividing a plurality of processing cores in a system-level chip into at least one processing domain based on service requirements; configuring memory access permissions for each processing domain to realize memory access isolation between different processing domains; configuring hardware resource access permissions for each processing domain to realize hardware resource access isolation between different processing domains; if a plurality of processing domains are obtained by division, a domain-to-domain cache consistency maintenance mechanism is configured; if one processing domain is obtained by division, an intra-domain cache consistency maintenance mechanism is configured; wherein the plurality of processing cores are connected through a consistent interconnection network; and the processing cores in the target processing domain are configured to a lockstep running mode according to the functional safety level requirement corresponding to the service requirement. Through the present application, the cost and time for developing special-purpose chips for different scenarios are reduced, and the reuse of hardware resources and the improvement of research and development efficiency are realized.

Description

Technical Field

[0001] This application relates to the field of chip design technology, specifically to a method, apparatus, device, and computer-readable storage medium for adapting to multiple service requirements based on a single chip. Background Technology

[0002] In existing technologies, dedicated chips are typically designed to meet the needs of different business scenarios (such as smart cockpits and autonomous driving). These dedicated chips usually employ fixed SMP (Symmetric Multiprocessing) or AMP (Asymmetric Multiprocessing) architectures, which lack flexibility and versatility. Developing multiple dedicated chips to meet the needs of different scenarios leads to long development cycles, high costs, and wasted resources. Therefore, a technical solution that can flexibly adapt to multiple scenarios based on a single chip is needed. Summary of the Invention

[0003] This application provides a method, apparatus, device, and computer-readable storage medium for adapting to multiple service requirements based on a single chip, which can solve the technical problem in the prior art of designing dedicated chips to meet the needs of different service scenarios.

[0004] In a first aspect, embodiments of this application provide a method for adapting to multiple service requirements based on a single chip, the method comprising:

[0005] Based on business requirements, the multiple processing cores in the system-on-a-chip are divided into at least one processing domain.

[0006] Configure memory access permissions for each processing domain to achieve memory access isolation between different processing domains;

[0007] Configure hardware resource access permissions for each processing domain to achieve hardware resource access isolation between different processing domains;

[0008] If multiple processing domains are obtained, an inter-domain cache consistency maintenance mechanism is configured; if only one processing domain is obtained, an intra-domain cache consistency maintenance mechanism is configured; wherein, the multiple processing cores are connected through a consistency interconnection network.

[0009] Based on the functional safety level requirements corresponding to business needs, the processing core within the target processing domain is configured to lockstep operation mode.

[0010] In conjunction with the first aspect, in one implementation, the inter-domain cache consistency maintenance mechanism includes:

[0011] The cache controller maintains directory information, which is used to record the existence status of each cached data in the shared cache in the exclusive cache of each processing core;

[0012] When any processing core triggers an operation instruction on the target cached data, it queries the directory information to determine the target processing core in the exclusive cache where the target cached data exists.

[0013] Based on the domain identifier of the processing domain to which the target processing core belongs and the core identifier of the target processing core, the operation instructions are sent to the target processing core.

[0014] In conjunction with the first aspect, in one implementation, the intra-domain cache consistency maintenance mechanism includes:

[0015] The cache controller maintains directory information, which is used to record the existence status of each cached data in the shared cache in the exclusive cache of each processing core;

[0016] When any processing core triggers an operation instruction on the target cached data, it queries the directory information to determine the target processing core in the exclusive cache where the target cached data exists.

[0017] Based on the core identifier of the target processing core, the operation instructions are sent to the target processing core.

[0018] In conjunction with the first aspect, in one implementation, configuring the processing core within the target processing domain to lockstep operation mode includes:

[0019] The lockstep operation mode of the core is started by configuring the board-level external pins of the system-on-a-chip;

[0020] The lockstep operation mode of the non-booting core can be configured through the hardware security module integrated within the system-on-a-chip.

[0021] In conjunction with the first aspect, in one implementation, configuring hardware resource access permissions for each processing domain includes:

[0022] Assign a unique domain identifier and associated hardware resources to each processing domain;

[0023] Configure access control rules based on domain identifiers for each processing domain.

[0024] Secondly, embodiments of this application provide a multi-service requirement adaptation device based on a single chip, the multi-service requirement adaptation device based on a single chip includes:

[0025] The partitioning module is used to divide multiple processing cores in a system-on-a-chip into at least one processing domain based on business requirements.

[0026] The first configuration module is used to configure memory access permissions for each processing domain in order to achieve memory access isolation between different processing domains;

[0027] The second configuration module is used to configure hardware resource access permissions for each processing domain in order to achieve hardware resource access isolation between different processing domains.

[0028] The third configuration module is used to configure an inter-domain cache consistency maintenance mechanism if multiple processing domains are obtained, and to configure an intra-domain cache consistency maintenance mechanism if only one processing domain is obtained; wherein the multiple processing cores are connected through a consistency interconnection network.

[0029] The fourth configuration module is used to configure the processing core in the target processing domain to lockstep operation mode according to the functional safety level requirements corresponding to business needs.

[0030] In conjunction with the second aspect, in one implementation, the inter-domain cache consistency maintenance mechanism includes:

[0031] The cache controller maintains directory information, which is used to record the existence status of each cached data in the shared cache in the exclusive cache of each processing core;

[0032] When any processing core triggers an operation instruction on the target cached data, it queries the directory information to determine the target processing core in the exclusive cache where the target cached data exists.

[0033] Based on the domain identifier of the processing domain to which the target processing core belongs and the core identifier of the target processing core, the operation instructions are sent to the target processing core.

[0034] In conjunction with the second aspect, in one implementation, the intra-domain cache consistency maintenance mechanism includes:

[0035] The cache controller maintains directory information, which is used to record the existence status of each cached data in the shared cache in the exclusive cache of each processing core;

[0036] When any processing core triggers an operation instruction on the target cached data, it queries the directory information to determine the target processing core in the exclusive cache where the target cached data exists.

[0037] Based on the core identifier of the target processing core, the operation instructions are sent to the target processing core.

[0038] Thirdly, embodiments of this application provide a single-chip-based multi-service requirement adaptation device, which includes a processor, a memory, and a single-chip-based multi-service requirement adaptation program stored in the memory and executable by the processor. When the single-chip-based multi-service requirement adaptation program is executed by the processor, it implements the steps of the single-chip-based multi-service requirement adaptation method as described in the first aspect.

[0039] Fourthly, embodiments of this application provide a computer-readable storage medium storing a multi-service requirement adaptation program based on a single chip, wherein when the multi-service requirement adaptation program based on a single chip is executed by a processor, it implements the steps of the multi-service requirement adaptation method based on a single chip as described in the first aspect.

[0040] The beneficial effects of the technical solutions provided in this application include:

[0041] In this embodiment, multiple processing cores in a system-on-a-chip (SoC) are divided into at least one processing domain based on business requirements. Memory access permissions are configured for each processing domain to achieve memory access isolation between different processing domains. Hardware resource access permissions are also configured for each processing domain to achieve hardware resource access isolation between different processing domains. If multiple processing domains are obtained, an inter-domain cache consistency maintenance mechanism is configured; if only one processing domain is obtained, an intra-domain cache consistency maintenance mechanism is configured. The multiple processing cores are connected via a consistency interconnect network. Based on the functional safety level requirements corresponding to the business needs, the processing cores within the target processing domain are configured to operate in lockstep mode. Through this embodiment, based on processing domain division and configuration, a single chip can be quickly deployed to different business scenarios, thereby significantly reducing the cost and time of developing dedicated chips for different scenarios, achieving maximum reuse of hardware resources and a significant improvement in R&D efficiency. Attached Figure Description

[0042] Figure 1 This is a flowchart illustrating an embodiment of the multi-service requirement adaptation method based on a single chip according to this application;

[0043] Figure 2 This is a schematic diagram of the functional modules of an embodiment of the multi-service requirement adaptation device based on a single chip according to this application.

[0044] Figure 3 This is a schematic diagram of the hardware structure of a multi-service requirement adaptation device based on a single chip involved in the embodiments of this application. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0047] In a first aspect, embodiments of this application provide a method for adapting to multiple service requirements based on a single chip.

[0048] In one embodiment, reference is made to Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the multi-service requirement adaptation method based on a single chip according to this application. Figure 1 As shown, the multi-service requirement adaptation method based on a single chip includes:

[0049] Step S10: Based on business requirements, divide the multiple processing cores in the system-on-a-chip into at least one processing domain;

[0050] In this embodiment, taking a system-on-a-chip (SoC) with 10 processing cores as an example, the following explanation is provided:

[0051] If the business requirement is a smart cockpit requirement, the 10 processing cores can be dynamically divided into two processing domains by configuring the hardware configuration registers inside the system-on-a-chip: the in-vehicle infotainment system domain and the instrument cluster domain. The in-vehicle infotainment system domain includes 8 processing cores (processing cores 0 to 7), and the instrument cluster domain includes two processing cores (processing cores 8 to 9).

[0052] If the business requirement is intelligent driving, the 10 processing cores can be dynamically divided into a processing domain by configuring the hardware configuration registers inside the system-on-a-chip: the advanced driver assistance system domain, which includes processing cores 0 to 9.

[0053] If the business requirements are for intelligent cockpit, driving, and parking, the 10 processing cores are dynamically divided into three processing domains by configuring the hardware configuration registers inside the system-on-a-chip: the in-vehicle infotainment system (IVI) domain, the instrument cluster domain, and the advanced driver assistance system (ADAS) domain. The IVI domain includes 4 processing cores (processing cores 0 to 3), the ADAS domain includes 4 processing cores (processing cores 4 to 7), and the instrument cluster domain includes 2 processing cores (processing cores 8 to 9).

[0054] Step S20: Configure memory access permissions for each processing domain to achieve memory access isolation between different processing domains;

[0055] In this embodiment, to achieve memory access isolation between different processing domains, each processing domain is configured with its own dedicated memory access permissions. For example, taking the dynamic division of 10 processing cores into three processing domains: the in-vehicle infotainment system (IVI) domain, the instrument cluster domain, and the advanced driver assistance system (ADAS) domain, the system's physical memory space is divided into multiple regions. This is configured programmatically:

[0056] Configure a dedicated memory region (e.g., Region_A) for the IVI domain, and prohibit it from accessing the dedicated memory regions of the ADAS domain and the instrumentation domain; configure a dedicated memory region (e.g., Region_B) for the ADAS domain, and prohibit it from accessing the dedicated memory regions of the IVI domain and the instrumentation domain; configure a dedicated memory region (e.g., Region_C) for the instrumentation domain, and prohibit it from accessing the dedicated memory regions of the IVI domain and the ADAS domain.

[0057] This step, through hardware-level access control, ensures that software failures or malicious behavior in one processing domain cannot tamper with or read private data in another processing domain, thus laying the foundation for system security.

[0058] The configuration of memory access permissions is illustrated through a specific scenario:

[0059] Assume the system-on-a-chip (SoC) contains 12 processing cores, and the business requirement is for an integrated cabin-parking scenario. This can be divided into three processing domains:

[0060] IVI domain: Contains processing cores 0-3, which run the in-vehicle infotainment system.

[0061] ADAS Domain: Contains processing cores 4-7, which run the autonomous driving system.

[0062] Instrumentation Domain: Contains processing cores 8-11, which run digital instrumentation systems.

[0063] Memory layout: Physical DDR memory is pre-planned into four main regions: Region_A, Region_B, Region_C, and Region_Shared, where Region_Shared is a shared cache region.

[0064] Configuration Method 1:

[0065] Configure a memory protection unit (MPU) integrated within the processing core or processing cluster.

[0066] Configuration action: The system bootloader or security management software configures the MPU within each core or its associated processing cluster by writing to registers. Specific configuration process:

[0067] For cores 0-3 of the IVI domain, the following rules are programmed in their respective MPUs:

[0068] Rule 1: Reading and writing to Region_A is allowed;

[0069] Rule 2: Read and write to Region_Shared are allowed;

[0070] Rule 3: Deny access to Region_B and Region_C (or deny all access that is not explicitly permitted by default).

[0071] For cores 4-7 of the ADAS domain, program them in their respective MPUs:

[0072] Rule 1: Reading and writing to Region_B is allowed;

[0073] Rule 2: Read and write to Region_Shared are allowed;

[0074] Rule 3: Access to Region_A and Region_C is prohibited.

[0075] For the cores 8-11 of the instrumentation domain, program them in their respective MPUs:

[0076] Rule 1: Read and write access to Region_C is allowed;

[0077] Rule 2: Read and write to Region_Shared are allowed;

[0078] Rule 3: Deny access to Region_A and Region_B (or deny all access that is not explicitly permitted by default).

[0079] Runtime effect:

[0080] When the processing core 0 of the IVI domain attempts to write data to 0x8100_1000 (belonging to Region_B), its local MPU will immediately detect that the address is not in its allowed list, triggering a memory protection fault exception and preventing the write.

[0081] Configuration Method 2:

[0082] Configure the access control unit on the consistent interconnect network interface.

[0083] Configuration Action: During system-on-a-chip initialization, the access control unit of the master device interface connecting each processing domain's coherent interconnect network (such as CMN) is programmed via the configuration bus. Specific configuration process:

[0084] Assume that the IVI domain, ADAS domain, and instrumentation domain are connected to Port_1, Port_2, and Port_3 of the conformance interconnection network, respectively.

[0085] Configure the access control unit for Port_1: Set its address filter to allow only the processing chip from the IVI domain to read and write the address ranges of Region_A and Region_Shared.

[0086] Configure the access control unit of Port_2: Set its address filter to allow only the processing chip from the ADAS domain to read and write the address ranges of Region_B and Region_Shared.

[0087] Configure the access control unit for Port_3: Set its address filter to allow only the processing chip from the instrument domain to read and write the address ranges of Region_C and Region_Shared.

[0088] Runtime effect:

[0089] When the ADAS domain's processing core 5 initiates a read request for 0x8200_2000 (belonging to Region C), the request reaches the access control unit of Port_2 through the consistency interconnect network. The access control unit of Port_2 checks the target address and finds that 0x8200_2000 is not in the address list (Region_B and Region_Shared) allowed by processing core 5. Therefore, it intercepts the transaction and returns a bus error response to processing core 5.

[0090] Step S30: Configure hardware resource access permissions for each processing domain to achieve hardware resource access isolation between different processing domains;

[0091] In this embodiment, the correspondence between different processing domains and hardware resources can be pre-set, and hardware resource access permissions can be configured for each processing domain based on the correspondence.

[0092] Furthermore, in one embodiment, a unique domain identifier and bound hardware resources are assigned to each processing domain; and access control rules based on the domain identifier are set for each processing domain.

[0093] In this embodiment, a unique domain identifier and associated hardware resources can be assigned to each processing domain through the device manager. For example, the graphics processing unit, high-definition display interface, and audio codec are bound to the domain identifier of the IVI domain. The artificial intelligence computing unit and multiple camera / radar interfaces are bound to the domain identifier of the ADAS domain. The instrument display controller and ultrasonic radar interface are bound to the domain identifier of the instrument domain. Simultaneously, the firewall sets access control rules based on the domain identifier. This step achieves physical isolation of hardware resources, prevents resource contention and unauthorized access, and ensures the independence and determinism of each domain's functions.

[0094] Step S40: If multiple processing domains are obtained, an inter-domain cache consistency maintenance mechanism is configured; if only one processing domain is obtained, an intra-domain cache consistency maintenance mechanism is configured; wherein, the multiple processing cores are connected through a consistency interconnection network.

[0095] In this embodiment, since multiple processing domains are divided, an inter-domain / intra-domain cache consistency maintenance mechanism is configured. The core of this mechanism is that when cores of different domains / same domains need to access shared data, they can efficiently and correctly maintain data consistency while avoiding unnecessary global communication overhead.

[0096] Furthermore, in one embodiment, the inter-domain cache consistency maintenance mechanism includes:

[0097] The cache controller maintains directory information, which records the existence status of each cached data in the shared cache in the exclusive cache of each processing core. When any processing core triggers an operation instruction on the target cached data, it queries the directory information to determine the target processing core in the exclusive cache where the target cached data exists. Based on the domain identifier of the processing domain to which the target processing core belongs and the core identifier of the target processing core, the operation instruction is sent to the target processing core.

[0098] In this embodiment, the cache controller maintains a directory information for each cache line (i.e., cached data). The directory information can exist in bitmap form, with each bit corresponding to a specific processing core, used to record whether a copy of this cache line exists in the exclusive cache of that core.

[0099] For example, the directory bitmap of cache line Data_X is 0b0000_0011_0011, indicating that a copy of Data_X is held in the exclusive cache of processing cores 0, 1, 4, and 5 (belonging to the IVI domain and ADAS domain, respectively).

[0100] When processing core 6 in the ADAS domain initiates a write operation to Data_X, the cache controller queries the directory information of Data_X to determine that the target processing cores currently holding a copy of this data are cores 0, 1, 4, and 5. It then obtains the processing domain information to which these target processing cores belong (e.g., processing cores 0 and 1 belong to the IVI domain, and processing cores 4 and 5 belong to the ADAS domain). Subsequently, instead of performing a full chip broadcast, it generates precise delivery instructions:

[0101] Generate a cache consistency message (such as an invalidation request) destined for the IVI domain, specifying processing cores 0 and 1 as the destination in the message header. Generate a similar message destined for the ADAS domain, specifying processing cores 4 and 5 as the destination. The consistency interconnect network routes the messages precisely to the specified processing cores within the target processing domain based on these instructions.

[0102] This embodiment avoids broadcasting by using directory information. In chips with many processing cores and complex domain partitioning, it can significantly alleviate bus congestion, reduce system power consumption, and reduce the number of interrupts to irrelevant cores, thereby improving overall performance and real-time performance.

[0103] Furthermore, in one embodiment, the intra-domain cache consistency maintenance mechanism includes:

[0104] The cache controller maintains directory information, which records the existence status of each cached data in the shared cache in the exclusive cache of each processing core. When any processing core triggers an operation instruction on the target cached data, it queries the directory information to determine the target processing core in the exclusive cache where the target cached data exists. Based on the core identifier of the target processing core, the operation instruction is sent to the target processing core.

[0105] In this embodiment, taking intelligent driving requirements as an example, as shown above, by configuring the hardware configuration register inside the system-on-a-chip, the 10 processing cores are dynamically divided into a processing domain: the advanced driver assistance system domain, which includes processing cores 0 to 9.

[0106] In the cache controller, a directory bitmap is maintained for each cache line, recording its distribution across the dedicated caches of the 10 processing cores. For example, when processing core 3 needs to modify Data_Y, the cache controller queries the directory bitmap and finds that processing cores 1, 7, and 10 hold copies of Data_Y. Since all cores belong to the same processing domain, no processing domain identifier is needed; the cache controller directly generates a target list containing the identifiers of processing cores 1, 7, and 10, and triggers a domain-wide consistency transaction. This transaction, through the consistency interconnect network, efficiently multicasts or peers to send "invalidation requests" only to cores 1, 7, and 10; other cores (such as cores 0, 2, and 4) do not participate in this transaction.

[0107] Step S50: Based on the functional safety level requirements corresponding to the business needs, configure the processing core within the target processing domain to lockstep operation mode.

[0108] In this embodiment, since the functional safety requirements corresponding to driving needs and instrument display needs are relatively high, the processing cores in the ADAS domain and instrument domain can be configured to lockstep operation mode.

[0109] Further, in one embodiment, step S50 includes:

[0110] The lockstep operation mode of the boot core can be configured via the board-level external pins of the system-on-a-chip; the lockstep operation mode of the non-boot core can be configured via the hardware security module integrated within the system-on-a-chip.

[0111] In this embodiment, the startup core refers to the first (or first group of) processing cores that begin executing startup code after the chip is powered on or reset. Non-startup cores refer to other processing cores that are only awakened or allowed to execute code after the startup core has completed its basic initialization.

[0112] The chip package has specific functional safety configuration pins. During board-level design, if the product is positioned as high-safety level, these pins are connected to a high level via soldered resistors. Upon power-on reset, the BootROM hardware circuit reads the level of this pin; if it is high, it automatically configures the boot core to lockstep operation mode. After system startup, the independently operating Hardware Safety Module (HSM) within the chip begins operation. Based on preset safety policies or received dynamic instructions, the HSM accesses the control registers of other non-boot cores via a secure configuration bus. For example, the HSM writes specific values ​​to the registers of cores 5, 6, and 7, pairing them up to set them to lockstep mode.

[0113] It should be noted that steps S20 to S40 can be executed sequentially in a preset order. In this embodiment, the step numbers do not limit the execution order between them; or some / all can be executed in parallel.

[0114] In this embodiment, multiple processing cores in a system-on-a-chip (SoC) are divided into at least one processing domain based on business requirements. Memory access permissions are configured for each processing domain to achieve memory access isolation between different processing domains. Hardware resource access permissions are also configured for each processing domain to achieve hardware resource access isolation between different processing domains. If multiple processing domains are obtained, an inter-domain cache consistency maintenance mechanism is configured; if only one processing domain is obtained, an intra-domain cache consistency maintenance mechanism is configured. The multiple processing cores are connected via a consistency interconnect network. Based on the functional safety level requirements corresponding to the business needs, the processing cores within the target processing domain are configured to operate in lockstep mode. Through this embodiment, based on processing domain division and configuration, a single chip can be quickly deployed to different business scenarios, thereby significantly reducing the cost and time of developing dedicated chips for different scenarios, achieving maximum reuse of hardware resources and a significant improvement in R&D efficiency.

[0115] Secondly, embodiments of this application also provide a multi-service requirement adaptation device based on a single chip.

[0116] In one embodiment, reference is made to Figure 2 , Figure 2 This is a functional module diagram of an embodiment of the multi-service requirement adaptation device based on a single chip according to this application. Figure 2 As shown, the multi-service requirement adaptation device based on a single chip includes:

[0117] The partitioning module 10 is used to divide multiple processing cores in the system-on-a-chip into at least one processing domain based on business requirements.

[0118] The first configuration module 20 is used to configure memory access permissions for each processing domain in order to achieve memory access isolation between different processing domains;

[0119] The second configuration module 30 is used to configure hardware resource access permissions for each processing domain in order to achieve hardware resource access isolation between different processing domains.

[0120] The third configuration module 40 is used to configure an inter-domain cache consistency maintenance mechanism if multiple processing domains are obtained; and to configure an intra-domain cache consistency maintenance mechanism if only one processing domain is obtained; wherein the multiple processing cores are connected through a consistency interconnection network.

[0121] The fourth configuration module 50 is used to configure the processing core in the target processing domain to lockstep operation mode according to the functional safety level requirements corresponding to business needs.

[0122] Furthermore, in one embodiment, the inter-domain cache consistency maintenance mechanism includes:

[0123] The cache controller maintains directory information, which is used to record the existence status of each cached data in the shared cache in the exclusive cache of each processing core;

[0124] When any processing core triggers an operation instruction on the target cached data, it queries the directory information to determine the target processing core in the exclusive cache where the target cached data exists.

[0125] Based on the domain identifier of the processing domain to which the target processing core belongs and the core identifier of the target processing core, the operation instructions are sent to the target processing core.

[0126] Furthermore, in one embodiment, the intra-domain cache consistency maintenance mechanism includes:

[0127] The cache controller maintains directory information, which is used to record the existence status of each cached data in the shared cache in the exclusive cache of each processing core;

[0128] When any processing core triggers an operation instruction on the target cached data, it queries the directory information to determine the target processing core in the exclusive cache where the target cached data exists.

[0129] Based on the core identifier of the target processing core, the operation instructions are sent to the target processing core.

[0130] Furthermore, in one embodiment, the fourth configuration module 50 is used for:

[0131] The lockstep operation mode of the core is started by configuring the board-level external pins of the system-on-a-chip;

[0132] The lockstep operation mode of the non-booting core can be configured through the hardware security module integrated within the system-on-a-chip.

[0133] Furthermore, in one embodiment, the second configuration module 30 is used for:

[0134] Assign a unique domain identifier and associated hardware resources to each processing domain;

[0135] Configure access control rules based on domain identifiers for each processing domain.

[0136] The functions of each module in the above-mentioned single-chip-based multi-service requirement adaptation device correspond to the steps in the above-mentioned single-chip-based multi-service requirement adaptation method embodiment, and their functions and implementation processes will not be described in detail here.

[0137] Thirdly, embodiments of this application provide a multi-service requirement adaptation device based on a single chip. The multi-service requirement adaptation device based on a single chip can be a personal computer (PC), a laptop computer, a server, or other devices with data processing capabilities.

[0138] Reference Figure 3 , Figure 3 This is a schematic diagram of the hardware structure of a single-chip-based multi-service requirement adaptation device involved in the embodiments of this application. In the embodiments of this application, the single-chip-based multi-service requirement adaptation device may include a processor, a memory, a communication interface, and a communication bus.

[0139] The communication bus can be of any type and is used to interconnect the processor, memory, and communication interface.

[0140] Communication interfaces include input / output (I / O) interfaces, physical interfaces, and logical interfaces used for interconnecting devices within a single-chip multi-service requirement adaptation device, as well as interfaces used for interconnecting the single-chip multi-service requirement adaptation device with other devices (such as other computing devices or user equipment). Physical interfaces can be Ethernet interfaces, fiber optic interfaces, ATM interfaces, etc.; user equipment can be displays, keyboards, etc.

[0141] Memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0142] The processor can be a general-purpose processor, which can call a single-chip-based multi-service requirement adaptation program stored in memory and execute the single-chip-based multi-service requirement adaptation method provided in the embodiments of this application. For example, the general-purpose processor can be a central processing unit (CPU). The method executed when the single-chip-based multi-service requirement adaptation program is called can be referred to in the various embodiments of the single-chip-based multi-service requirement adaptation method of this application, and will not be repeated here.

[0143] Those skilled in the art will understand that Figure 3 The hardware structure shown does not constitute a limitation of this application and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0144] Fourthly, embodiments of this application also provide a computer-readable storage medium.

[0145] The present application stores a single-chip-based multi-service requirement adaptation program on a computer-readable storage medium, wherein when the single-chip-based multi-service requirement adaptation program is executed by a processor, it implements the steps of the single-chip-based multi-service requirement adaptation method described above.

[0146] The method implemented when the multi-service requirement adaptation program based on a single chip is executed can be referred to in various embodiments of the multi-service requirement adaptation method based on a single chip in this application, and will not be repeated here.

[0147] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0148] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0149] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0150] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0151] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0152] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0153] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for adapting to multiple service requirements based on a single chip, characterized in that, The single-chip-based multi-service requirement adaptation method includes: Based on business requirements, the multiple processing cores in the system-on-a-chip are divided into at least one processing domain. Configure memory access permissions for each processing domain to achieve memory access isolation between different processing domains; Configure hardware resource access permissions for each processing domain to achieve hardware resource access isolation between different processing domains; If multiple processing domains are obtained, an inter-domain cache consistency maintenance mechanism is configured; if only one processing domain is obtained, an intra-domain cache consistency maintenance mechanism is configured; wherein, the multiple processing cores are connected through a consistency interconnection network. Based on the functional safety level requirements corresponding to business needs, the processing core within the target processing domain is configured to lockstep operation mode; The step of configuring the processing core within the target processing domain to lockstep operation mode includes: The lockstep operation mode of the core is started by configuring the board-level external pins of the system-on-a-chip; The lockstep operation mode of the non-booting core can be configured through the hardware security module integrated within the system-on-a-chip.

2. The multi-service requirement adaptation method based on a single chip as described in claim 1, characterized in that, The inter-domain cache consistency maintenance mechanism includes: The cache controller maintains directory information, which is used to record the existence status of each cached data in the shared cache in the exclusive cache of each processing core; When any processing core triggers an operation instruction on the target cached data, it queries the directory information to determine the target processing core in the exclusive cache where the target cached data exists. Based on the domain identifier of the processing domain to which the target processing core belongs and the core identifier of the target processing core, the operation instructions are sent to the target processing core.

3. The multi-service requirement adaptation method based on a single chip as described in claim 1, characterized in that, The intra-domain cache consistency maintenance mechanism includes: The cache controller maintains directory information, which is used to record the existence status of each cached data in the shared cache in the exclusive cache of each processing core; When any processing core triggers an operation instruction on the target cached data, it queries the directory information to determine the target processing core in the exclusive cache where the target cached data exists. Based on the core identifier of the target processing core, the operation instructions are sent to the target processing core.

4. The multi-service requirement adaptation method based on a single chip as described in claim 1, characterized in that, The configuration of hardware resource access permissions for each processing domain includes: Assign a unique domain identifier and associated hardware resources to each processing domain; Configure access control rules based on domain identifiers for each processing domain.

5. A multi-service requirement adaptation device based on a single chip, characterized in that, The single-chip-based multi-service requirement adaptation device includes: The partitioning module is used to divide multiple processing cores in a system-on-a-chip into at least one processing domain based on business requirements. The first configuration module is used to configure memory access permissions for each processing domain in order to achieve memory access isolation between different processing domains; The second configuration module is used to configure hardware resource access permissions for each processing domain in order to achieve hardware resource access isolation between different processing domains. The third configuration module is used to configure an inter-domain cache consistency maintenance mechanism if multiple processing domains are obtained, and to configure an intra-domain cache consistency maintenance mechanism if only one processing domain is obtained; wherein the multiple processing cores are connected through a consistency interconnection network. The fourth configuration module is used to configure the processing core in the target processing domain to lockstep operation mode according to the functional safety level requirements corresponding to business needs. The step of configuring the processing core within the target processing domain to lockstep operation mode includes: The lockstep operation mode of the core is started by configuring the board-level external pins of the system-on-a-chip; The lockstep operation mode of the non-booting core can be configured through the hardware security module integrated within the system-on-a-chip.

6. The multi-service requirement adaptation device based on a single chip as described in claim 5, characterized in that, The inter-domain cache consistency maintenance mechanism includes: The cache controller maintains directory information, which is used to record the existence status of each cached data in the shared cache in the exclusive cache of each processing core; When any processing core triggers an operation instruction on the target cached data, it queries the directory information to determine the target processing core in the exclusive cache where the target cached data exists. Based on the domain identifier of the processing domain to which the target processing core belongs and the core identifier of the target processing core, the operation instructions are sent to the target processing core.

7. The multi-service requirement adaptation device based on a single chip as described in claim 5, characterized in that, The intra-domain cache consistency maintenance mechanism includes: The cache controller maintains directory information, which is used to record the existence status of each cached data in the shared cache in the exclusive cache of each processing core; When any processing core triggers an operation instruction on the target cached data, it queries the directory information to determine the target processing core in the exclusive cache where the target cached data exists. Based on the core identifier of the target processing core, the operation instructions are sent to the target processing core.

8. A multi-service requirement adaptation device based on a single chip, characterized in that, The single-chip-based multi-service requirement adaptation device includes a processor, a memory, and a single-chip-based multi-service requirement adaptation program stored in the memory and executable by the processor. When the single-chip-based multi-service requirement adaptation program is executed by the processor, it implements the steps of the single-chip-based multi-service requirement adaptation method as described in any one of claims 1 to 4.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a multi-service requirement adaptation program based on a single chip, wherein when the multi-service requirement adaptation program based on a single chip is executed by a processor, it implements the steps of the multi-service requirement adaptation method based on a single chip as described in any one of claims 1 to 4.

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