High-precision temperature sensor temperature-sensing front-end circuit based on chopping technology

Abstract

The invention relates to the technical field of analog integrated circuits, in particular to a high-precision temperature sensor temperature-sensing front-end circuit based on a chopping technology, and aims to solve the problems of low-frequency 1 / f noise, operational amplifier input offset voltage drift, band-gap reference temperature drift, limited output driving capability and the like existing at the front end of a traditional temperature sensor. The front-end circuit comprises a chopping band-gap reference source circuit, a chopping buffer circuit and a two-phase non-overlapping clock generation circuit, wherein the chopping band-gap reference source circuit adopts a parasitic bipolar PNP transistor with an emitter junction area ratio of 8: 1 as a temperature sensing device, and a high-gain chopping folded cascode operational amplifier is embedded in the chopping band-gap reference source circuit; and stable positive temperature coefficient voltage and low-temperature drift reference voltage are generated. Noise and maladjustment are inhibited from the system architecture level, the temperature measurement precision can reach the sub-degree centigrade level, the loading capacity is high, the method is achieved based on the standard CMOS technology, a special technology and complex temperature calibration are not needed, and the method has the advantages of being low in cost, high in stability and large-scale integration.

Description

A high-precision temperature sensor front-end circuit based on chopper technology Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, specifically to a high-precision temperature sensor front-end circuit based on chopper technology. Background Technology

[0002] As is well known, on-chip integrated temperature sensors are the core module of modern integrated circuit precision thermal management, and their performance directly determines the reliability and energy efficiency of electronic devices. Among the many temperature sensing technologies, those based on the base-emitter voltage difference (ΔV) of bipolar transistors are particularly important. BE Based on the principle of CMOS, this solution has become the mainstream choice in the field of high-precision temperature sensing due to its outstanding advantages of high theoretical accuracy and good compatibility with standard CMOS processes. It is widely used in scenarios that require real-time temperature monitoring, such as microprocessors, power management chips, automotive electronics and IoT terminals.

[0003] However, existing methods based on ΔV BE The temperature sensing front-end circuit based on this principle has many inherent technical limitations, which severely restrict its temperature measurement accuracy and application scalability:

[0004] First, the input offset voltage (V) of the operational amplifier os The operational amplifier (OPA) suffers from significant drift issues. As a core component of the bandgap reference circuit, its inherent input offset voltage is directly superimposed on the temperature sensing signal, introducing fundamental temperature measurement errors. More importantly, this offset voltage drifts with fluctuations in manufacturing processes, operating temperature, and power supply voltage, resulting in non-linear temperature measurement errors that are difficult to completely eliminate through simple calibration.

[0005] Secondly, low-frequency 1 / f noise degrades the signal-to-noise ratio. The low-frequency flicker noise (1 / f noise) generated by the amplifier during operation has a particularly significant impact in low-frequency output scenarios such as temperature signals. It can directly drown out weak temperature change signals, leading to a decrease in sensor resolution and long-term stability. To balance noise performance, designers often need to sacrifice chip area or increase power consumption, creating a "noise-power-area" trade-off dilemma.

[0006] Furthermore, performance bottlenecks are exacerbated under low-voltage conditions. As CMOS process nodes continue to evolve and chip power supply voltages decrease, the usable signal dynamic range of traditional temperature sensing front-end architectures is significantly compressed, making it dramatically more difficult to simultaneously achieve low offset, low noise, and high linearity under low-voltage conditions. This problem is particularly prominent in low-power devices such as those used in the Internet of Things (IoT), limiting the application of high-precision temperature sensors in low-power scenarios.

[0007] Finally, complex calibration leads to high costs. To achieve absolute temperature measurement accuracy at the sub-Celsius level (e.g., within ±0.5℃), existing technologies typically require multi-point temperature calibration of each chip during the manufacturing process, correcting errors caused by process drift and device discreteness through additional testing procedures. This calibration process not only consumes a significant amount of testing time but also requires specialized testing equipment, significantly increasing product manufacturing costs and production cycles. This has become a core bottleneck for the large-scale integration of high-precision temperature sensors in low-cost, high-volume applications such as consumer electronics and the Internet of Things.

[0008] To address the aforementioned technical issues, existing improvement solutions mostly focus on optimizing backend calibration algorithms or making localized improvements to single modules. These solutions fail to achieve systematic suppression of noise and offset at the system architecture level, making it difficult to fundamentally resolve the contradictions between accuracy, power consumption, cost, and integration. Therefore, developing a high-precision temperature sensing front-end circuit that can suppress noise and offset at the source, adapt to low-voltage environments, and requires no complex calibration has become an urgent need in this field. Summary of the Invention

[0009] (a) Technical problems to be solved

[0010] To address the problems of low-frequency flicker noise (1 / f noise), operational amplifier input offset voltage drift, bandgap reference temperature drift, and limited output drive capability in the front-end of existing high-precision temperature sensors, a high-precision temperature sensor front-end circuit based on chopper technology is provided. This circuit comprehensively suppresses noise and offset at the system architecture level, thereby improving the DC accuracy, long-term stability, and load capacity of temperature sensing.

[0011] (II) Technical Solution

[0012] To achieve the above objectives, the present invention provides the following technical solution: a high-precision temperature sensor front-end circuit based on chopper technology, comprising a chopper bandgap reference source circuit for generating a positive temperature coefficient (PTAT) voltage proportional to temperature and a reference voltage independent of temperature; a chopper buffer circuit, the input of which is electrically connected to the output of the chopper bandgap reference source circuit, for regulating, enhancing, and isolating the PTAT voltage or reference voltage; and a two-phase non-overlapping clock generation circuit, the output of which is electrically connected to the clock inputs of the chopper bandgap reference source circuit and the chopper buffer circuit respectively, for providing synchronous and non-overlapping timing control signals for each chopper module; both the chopper bandgap reference source circuit and the chopper buffer circuit employ chopper modulation technology based on the clock signal to systematically suppress low-frequency noise and DC offset of the circuit.

[0013] Furthermore, the chopper bandgap reference source circuit includes a bandgap reference core circuit, a startup circuit, and an embedded high-gain chopper operational amplifier. The bandgap reference core circuit uses a pair of parasitic bipolar PNP transistors with an emitter-junction area ratio of N:1 as temperature sensing devices, with their emitters connected to the differential input terminals of the high-gain chopper operational amplifier. The startup circuit is connected to the bandgap reference core circuit to ensure that the circuit leaves the degeneracy point and enters normal operation after power-on. The high-gain chopper operational amplifier forms a negative feedback loop, clamping its two input terminals to approximately equal potentials, so that the base-emitter voltage difference (ΔV) generated by the two transistors... BE It is applied entirely to the preset resistor to generate a precise PTAT current.

[0014] Furthermore, the ratio of the emitter junction area of ​​the parasitic bipolar PNP transistor is N = 8.

[0015] Furthermore, the high-gain chopper operational amplifier is a chopper-folded cascode operational amplifier, comprising: a bias circuit for generating multiple stable PMOS and NMOS bias voltages; a folded cascode amplifier circuit connected to the bias circuit for achieving high-gain amplification of the differential signal; at least three chopper circuits, namely a first chopper circuit, a second chopper circuit, and a third chopper circuit; the first chopper circuit is connected to the differential signal input path of the amplifier, and the second and third chopper circuits are both connected to the cascode stage signal path of the amplifier; each chopper circuit is controlled by the clock signal output by the two-phase non-overlapping clock generation circuit, and the three chopper circuits are controlled by the clock signal to perform periodic synchronous polarity switching to achieve modulation and spectrum shifting of the input offset voltage and 1 / f noise.

[0016] Furthermore, the chopper circuit is a differential clock-controlled chopper switch circuit, including four transmission gates (TG1, TG2, TG3, TG4). The transmission gates are composed of complementary MOS transistors, and their control terminals are connected to the clock signals (clk1, clk2, clk1d, clk2d) output by the two-phase non-overlapping clock generation circuit, which are used to realize the polarity switching of the differential input signal.

[0017] Furthermore, the chopper buffer circuit includes a chopper operational amplifier, a resistor feedback network, a phase compensation network, and a current mirror output stage. The resistor feedback network is connected between the output terminal and the inverting input terminal of the chopper operational amplifier, and forms a negative feedback loop with the voltage divider node of the non-inverting input terminal to lock and buffer the input voltage. The phase compensation network is composed of a resistor and a capacitor connected in series, and is connected between the output terminal and the inverting input terminal of the chopper operational amplifier to improve the stability of the negative feedback loop. The current mirror output stage is composed of a matched PMOS transistor, whose gate is controlled by the output of the chopper operational amplifier, outputting a stable mirror current to the load resistor to generate a final output voltage with strong driving capability.

[0018] Furthermore, the chopper operational amplifier in the chopper buffer circuit has the same structure as the high-gain chopper operational amplifier in the chopper bandgap reference source circuit.

[0019] Furthermore, the two-phase non-overlapping clock generation circuit includes logic gate circuits and a multi-stage inverter delay chain, used to receive a single external input clock, and through logic processing and adjustable delay, generate two main clock signals (clk1, clk2) with opposite phases and no overlapping conduction windows, as well as delayed clock signals (clk1d, clk2d) that are synchronized with the two main clock signals and have fixed delays.

[0020] Furthermore, the logic gate circuit includes an input inverter (INV1) and two NAND gates (NAND1, NAND2), and the multi-stage inverter delay chain includes eighteen cascaded inverters (INV2 to INV19); the input clock signal (CLK) is transmitted in two paths: one path is directly connected to the first input terminal of NAND1 and NAND2, and the other path is connected to the second input terminal of NAND1 and NAND2 after being inverted by INV1; the output of NAND1 is delayed by the multi-stage inverter to generate the main clock signal clk1 and the delayed clock signal clk1d, and the output of NAND2 is delayed by the multi-stage inverter to generate the main clock signal clk2 and the delayed clock signal clk2d.

[0021] Furthermore, the PTAT voltage output by the chopper bandgap reference source circuit can be directly used as a temperature sensing signal output, and its low temperature drift reference voltage can be used as a reference for other modules inside the sensor or output after being driven by the chopper buffer circuit.

[0022] (III) Beneficial Effects

[0023] Compared with the prior art, the present invention provides a high-precision temperature sensor front-end circuit based on chopper technology, which has the following advantages:

[0024] This invention presents a high-precision temperature sensor front-end circuit based on chopper technology. It deeply integrates chopper modulation technology into the chopper bandgap reference source and chopper buffer, and innovatively employs a folded common-source common-gate operational amplifier architecture with multi-node synchronous chopping in the input stage, intermediate stage, and tail current stage. This systematically suppresses input offset voltage and low-frequency 1 / f noise from the signal transmission source. By controlling the chopper circuit to periodically switch signal polarity via a clock signal, the spectrum of offset voltage and 1 / f noise is shifted to a high-frequency clock band, where they are effectively filtered out by subsequent filtering stages. This results in an input offset voltage cancellation rate approaching 95% and a 1 / f noise suppression effect improved by more than an order of magnitude. Ultimately, it achieves sub-Celsius absolute temperature measurement accuracy (within ±0.5℃) and long-term operational stability (temperature drift coefficient) better than 50ppm / ℃, solving the accuracy bottleneck caused by noise and offset in traditional circuits.

[0025] The independently designed chopper buffer circuit forms a closed-loop voltage regulation system with the chopper operational amplifier through a resistor feedback network. It utilizes the "virtual short" characteristic of the operational amplifier to accurately lock the input voltage and effectively cancel voltage fluctuation interference. The phase compensation network optimizes the loop phase margin through an RC series structure, completely suppressing the oscillation risk of the negative feedback loop and ensuring stable operation of the circuit over a wide load range. The current mirror output stage adopts a matched PMOS transistor structure to achieve stable current mirroring and amplification, increasing the load-driving capability to more than 10 times that of traditional bandgap reference sources. It can directly drive downstream ADC, DAC and other modules, while isolating the impact of downstream load fluctuations on sensitive reference circuits, avoiding signal distortion, and significantly improving the application scalability and signal transmission reliability of the circuit.

[0026] A dedicated two-phase non-overlapping clock generation circuit uses logic gates and an 18-stage inverter delay chain to generate a main clock (clk1, clk2) and a synchronous delayed clock (clk1d, clk2d) with opposite phases and no overlapping conduction windows. The main clock avoids the shoot-through current caused by simultaneous conduction of chopper switches, while the delayed clock ensures synchronized chopping operations across multiple modules, completely eliminating glitches and timing deviations during signal switching and guaranteeing the effectiveness of chopping modulation at the timing level. This clock circuit requires only a single external input clock, simplifying the process. This invention is entirely based on standard CMOS technology, and the core temperature sensing device uses a bipolar PNP transistor parasitic in the process, requiring no additional special process steps or custom components, significantly reducing manufacturing costs and process complexity. Simultaneously, the systematic suppression of noise and offset achieved through architectural innovation significantly reduces the circuit's sensitivity to manufacturing process fluctuations, perfectly adapting to the large-scale integration needs of low-cost, high-volume applications such as consumer electronics and the Internet of Things.

[0027] This invention optimizes the circuit's operating voltage range through a folded cascode amplifier structure. The chopper circuit employs a transmission gate design using complementary MOSFETs, ensuring low on-resistance and high signal transmission efficiency even at low supply voltages (1.8V-3.3V). The bias circuits of each module utilize current mirroring and resistor voltage division mechanisms to achieve temperature consistency and supply voltage robustness of the bias voltage, maintaining stable performance over a wide supply voltage fluctuation range (±10%). This solves the problem of insufficient signal dynamic range in traditional architectures under low voltage environments, adapting to the application requirements of low-power electronic devices. Attached Figure Description

[0028] Figure 1 is a circuit diagram of the temperature sensing front-end of a high-precision temperature sensor based on chopper technology provided in an embodiment of the present invention.

[0029] Figure 2 is a circuit diagram of the chopper bandgap reference source in the temperature sensing front-end circuit of the high-precision integrated temperature sensor based on chopper technology provided in an embodiment of the present invention.

[0030] Figure 3 is a high-gain chopper operational amplifier circuit diagram in the chopper bandgap reference source circuit diagram of the temperature sensing front-end circuit of the high-precision integrated temperature sensor based on chopper technology provided in the embodiment of the present invention.

[0031] Figure 4 is a chopper switch circuit diagram in the high-gain chopper operational amplifier of the chopper bandgap reference source circuit diagram in the temperature sensing front-end circuit of the high-precision integrated temperature sensor based on chopper technology provided in the embodiment of the present invention.

[0032] Figure 5 is a circuit diagram of the chopper buffer in the temperature sensing front-end circuit of the high-precision integrated temperature sensor based on chopper technology provided in an embodiment of the present invention.

[0033] Figure 6 is a circuit diagram of a two-phase non-overlapping clock generation circuit in the temperature sensing front-end circuit of a high-precision integrated temperature sensor based on chopper technology provided in an embodiment of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] Please refer to Figures 1 to 6. This invention is a high-precision temperature sensor front-end circuit based on chopper technology, including a chopper bandgap reference source circuit for generating a positive temperature coefficient (PTAT) voltage proportional to temperature and a reference voltage independent of temperature; a chopper buffer circuit, whose input terminal is electrically connected to the output terminal of the chopper bandgap reference source circuit, for regulating, enhancing, and isolating the PTAT voltage or reference voltage; and a two-phase non-overlapping clock generation circuit, whose output terminal is electrically connected to the clock input terminals of the chopper bandgap reference source circuit and the chopper buffer circuit respectively, for providing synchronous and non-overlapping timing control signals for each chopper module; both the chopper bandgap reference source circuit and the chopper buffer circuit employ chopper modulation technology based on the clock signal to systematically suppress low-frequency noise and DC offset of the circuit.

[0036] In this scheme, the chopper bandgap reference source circuit includes a bandgap reference core circuit, a startup circuit, and an embedded high-gain chopper operational amplifier. The bandgap reference core circuit uses a pair of parasitic bipolar PNP transistors with an emitter-junction area ratio of N:1 as temperature sensing devices, with their emitters connected to the differential input terminals of the high-gain chopper operational amplifier. The startup circuit is connected to the bandgap reference core circuit to ensure that the circuit leaves the degeneracy point and enters normal operation after power-on. The high-gain chopper operational amplifier forms a negative feedback loop, clamping its two input terminals to approximately equal potentials, so that the base-emitter voltage difference (ΔV) generated by the two transistors... BE The PTAT current is applied entirely across a preset resistor to generate a precise PTAT current. The core circuit of the bandgap reference uses a pair of parasitic bipolar PNP transistors with an emitter-junction area ratio of N:1 as the temperature sensing device, utilizing the transistor's ΔV... BE The positive temperature coefficient characteristic, combined with the "virtual short" characteristic of the high-gain chopper operational amplifier, will reduce ΔV BE A precise PTAT current is generated by applying the full amount of the preset resistor.

[0037] The startup circuit uses a combination of resistors and MOSFETs to break the circuit degeneracy point during the power-on phase, preventing the core circuit from falling into a zero-current ineffective state and ensuring that the circuit quickly enters a stable working mode.

[0038] An embedded high-gain chopper operational amplifier forms a negative feedback loop, clamping the potentials at both input terminals to approximately equal levels, ensuring the accuracy of the PTAT current. Simultaneously, chopping technology suppresses its own offset voltage and noise. The parasitic bipolar PNP transistor is compatible with standard CMOS processes, requiring no special fabrication, reducing costs while maintaining temperature sensing sensitivity. The startup circuit ensures reliable power-on, preventing malfunctions due to degeneracy points and improving product yield. The combination of the negative feedback loop and chopping technology significantly improves the accuracy of the PTAT current, thereby optimizing the stability of the PTAT voltage and reference voltage, reducing errors caused by process and temperature drift. It provides a low-noise, low-temperature-drift core reference signal for the entire front-end circuit, laying the foundation for high-precision temperature measurement.

[0039] In this scheme, the emitter-junction area ratio N of the parasitic bipolar PNP transistor is 8. The emitter-junction area ratio N of the parasitic bipolar PNP transistor is limited to 8. This ratio is an optimal value obtained by optimizing the device matching characteristics and temperature sensing accuracy requirements of standard CMOS processes: when the emitter-junction area ratio N = 8, the current density difference of the transistor can generate a stable and moderately large ΔV. BE This approach ensures the sensitivity of the PTAT signal while avoiding device layout mismatch caused by an excessively large area ratio. The 8:1 area ratio facilitates high-precision matching during manufacturing, reducing ΔV caused by device discreteness. BE Fluctuations, thereby improving the consistency of PTAT current and voltage. Optimizing transistor matching accuracy, making ΔV BE The signal is more stable, the temperature linearity of the PTAT voltage is significantly improved, and the temperature measurement accuracy can reach the sub-Celsius level (within ±0.5℃); it balances signal sensitivity and process feasibility, avoiding the decrease in accuracy or increase in manufacturing cost caused by unreasonable area ratio; it reduces the impact of device discreteness on circuit performance and improves product consistency during mass production.

[0040] In this scheme, the high-gain chopper operational amplifier is a chopper-folded cascode operational amplifier, comprising: a bias circuit for generating multiple stable PMOS and NMOS bias voltages; a folded cascode amplifier circuit connected to the bias circuit for achieving high-gain amplification of differential signals; at least three chopper circuits, namely a first chopper circuit, a second chopper circuit, and a third chopper circuit; the first chopper circuit is connected to the differential signal input path of the amplifier, and the second and third chopper circuits are both connected to the cascode stage signal path of the amplifier; each chopper circuit is controlled by the clock signal output by the two-phase non-overlapping clock generation circuit, and the three chopper circuits are controlled by the clock signal to perform periodic synchronous polarity switching to achieve modulation and spectrum shifting of the input offset voltage and 1 / f noise. The high-gain chopper operational amplifier is defined as a chopper-folded cascode structure. Its working principle is as follows: The bias circuit generates stable PMOS and NMOS bias voltages through current mirroring and resistor voltage division, providing constant operating current for each module of the amplifier circuit and ensuring gain stability; the folded cascode amplifier circuit improves the output impedance through a multi-stage cascode structure, thereby achieving high-gain amplification of differential signals and meeting the amplification factor requirements of the reference source; three chopper circuits are connected to the input path and the cascode path respectively, and periodically and synchronously switch the signal polarity under the control of the clock signal: the input stage chopper modulates the input offset and noise, and the cascode path chopper synchronously modulates the signal polarity, ensuring that the useful signal recovers its original polarity after amplification, while the offset and noise are canceled or shifted. The folded cascode structure achieves high voltage gain (more than an order of magnitude higher than traditional cascode circuits), enhancing signal amplification capabilities. The multi-node synchronous chopper design maximizes the suppression of input offset voltage and 1 / f noise, significantly improving the offset voltage rejection ratio and greatly reducing noise levels. The stable bias circuit ensures consistent amplifier performance over a wide temperature and power supply voltage range, reducing the impact of environmental changes on amplification accuracy. It provides a core amplification unit for the chopper bandgap reference source, ensuring the accuracy of PTAT current and reference voltage, which is crucial for achieving high precision in the entire front-end circuit.

[0041] In this scheme, the chopper circuit is a differential clock-controlled chopper switch circuit, which includes four transmission gates (TG1, TG2, TG3, TG4). The transmission gates are composed of complementary MOS transistors, and their control terminals are connected to the clock signals (clk1, clk2, clk1d, clk2d) output by the two-phase non-overlapping clock generation circuit, which are used to realize the polarity switching of the differential input signal. The chopper circuit is defined as a differential clock-controlled chopper switch circuit, consisting of four complementary MOS transistors forming transmission gates (TG1-TG4). The transmission gates adopt a parallel PMOS and NMOS structure to ensure low on-resistance over a wide voltage range and reduce signal transmission loss. The clock control terminal is connected to two non-overlapping clocks (clk1, clk2) and a delayed clock (clk1d, clk2d). The switching of the transmission gates is controlled by the alternating changes in the clock level: when clk1 is valid, TG1 and TG4 are turned on, and the signal is transmitted directly; when clk2 is valid, TG2 and TG3 are turned on, and the signal is transmitted crosswise, realizing the polarity switching of the differential signal. The delayed clocks (clk1d, clk2d) are used to avoid signal glitches and through-current during transmission gate switching, ensuring signal integrity. Complementary MOS transmission gates enable low-loss signal transmission, reduce signal distortion during chopping, and ensure the fidelity of useful signals. Precise clock control enables periodic polarity switching of differential signals, efficiently modulating low-frequency offset and 1 / f noise. The modulated noise can be completely filtered out by subsequent low-pass filtering. The delayed clock design avoids overlapping conduction problems during switching, eliminates signal glitches and shoot-through current, and improves the stability and reliability of circuit operation. The structure is simple and has good process compatibility, and can be implemented in standard CMOS processes without increasing additional manufacturing costs.

[0042] In this scheme, the chopper buffer circuit includes a chopper operational amplifier, a resistor feedback network, a phase compensation network, and a current mirror output stage. The resistor feedback network is connected between the output terminal and the inverting input terminal of the chopper operational amplifier, and forms a negative feedback loop with the voltage divider node of the non-inverting input terminal to lock and buffer the input voltage. The phase compensation network is composed of a resistor and a capacitor connected in series, and is connected between the output terminal and the inverting input terminal of the chopper operational amplifier to improve the stability of the negative feedback loop. The current mirror output stage is composed of a matched PMOS transistor, whose gate is controlled by the output of the chopper operational amplifier, outputting a stable mirror current to the load resistor to generate a final output voltage with strong driving capability. The internal structure and working mechanism of the chopper buffer circuit: The resistive feedback network and the chopper operational amplifier form a negative feedback loop, utilizing the "virtual short" characteristic of the operational amplifier to lock the input voltage (PTAT voltage or reference voltage), achieving voltage buffering and regulation; the phase compensation network consists of a resistor and a capacitor in series, which, by adjusting the loop phase margin, suppresses the oscillation risk of the negative feedback loop and improves circuit stability; the current mirror output stage consists of matched PMOS transistors, which achieve drain current mirroring through gate common connection, outputting a stable current to the load resistor, generating a strong driving output voltage, while isolating the impact of load fluctuations on the front-end reference circuit. The negative feedback loop achieves high-precision voltage locking, reduces input voltage fluctuations, and improves the DC stability of the signal; the phase compensation network ensures that the circuit is oscillating-free over a wide load range, improving operational reliability; the current mirror output stage significantly enhances the output driving capability, solving the problem of weak output driving of traditional bandgap reference sources, and can directly drive back-end ADC and other modules; the load isolation function avoids interference from back-end circuit fluctuations to the reference source, further improving the stability and temperature measurement accuracy of the entire front-end circuit.

[0043] In this solution, the chopper operational amplifier in the chopper buffer circuit has the same structure as the high-gain chopper operational amplifier in the chopper bandgap reference source circuit. The core principle behind this identical structure lies in reusing a mature, high-performance amplifier architecture: both employ a chopper-folded cascode structure, exhibiting high gain, low offset, and low noise characteristics, ensuring performance consistency between the buffer and the reference source. Reusing the same architecture allows for direct adaptation of clock control signals (clk1, clk2, clk1d, clk2d) without the need for additional timing adaptation circuits, simplifying system integration. This ensures the buffer's low noise and low offset performance, creating a synergistic effect with the reference source to suppress noise and offset, further improving the signal quality of the entire front-end circuit. It also simplifies circuit design complexity, reduces chip area footprint, and lowers manufacturing costs. The unified device architecture improves process compatibility and mass production consistency, reducing performance dispersion caused by different amplifier architectures. Furthermore, it reduces timing design difficulty, avoids chopper modulation failures due to timing mismatches, and improves system stability.

[0044] In this scheme, the two-phase non-overlapping clock generation circuit includes logic gate circuits and a multi-stage inverter delay chain. It receives a single external input clock and, through logic processing and adjustable delay, generates two main clock signals (clk1, clk2) with opposite phases and no overlapping conduction windows, as well as delayed clock signals (clk1d, clk2d) synchronized with the two main clock signals and with fixed delays. The core structure and working mechanism of the two-phase non-overlapping clock generation circuit are as follows: The logic gate circuit (inverter + NAND gate) splits the phase of the input clock and generates two initially inverted signals through the logic operation of the NAND gate, avoiding clock overlap; the multi-stage inverter delay chain optimizes the delay of the initial signal through adjustable delay design: on the one hand, it generates non-overlapping main clocks clk1 and clk2 (only one clock is valid at a time); on the other hand, it generates delayed clocks clk1d and clk2d. The delayed clocks are synchronized with the main clocks to match the switching timing of the chopper switch, avoiding signal glitches and shoot-through current during switch switching. A master clock with opposite phase and no overlapping conduction windows is generated to prevent simultaneous conduction of chopper switches, avoiding power loss and signal distortion caused by shoot-through current. The delayed clock ensures synchronous switching of multiple chopper modules (reference source, chopper circuit in buffer), ensuring the consistency of chopper modulation and improving noise and offset suppression. The multi-stage inverter delay chain enhances the driving capability of the clock signal, ensuring that the clock remains intact after long-distance transmission within the chip, adapting to the timing requirements of complex circuits. Only a single external input clock is required, simplifying the system clock interface design and improving circuit usability.

[0045] In this scheme, the logic gate circuit includes one input inverter (INV1) and two NAND gates (NAND1, NAND2), and the multi-stage inverter delay chain includes eighteen cascaded inverters (INV2 to INV19); the input clock signal (CLK) is transmitted in two paths: one path is directly connected to the first input terminal of NAND1 and NAND2, and the other path is connected to the second input terminal of NAND1 and NAND2 after being inverted by INV1; the output of NAND1 is delayed by the multi-stage inverter to generate the main clock signal clk1 and the delayed clock signal clk1d, and the output of NAND2 is delayed by the multi-stage inverter to generate the main clock signal clk2 and the delayed clock signal clk2d. The specific component connections and signal transmission paths of the two-phase non-overlapping clock generation circuit are as follows: The input clock CLK is transmitted in two paths: one path is directly input to NAND gates NAND1 and NAND2, and the other path is inverted by inverter INV1 and input to two NAND gates. The NAND gate logic operations generate two initially inverted signals, laying the foundation for the non-overlapping clock. The output of NAND1 is delayed by INV2-INV4 and then split into two paths to generate the main clock clk1 through INV5-INV6 and the delayed clock clk1d through INV7-INV10. The output of NAND2 is delayed by INV11-INV13 and then split into two paths to generate the main clock clk2 through INV14-INV15 and the delayed clock clk2d through INV16-INV19. The design of the eighteen-stage inverter delay chain can precisely adjust the delay duration to ensure that clk1d, clk2d and the main clock are matched in timing, while enhancing the driving capability of the clock signal. Precise control of clock delay duration ensures no overlap of the master clock and synchronization between the delayed clock and the master clock, completely avoiding signal glitches and shoot-through current during chopper switch switching; a buffer structure composed of multi-stage inverters enhances the driving capability of the clock signal, enabling simultaneous driving of multiple chopper modules in the reference source and buffer, ensuring global timing consistency; clear device connection relationships make circuit fabrication more reliable, reducing chopper modulation failures caused by timing deviations; the combined design of logic gates and delay chains balances timing accuracy and circuit stability, adapting to operating requirements across a wide temperature and power supply voltage range.

[0046] In this scheme, the PTAT voltage output by the chopper bandgap reference source circuit can be directly used as a temperature sensing signal output. Its low-temperature-drift reference voltage can be used as a reference for other modules within the sensor or output after being driven by the chopper buffer circuit. The application of the chopper bandgap reference source output voltage is flexibly adapted based on signal characteristics: the PTAT voltage has a linear characteristic proportional to temperature, and can be directly output as a temperature sensing signal to downstream modules such as the ADC without additional signal conversion, simplifying the temperature measurement link; the low-temperature-drift reference voltage has temperature stability and can be directly used as a reference signal for other modules within the sensor (such as the ADC reference voltage and bias circuit), or output after being enhanced and driven by the chopper buffer, adapting to different load requirements; the reference voltage driven by the buffer retains low noise and low drift characteristics, while also possessing strong driving capability, meeting the reference voltage requirements of multiple external modules. Enhance circuit application flexibility to adapt to different back-end circuit design requirements (direct temperature sensing output or multi-module reference voltage output); direct PTAT voltage output simplifies the temperature measurement link, reduces errors in the signal conversion process, and improves temperature measurement response speed; multi-scenario application of low-temperature drift reference voltage reduces the design complexity of the sensor's internal circuitry, reduces the use of additional reference sources, and reduces chip area and power consumption; the output signal after buffer driving balances stability and driving capability, expands the circuit's applicability, and improves product compatibility.

[0047] The high-precision temperature sensor front-end circuit based on chopper technology provided in this invention has a core architecture consisting of a chopper bandgap reference source circuit, a chopper buffer circuit, and a two-phase non-overlapping clock generation circuit, as shown in Figure 1. The chopper bandgap reference source circuit serves as the core signal generation module, outputting the PTAT voltage (the core temperature sensing signal) and the low-temperature drift reference voltage (reference signal). The chopper buffer circuit regulates the reference source output signal, enhances its drive, and isolates noise to adapt to the requirements of the downstream load. The two-phase non-overlapping clock generation circuit provides synchronous, non-overlapping timing control signals for the entire system, ensuring accurate chopper modulation. These three components are electrically connected to form a closed-loop system, suppressing noise and offset at the architectural level to achieve high-precision temperature sensing.

[0048] Chopper bandgap reference source circuit:

[0049] As shown in Figure 2, the chopper bandgap reference source circuit includes a bandgap reference core circuit, a startup circuit, and an embedded high-gain chopper operational amplifier.

[0050] 1. Start-up circuit: It consists of resistor R0 and MOSFETs M0, M1 and M2. During the power-on phase, it pulls the core circuit out of the zero-current state, ensuring that it leaves the degeneracy point and enters the normal working state, and avoids the circuit from falling into an invalid working mode.

[0051] 2. Bandgap Reference Core Circuit: A pair of parasitic bipolar PNP transistors (Q0, Q1) with an emitter-junction area ratio of 8:1 are used as temperature sensing devices. Their emitters are connected to the differential inputs of a high-gain chopper operational amplifier. The high-gain chopper operational amplifier forms a negative feedback loop, utilizing the "virtual short" characteristic to clamp the two input terminals to approximately equal potentials, thus reducing the base-emitter voltage difference (ΔV) generated by the two transistors. BE2 The current is fully applied across the preset resistor R1, generating a precise PTAT current according to formula (1): (1) Where, ΔV BE2 Determined by the emitter junction area ratio of Q0 and Q1, and due to its positive temperature coefficient, I... PTAT It also exhibits a positive temperature coefficient.

[0052] 3. Output Voltage Generation: The PTAT current is replicated to the voltage generation circuit through the current mirror, and then generates the PTAT voltage (Formula 2) through resistor R3. This voltage is then converted to voltage across resistor R2 and transistor Q2. BE The superposition of negative temperature coefficients generates a low-temperature drift reference voltage V. REF (Formula 3):

[0053] V PTAT =I PTAT ·R3(2)

[0054]

[0055] Where N = 8 (the ratio of the emitter junction areas of Q0 to Q1), V T This is the thermal voltage. By adjusting the resistance values ​​of R1 and R2, V can be adjusted. BE2 The negative temperature drift and the positive temperature drift generated by the PTAT current on R2 cancel each other out, ultimately achieving V REF It is unrelated to temperature.

[0056] High-gain chopper operational amplifier:

[0057] As shown in Figure 3, the high-gain chopper operational amplifier is a chopper folded cascode structure, including a bias circuit, three chopper circuits (chopper1, chopper2, chopper3) and a folded cascode amplifier circuit.

[0058] 1. Bias Circuit: Composed of 4 PMOS transistors (MP1-MP4), 2 resistors (R1-R2), 2 NMOS transistors (MN1-MN2), and a constant current source Idc. The power supply terminals are connected to VDD and VSS respectively. Its operation is based on a current mirror and resistor voltage divider mechanism, outputting two PMOS bias voltages (Vpb1, Vpb2) and two NMOS bias voltages (Vnb1, Vnb2).

[0059] -Vnb1 is taken from the gate nodes of MP1 and MP3 and supplies the gates of the input stage PMOS transistors MP5 and MP7 to ensure the stability of the input stage static current.

[0060] -Vnb2 is taken from the gate nodes of MP2 and MP4 and supplied to the gates of the common-source cascode PMOS transistors MP10 and MP11 to maintain the output impedance and voltage gain of the common-source cascode structure.

[0061] -Vnb1 is the pole node that supplies the gates of the tail current stage NMOS transistors MN5 and MN6;

[0062] -Vnb2 is taken from the drain node of MN1 and supplies the gates of the common-source cascode NMOS transistors MN3 and MN4 to ensure that the tail current matches the current of the common-source cascode.

[0063] 2. Folded Cascode Amplifier Circuit: Composed of 7 PMOS transistors (MP5-MP11) and 6 NMOS transistors (MN3-MN6), it increases the output impedance through a cascode structure, thereby achieving high-gain amplification of differential signals. Its connection relationship is as follows:

[0064] - Input stage: MP5 gate connected to Vpb1, source connected to VDD, drain connected to MP6 source; MP6 gate connected to chopper1 output, drain connected to MP7 source; MP7 gate connected to Vpb1, drain connected to MN3 drain;

[0065] - Common source and common gate stage: The gates of MP8 and MP9 are connected to the drain of MP7, and the source is connected to VDD. The drains are connected to the sources of MP10 and MP11 respectively. The gates of MP10 and MP11 are connected to Vpb2, and the drains are connected to the drains of MN3 and MN4 respectively. The drain of MP11 is the differential output terminal VOUT.

[0066] - Tail current stage: MN3 and MN4 gates are connected to the output terminal of chopper2, and the sources are connected to the drains of MN5 and MN6 respectively; MN5 and MN6 gates are connected to Vnb1, the sources are connected to VSS, and the drain nodes are connected to the input terminal of chopper3.

[0067] 3. Chopper modulation process: The three chopper circuits are all controlled by clk1, clk2, clk1d, and clk2d, and offset and noise suppression are achieved through periodic synchronous polarity switching.

[0068] - Phase 1 (clk1 valid, clk2 invalid): chopper1 is in pass-through mode, differential input signals VIN and VIP are directly connected to the input stage, superimposed with the input offset voltage V OS After being amplified, the output Vout1 = Vmid1 = A·(Vidl + V OS(A is the voltage gain, Vidl = VIP - VIN);

[0069] - Stage 2 (clk2 valid, clk1 invalid): chopper1 is in crossover state, input signal polarity is reversed (Vidl2 = -Vidl), the amplified intermediate stage signal Vmid2 = A·(-Vidl + V OS Simultaneously, chopper2 and chopper3 are in a crossover state, the polarity of the intermediate stage signal and the tail current stage signal is reversed, and the final output Vout2 = A·Vidl - A·V OS ;

[0070] - Subsequent low-pass filtering averages the outputs of the two stages. The useful signal is recovered to A·Vidl, and the offset voltages cancel each other out (A·V). OS -A·V OS =0), 1 / f noise is modulated to a high frequency and then filtered out, achieving low offset and low noise amplification.

[0071] Chopper switch circuit:

[0072] As shown in Figure 4, the chopper switch is a differential clock controlled type, including four transmission gates (TG1-TG4). The transmission gates are composed of complementary MOSFETs, and the control terminals are connected to clk1, clk2, clk1d, and clk2d.

[0073] - When clk1 is valid and clk2 is invalid, TG1 and TG4 are turned on, TG2 and TG3 are turned off, VIN is directly transmitted to VON, and VIP is directly transmitted to VOP (straight-through state).

[0074] - When clk2 is valid and clk1 is invalid, TG2 and TG3 are turned on, TG1 and TG4 are turned off, VIN is transmitted to VOP via TG2, and VON is transmitted to VOP via TG3 (cross state);

[0075] This design enables periodic polarity switching of the differential input signal, shifting low-frequency offset and 1 / f noise to near the clock frequency for easier subsequent filtering and suppression. Meanwhile, delaying the clocks clk1d and clk2d avoids signal glitches and shoot-through current during switching.

[0076] Chopper buffer circuit:

[0077] As shown in Figure 5, the chopper buffer circuit includes a chopper operational amplifier, a resistor feedback network, a phase compensation network, and a current mirror output stage.

[0078] 1. Resistive feedback network: Composed of R1 and R2, connected between the output and inverting input of the chopper operational amplifier, forming a negative feedback loop with the voltage divider node at the non-inverting input. It utilizes the "virtual short" characteristic of the operational amplifier to lock the input voltage (V). REF or V PTAT This enables voltage buffering and regulation.

[0079] 2. Phase compensation network: It consists of a resistor R0 and a capacitor C0 connected in series and is connected between the output terminal and the inverting input terminal of the chopper operational amplifier. By adjusting the loop phase margin, it suppresses the oscillation risk of the negative feedback loop and improves the circuit stability.

[0080] 3. Current Mirror Output Stage: Composed of matched PMOS transistors M1 and M2, with their gates connected to the output of the chopper operational amplifier. The drain of M1 is connected to VDD, and its source is connected to R1. The drain of M2 is connected to VDD, and its source is connected to R3. Through the current mirror effect, the drain current of M2 matches the drain current of M1, and the output voltage VOUT is generated by the load resistor R3. Its expression is:

[0081]

[0082] Where VIN is the input V REF or V PTAT The output voltage amplitude can be adjusted by changing the ratio of R3 to R2. This output stage significantly enhances the load-driving capability and isolates the impact of downstream load fluctuations on the reference circuit.

[0083] 4. Chopper Operational Amplifier: The structure is the same as that of the high-gain chopper operational amplifier in the chopper bandgap reference source, ensuring the low noise and low offset performance of the buffer and forming a synergistic suppression effect with the reference source.

[0084] Two-phase non-overlapping clock generation circuit:

[0085] As shown in Figure 6, the two-phase non-overlapping clock generation circuit includes one input inverter (INV1), two NAND gates (NAND1, NAND2), and 18 cascaded inverters (INV2-INV19), used to convert the input clock CLK into clk1, clk2, clk1d, and clk2d.

[0086] 1. Clock splitting logic: CLK is transmitted in two paths. One path is directly connected to the first input terminal of NAND1 and NAND2, and the other path is connected to the second input terminal of NAND1 and NAND2 after being inverted by INV1. The two initially inverted signals are generated through NAND gate logic operations, laying the foundation for non-overlapping clock.

[0087] 2. Master Clock Generation: The output of NAND1 is delayed by INV2-INV4 and then split into two paths, INV5-INV6, to generate clk1; the output of NAND2 is delayed by INV11-INV13 and then split into two paths, INV14-INV15, to generate clk2. clk1 and clk2 are out of phase and have no overlapping conduction windows, avoiding simultaneous conduction of the chopper switches and the generation of shoot-through current.

[0088] 3. Delayed Clock Generation: Another output path of NAND1 generates clk1d (the delayed signal of clk1) via INV7-INV10; another output path of NAND2 generates clk2d (the delayed signal of clk2) via INV16-INV19. The delayed clock is used to match the switching timing of the chopper switches, ensuring that multiple chopper modules operate synchronously and avoiding signal glitches.

[0089] 4. Enhanced Drive: The multi-stage inverter delay chain also acts as a buffer, enhancing the driving capability of the clock signal and ensuring that the clock remains intact after long-distance transmission within the chip. It can simultaneously drive multiple chopper modules in the reference source and buffer.

[0090] System collaborative workflow:

[0091] 1. Power-on startup: The startup circuit pulls the chopper bandgap reference source circuit out of the degeneracy point, so that it enters the normal working state; the two-phase non-overlapping clock generation circuit receives the external input clock CLK, generates clk1, clk2, clk1d, clk2d and outputs them to each chopper module.

[0092] 2. Signal Generation: The chopper bandgap reference source circuit senses temperature changes through a parasitic bipolar PNP transistor. Under the negative feedback of the high-gain chopper operational amplifier, it generates a precise PTAT current, which in turn generates a PTAT voltage (temperature sensing signal) and V. REF (Low temperature drift reference voltage).

[0093] 3. Signal Processing: The PTAT voltage can be directly output to the downstream temperature measurement module; V REF It can be directly used as a reference voltage for other modules within the sensor, or input to a chopper buffer circuit. The chopper buffer circuit enhances V through negative feedback regulation, phase compensation, and a current mirror output stage. REF It has strong driving capability and isolates load interference, outputting a stable high driving voltage.

[0094] 4. Noise and offset suppression: Throughout the process, the polarity of each chopper circuit is periodically switched by a two-phase non-overlapping clock to modulate the input offset voltage and 1 / f noise to the high frequency band, which is then filtered out by a subsequent low-pass filter to ensure the high purity and high precision of the output signal.

[0095] In summary, this invention, through architectural innovation, deeply integrates chopper modulation technology into the bandgap reference and buffer circuit, and combines it with a dedicated two-phase non-overlapping clock circuit, systematically solving the noise and offset problems of traditional temperature sensing front-ends. It achieves a high-precision, low-drift, and strong-drive temperature sensing front-end solution under standard CMOS technology, which can meet sub-Celsius temperature measurement requirements without complex temperature calibration and has broad application prospects.

[0096] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-precision temperature sensor front-end circuit based on chopper technology, characterized in that, It includes a chopper bandgap reference source circuit for generating a positive temperature coefficient (PTAT) voltage that is proportional to temperature and a reference voltage that is independent of temperature; and a chopper buffer circuit whose input terminal is electrically connected to the output terminal of the chopper bandgap reference source circuit for regulating, enhancing the drive, and isolating noise from the PTAT voltage or the reference voltage. The two-phase non-overlapping clock generation circuit has its output terminal electrically connected to the clock input terminals of the chopper bandgap reference source circuit and the chopper buffer circuit, respectively, to provide synchronous and non-overlapping timing control signals for each chopper module; both the chopper bandgap reference source circuit and the chopper buffer circuit adopt chopper modulation technology based on the clock signal to systematically suppress low-frequency noise and DC offset of the circuit.

2. The temperature sensing front-end circuit of a high-precision temperature sensor based on chopper technology according to claim 1, characterized in that, The chopper bandgap reference source circuit includes a bandgap reference core circuit, a startup circuit, and an embedded high-gain chopper operational amplifier. The bandgap reference core circuit uses a pair of parasitic bipolar PNP transistors with an emitter-junction area ratio of N:1 as temperature sensing devices, with their emitters connected to the differential input terminals of the high-gain chopper operational amplifier. The startup circuit is connected to the bandgap reference core circuit to ensure that the circuit moves away from the degeneracy point and enters normal operation after power-on. The high-gain chopper operational amplifier forms a negative feedback loop, clamping its two input terminals to approximately equal potentials, so that the base-emitter voltage difference (ΔV) generated by the two transistors... BE It is applied entirely to the preset resistor to generate a precise PTAT current.

3. The temperature sensing front-end circuit of a high-precision temperature sensor based on chopper technology according to claim 2, characterized in that, The ratio of the emitter junction area of ​​the parasitic bipolar PNP transistor is N = 8.

4. The temperature sensing front-end circuit of a high-precision temperature sensor based on chopper technology according to claim 2, characterized in that, The high-gain chopper operational amplifier is a chopper-folded cascode operational amplifier, comprising: a bias circuit for generating multiple stable PMOS and NMOS bias voltages; a folded cascode amplifier circuit connected to the bias circuit for achieving high-gain amplification of differential signals; at least three chopper circuits, namely a first chopper circuit, a second chopper circuit, and a third chopper circuit; the first chopper circuit is connected to the differential signal input path of the amplifier, and the second and third chopper circuits are all connected to the cascode stage signal path of the amplifier; each chopper circuit is controlled by the clock signal output by the two-phase non-overlapping clock generation circuit, and the clock signal controls the three chopper circuits to perform periodic synchronous polarity switching to achieve modulation and spectrum shifting of the input offset voltage and 1 / f noise.

5. The temperature sensing front-end circuit of a high-precision temperature sensor based on chopper technology according to claim 4, characterized in that, The chopper circuit is a differential clock-controlled chopper switch circuit, including four transmission gates (TG1, TG2, TG3, TG4). The transmission gates are composed of complementary MOS transistors, and their control terminals are connected to the clock signals (clk1, clk2, clk1d, clk2d) output by the two-phase non-overlapping clock generation circuit, which are used to realize the polarity switching of the differential input signal.

6. The temperature sensing front-end circuit of a high-precision temperature sensor based on chopper technology according to claim 1, characterized in that, The chopper buffer circuit includes a chopper operational amplifier, a resistor feedback network, a phase compensation network, and a current mirror output stage. The resistor feedback network is connected between the output terminal and the inverting input terminal of the chopper operational amplifier, and forms a negative feedback loop with the voltage divider node of the non-inverting input terminal to lock and buffer the input voltage. The phase compensation network consists of a resistor and a capacitor connected in series, and is connected between the output terminal and the inverting input terminal of the chopper operational amplifier to improve the stability of the negative feedback loop. The current mirror output stage consists of a matched PMOS transistor, whose gate is controlled by the output of the chopper operational amplifier, outputting a stable mirror current to the load resistor to generate a final output voltage with strong driving capability.

7. The temperature sensing front-end circuit of a high-precision temperature sensor based on chopper technology according to claim 6, characterized in that, The chopper operational amplifier in the chopper buffer circuit has the same structure as the high-gain chopper operational amplifier in the chopper bandgap reference source circuit.

8. The temperature sensing front-end circuit of a high-precision temperature sensor based on chopper technology according to claim 1, characterized in that, The two-phase non-overlapping clock generation circuit includes logic gate circuits and a multi-stage inverter delay chain, used to receive a single external input clock, and through logic processing and adjustable delay, generate two main clock signals (clk1, clk2) with opposite phases and no overlapping conduction windows, as well as delayed clock signals (clk1d, clk2d) that are synchronized with the two main clock signals and have fixed delays.

9. The temperature sensing front-end circuit of a high-precision temperature sensor based on chopper technology according to claim 8, characterized in that, The logic gate circuit includes an input inverter (INV1) and two NAND gates (NAND1, NAND2). The multi-stage inverter delay chain includes eighteen cascaded inverters (INV2 to INV19). The input clock signal (CLK) is transmitted in two paths: one path is directly connected to the first input terminal of NAND1 and NAND2, and the other path is connected to the second input terminal of NAND1 and NAND2 after being inverted by INV1. The output of NAND1 is delayed by the multi-stage inverter to generate the main clock signal clk1 and the delayed clock signal clk1d. The output of NAND2 is delayed by the multi-stage inverter to generate the main clock signal clk2 and the delayed clock signal clk2d.

10. A high-precision temperature sensor front-end circuit based on chopper technology according to any one of claims 1 to 9, characterized in that, The PTAT voltage output by the chopper bandgap reference source circuit can be directly used as a temperature sensing signal output. Its low temperature drift reference voltage can be used as a reference for other modules inside the sensor or output after being driven by the chopper buffer circuit.

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