Wiring method, electronic equipment and computer readable storage medium

Abstract

The invention relates to the technical field of wiring, and discloses a wiring method, electronic equipment and a computer readable storage medium, and the method comprises the steps: converting an initial layout layout of a circuit board into a grid chart; according to the grid chart, a coarse wiring result of the initial layout layout is determined, and the coarse wiring result is an initial wiring path meeting a wiring task and achieving a wiring cross minimization target; generating a wiring geometric figure according to the safety spacing and the initial wiring path, and generating a device geometric figure according to the safety spacing and component information in the initial layout layout; and under the limitation of the geometric figure of the device, optimizing the position of the geometric figure of the wiring by taking the wiring constraint as a target to obtain a fine wiring result. According to the method, the wiring process is divided into a coarse wiring stage meeting the goals of connectivity and minimum wiring intersection number and a fine wiring stage meeting the wiring constraint, so that the solving complexity can be reduced, and a wiring scheme with the minimum wiring intersection number can be obtained in a relatively short time.

Description

Technical Field

[0001] This invention relates to the field of cabling technology, and more specifically to a cabling method, electronic device, and computer-readable storage medium. Background Technology

[0002] In integrated circuit design and printed circuit board (PCB) design, routing is an important step, requiring the connection of a large number of circuit components (multiple pins) without violating printed circuit or integrated circuit rules.

[0003] Currently, automatic routing is performed using heuristic algorithms from Electronic Design Automation (EDA) software. However, when optimizing for the minimum number of routing crossovers while ensuring connectivity, the number of possible routing schemes increases exponentially with the increase in loop size, making it difficult to find the optimal solution with the fewest routing crossovers in a short period of time. Summary of the Invention

[0004] This invention provides a wiring method, an electronic device, and a computer-readable storage medium to improve the problem of finding the optimal solution with the fewest wiring crossovers in a short time.

[0005] In a first aspect, the present invention provides a routing method, comprising: converting an initial layout of a circuit board into a mesh diagram, wherein the mesh diagram includes multiple nodes and meshes corresponding one-to-one with the multiple nodes, the nodes representing a pin in the initial layout, and the meshes representing the routable areas of the corresponding nodes; determining a coarse routing result of the initial layout based on the mesh diagram, wherein the coarse routing result is an initial routing path that satisfies the routing task and achieves the goal of minimizing routing intersections; generating a routing geometry based on safety spacing and the initial routing path, and generating a device geometry based on safety spacing and component information in the initial layout; and optimizing the position of the routing geometry under the constraints of the device geometry, with the goal of satisfying routing constraints, to obtain a fine routing result.

[0006] The routing method provided in this embodiment first converts the initial layout diagram into a mesh diagram, then determines the coarse routing result based on the mesh diagram, and finally converts the coarse routing result into a fine routing result that satisfies routing constraints. By decoupling and splitting the routing problem that satisfies connectivity, routing constraints, and the minimum number of routing intersections into a two-stage solution, the solution complexity can be reduced, thereby significantly improving the solution speed. This allows for the achievement of a routing scheme with the minimum number of routing intersections in a shorter time, improving design efficiency and reducing design costs. Moreover, by combining the action reduction of the geometric push strategy and path optimization design, the coarse routing result is converted into a fine routing result, which not only solves the problem of low conflict resolution efficiency in the traditional conversion process but also ensures routing quality through geometric optimization.

[0007] In one optional implementation, determining the coarse routing result of the initial layout based on the mesh diagram includes: when the initial layout is of a target type, determining the coarse routing result based on the target reinforcement learning model and the mesh diagram, wherein the target type is a layout with corresponding routing results and a storage capacity greater than a preset capacity.

[0008] In one optional implementation, the target reinforcement learning model includes an agent and a policy network employing a multi-layer graph sampling aggregation layer. Based on the target reinforcement learning model and the mesh graph, a coarse wiring result is determined, including: determining the node features and edge features corresponding to the node where the agent is located based on the node information of the mesh graph; inputting the node features and edge features into the policy network; determining the agent's action set based on the output of the policy network, wherein the action set includes at least one optional action and the probability corresponding to each optional action; and determining the agent's next action based on the probability of the optional action and whether the optional action will cause path crossing, to obtain the coarse wiring result.

[0009] In this embodiment, by k Layered graph sampling aggregation layers can extend the perceptual range of an agent to... k By using neighboring nodes, the agent's next action is determined based on the probability of the available actions and whether the available actions will cause path crossings. This enables the wiring strategy to make real-time decisions, thereby improving the algorithm's solution speed.

[0010] In one alternative implementation, the number of agents is multiple, and the mesh graph includes multiple local mesh graphs, with multiple agents and multiple local meshes. Figure 1 One-to-one correspondence, multiple agents adopt the same policy network; based on the node information of the mesh graph, determine the node features and edge features corresponding to the nodes selected by the agents, including: based on the node information of the local mesh graph, determine the node features and edge features of the agents corresponding to the local mesh graph.

[0011] In one alternative implementation, after obtaining the next action of the agent, the wiring method further includes: updating the node information of the local mesh graph; updating the node information of the mesh graph and updating the node information of the mesh graph containing prior information based on the updated node information of multiple local mesh graphs.

[0012] In this embodiment, updating the node information of the mesh graph and updating the node information of the mesh graph containing prior information can more accurately calculate the global prior information while maintaining the optimization requirements of the agent's dynamic perception capability.

[0013] In one optional implementation, the node information includes information indicating whether a node is occupied and distance information. When a first node is occupied by an agent but the distance corresponding to the first node does not reach the maximum value, the first node is marked as unoccupied. The first node is a node in the local mesh graph corresponding to the agent, excluding the starting node and the target node.

[0014] In one alternative implementation, the mesh diagram is a Voronoi diagram.

[0015] Compared to the traditional grid-based modeling of path search algorithms, V-graph-based graph design has a larger granularity, which greatly reduces the time and space complexity of path planning problems, and reduces decision variables by 99% compared to not constructing a graph.

[0016] In one alternative implementation, determining the coarse routing result of the initial layout based on the mesh diagram further includes: when the initial layout is not a target type, determining the coarse routing result based on a constraint relaxation flow model.

[0017] In this embodiment, the global optimal solution of the initial layout can be directly solved through mathematical modeling without relying on historical data, ensuring the accuracy of decision-making in unknown scenarios.

[0018] In one optional implementation, the coarse wiring result is determined according to the constraint relaxation flow model, including: solving the constraint relaxation flow model with the optimization objectives of maximizing the number of connected loops and minimizing the length of loops while satisfying the wiring task, to obtain the initial coarse wiring result; when there are conflicting edges in the initial coarse wiring result, the conflicting edges are added as constraints to the constraint relaxation flow model and the solution is repeated until there are no conflicting edges or the number of solutions reaches the maximum limit; the initial coarse wiring result without conflicting edges is determined as the coarse wiring result, or the initial coarse wiring result after the number of solutions reaches the maximum limit is determined as the coarse wiring result.

[0019] In this embodiment, a coarse wiring result is generated by introducing a column generation iteration method that restricts cross constraints. This avoids the problem of increased solution complexity caused by directly adding cross constraints to the mathematical model, which leads to a sharp increase in solution time and improves the solution speed.

[0020] In one optional implementation, there are multiple wiring geometries, and the initial wiring path includes multiple loops. Under the constraints of the device geometry, with the goal of satisfying the wiring constraints, the position of the wiring geometry is optimized to obtain a fine wiring result. This includes: traversing the wiring geometry, identifying a second wiring geometry that spatially overlaps with the first wiring geometry, forming a conflict set, wherein the first wiring geometry is any one of the multiple wiring geometries; determining at least one push loop based on the conflict set, wherein the push loop is a loop among the multiple loops that has a conflict point; performing push processing on the wiring geometry in the at least one push loop to obtain a push result; updating the position of the multiple wiring geometries based on the push result, and returning to the step of forming the conflict set, until the multiple wiring geometries satisfy the wiring constraints or the number of updates reaches a preset number of updates.

[0021] In a second aspect, the present invention provides an electronic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the wiring method of the first aspect or any corresponding embodiment described above.

[0022] Thirdly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the wiring method of the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0023] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of an application scenario according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a pre-routing scheme according to an embodiment of the present invention; Figure 3 This is a schematic diagram of another pre-routing scheme according to an embodiment of the present invention; Figure 4 This is a flowchart illustrating a wiring method according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a Delaunay triangulation based on Hanan according to an embodiment of the present invention; Figure 6This is a schematic diagram of a Delaunay triangulation based on Hanan according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a Delaunay triangulation based on Hanan according to an embodiment of the present invention; Figure 8 This is a schematic diagram of a standard wiring result according to an embodiment of the present invention; Figure 9 This is a schematic diagram of a wiring prediction path according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the wiring geometry according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the device geometry according to an embodiment of the present invention; Figure 12 This is a schematic diagram illustrating the transformation from coarse to fine routing results according to an embodiment of the present invention; Figure 13 This is a schematic diagram of another wiring method according to an embodiment of the present invention; Figure 14 This is a schematic diagram of the training and inference process of a reinforcement learning model according to an embodiment of the present invention; Figure 15 This is a schematic diagram of a policy network according to an embodiment of the present invention; Figure 16 This is a schematic diagram of node information encoding according to an embodiment of the present invention; Figure 17 This is a flowchart illustrating the process of determining coarse wiring results using a reinforcement learning model according to an embodiment of the present invention. Figure 18 This is a schematic diagram of a sampling mechanism for dynamic perception enhancement according to an embodiment of the present invention; Figure 19 This is a schematic diagram of multi-agent-based multi-line co-location and topology information updating according to an embodiment of the present invention; Figure 20 This is a flowchart illustrating another wiring method according to an embodiment of the present invention; Figure 21 This is a flowchart illustrating the process of determining coarse wiring results using a constraint relaxation flow model according to an embodiment of the present invention. Figure 22 This is a flowchart illustrating another wiring method according to an embodiment of the present invention; Figure 23 This is a schematic diagram of an obstacle according to an embodiment of the present invention; Figure 24 This is a schematic diagram of the geometric pushing result according to an embodiment of the present invention; Figure 25 This is a schematic diagram of a pushing strategy according to an embodiment of the present invention; Figure 26 This is a flowchart illustrating a wiring method in a patch cord design scenario according to an embodiment of the present invention. Figure 27 This is a schematic diagram of the geometric pushing process according to an embodiment of the present invention; Figure 28 This is a structural block diagram of a wiring device according to an embodiment of the present invention; Figure 29 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0027] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0028] The execution of the routing method provided by this invention depends on the specific application scenario architecture. As an optional application scenario for an embodiment of this invention, such as... Figure 1 As shown, the architecture may include at least one terminal device and at least one server. Figure 1 The system is illustrated in the example, which includes a computer 101, a mobile terminal 102, and a server 103, and the terminal devices such as the computer 101 and the mobile terminal 102 are connected to the server 103 through a network 110.

[0029] Specifically, the terminal device can be a smartphone, tablet, laptop, PDA, desktop computer, game console, smart TV, smart wearable device, in-vehicle terminal, VR (Virtual Reality) device, AR (Augmented Reality) device, etc. Server 103 can be a standalone physical server, a server cluster, a distributed system, or a cloud server providing cloud services. Network 110 can be a wired or wireless network, examples of which include, but are not limited to, the Internet, corporate intranet, local area network, wide area network, mobile communication network, and combinations thereof.

[0030] The wiring method provided by this invention can be applied to single-sided patch cord design. Currently, single-sided patch cord design is mainly completed manually, and the specific process is divided into three stages: pre-wiring, patch cord resistor planning, and patch cord result adjustment.

[0031] Pre-routing refers to engineers planning the routing path in advance based on the pin connections and routing direction. This involves obtaining a preliminary routing scheme with the fewest possible crossovers while satisfying connectivity and routing constraints. After pre-routing, jumper resistor planning is performed for crossover loops (loops that cause conflicts), resolving crossover issues by selecting appropriate jumper resistors. Finally, the jumper configuration is adjusted until design standards are met. Routing constraints may include wiring safety spacing and wiring angle constraints.

[0032] For example, pre-wiring schemes may be as follows Figure 2 As shown, eight jumper resistors were ultimately used; for example, the pre-routing scheme might be as follows: Figure 3 As shown, three jumper resistors were ultimately used.

[0033] Pre-routing is a critical step, relying heavily on the engineer's subjective experience and potentially yielding suboptimal results. Manual pre-routing increases the cost of jumper resistors and requires multiple adjustments to reduce their usage, thus lengthening the design cycle for single-sided boards. Statistics show that manual design time is approximately 30 minutes when the loop size is 30 (for single-sided boards with 80-30,000+ loops). Design time increases linearly with increasing loop size.

[0034] As mentioned in the background section, routing design can also be performed using the automatic routing function of EDA software. However, the automatic routing function is based on heuristic search-based path planning algorithms (A-Star Algorithm, A*), jump point search (JPS), and re-stepping algorithms. These algorithms are prone to getting trapped in local optima, and the solution time increases exponentially with the problem size. This makes it difficult to achieve the globally optimal result with the fewest routing intersections within a limited time, while satisfying connectivity and routing constraints, thus failing to meet the goal of minimizing the number of jumper resistors used.

[0035] In view of this, the present invention provides a wiring method, an electronic device, and a computer-readable storage medium, which divides the wiring process into a coarse wiring stage that satisfies connectivity and minimizes the number of wiring intersections, and a fine wiring stage that satisfies wiring constraints. This can reduce the solution complexity and thus obtain a wiring scheme that satisfies connectivity, wiring constraints, and minimizes the number of wiring intersections in a shorter time.

[0036] This embodiment provides a wiring method that can be used in the aforementioned terminal device. Figure 4 This is a flowchart of a wiring method according to an embodiment of the present invention, such as... Figure 4 As shown, the process includes the following steps: Step S401: Convert the initial layout of the circuit board into a mesh diagram.

[0037] The circuit board can be a PCB board, and the mesh diagram includes multiple nodes and grids that correspond one-to-one with the nodes. The nodes are used to represent a pin in the initial layout, and the grids are used to represent the routable area of ​​the corresponding node.

[0038] Specifically, layout is the process of transforming abstract circuit logic / schematics into physical graphics recognizable by the manufacturing process. The layout design process includes six stages: front-end design output (generating a gate-level netlist), layout planning, placement, routing, physical verification, and output of manufacturing files. The initial layout refers to the layout after completing the placement stage. The initial layout shows the placement positions of various components (such as transistors, resistors, or capacitors) and auxiliary graphics (such as pads and alignment marks) in the gate-level netlist.

[0039] For example, the mesh graph can be a Hanan-based Delaunay triangular graph, a dual graph, or a Voronoi graph. A Hanan-based Delaunay triangular graph can be as follows: Figure 5 As shown, the dual graph can be represented as follows: Figure 6 As shown, a Voronoi diagram (V diagram for short) can be represented as follows: Figure 7 As shown.

[0040] After obtaining the initial layout, the initial layout can be converted into a mesh diagram through plugins or interfaces in EDA software, and the routeable area can be discretized to address the problem of large and complex routing space in the initial layout.

[0041] In some embodiments, the mesh diagram is a V-graph, which is spatially discretized. The wireable area is discretized by V-graph decomposition technology, and the gaps between pins of equal length are divided into wireable sub-regions. Multiple polygonal sub-units (mesh) are constructed to achieve coverage of most areas, and the distance from each edge to the nearest obstacle is equal.

[0042] Compared to the grid-based modeling of traditional path search algorithms, V-graph-based graph design has a larger granularity, significantly reducing time and space complexity in path planning problems, and reducing decision variables by 99% compared to not constructing a graph. Figure 8 Taking the standard cabling results as an example, the center point of the divided sub-regions is used as a node. Capacity calculation is performed on the adjacency width between regions to establish edge weights. A multi-source, multi-sink graph search model is established to obtain the estimated cabling path with the fewest intersections in the V-graph, such as... Figure 9 As shown.

[0043] Step S402: Determine the coarse routing result of the initial layout based on the mesh diagram.

[0044] The coarse routing result is the initial routing path that satisfies the routing task and achieves the goal of minimizing routing crossovers. The routing task is used to indicate the connection relationship between multiple pins in the initial layout.

[0045] The present invention determines the coarse wiring result based on the mesh graph in two main ways: one is to use a reinforcement learning model and mesh graph to determine the coarse wiring result, and the other is to use a mathematical model of wiring conflict iterative feedback and mesh graph to determine the coarse wiring result. The above two methods will be described in detail below, and will not be repeated here.

[0046] Step S403: Generate wiring geometry based on safety spacing and initial wiring path, and generate device geometry based on safety spacing and component information in the initial layout.

[0047] Among them, the safety clearance is the minimum distance between initial wiring paths specified to avoid electrical and physical risks.

[0048] Specifically, after obtaining the initial routing path, the initial routing path is constructed as a line object (LineString), and a safety gap (safe_gap) is added to the line object to obtain the following: Figure 10The routing geometry is shown; simultaneously, components such as pads, vias, and keep-away regions are constructed as polygon objects, and a safe gap is added to the polygon objects to obtain the following result: Figure 11 The device geometry is shown.

[0049] Step S404: Under the constraints of the device geometry, with the goal of satisfying the wiring constraints, optimize the position of the wiring geometry to obtain a fine wiring result.

[0050] Routing constraints can include wiring safety spacing, wiring angle constraints, and wiring width.

[0051] Specifically, after determining the wiring geometry and device geometry, the wiring geometry that overlaps in space is moved under the constraints of the device geometry so that all wiring geometries satisfy the wiring constraints. The wiring path when all wiring geometries satisfy the wiring constraints is the fine wiring result.

[0052] Coarse routing results are path planning results based on a mesh graph (such as a V-graph) search. They represent the predicted routing direction of loops, considering only connectivity and the number of routing intersections, but not the effects of routing width and safety spacing, and therefore do not fully meet design standards. Therefore, after obtaining the coarse routing results, they need to be transformed into fine routing results (detailed routing results) that satisfy routing constraints. For example, after obtaining... Figure 12 After the coarse routing result shown on the far left, the coarse routing result is legalized (rationalized) and gradually transformed into... Figure 12 The rightmost result shows the fine wiring result, while the middle result is a schematic diagram of the result obtained during the wiring legalization process.

[0053] The routing method provided in this embodiment first converts the initial layout diagram into a mesh diagram, then determines the coarse routing result based on the mesh diagram, and finally converts the coarse routing result into a fine routing result that satisfies routing constraints. By decoupling and splitting the routing problem that satisfies the requirements of connectivity, routing constraints, and minimizing the number of routing intersections into a two-stage solution, the solution complexity can be reduced, thereby significantly improving the solution speed. This allows for the achievement of a routing scheme with the fewest routing intersections in a shorter time, improving design efficiency and reducing design costs. Moreover, by combining the action reduction of the geometric push strategy and path optimization design, the coarse routing result is transformed into a fine routing result, which not only solves the problem of low conflict resolution efficiency in the traditional transformation process but also ensures routing quality through geometric optimization.

[0054] The routing method provided by this invention is applicable to single-sided board patch cord design, achieving a routing result with the minimum number of patch cord resistors. This routing method is also applicable to other routing scenarios, such as serving as initial input for multi-layer routing scenarios requiring the fewest vias, improving layout design efficiency and shortening delivery cycles.

[0055] This embodiment also provides another routing method that can be used in the aforementioned terminal device. This embodiment specifically illustrates the process of using a reinforcement learning module to determine the coarse routing result. Figure 13 This is a flowchart of another wiring method according to an embodiment of the present invention, such as... Figure 13 As shown, the process includes the following steps: Step S1301: Convert the initial layout of the circuit board into a mesh diagram.

[0056] Please see details Figure 4 Step S401 of the illustrated embodiment will not be described again here.

[0057] Step S1302: When the initial layout is of the target type, determine the coarse wiring result based on the target reinforcement learning model and the mesh diagram.

[0058] Step S1302 is a specific implementation of determining the coarse wiring result based on the mesh diagram (i.e., step S402 above).

[0059] Among them, the target type layout is a layout with corresponding wiring results and storage capacity greater than the preset capacity. The target reinforcement learning model is trained based on the target type layout and its corresponding wiring results.

[0060] The target type layout has a stable data distribution, high scene repeatability, and has accumulated a sufficient amount of interaction samples and feedback labels. The preset capacity is the threshold value of the amount of data required to train the reinforcement learning model to convergence. That is, by training the reinforcement learning model with the target type layout and corresponding wiring results of the preset capacity, the prediction accuracy of the obtained target reinforcement learning model can meet the requirements. The preset capacity can be determined by the designer according to the requirements.

[0061] Specifically, after obtaining the mesh diagram, if the initial layout is of the target type, the mesh diagram is input into the target reinforcement learning model, and the output of the target reinforcement learning model is determined as the coarse wiring result. The target reinforcement learning model includes an agent and a policy network.

[0062] For example, the training and inference process of a reinforcement learning model can be as follows: Figure 14As shown, firstly, the component information (location information) of the region is obtained from the old schematic (existing layout), and the path planning problem (routing task) of the component information is determined, such as the shortest path from node A to node B. Then, the topology dataset (node ​​information and connection relationship) is extracted from the old path planning problem, and the reinforcement learning model is trained based on the topology dataset.

[0063] Specifically, an interactive environment is constructed using a large amount of existing layout and routing information. By sampling the interaction data between the agent and the environment, the parameters of the graph neural network are updated using the Proximal Policy Optimization (PPO) algorithm and optimizer. The resulting routing policy (policy network) has real-time decision-making and dynamic perception capabilities.

[0064] After training is completed, the trained reinforcement learning model (i.e. the target reinforcement learning model) is deployed locally. After obtaining the new schematic, the topology of the new schematic is determined and the topology is input into the target reinforcement learning model (the trained policy network) to obtain the coarse wiring result.

[0065] Specifically, in the design of reinforcement learning models, the local mesh graph observable by the agent is modeled as the state space, and the neighbor nodes that the agent can reach in one step are set as the action space.

[0066] On the one hand, within the same wiring scenario, the sub-mesh graph structure centered on the agent's current position changes as the agent moves. On the other hand, in different wiring scenarios, the overall structure of the mesh graph varies significantly due to layout changes. To avoid differences between different wiring scenarios, it is necessary to control the complexity of the state space, reduce the learning difficulty, improve efficiency, and prevent local changes in complex states from causing overfitting of the value network, which in turn affects the updating of the policy network.

[0067] Meanwhile, to ensure the applicability and generalization ability of the reinforcement learning model, the form of the model's learnable parameters should not depend on the network structure in the current agent's field of vision. Based on this, in some embodiments, multi-layer ( k The policy network of the Graph Sampling and Aggregation (GraphSAGE) layer, through... k Layered graph sampling aggregation layers can extend the perceptual range of an agent to... k Neighboring nodes.

[0068] This invention employs GraphSAGE in the policy network for the following three considerations.

[0069] Firstly, GraphSAGE employs a fixed number of neighbor sampling strategies, ensuring it remains unaffected by the number of graph nodes. Secondly, GraphSAGE's aggregation layers (such as Mean aggregation, Max aggregation, and LSTM aggregation) are general functions independent of specific topologies, reducing the impact of differences in the grid graph structure. Thirdly, GraphSAGE uses inductive learning, learning feature extraction rules rather than memorizing structures, ensuring that learnable parameters do not depend on the current agent's vision network structure.

[0070] For example, in this embodiment k The policy network structure of layer GraphSAGE can be as follows: Figure 15 As shown, it includes a node feature input layer, an edge feature input layer, a node feature graph sampling aggregation layer (GraphSAGE-node), an edge feature graph sampling aggregation layer (GraphSAGE-edge), an intermediate fusion module (Fusion), a multilayer perceptron (MLP), and an output layer (Prob.).

[0071] The node feature input layer extracts node features from the subgraph and inputs them into GraphSAGE-node. GraphSAGE-node performs GraphSAGE operations on the nodes in the subgraph to generate node-level embedding representations, which are then input into Fusion. The edge feature input layer extracts edge features from the line graph and inputs them into GraphSAGE-edge. GraphSAGE-edge performs GraphSAGE operations on the edge nodes in the line graph to generate edge-level embedding representations, which are then input into Fusion. Fusion fuses the node-level and edge-level embedding representations to obtain a more comprehensive multimodal feature representation. The multimodal feature representation is represented in matrix form and input into the MLP. The MLP performs a nonlinear transformation on the fused feature matrix. The feature obtained after the nonlinear transformation is input into the output layer. The output layer transforms the output of the MLP into a probability distribution, which refers to the probability distribution of the agent's selectable action dimensions.

[0072] The subgraph is a local subgraph centered on the current node of the agent (target node). The local subgraph contains the neighboring nodes and connections of the target node. The line graph is a structural transformation of the edges. The edges connected to the target node in the subgraph are regarded as new nodes, and the adjacency relationship between edges (such as sharing the same node) is regarded as new edges.

[0073] The information represented by the node features includes the distance from the target node, whether it is occupied by the current agent path or other paths, and the remaining number of steps. The information represented by the edge features includes the remaining capacity and the heat. The remaining capacity is used to represent the remaining wiring area of ​​the wiring area where the corresponding edge is located. The heat is used to describe the busyness or attention level of the connection or related area. The heat can be determined by the following formula (1).

[0074]

[0075] In the formula, the initial capacity is used to represent the allowable wiring area of ​​the wiring area where the corresponding edge is located.

[0076] Specifically, the policy network in this embodiment extracts and fuses features from two perspectives: node features and edge features. It inputs the features of neighboring nodes into the same multilayer perceptron and finally outputs the probability distribution of the corresponding agent's selectable action dimensions.

[0077] For example, step S1302 above may include: Step S13021: Based on the node information of the mesh graph, determine the node features and edge features corresponding to the node where the agent is located.

[0078] Specifically, the node where the agent is located is the target node mentioned above. The node features are the features of the target node's neighboring nodes, and the edge features are the features of the edges connected to the target node. Node features include distance from the target node, whether it is occupied by the current agent's path or other paths, and the remaining number of steps; edge features include remaining capacity and popularity.

[0079] Node information includes information indicating whether a node is occupied and distance information. If the first node is occupied by the agent but the distance to the first node has not reached its maximum value, the first node is marked as unoccupied. The first node is a node in the local mesh graph corresponding to the agent, excluding the starting node and the target node. It should be noted that the starting node and the target node cannot be set as occupied nodes.

[0080] Node information encoding can be as follows Figure 16 As shown, for example, when the first node is occupied, the distance information of the first node can be the product of the maximum distance between unoccupied nodes in the local mesh graph and the penalty coefficient. The penalty coefficient can reflect the occupancy status of the wired area corresponding to the first node, enhancing the agent's perception of occupied nodes and avoiding intersections and collisions. Here, a collision indicates that two initial wired paths overlap.

[0081] Step S13022: Input the node features and edge features into the policy network, and determine the action set of the agent based on the output of the policy network.

[0082] The action set includes at least one optional action and the probability corresponding to each optional action. The output of the policy network is the action set of the agent.

[0083] Step S13023: Determine the next action of the agent based on the probability of the optional action and whether the optional action will cause path crossing, so as to obtain the coarse wiring result.

[0084] Specifically, the action with the highest probability that will not cause path intersection in the action set is determined as the agent's next action, i.e. the next node selected by the agent. The node position of the agent is updated, and the above steps S13021 to S13023 are re-executed until all nodes are connected, and the coarse wiring result is obtained.

[0085] For example, the process of determining the coarse wiring result using a reinforcement learning model can be as follows: Figure 17 As shown, the topology extracted from the mesh graph is input into the wiring strategy (strategy model) to obtain an action set. For example, the action set may include a first action with a probability of 0.75 and a second action with a probability of 0.25. After obtaining the action set, a reinforcement learning-based mechanism can determine whether an action in the action set will cause a path intersection based on the edge weights and existing paths and perform real-time avoidance. For example, if it is determined that the first action with the highest probability will cause a path intersection, an action mask is added to block the first action, so that the agent selects the second action with a probability of 0.25 as the next action and updates the topology information; if it is determined that the first action with the highest probability will not cause a path intersection, the agent selects an action according to probability, that is, the first action with the highest probability is selected as the next action and the topology information is updated.

[0086] This embodiment adopts k The policy network structure of the GraphSAGE layer determines the agent's next action based on the probability of optional actions and whether the optional actions will cause path intersections. This endows the wiring policy with real-time decision-making capabilities, thereby improving the algorithm's solution speed. In other words, the policy network in this embodiment not only has basic pathfinding capabilities but also real-time decision-making capabilities.

[0087] In some embodiments, the number of agents is multiple, the mesh graph includes multiple local mesh graphs, and the multiple agents are associated with the multiple local mesh graphs. Figure 1 With one-to-one correspondence, multiple agents can perform wiring simultaneously. In this case, step S13021 specifically involves: determining the node features and edge features of the agent corresponding to the local mesh graph based on the node information of the local mesh graph.

[0088] Specifically, in a multi-line synchronization scenario (where multiple agents simultaneously wire multiple pins to be connected), the environment in which the agents operate changes from a steady state to a dynamic state. As the time step progresses, the obstacle information within the agent's observable space becomes dynamic, mainly due to node occupancy caused by the movement of other agents and the dynamic updating of prior information (distance information from the target node in the node feature vector) caused by changes in the graph model's topology.

[0089] To ensure the stability of the routing policy inference obtained through training, sufficient dynamic factors need to be simulated during the training process. Therefore, unlike the sampling of single-episode data in traditional coarse-grained routing of network flows, such as... Figure 18 As shown, multiple agents are deployed to interact with the simulated wiring scenario in real time, introducing sufficient dynamic factors into the agents' observation space. Simultaneously, the system detects in real time whether collisions or path intersections cause trajectory interruptions, and samples multiple sets (multi-scene) of data for policy updates. This enables the current agent to effectively perceive and avoid other agents and their paths, improving the stability of the wiring strategy in dynamic environments.

[0090] Furthermore, in multi-line synchronization scenarios, different wiring scenarios exhibit certain differences, making it difficult to determine the number of agents (which depends on the number of point pairs to be connected). For example, training multiple agents in scenario A yields a converged policy network based on the dynamic environment of scenario A. Neither the policy network nor the number of agents may be applicable to scenario B. To address this issue, this invention employs policy isomorphism (i.e., multiple agents use the same policy network) to achieve a universal wiring model, ensuring stable and generalizable wiring performance across graphs of different sizes, layouts, and numbers of point pairs to be connected.

[0091] Since the state is based on local information, such as Figure 19 As shown in (a), the strategy optimized on a small-scale mesh graph can be transferred to a large-scale mesh graph, avoiding poor generalization caused by differences in graph size. The routing strategy is trained by using the PPO algorithm combined with a dynamic perception-enhanced sampling mechanism.

[0092] In multi-line synchronization scenarios, due to the presence of multiple agents in the same wiring environment, a different graph topology information update and encoding mechanism is needed when encoding node information compared to a single agent. To more accurately calculate global prior information (the distance between a node and the target node) while maintaining the optimized dynamic perception capabilities of the agents, after obtaining the agent's next action, not only is the node information of the local mesh graph updated, but also the node information of the overall mesh graph and the mesh graph containing prior information are updated based on the updated node information from multiple local mesh graphs.

[0093] In other words, after obtaining the next action of the intelligent agent, it is also necessary to maintain... Figure 19 (b) and Figure 19 (c) Figure 19 (b) preserves the complete topological structure of the mesh graph for agent state generation. Figure 19 (c) contains prior information.

[0094] Step S1303: Generate wiring geometry based on safety spacing and initial wiring path, and generate device geometry based on safety spacing and component information in the initial layout.

[0095] Please see details Figure 4 Step S403 of the illustrated embodiment will not be described again here.

[0096] Step S1304: Under the constraints of the device geometry, with the goal of satisfying the wiring constraints, optimize the position of the wiring geometry to obtain a fine wiring result.

[0097] Please see details Figure 4 Step S404 of the illustrated embodiment will not be described again here.

[0098] In this embodiment, the policy network utilizes a large amount of historical data for learning, enabling real-time obstacle avoidance during the agent's path planning process and significantly improving the solution speed of the coarse-wired network flow model. Simultaneously, it ensures the applicability of the framework in diverse topology scenarios. Furthermore, the adoption of a graph topology information update and encoding mechanism facilitates the agent's dynamic information perception and obstacle avoidance strategy learning during model training, enhancing the robustness and wiring performance of the solution.

[0099] Specifically, the initial layout may not be the target type layout, but rather a customized layout based on the user's specific needs. This layout may contain newly added functional modules, heterogeneous scene features, and unseen constraint combinations. Its data sample size is limited, and its feature distribution differs from historical data. Figure 11 The wiring method shown may have poor generalization due to insufficient training data, resulting in a decrease in the accuracy of the coarse wiring results.

[0100] Based on this, this embodiment also provides another wiring method that can be used in the aforementioned terminal device. This embodiment specifically illustrates the process of determining the coarse wiring result using a mathematical model of wiring conflict iterative feedback. Figure 20 This is a flowchart of another wiring method according to an embodiment of the present invention, such as... Figure 20 As shown, the process includes the following steps: Step S2001: Convert the initial layout of the circuit board into a mesh diagram.

[0101] Please see details Figure 4 Step S401 of the illustrated embodiment will not be described again here.

[0102] Step S2002: When the initial layout is of the target type, determine the coarse wiring result based on the target reinforcement learning model and the mesh diagram.

[0103] Please see details Figure 13 Step S1302 of the illustrated embodiment will not be described again here.

[0104] Step S2003: When the initial layout is not the target type, determine the coarse routing result according to the constraint relaxation flow model.

[0105] Among them, the constrained relaxation flow model is a mathematical model based on a mesh graph. The constrained relaxation flow model can include functions and constraints that characterize the number of connected loops and the length of loops in the mesh graph.

[0106] Specifically, after determining the routing task and constraints, the constraints are first relaxed to obtain initial constraints. Relaxation involves loosening the constraints to a certain extent, but this relaxation is not indiscriminate; rather, it increases the flexibility of routing while ensuring a certain performance baseline. Then, a flow network model is constructed, abstracting the routing region represented by the mesh graph into a flow network. The pins of circuit elements serve as nodes in the flow network, and possible routing paths are treated as edges. Each edge is assigned corresponding attributes, such as capacity (analogous to the flow rate the path can carry, reflecting the number of wires allowed to pass) and cost (reflecting the cost of routing along the path, such as path length and potential interference). Relevant algorithms from graph theory and operations research (such as the maximum flow algorithm and the minimum cost maximum flow algorithm) are used to analyze the constructed flow network model and solve for the optimal flow distribution. During this process, by adjusting the degree of constraint relaxation and the parameters of the flow network model, different routing schemes can be obtained, and the routing scheme with the fewest routing intersections is determined as the coarse routing result.

[0107] For example, step S2003 above may include: Step a1: Under the condition of satisfying the routing task, solve the constrained relaxation flow model with the optimization objectives of maximizing the number of connected loops and minimizing the length of loops to obtain the initial coarse routing results.

[0108] The optimization objective is to maximize the number of connected loops and minimize the length of the connected loops, while keeping the connected paths as short as possible.

[0109] Step a2: If there are conflicting edges in the initial coarse wiring result, add the conflicting edges as constraints to the constraint relaxation flow model and solve it again until there are no conflicting edges or the number of solutions reaches the maximum limit.

[0110] Step a3: The initial coarse wiring result without conflicting edges is determined as the coarse wiring result, or the initial coarse wiring result after the number of solutions reaches the maximum limit is determined as the coarse wiring result.

[0111] Specifically, the mathematical expression for maximizing the number of connected loops and minimizing the length of loops, as well as the expression for the initial constraint condition (st) of the constrained relaxed flow model, can be shown in Equation (2):

[0112] In the formula, Weights representing the number of connected components i Indicates a loop. N Indicates the number of loops. Representing a circuit i Whether it is connected, The weight representing the line length, e Represents an edge. E Indicates the number of edges. Representing a circuit i Selected edge e Traffic, Representing an edge e Cost (line length) e + and e－ Representing an edge e For the two nodes, constraint 1 represents the law of conservation of flow, for the loop i When the side e When selected, the edge e nodes e + and e－ If a node is an intermediate node (neither the start nor the end point), then for the edge... e Inflow equals outflow; constraint 2 indicates that when the loop... i When a connection is established, there must be traffic. Representing an edge e The capacity, when the circuit i When the edges are not connected, the flow is 0; constraint 3 represents an edge capacity constraint, meaning that the flow must not exceed the edge capacity. e The capacity, constraint 4 indicates the variable Value constraints, constraint 5 indicates that the variable Value constraints.

[0113] Specifically, such as Figure 21As shown, after constructing the constraint relaxation flow model, the constraint relaxation flow model is solved based on the above formula (2) to obtain the initial coarse wiring result. Then, it is determined whether the edges in the initial coarse wiring result cause conflicts. If a conflict occurs, the conflicting edge is added as a constraint condition to the constraint relaxation flow model, and iterative solution is performed until the generated solution has no conflicting edges or the number of solutions (iterations) reaches the maximum limit, and the final result (i.e., the coarse wiring result) is obtained. When a conflicting edge is generated, the newly added constraint condition can be as shown in formula (3):

[0114] In the formula, j , k , and h Represents four distinct edges, a cycle and loop i When sharing the same node, the newly added constraint means that if there are four edges in the paths of two different network loops that cause intersection conflicts, then the new constraint restricts these four edges from being selected as the initial routing paths of the two different loops at the same time.

[0115] The solutions obtained above will be labeled as high-quality training samples and added to the training set of the policy network. In this way, on the one hand, the new samples expand the feature coverage of the model, enabling it to gradually acquire the ability to handle similar new modules; on the other hand, the optimal results provide supervision signals for the policy network, accelerating the convergence of the model in the new feature space. This approach leverages the efficient processing capability of reinforcement learning for standardized scenarios, ensures the reliability of decisions for new modules through accurate solutions, and achieves continuous algorithm evolution through sample closure.

[0116] Step S2004: Generate wiring geometry based on safety spacing and initial wiring path, and generate device geometry based on safety spacing and component information in the initial layout.

[0117] Please see details Figure 4 Step S403 of the illustrated embodiment will not be described again here.

[0118] Step S2005: Under the constraints of the device geometry, with the goal of satisfying the wiring constraints, optimize the position of the wiring geometry to obtain a fine wiring result.

[0119] Please see details Figure 4 Step S404 of the illustrated embodiment will not be described again here.

[0120] In this embodiment, when the initial layout is not the target type, the coarse wiring result is determined based on the constraint relaxation flow model. This allows for the direct solution of the global optimum of the initial layout without relying on historical data, ensuring decision-making accuracy in unknown scenarios. Furthermore, by introducing restricted cross constraints through column generation iteration, the coarse wiring result is generated. This avoids the increased solution complexity and drastically increased solution time caused by directly adding cross-constraints to the mathematical model, thus improving the solution speed.

[0121] This embodiment also provides another wiring method, which can be used in the aforementioned terminal device. Figure 22 This is a flowchart of another wiring method according to an embodiment of the present invention, such as... Figure 22 As shown, the process includes the following steps: Step S2201: Convert the initial layout of the circuit board into a mesh diagram.

[0122] Please see details Figure 4 Step S401 of the illustrated embodiment will not be described again here.

[0123] Step S2202: When the initial layout is of the target type, determine the coarse wiring result based on the target reinforcement learning model and the mesh diagram.

[0124] Please see details Figure 13 Step S1302 of the illustrated embodiment will not be described again here.

[0125] Step S2203: When the initial layout is not the target type, determine the coarse routing result according to the constraint relaxation flow model.

[0126] Please see details Figure 20 Step S2003 of the illustrated embodiment will not be described again here.

[0127] Step S2204: Generate wiring geometry based on safety spacing and initial wiring path, and generate device geometry based on safety spacing and component information in the initial layout.

[0128] Please see details Figure 4 Step S403 of the illustrated embodiment will not be described again here.

[0129] Step S2205: Under the constraints of the device geometry, with the goal of satisfying the wiring constraints, optimize the position of the wiring geometry to obtain a fine wiring result.

[0130] For example, if there are multiple wiring geometries and the initial wiring path includes multiple loops, step S2205 may include: Step 22051: Traverse the wiring geometry and identify the second wiring geometry that spatially overlaps with the first wiring geometry to form a conflict set.

[0131] The first routing geometry can be any one of multiple routing geometries, and the routing geometry can be traversed using the Depth-First Search (DFS) algorithm.

[0132] The core idea of ​​depth-first search is to start from a certain starting node in the graph, explore the nodes of the graph as deep as possible along a path, until it is impossible to continue or the target condition is reached, and then backtrack to the previous node to continue exploring other unvisited paths.

[0133] In some embodiments, before traversing the routing geometry, the routing method further includes: storing multiple routing geometries using an STR (Sort-Tile-Recursive) tree; in this case, step 22051 above specifically involves: determining a second routing geometry through the STR tree to form a conflict set.

[0134] Specifically, a spatial index is constructed using an STR tree. Based on the characteristics of the STR tree, global coverage of conflict paths can be achieved and a dynamic spatial index can be built. The routing result lines are represented by both center lines and bounding boxes to establish a dynamically updated global spatial index, which solves the problem that traditional indexes only support static entities and cannot adapt to dynamic adjustments in routing.

[0135] For each initial routing path to be inspected, a dynamic buffer region (i.e., an irregular area extending from the centerline to both sides of the buffer region, rather than a traditional fixed rectangle) is automatically generated based on the safety distance constraints of the routing design (such as minimum line spacing and line-pad spacing). This transforms the initial routing path into a routing geometry. Using the STR tree's region intersection query function, all adjacent routings (candidate lines) that spatially overlap with the buffer region can be accurately filtered out, and conflict types (such as line-to-line conflicts and line-to-pad conflicts) are automatically marked, forming a conflict set for each routing geometry (i.e., each initial routing path).

[0136] By introducing STR trees, the time complexity of conflict lookup can be reduced from O(n^2) to O(n^2). 2 The time complexity is reduced to O(n log n), and the problem of missing edge region conflicts in traditional traversal can be avoided.

[0137] Step 22052: Based on the conflict set, determine at least one pushing loop.

[0138] Among them, the pushing loop is a loop with conflict points among multiple loops.

[0139] Step 22053: Perform push processing on the wiring geometry in at least one push loop to obtain the push result.

[0140] Specifically, to satisfy wiring constraints, the wiring geometry at conflict points in each push loop is offset. For example, the position of the device geometry (or obstacle) can be as follows: Figure 23 As shown, the results before and after the push can be as follows: Figure 24 As shown.

[0141] Step 22054: Update the positions of multiple routing geometries based on the pushing results, and return to the step of forming a conflict set until multiple routing geometries satisfy the routing constraints or the number of updates reaches the preset number of updates.

[0142] Optionally, step 22053 above may include: Step b1: Identify the associated loops that intersect with the first pushing loop, and geometrically merge the conflict areas of the associated loops and the first pushing loop to form a unified pushing area.

[0143] The first pushing circuit is one of at least one pushing circuit.

[0144] Step b2: Offset the wiring geometry of the unified pushing area according to the target pushing order and the target pushing sequence.

[0145] Among them, the target pushing order is used to characterize the order in which the wiring geometry of the unified pushing area is offset, and the target pushing sequence is used to characterize the direction in which the wiring geometry is offset.

[0146] Specifically, traditional push-pull schemes often process each conflicting loop (push-pull loop) separately, leading to repeated push-pulls and redundant actions. This embodiment adopts a merged push-pull operation. For the first push-pull loop, it first traverses all loops in its conflict set through geometric topology analysis to identify associated loops that intersect with the first push-pull loop; then, it geometrically merges the conflict areas of these associated loops with the first push-pull loop (merging conflicting loops and pads in the associated loops into one unit) to form a unified push-pull area. Subsequently, only one push-pull action needs to be performed on the unified push-pull area to simultaneously resolve conflicts of multiple loops, which can significantly improve push-pull efficiency compared to the traditional single-loop push-pull operation on trace units.

[0147] In cabling conflict scenarios, the determination of the target pushing order should be based on the core objective of not violating the core design constraints and minimizing the impact on the overall cabling quality, rather than relying on a single fixed direction (such as simply from left to right or from right to left). A reasonable target pushing order should be designed by combining the following multi-layered criteria for comprehensive decision-making.

[0148] First, predefine routing priorities (e.g., power lines > high-speed differential signal lines > general signal lines > ground lines). When a conflict occurs, lower-priority routing should be pushed in a direction that does not interfere with higher-priority routing, preferably shifting to open areas away from higher-priority routing to avoid impedance abrupt changes and increased crosstalk in higher-priority signals due to pushing. Second, determine the pushing space based on space availability constraints. By analyzing the physical environment around the conflict area, prioritize directions with "no fixed obstacles and sufficient routing slack." Third, consider the overall layout balance. If pushing in one direction may lead to overcrowding in a local area (e.g., concentrating all conflicting routing in a corner) or exceeding the boundary, the direction needs to be dynamically adjusted.

[0149] In summary, the target pushing order is a comprehensive decision-making process that prioritizes rules, adapts to spatial conditions, and ensures signal coverage. It adaptively sorts data based on the start and end points of different data loops and the loop priority to ensure pushing quality.

[0150] For example, the wiring geometry corresponding to the two furthest conflict points in a unified pushing area can be prioritized as the target pushing order.

[0151] To avoid wasting space due to blind pushing, this embodiment adopts the principle of prioritizing the furthest conflict point to offset the wiring geometry of the unified pushing area. Specifically, the distance between the first pushing loop and all conflict points of each loop in the conflict set is calculated, and then the offset is performed in descending order of distance, that is, the two conflict points with the furthest distance are processed first.

[0152] In this embodiment, pushing at the furthest point of conflict can resolve all conflicts at once, avoiding the problem of "segmented pushing and multiple adjustments" caused by pushing from the endpoint. At the same time, the pushing direction is determined based on this point and the surrounding space margin (such as being far away from the board edge and avoiding high-priority wiring areas), further reducing the need for repeated corrections of the pushing action.

[0153] In some embodiments, step b2 above may include: Step b21: Perform polygon fitting on the geometry between conflict points of the wiring geometry to extract all feasible paths within the wiring area.

[0154] Step b22: With the goal of minimizing the path length and the number of bends, determine the optimal feasible path from all feasible paths.

[0155] Step b23 updates the path indicated by the wiring geometry to the optimal feasible path.

[0156] Specifically, traditional pushing often involves directly offsetting existing paths, which can easily lead to excessive path detours and low space utilization. This embodiment achieves path rationalization by extracting the geometric contours of conflict areas and optimizing the shortest path.

[0157] like Figure 25 As shown, firstly, polygon fitting is performed on the geometry between conflict points on both sides of the reference anchor point (such as the boundary of the conflict area and the outline of the surrounding free area) to extract all feasible paths (all feasible contours) within the routing area; then, based on the dual objective function of the shortest path length and the fewest bends, the optimal feasible contour is selected (e.g., the contour that only requires one 135° bend is preferred over the contour with multiple right-angle bends); then the selected optimal feasible contour (optimal feasible path) is used to replace the original conflict path, and the global routing results and STR tree index are updated synchronously to ensure the real-time performance of subsequent conflict detection.

[0158] In this embodiment, by leveraging the global high-efficiency search capability of the STR tree spatial index, combined with the action reduction and path optimization design of the DFS geometric push strategy, the problem of low efficiency in traditional conflict resolution is solved, and the wiring quality is ensured through geometric optimization.

[0159] The wiring process will be explained below in conjunction with the attached diagram, using a single-sided patch cord design as an example.

[0160] like Figure 26 As shown, after obtaining the initial layout of the circuit board, the routing area information is first extracted, and then the initial layout is transformed into a V-graph based on the routing area information. Edges that are equidistant and connected are merged to simplify the mesh structure. After obtaining the V-graph, it is determined whether the introduced new module data (initial layout) is a layout with sufficient stock (greater than the preset capacity) and routing results.

[0161] When the available resources are sufficient, a reinforcement learning approach is used to obtain coarse-wired results. When the available resources are insufficient, a mathematical modeling approach is used to obtain coarse-wired results. After obtaining the coarse-wired results, a combination of depth-first search (DFS) and geometric push approaches is used to transform the coarse-wired results into fine-wired results.

[0162] The process of converting coarse routing results into fine routing results can be as follows: Figure 27 As shown, after obtaining the coarse routing results, the target pushing order is first determined, then the STR tree is constructed, and a spatial index of the routing geometry is established. Then, combined with the safety distance constraints of the routing design, the dynamic buffer area of ​​each routing is automatically generated, and all adjacent routings that have spatial overlap with the dynamic buffer area are filtered out to form the conflict set of each routing. The conflict tree is determined based on the conflict set of each routing.

[0163] Afterwards, conflicts are merged to form unified pushing units. To avoid wasting space due to blind pushing, a pushing order (pushing direction) is established, prioritizing the farthest conflict points. Then, according to the pushing order, the optimal path for each path to be pushed is determined through geometric contour extraction of the conflict area and shortest path optimization. After replacing the original conflict path with the optimal path, the spatial index of the currently updated path is updated through the STR tree, and its conflict status with other nodes in the association tree is queried again.

[0164] If conflicts still exist (e.g., a new conflict arises with C after pushing B), then C is added back to the conflict association tree as a path to be pushed, and a depth-first search is performed to complete the traversal, updating the conflict chain before pushing loop B again to ensure no omissions. If no conflicts exist, the next level of pushing is performed, and it is determined whether all conflicts have been resolved or whether the maximum number of iterations has been reached. The wiring result with all conflicts resolved or the wiring result with the maximum number of iterations reached is the detailed wiring result.

[0165] This application addresses the problems of slow global conflict location, redundant pushing actions, and inefficient space utilization in traditional conflict resolution methods. It innovatively integrates STR tree spatial indexing technology and hierarchical geometric optimization logic to construct a closed-loop process that includes global conflict determination, conflict loop merging, directional pushing action reduction, and optimal contour adaptive extraction, thereby achieving a dual improvement in conflict resolution efficiency and cabling quality.

[0166] This embodiment also provides a wiring device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0167] This embodiment provides a wiring device, such as Figure 28 As shown, it includes: The conversion module 2801 is used to convert the initial layout of the circuit board into a mesh diagram. The mesh diagram includes multiple nodes and a mesh corresponding to each node. The node is used to represent a pin in the initial layout diagram, and the mesh is used to represent the routable area of ​​the corresponding node. The coarse routing result generation module 2802 is used to determine the coarse routing result based on the mesh diagram, wherein the coarse routing result is the initial routing path that satisfies the routing task and achieves the goal of minimizing routing crossovers; The geometry generation module 2803 is used to generate wiring geometry based on safety spacing and initial wiring path, and to generate device geometry based on safety spacing and component information in the initial layout. The fine wiring result generation module 2804 is used to optimize the position of the wiring geometry under the constraints of the device geometry, with the goal of satisfying the wiring constraints, and obtain fine wiring results.

[0168] The wiring apparatus provided in this embodiment of the invention can execute the wiring method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects for executing the method. Further functional descriptions of the various modules and units described above are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0169] Figure 29 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0170] The following is a detailed reference. Figure 29 The diagram illustrates a structural schematic suitable for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 2901, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 2902 or a program loaded from memory 2908 into random access memory (RAM) 2903. The RAM 2903 also stores various programs and data required for the operation of the electronic device. The processor 2901, ROM 2902, and RAM 2903 are interconnected via bus 2904. An input / output (I / O) interface 2905 is also connected to bus 2904.

[0171] Typically, the following devices can be connected to I / O interface 2905: input devices 2906 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 2907 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 2908 including, for example, magnetic tapes, hard disks, etc.; and communication devices 2909. Communication device 2909 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 29 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0172] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 2909, or installed from a memory 2908, or installed from a ROM 2902. When the computer program is executed by the processor 2901, it performs the functions defined in the wiring method of the embodiments of the present invention.

[0173] Figure 29 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0174] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the wiring method shown in the above embodiments is implemented.

[0175] A portion of this invention can be applied to computer program products, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installation program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0176] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A wiring method, characterized in that, The wiring method includes: The initial layout of the circuit board is converted into a mesh diagram, wherein the mesh diagram includes multiple nodes and meshes corresponding to the multiple nodes one by one. The nodes are used to represent a pin in the initial layout diagram, and the meshes are used to represent the routable area of ​​the corresponding node. Based on the mesh diagram, the coarse routing result of the initial layout is determined, wherein the coarse routing result is the initial routing path that satisfies the routing task and achieves the goal of minimizing routing crossovers; Based on the safety spacing and the initial wiring path, a wiring geometry is generated, and based on the safety spacing and the component information in the initial layout, a device geometry is generated. Under the constraints of the device geometry, and with the goal of satisfying the wiring constraints, the position of the wiring geometry is optimized to obtain a fine wiring result.

2. The wiring method according to claim 1, characterized in that, The step of determining the coarse routing result of the initial layout based on the mesh diagram includes: When the initial layout is of the target type, a coarse wiring result is determined based on the target reinforcement learning model and the mesh graph, wherein the target type is a layout with a corresponding wiring result and a storage capacity greater than a preset capacity.

3. The wiring method according to claim 2, characterized in that, The target reinforcement learning model includes an agent and a policy network employing a multi-layer graph sampling aggregation layer. Determining the coarse wiring result based on the target reinforcement learning model and the mesh graph includes: Based on the node information of the mesh graph, determine the node features and edge features corresponding to the node where the agent is located; The node features and edge features are input into the policy network, and the action set of the agent is determined according to the output of the policy network. The action set includes at least one optional action and the probability corresponding to each optional action. Based on the probability of the optional action and whether the optional action will cause path crossing, the next action of the agent is determined to obtain the coarse wiring result.

4. The wiring method according to claim 3, characterized in that, The number of agents is multiple, the mesh graph includes multiple local mesh graphs, and each agent corresponds one-to-one with one of the local mesh graphs. All agents employ the same policy network. The step of determining the node features and edge features corresponding to the node selected by the agent based on the node information of the mesh graph includes: Based on the node information of the local mesh graph, determine the node features and edge features of the agent corresponding to the local mesh graph.

5. The wiring method according to claim 4, characterized in that, After obtaining the next action of the agent, the wiring method further includes: Update the node information of the local mesh graph; Based on the updated node information of the multiple local mesh graphs, update the node information of the mesh graph and update the node information of the mesh graph containing prior information.

6. The wiring method according to claim 4 or 5, characterized in that, The node information includes information indicating whether a node is occupied and distance information. When a first node is occupied by the agent but the distance corresponding to the first node does not reach the maximum value, the first node is marked as unoccupied. The first node is a node in the local mesh graph corresponding to the agent, excluding the starting node and the target node.

7. The wiring method according to any one of claims 1 to 5, characterized in that, The grid diagram is a Voronoi diagram.

8. The wiring method according to claim 1, characterized in that, The step of determining the coarse routing result of the initial layout based on the mesh diagram includes: When the initial layout is not the target type, the coarse routing result is determined according to the constraint relaxation flow model.

9. The wiring method according to claim 8, characterized in that, The determination of the coarse wiring result based on the constrained relaxation flow model includes: Under the condition of satisfying the routing task, the constrained relaxation flow model is solved with the optimization objectives of maximizing the number of connected loops and minimizing the length of loops to obtain the initial coarse routing result. If there are conflicting edges in the initial coarse wiring result, the conflicting edges are added as constraints to the constraint relaxation flow model and the solution is repeated until there are no conflicting edges or the number of solutions reaches the maximum limit. The initial coarse wiring result without conflicting edges is determined as the coarse wiring result, or the initial coarse wiring result after the number of solutions reaches the maximum limit is determined as the coarse wiring result.

10. The wiring method according to any one of claims 1 to 5, characterized in that, The number of wiring geometries is multiple, and the initial wiring path includes multiple loops. Under the constraints of the device geometry, and with the goal of satisfying wiring constraints, the position of the wiring geometries is optimized to obtain a fine wiring result, including: Traverse the wiring geometry to identify a second wiring geometry that spatially overlaps with the first wiring geometry, forming a conflict set, wherein the first wiring geometry is any one of the plurality of wiring geometries; Based on the conflict set, at least one pushing loop is determined, wherein the pushing loop is a loop among the plurality of loops that has a conflict point; The wiring geometry in at least one of the push-out loops is pushed out to obtain a push-out result. The positions of the multiple wiring geometries are updated based on the pushing results, and the step of forming a conflict set is returned until the multiple wiring geometries satisfy the wiring constraints or the number of updates reaches the preset number of updates.

11. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory storing computer instructions, and the processor executing the computer instructions to perform the wiring method of any one of claims 1 to 10.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the wiring method according to any one of claims 1 to 10.

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