Time synchronization method, distributed network system, electronic equipment, medium and product

Abstract

The invention relates to the technical field of computers, in particular to a time synchronization method, a distributed network system, electronic equipment, a medium and a product. In the method, each device in the distributed network system respectively synchronizes data plane time and management plane time through a hardware clock and a software clock. Wherein the data plane time of the master device is the hardware time of the hardware clock, and the management plane time of the master device is the UTC time of the software clock. Therefore, the management plane time synchronization of each device in the distributed network system can be realized through a software clock, an additional hardware clock is not needed, and the hardware deployment cost can be reduced.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a time synchronization method, a distributed network system, electronic equipment, media, and products. Background Technology

[0002] In computer systems and networks, time synchronization methods based on dual time axes are widely used. This method introduces two independent time axes: data plane time and management plane time. Data plane time is used for processes that are not sensitive to changes in Coordinated Universal Time (UTC), such as data transmission and real-time control (e.g., sensing, planning and control, positioning). Management plane time is used for processes that must be consistent with UTC time, such as system administration and logging (e.g., log services).

[0003] Existing time synchronization methods are based on two hardware clocks. For example, a distributed network system includes multiple devices, each of which needs to be configured with two hardware clocks: one for the management plane time (hereinafter referred to as the management hardware clock) and the other for the data plane time (hereinafter referred to as the data hardware clock). Configuring two hardware clocks for each device results in high hardware costs. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a time synchronization method, a distributed network system, an electronic device, a medium, and a product.

[0005] Firstly, this application provides a time synchronization method applied to a distributed network system, which includes a master device and at least one slave device. The master device includes a master software clock and a master hardware clock, and the slave device includes a slave software clock and a slave hardware clock. The master device can send a first time message to the slave device, wherein the first time message may include: a first hardware time of the master hardware clock when the master device sends the first time message, and a first UTC time of the master software clock when the master device sends the first time message. The slave device determines the transmission duration of the first time message based on the first hardware time in the received first time message and a second hardware time of the slave hardware clock in the slave device, and adjusts the time of the slave software clock to the second UTC time based on the first UTC time in the received first time message and the transmission duration of the first time message, so as to achieve time synchronization between the master software clock and the slave software clock, that is, to achieve time synchronization between the management plane of the master device and the slave device.

[0006] Thus, in the time synchronization method provided in this application embodiment, each device in the distributed network system can synchronize and manage the time using a software clock, without the need for an additional hardware clock, which can reduce hardware deployment costs.

[0007] It is understandable that the initial value of the master software clock can come from the master hardware clock of the master device, but the master software clock does not depend on the master hardware clock during operation; instead, it is maintained independently by the kernel of the master device's operating system. Similarly, the slave software clock of the slave device does not depend on the slave hardware clock; it only uses the slave hardware clock's time when the slave software clock is synchronized with the master software clock.

[0008] In this embodiment, the time of the master software clock of the master device can be used as the time reference for one time axis (e.g., the management plane time axis), and the time of the master hardware clock of the master device can be used as the reference for another time axis (e.g., the data plane time axis). Thus, the time synchronization method provided in this embodiment can achieve dual-time axis time synchronization using a single hardware clock. Each device in the distributed system only needs one hardware clock, which can reduce hardware costs and system complexity, and is easy to deploy and maintain.

[0009] In one possible implementation of the first aspect described above, the transmission duration of the first time message is the time difference between the first hardware time in the first time message and the second hardware time of the slave hardware clock in the slave device, and the second UTC time is the sum of the first UTC time in the first time message and the transmission duration of the first time message.

[0010] In one possible implementation of the first aspect described above, before the master device sends the first time message to the slave device, the method further includes: the master device sending a second time message to the slave device, the second time message including: a third hardware time of the master hardware clock when the master device sends the second time message, and a transmission link delay when transmitting the second time message; the slave device determining a target frequency of the slave hardware clock based on the third hardware time and transmission link delay in the received second time message, and adjusting the frequency of the slave hardware clock to the target frequency, so that the time of the slave hardware clock is synchronized with the time of the master hardware clock; or, the slave device determining a time difference between the third hardware time and the fourth hardware time based on the third hardware time in the received second time message, the transmission link delay, and a fourth hardware time of the slave hardware clock when the slave device receives the second time message, and adjusting the time of the slave hardware clock based on the determined time difference, so that the time of the slave hardware clock is synchronized with the time of the master hardware clock.

[0011] It is understandable that strategies for synchronizing hardware clock time can include frequency modulation (FM) and stepping (AM) strategies. FM strategy refers to the slave device indirectly modifying the slave clock's time by changing its frequency to smoothly approximate the master clock's time. Stepping strategy refers to the slave device directly modifying the slave clock's time to make it approximately equal to the master clock's time.

[0012] In some embodiments, when the slave device receives the second time message, it can determine the time difference between the third hardware time and the fourth hardware time (i.e., the time difference between the master hardware clock time and the slave hardware clock time) based on the third hardware time in the received second time message, the transmission link delay, and the fourth hardware time of the slave hardware clock when the slave device receives the second time message.

[0013] When the time difference between the master and slave hardware clocks is less than a preset threshold, the slave device can use a frequency modulation strategy to synchronize its time with the master hardware clock. This ensures that the slave hardware clock remains continuous without jumps and guarantees the system stability of the slave device. When the time difference between the master and slave hardware clocks exceeds a preset threshold, the slave device can use a stepping strategy to synchronize its time with the master hardware clock.

[0014] It should be noted that the aforementioned preset threshold can be set according to actual application requirements, such as 1 millisecond, 128 milliseconds, 500 milliseconds, etc., and this application does not limit it. It is understood that a time difference between the slave hardware clock and the master hardware clock greater than the preset threshold indicates a serious time deviation between the two hardware clocks, which may constitute a systemic risk. In the embodiments of this application, when the time difference between the slave hardware clock and the master hardware clock is large, the time of the slave hardware clock can be directly adjusted in steps to quickly eliminate serious errors and prevent long-term accumulation of errors.

[0015] Furthermore, as mentioned earlier, hardware clocks can provide a high-precision time base. By modifying the frequency of the slave hardware clock, the time of the slave hardware clock can gradually approach the time of the master hardware clock, thereby achieving a time synchronization accuracy of microseconds between the master and slave hardware clocks.

[0016] In one possible implementation of the first aspect described above, the master device further includes a master monotonically increasing clock, and the slave device further includes a slave monotonically increasing clock; the method further includes: the master device periodically calculating a first hardware time deviation between the master monotonically increasing clock and the master hardware clock, and writing the first hardware time deviation into the system memory of the master device, wherein the system memory of the master device can be accessed by a data plane process, and the data plane process of the master device is configured to: determine the current time of the master hardware clock by reading the first hardware time deviation and the current time of the master monotonically increasing clock in the system memory of the master device; the slave device periodically calculating a second hardware time deviation between the slave monotonically increasing clock and the slave hardware clock, and writing the second hardware time deviation into the system memory of the slave device, wherein the system memory of the slave device can be accessed by a data plane process, and the data plane process of the slave device is configured to: determine the current time of the slave hardware clock by reading the second hardware time deviation and the current time of the slave monotonically increasing clock in the system memory of the slave device.

[0017] The aforementioned master monotonically increasing clock is a virtual clock provided by the operating system within the master device. The master monotonically increasing clock starts counting from the master device's system startup or a fixed starting point; its time value only increases and never decreases, and it will not backtrack or jump with system time adjustments. The slave monotonically increasing clock is a virtual clock provided by the operating system within the slave device. The slave monotonically increasing clock starts counting from the slave device's system startup or a fixed starting point; its time value only increases and never decreases, and it will not backtrack or jump with system time adjustments.

[0018] It's understandable that when data plane processes directly access the hardware clock, they need to make system calls, undergo multiple context switches between user mode and kernel mode, and may also interact with hardware, resulting in significant overhead. However, when data plane processes access the time of a monotonically increasing clock, they do not need to perform complex hardware interactions or external synchronization operations, thus the overhead of obtaining the time of a monotonically increasing clock is relatively small.

[0019] In this embodiment, the data plane process in the master device can indirectly access the current time of the master hardware clock through the first hardware time offset and the current time of the master monotonically increasing clock. This reduces the number of accesses to the master hardware clock, thereby reducing system resource waste and overhead. Similarly, the data plane process in the slave device can also indirectly access the current time of the slave hardware clock, thus reducing the number of accesses to the slave hardware clock and further reducing system resource waste and overhead.

[0020] In one possible implementation of the first aspect described above, the management plane process of the master device is configured to determine the current UTC time by reading the current time of the master software clock in the master device, and the management plane process of the slave device is configured to determine the current UTC time by reading the current time of the slave software clock in the slave device.

[0021] It is understandable that, since the master software clock and the slave software clock are synchronized, at the same time, the current UTC time obtained by the first management plane process is the same as the current UTC time obtained by the second management plane process, that is, the management plane time of the master device is synchronized with the management plane time of the slave device.

[0022] It should be noted that the time synchronization in the embodiments of this application refers to high-precision time synchronization, not absolute time synchronization. For example, at the same time, the error between the current time of the master software clock and the current time of the slave software clock is on the order of microseconds, such as 10 microseconds.

[0023] In one possible implementation of the first aspect described above, both the master device and the slave device include a third-party library; the third-party library in the master device is configured to determine the current UTC time by reading the current time of the master software clock in the master device; the third-party library in the slave device is configured to determine the current UTC time by reading the current time of the slave software clock in the slave device.

[0024] It is understandable that third-party libraries in the master or slave device can use the software clock time (i.e., management plane time).

[0025] For example, if the distributed network system is a vehicle distributed network and the master device is a vehicle domain controller, the vehicle domain controller may deploy third-party libraries involved in uploading or distributing vehicle-to-cloud (V2X) data. When the third-party library receives V2X data, it verifies the timestamp of the V2X data to ensure its validity. Since the third-party library uses the management plane time of the vehicle domain controller, which is equal to UTC time, the verification of the V2X data can be guaranteed to proceed normally, thereby ensuring successful data reception by the third-party library. Therefore, the time synchronization method provided in this application embodiment is also compatible with third-party libraries.

[0026] In one possible implementation of the first aspect described above, the first time message is sent via User Datagram Protocol (UDP), and the second time message is sent via Generalized Precision Clock Protocol (GPTP).

[0027] As can be understood, GPTP is a network time synchronization protocol based on the IEEE 1588 standard. It can achieve high-precision synchronization with the sending device's hardware clock (e.g., the master hardware clock) by sending time messages containing the sending time and transmission delay (e.g., a second time message). This allows the receiving device (e.g., a slave device) to adjust its local hardware clock frequency (e.g., the slave hardware clock) and gradually achieve high-precision synchronization with the sending device's hardware clock (e.g., the master hardware clock). This avoids time jumps in the slave hardware clock and ensures its continuity and stability.

[0028] It is understandable that the master device can send a first-time message to at least one slave device simultaneously via the UDP protocol, without needing to establish a separate connection for each slave device. This reduces the master device's resource overhead and network latency, and improves the efficiency and real-time performance of time synchronization. Furthermore, the connectionless nature of the UDP protocol makes the broadcasting process of the first-time message simple and fast, ensuring that each slave device can receive the first-time message almost simultaneously, thereby achieving high-precision time synchronization.

[0029] Secondly, this application provides a distributed network system, comprising: a master device and at least one slave device, wherein the master device includes a master software clock and a master hardware clock, and the slave device includes a slave software clock and a slave hardware clock; the master device is configured to send a first time message to the slave device, the first time message including: a first hardware time of the master hardware clock when the master device sends the first time message, and a first UTC time of the master software clock when the master device sends the first time message; the slave device is configured to determine the transmission duration of the first time message based on the first hardware time in the received first time message and a second hardware time of the slave hardware clock in the slave device, and adjust the time of the slave software clock to the second UTC time based on the first UTC time in the received first time message and the transmission duration of the first time message.

[0030] In one possible implementation of the second aspect described above, the master device is further configured to send a second time message to the slave device. The second time message includes: a third hardware time of the master hardware clock when the master device sends the second time message, and a transmission link delay when transmitting the second time message. The slave device is further configured to determine a target frequency of the slave hardware clock based on the third hardware time and transmission link delay in the received second time message, and adjust the frequency of the slave hardware clock to the target frequency so that the time of the slave hardware clock is synchronized with the time of the master hardware clock. Alternatively, the slave device is further configured to determine a time difference between the third hardware time and the fourth hardware time based on the third hardware time in the received second time message, the transmission link delay, and a fourth hardware time of the slave hardware clock when the slave device receives the second time message, and adjust the time of the slave hardware clock based on the determined time difference so that the time of the slave hardware clock is synchronized with the time of the master hardware clock.

[0031] Thirdly, this application provides an electronic device, including a processor and a memory, wherein the memory stores a computer program or instructions executable by the processor, and the processor executes the computer program or instructions to implement the time synchronization method provided by the first aspect and various possible implementations of the first aspect.

[0032] Fourthly, this application provides a computer-readable storage medium storing a program or instructions that, when executed by a master device or slave device, implement the time synchronization method provided in the first aspect and various possible implementations of the first aspect.

[0033] Fifthly, this application provides a computer program product, including a computer program or instructions, which, when executed by a master device or a slave device, enables the time synchronization method provided by the first aspect and various possible implementations of the first aspect to be implemented.

[0034] The beneficial effects of the second to fourth aspects mentioned above can be referred to the relevant descriptions in the first aspect and various possible implementations of the first aspect, which will not be repeated here. Attached Figure Description

[0035] Figure 1 A schematic diagram illustrating the principle of a time synchronization method is shown based on some embodiments.

[0036] Figure 2 A flowchart illustrating a time synchronization method is shown based on the method provided in the embodiments of this application.

[0037] Figure 3 According to the method provided in the embodiments of this application, a schematic diagram of another time synchronization method is shown;

[0038] Figure 4 A schematic diagram of the structure of a distributed network system is shown according to the method provided in the embodiments of this application;

[0039] Figure 5 A schematic diagram of the structure of an electronic device is shown according to the method provided in the embodiments of this application. Detailed Implementation

[0040] The illustrative embodiments of this application include, but are not limited to, a time synchronization method, a distributed network system, an electronic device, a medium, and a product.

[0041] To more clearly illustrate the solutions of the embodiments of this application, the relevant field terms involved in this application will be explained below.

[0042] (1) UTC time (e.g., the first UTC time and the second UTC time mentioned in this application).

[0043] UTC time is a globally unified time standard based on atomic time, used to ensure time consistency around the world, and is an internationally recognized standard time reference.

[0044] (2) Hardware clock.

[0045] A hardware clock is a physical hardware component, essentially a counter driven by a highly stable crystal oscillator. The count value represents the crystal oscillator's period, not time. Electronic devices can obtain the hardware clock's time by setting an initial value for the hardware clock and converting the count value into time based on that initial value and the crystal oscillator's period.

[0046] For example, the initial value of the hardware clock can be the time value obtained from the physical real-time clock (RTC) chip, or it can be the compilation time of the software firmware in the electronic device. As another example, in a vehicle distributed network, which may include electronic devices such as vehicle domain controllers, remote communication units, and sensors, the initial value of the hardware clock in each electronic device can be the time reference value obtained by the electronic device from the vehicle's CAN bus.

[0047] It is understandable that if the device is powered off for a long time, the time of the RTC chip may not be equal to the UTC time when the device is powered on again. If the initial value of the hardware clock is obtained from the time value of the RTC chip, it may cause the hardware clock time to be different from the UTC time.

[0048] (3) Software clock.

[0049] A software clock is a time management mechanism implemented through software logic and has no physical entity. In some embodiments, a software clock can serve as the system clock of the device's internal operating system, or in other words, the operating system's system clock is a specific implementation of the software clock.

[0050] (4) Distributed network system.

[0051] A distributed network system can include multiple network nodes (or device nodes), each of which is an independent electronic device (such as a server, sensor, etc.). These electronic devices are connected via a network and can work collaboratively to complete complex tasks. A distributed network system can include one master device and at least one slave device. Only when the time base of the master device and all slave devices is consistent can the coordinated execution of tasks, data consistency, and accurate sequencing of events be guaranteed, thus ensuring the overall performance and reliability of the system. Therefore, time synchronization is required between the master device and all slave devices.

[0052] like Figure 1 As shown, in some embodiments, the distributed network system may include a master device 10 and a slave device 20, wherein the master device 10 may include a data master hardware clock 11 and a management master hardware clock 12, and the slave device 20 may include a data slave hardware clock 21 and a management slave hardware clock 22.

[0053] The master device 10 can use the time of the master hardware clock 11 as the system time, and the master device 10 can send the time of the master hardware clock 11 (i.e., the system time) to the slave device 20. After receiving the system time, the slave device 20 can adjust the frequency of the slave hardware clock 21 based on the system time, so that the time of the slave hardware clock 21 is synchronized with the system time of the master device 10 (i.e., the time of the master hardware clock 11), thereby realizing the synchronization of the data plane time of each device in the distributed network system.

[0054] In addition, in some embodiments, the master device 10 may also obtain UTC time via the global navigation satellite system (GNSS) and pulse per second (PPS) signals, or via the network time protocol (NTP), and use the master hardware clock 12 as a metronome to update the UTC time in the master device.

[0055] The master device 10 can also send its UTC time to the slave device 20. After receiving the UTC time from the master device 10, the slave device 20 can adjust its UTC time to be synchronized with the master device 10's UTC time, and use the management hardware clock 22 as its own UTC time metronome to update the UTC time in the slave device 20. In this way, the UTC time of each device in the distributed network system is synchronized, thereby achieving management plane time synchronization.

[0056] In view of this, embodiments of this application provide a time synchronization method. In this method, each device in a distributed network system synchronizes its data plane time and management plane time using a hardware clock and a software clock, respectively. The master device's data plane time is the hardware time of the hardware clock, and the master device's management plane time is the UTC time of the software clock. For example, the master device can obtain UTC time through the Network Time Protocol (NTP) and synchronize the time of its software clock with the obtained UTC time, so that the time of the software clock in the master device is UTC time.

[0057] A distributed network system may include a master device and at least one slave device. The master device includes a master software clock and a master hardware clock, and the slave device includes a slave software clock and a slave hardware clock. The master device may send a first time message to the slave device. The first time message may include: a first hardware time of the master hardware clock when the master device sends the first time message, and a first UTC time of the master software clock when the master device sends the first time message. The slave device determines the transmission duration of the first time message based on the first hardware time in the received first time message and a second hardware time of the slave hardware clock in the slave device. Furthermore, based on the first UTC time in the received first time message and the transmission duration of the first time message, the slave device adjusts its software clock time to the second UTC time to achieve time synchronization between the master software clock and the slave software clock, that is, to achieve time synchronization of the management plane of the master device and the slave device.

[0058] It is understood that the initial value of the master software clock can come from the master hardware clock of the master device, but the master software clock does not depend on the master hardware clock during operation; instead, it is independently maintained by the kernel of the master device's operating system. Similarly, the operation of the slave software clock of the slave device does not depend on the slave hardware clock; it only uses the slave hardware clock's time when the slave software clock is synchronized with the master software clock. In this embodiment, the time of the master software clock of the master device can be used as the time base for one time axis (e.g., the management plane time axis), and the time of the master hardware clock of the master device can be used as the base for another time axis (e.g., the data plane time axis).

[0059] Thus, in the time synchronization method provided in this application embodiment, the management plane time synchronization of each device in the distributed network system can be achieved by a software clock, without the need for an additional hardware clock, which can reduce hardware deployment costs.

[0060] In some embodiments, each device uses the time of its data hardware clock as its system time. However, the data hardware clock may be the device's local time (e.g., Beijing time + 8 hours), meaning it is not equal to UTC time. Therefore, the device's system time may also not be equal to UTC time. Closed-source third-party libraries within the device typically use the system time and assume it to be UTC time. Since the system time and UTC time may not be equal in this case, it can lead to incompatibility issues with closed-source third-party libraries.

[0061] For example, in a vehicle distributed network (VDN), devices such as vehicle domain controllers, remote communication units, and sensors may be included. The vehicle domain controllers may deploy third-party libraries involved in uploading or distributing vehicle-to-cloud (V2X) data. When the third-party library receives V2X data, it verifies the data's timestamp to ensure its validity. Since the third-party library uses the vehicle domain controller's system time, which may not be equal to UTC time, a significant difference between the system time and UTC time can cause the V2X data verification to fail, resulting in data reception failure for the third-party library.

[0062] In this embodiment of the application, each device in the distributed system (e.g., a master device or a slave device) can use the software clock time as its system time (i.e., CLOCK_REALTIME). Taking the master device as an example, the master device can use the master software clock time as its system time. Since the master software clock time is equal to UTC time, the master device's system time is also equal to UTC time. Similarly, the slave device's system time is also equal to UTC time. Therefore, the system time used by closed-source third-party libraries in the master or slave devices is equal to UTC time, meaning that the time synchronization method provided in this embodiment of the application is also compatible with third-party libraries.

[0063] It is understood that the slave hardware clock in each slave device in a distributed network system can be synchronized with the master hardware clock of the master device, and the slave software clock in each slave device can be synchronized with the slave software clock of the master device, thereby achieving time synchronization of the hardware clock and the software clock of each device in the distributed network system.

[0064] It should be noted that the master device acting as the master device for time synchronization and the slave device acting as the slave device for time synchronization do not imply a master-slave relationship between the master device and the slave device. It only indicates that the master device is the sending device for time messages (such as the first time message or the second time message), and the slave device is the receiving device for time messages.

[0065] The master and slave devices mentioned in the embodiments of this application can be electronic devices running an operating system and having a hardware clock, including but not limited to mobile phones, wearable devices, tablets (Pads), desktop computers, laptops, vehicle sensor modules (such as vehicle cameras, millimeter-wave radar, lidar, etc.), etc. The embodiments of this application do not limit the specific form of the master and slave devices.

[0066] The following is combined Figure 2 The flowchart shown illustrates a time synchronization method provided by an embodiment of this application. Figure 2 As shown, the method includes:

[0067] S201, the master device sends a first time message to the slave device, wherein the first time message includes: the first hardware time of the master hardware clock when the master device sends the first time message, and the first UTC time of the master software clock when the master device sends the first time message.

[0068] In some embodiments, the distributed network system may include a master device and at least one slave device. The master device may include a master software clock (e.g., denoted as utc_master) and a master hardware clock (e.g., phc_master), and the slave device may include a slave software clock (e.g., denoted as utc_slave) and a slave hardware clock (e.g., phc_slave). The slave device may first synchronize its hardware clock time to the master device's master hardware clock time, and then synchronize its software clock time to the master device's master software clock time. That is, before the master device sends the first time message to the slave device, the slave device may first synchronize its hardware clock time to the master device's master hardware clock time.

[0069] The process of synchronizing the master and slave hardware clocks is explained below.

[0070] In some embodiments, the master device may send a second time message to the slave device. The second time message may include: a third hardware time of the master hardware clock when the master device sends the second time message, and a transmission link delay when transmitting the second time message. The slave device may determine a target frequency of its slave hardware clock based on the third hardware time and transmission link delay in the received second time message, and adjust the frequency of its slave hardware clock to the target frequency, so that the time of the slave hardware clock is synchronized with the time of the master hardware clock; or, the slave device may determine the time difference between the third hardware time and the fourth hardware time based on the third hardware time in the received second time message, the transmission link delay, and a fourth hardware time of its slave hardware clock when the slave device receives the second time message, and adjust the time of its slave hardware clock based on the determined time difference, so that the time of the slave hardware clock is synchronized with the time of the master hardware clock. The fourth hardware time may be the time of the slave hardware clock when the slave device receives the second time message.

[0071] It is understandable that strategies for synchronizing hardware clock time can include frequency modulation (FM) and stepping (AM) strategies. FM strategy refers to the slave device indirectly modifying the slave clock's time by changing its frequency to smoothly approximate the master clock's time. Stepping strategy refers to the slave device directly modifying the slave clock's time to make it approximately equal to the master clock's time.

[0072] In some embodiments, when the slave device receives the second time message, it can determine the time difference between the third hardware time and the fourth hardware time (i.e., the time difference between the master hardware clock time and the slave hardware clock time) based on the third hardware time in the received second time message, the transmission link delay, and the fourth hardware time of the slave hardware clock when the slave device receives the second time message.

[0073] When the time difference between the master and slave hardware clocks is less than a preset threshold, the slave device can use a frequency modulation strategy to synchronize its time with the master hardware clock. This ensures that the slave hardware clock remains continuous without jumps and guarantees the system stability of the slave device. When the time difference between the master and slave hardware clocks exceeds a preset threshold, the slave device can use a stepping strategy to synchronize its time with the master hardware clock.

[0074] It should be noted that the aforementioned preset threshold can be set according to actual application requirements, such as 1 millisecond, 128 milliseconds, 500 milliseconds, etc., and this application does not limit it. It is understood that a time difference between the slave hardware clock and the master hardware clock greater than the preset threshold indicates a serious time deviation between the two hardware clocks, which may constitute a systemic risk. In the embodiments of this application, when the time difference between the slave hardware clock and the master hardware clock is large, the time of the slave hardware clock can be directly adjusted in steps to quickly eliminate serious errors and prevent long-term accumulation of errors.

[0075] As mentioned earlier, hardware clocks can provide a high-precision time reference. By modifying the frequency of the slave hardware clock, the time of the slave hardware clock can gradually approach the time of the master hardware clock, thus achieving a time synchronization accuracy of microseconds between the master and slave hardware clocks.

[0076] In some embodiments, the aforementioned second time message is sent via the generalized precision time protocol (GPTP).

[0077] As can be understood, GPTP is a network time synchronization protocol based on the IEEE 1588 standard. It can achieve high-precision synchronization with the sending device's hardware clock (e.g., the master hardware clock) by sending time messages containing the sending time and transmission delay (e.g., a second time message). This allows the receiving device (e.g., a slave device) to adjust its local hardware clock frequency (e.g., the slave hardware clock) and gradually achieve high-precision synchronization with the sending device's hardware clock (e.g., the master hardware clock). This avoids time jumps in the slave hardware clock and ensures its continuity and stability.

[0078] like Figure 3As shown in this embodiment, the time of the master hardware clock 11 (as an example of a master hardware clock) of the master device 10 can be used as a time reference for a time axis (e.g., data plane time). After receiving the second time message, the slave device 20 can synchronize the time of its data from the hardware clock 21 (as an example of a slave hardware clock) to the time of the master hardware clock 11. Therefore, the data plane time of each device in the distributed system can use the time of the hardware clock in the device, thereby achieving data plane time synchronization of each device.

[0079] After the master hardware clock of the master device is synchronized with the slave hardware clock of the slave device, the master device can synchronize the master software clock to the slave software clock of the slave device through S201 and S202.

[0080] In some embodiments, the master device may send a first time message to the slave device, wherein the first time message includes: the first hardware time of the master hardware clock when the master device sends the first time message, and the first UTC time of the master software clock when the master device sends the first time message.

[0081] The aforementioned master or slave software clock can serve as the system clock. Taking the master software clock as an example, it can be maintained by the kernel of the master device's operating system. When the master device is connected to the network, its operating system can periodically synchronize with a remote time server via NTP, thereby calibrating the master software clock to UTC time; that is, the master software clock's time equals UTC time. Similarly, the slave software clock can also be maintained by the kernel of the slave device's operating system, and its time equals UTC time.

[0082] In some embodiments, the aforementioned first-time message is sent via the User Datagram Protocol (UDP).

[0083] It is understandable that the master device can send a first-time message to at least one slave device simultaneously via the UDP protocol, without needing to establish a separate connection for each slave device. This reduces the master device's resource overhead and network latency, and improves the efficiency and real-time performance of time synchronization. Furthermore, the connectionless nature of the UDP protocol makes the broadcasting process of the first-time message simple and fast, ensuring that each slave device can receive the first-time message almost simultaneously, thereby achieving high-precision time synchronization.

[0084] S202, the slave device determines the transmission duration of the first time message based on the first hardware time in the received first time message and the second hardware time of the slave hardware clock in the slave device, and adjusts the time of the slave software clock to the second UTC time based on the first UTC time in the received first time message and the transmission duration of the first time message.

[0085] In some embodiments, after receiving the first time message, the slave device can determine the transmission duration of the first time message based on the first hardware time in the received first time message and the second hardware time of the slave hardware clock in the slave device. Furthermore, based on the first UTC time in the received first time message and the transmission duration of the first time message, the time of the slave software clock is adjusted to the second UTC time. This enables time synchronization between the master software clock and the slave software clock.

[0086] It is understandable that, since the master hardware clock is synchronized with the slave hardware clock, the slave device can calculate the transmission duration of the first time message based on the time difference between the first hardware time (i.e., the master hardware clock time when the master device sends the first time message) and the second hardware time (i.e., the slave hardware clock time when the slave device receives the first time message), and calculate the second UTC time based on the first UTC time in the first time message and the transmission duration.

[0087] In some embodiments, the transmission duration of the first time message is the time difference between the first hardware time in the first time message and the second hardware time of the slave hardware clock in the slave device, and the second UTC time is the sum of the first UTC time in the first time message and the transmission duration of the first time message.

[0088] It is understood that the aforementioned second hardware time can be the time of the second hardware clock when the device receives the first time message.

[0089] In some embodiments, the second UTC time can be calculated using the following formula (1).

[0090] ,(1);

[0091] in, It can represent the second hardware time. It can represent the first hardware time. It can indicate the transmission time of the first message (which may include network latency). It can represent the first UTC time. It can represent the second UTC time.

[0092] like Figure 3As shown in this embodiment, the time of the master software clock 13 of the master device 10 (as an example of a master software clock) can be used as a time reference for a time axis (e.g., management plane time). After receiving the first time message, the slave device 20 can synchronize the time of its slave software clock 23 (as an example of a slave software clock) to the time of the master software clock 13. Therefore, the management plane time of each device in the distributed system can use the time of the software clock in the device, thereby achieving management plane time synchronization of each device.

[0093] In this embodiment, the master hardware clock in the master device can be one, and the slave hardware clock in the slave device can be one. Thus, the time synchronization method provided in this embodiment can achieve dual-time-axis time synchronization using a single hardware clock. Each device in the distributed system only needs one hardware clock, which reduces hardware costs and system complexity, and facilitates deployment and maintenance.

[0094] In some embodiments, a first management plane process in the master device is configured to determine the current UTC time by reading the current time of the master software clock in the master device, and a second management plane process in the slave device is configured to determine the current UTC time by reading the current time of the slave software clock in the slave device.

[0095] It is understandable that, since the master software clock and the slave software clock are synchronized, at the same time, the current UTC time obtained by the first management plane process is the same as the current UTC time obtained by the second management plane process, that is, the management plane time of the master device is synchronized with the management plane time of the slave device.

[0096] It should be noted that the time synchronization in the embodiments of this application refers to high-precision time synchronization, not absolute time synchronization. For example, at the same time, the error between the current time of the master software clock and the current time of the slave software clock is on the order of microseconds, such as 10 microseconds.

[0097] In some embodiments, the master device may further include a master monotonically increasing clock (CLOCK_MONOTONIC_RAW). The master device periodically calculates a first hardware time offset between the master monotonically increasing clock and the master hardware clock, and writes the first hardware time offset into a first system memory (e.g., shared memory (SHM)). The first system memory can be accessed by the data plane process, which is configured to determine the current time of the master hardware clock by reading the first hardware time offset and the current time of the master monotonically increasing clock from the first system memory.

[0098] The aforementioned master monotonically increasing clock is a virtual clock provided by the operating system within the master device. The master monotonically increasing clock starts counting from the master device system startup or a fixed starting point; its time value only increases and never decreases, and it will not roll back or jump with system time adjustments.

[0099] It's understandable that when data plane processes in the master device directly access the master hardware clock, they need to make system calls, undergo multiple context switches between user mode and kernel mode, and may also interact with hardware, resulting in significant overhead. However, when each data plane process in the master device accesses the master monotonically increasing clock, it doesn't require complex hardware interactions or external synchronization operations, thus the overhead of obtaining the master monotonically increasing clock is relatively small.

[0100] In this embodiment, the data plane process in the master device can indirectly access the current time of the master hardware clock through the first hardware time deviation and the current time of the master monotonically increasing clock. Therefore, the number of accesses to the master hardware clock can be reduced, thereby reducing system resource waste and overhead.

[0101] In some embodiments, the period for the master device to calculate the first hardware time deviation may be, for example, 1000 milliseconds, 800 milliseconds, 500 ms, etc.

[0102] It is understandable that, since the crystal oscillator of the main hardware clock is continuous, the time of the main hardware clock will not change too quickly within a certain time period (e.g., within 1000 milliseconds / 500 milliseconds). Therefore, even if the data plane process reads the first hardware time from the first system memory with a certain lag, it will not introduce too much time deviation. That is, the accuracy of the current time of the main hardware clock indirectly accessed by the data plane process of the main device is relatively high.

[0103] In some embodiments, the slave device further includes a monotonically increasing clock. The slave device periodically calculates a second hardware time deviation between the monotonically increasing clock and the slave hardware clock, and writes the second hardware time deviation into a second system memory, wherein the second system memory can be accessed by a data plane process, and the data plane process of the slave device is configured to determine the current time of the slave hardware clock by reading the second hardware time deviation from the second system memory and the current time of the monotonically increasing clock.

[0104] The aforementioned monotonically increasing clock is a virtual clock provided by the operating system from the device. The monotonically increasing clock starts counting from the device system startup or a fixed starting point; its time value only increases and never decreases, and it does not roll back or jump with system time adjustments.

[0105] As mentioned earlier, the data plane process in the slave device can indirectly access the current time of the slave hardware clock through the second hardware time skew and the current time of the monotonically increasing clock. Therefore, the number of accesses to the slave hardware clock can be reduced, thereby reducing system resource waste and overhead. Furthermore, the accuracy of the current time of the slave hardware clock indirectly accessed by the data plane process in the slave device is relatively high.

[0106] In some embodiments, the master and slave devices can perform the process of calculating the time offset and writing the time offset to system memory through a daemon (sw_timesyc).

[0107] Taking the master device as an example, if the calculation period of the first hardware time deviation is 500 milliseconds, the master device can calculate the first hardware time deviation between the master hardware clock and the master monotonically increasing clock every 500 milliseconds through sw_timesyc, and then write the first hardware time deviation into the first system memory.

[0108] In some embodiments, both the master device and the slave device include a third-party library; the third-party library in the master device is configured to determine the current UTC time by reading the current time of the master software clock in the master device; the third-party library in the slave device is configured to determine the current UTC time by reading the current time of the slave software clock in the slave device.

[0109] It is understandable that third-party libraries in the master or slave device can use the software clock time (i.e., management plane time).

[0110] For example, if the distributed network system is a vehicle distributed network and the master device is a vehicle domain controller, the vehicle domain controller may deploy third-party libraries involved in uploading or distributing vehicle-to-cloud (V2X) data. When the third-party library receives V2X data, it verifies the timestamp of the V2X data to ensure its validity. Since the third-party library uses the management plane time of the vehicle domain controller, which is equal to UTC time, the verification of the V2X data can be guaranteed to proceed normally, thereby ensuring successful data reception by the third-party library. Therefore, the time synchronization method provided in this application embodiment is also compatible with third-party libraries.

[0111] In some embodiments, the master device includes a first micro-programmed control unit (MCU) and a first system-on-chip (SOC), and the slave device includes a second microcontroller and a second SOC. The master hardware clock is deployed on the first MCU, or on the first SOC, and the master software clock is deployed on the first SOC. The slave hardware clock is deployed on the second MCU, or on the second SOC, and the slave software clock is deployed on the second SOC.

[0112] Understandably, when a hardware clock can be deployed on the MCU, developers can deploy the main hardware clock on the primary MCU of the main device. Since MCUs typically have lower costs and greater integration flexibility, making them suitable for mass production, the hardware clock can be integrated as a standalone module on the MCU, thus facilitating mass production of the main device. Conversely, when a hardware clock cannot be deployed on the MCU, developers can deploy the main hardware clock on the primary SoC of the main device.

[0113] It should be noted that this application does not limit the specific deployment location of the hardware clock. The hardware clock can be deployed in the MCU or SOC of the electronic device according to the actual application requirements.

[0114] This application also provides a distributed network system, which may include a master device and a slave device. The master device may include a master software clock and a master hardware clock, and the slave device may include a slave software clock and a slave hardware clock.

[0115] The master device is used to send a first time message to the slave device. The first time message may include: the first hardware time of the master hardware clock when the master device sends the first time message, and the first UTC time of the master software clock when the master device sends the first time message.

[0116] The slave device is used to determine the transmission duration of the first time message based on the first hardware time in the received first time message and the second hardware time of the slave hardware clock in the slave device, and to adjust the time of the slave software clock to the second UTC time based on the first UTC time in the received first time message and the transmission duration of the first time message.

[0117] The following is combined Figure 4 This application introduces a distributed network system provided by an embodiment.

[0118] like Figure 4 As shown, the distributed network system 40 may include a master device 41 and a slave device 42. The master device 41 may include a first MCU 411 and a first SOC 412. The first MCU 411 may be equipped with a master hardware clock 4111, and the first SOC 412 may be equipped with a master software clock 4121. The slave device 42 may include a second MCU 421 and a second SOC 422. The second MCU 421 may be equipped with a slave hardware clock 4211, and the second SOC 422 may be equipped with a slave software clock 4221.

[0119] The master device 41 is used to send a first time message to the slave device 42. The first time message includes: the first hardware time of the master hardware clock 4111 when the master device 41 sends the first time message, and the first UTC time of the master software clock 4121 when the master device 41 sends the first time message.

[0120] The slave device 42 is used to determine the transmission duration of the first time message based on the first hardware time in the received first time message and the second hardware time of the slave hardware clock in the slave device, and to adjust the time of the slave software clock 4221 to the second UTC time based on the first UTC time in the received first time message and the transmission duration of the first time message.

[0121] In some embodiments, the master device 41 is further configured to send a second time message to the slave device 42. The second time message includes: a third hardware time of the master hardware clock 4111 when the master device 41 sends the second time message, and a transmission link delay when transmitting the second time message.

[0122] The slave device 42 is further configured to determine the target frequency of the slave hardware clock 4211 based on the third hardware time and transmission link delay in the received second time message, and adjust the frequency of the slave hardware clock 4211 to the target frequency so that the time of the slave hardware clock 4211 is synchronized with the time of the master hardware clock 4111; or, the slave device is further configured to determine the time difference between the third hardware time and the fourth hardware time based on the third hardware time in the received second time message, the transmission link delay, and the fourth hardware time of the slave hardware clock when the slave device receives the second time message, and adjust the time of the slave hardware clock based on the determined time difference so that the time of the slave hardware clock is synchronized with the time of the master hardware clock.

[0123] The specific process of time synchronization between the master hardware clock 4111 and the slave hardware clock 4211 can be referred to the relevant description in S201 above, and will not be repeated here.

[0124] It is understandable that if it is necessary to expand device nodes in the distributed network system 40, the newly added electronic devices can be defined as slave devices for time synchronization. That is, using the newly added electronic devices as slave devices is equivalent to increasing the number of slave devices. In this way, the master device can also send a second time message to the newly added electronic devices to achieve hardware clock time synchronization, and can also send a first time message to the newly added electronic devices to achieve software clock time synchronization. In other words, the time synchronization method provided in this application supports dynamic expansion of device nodes, can be applied to various hardware scenarios, does not depend on specific hardware configurations, and has strong adaptability.

[0125] This application also provides an electronic device (such as the master or slave device mentioned in this application), which includes a memory and a processor. The memory stores computer programs or instructions executable by the processor, and the processor executes the computer programs or instructions to implement the time synchronization method mentioned in this application.

[0126] Figure 5 According to some embodiments of this application, a schematic diagram of the structure of an electronic device 100 is shown. For example... Figure 5 As shown, the electronic device 100 includes one or more processors 1001, system memory 1002, non-volatile memory (NVM) 1003, communication interface 1004, input / output (I / O) device 1005, and system control logic 1006 for coupling the processor 1001, system memory 1002, non-volatile memory 1003, communication interface 1004, and input / output (I / O) device 1005. Wherein:

[0127] The processor 1001 may include one or more processing units, such as data processing units or processing circuits that may include MCUs, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), artificial intelligence (AI) processors, or field programmable gate arrays (FPGAs), neural-network processing units (NPUs), etc., and may include one or more single-core or multi-core processors.

[0128] In this embodiment, the hardware clock can be deployed on the MCU of the electronic device 100. For example, if the electronic device 100 is the master device, the master hardware clock can be deployed on the MCU of the electronic device 100.

[0129] In some embodiments, at least one of the processors 1001 may be packaged together with the logic of one or more controllers for system control logic 1006 to form a system in package (SiP). In other embodiments, at least one of the processors 1001 may also be integrated on the same chip with the logic of one or more controllers for system control logic 1006 to form a system on chip (SOC).

[0130] In this embodiment, the software clock can be deployed on the SOC of the electronic device 100. For example, if the electronic device 100 is the master device, the master software clock can be deployed on the SOC of the electronic device 100.

[0131] System memory 1002 is volatile memory, such as random-access memory (RAM), double data rate synchronous dynamic random access memory (DDR SDRAM), etc. System memory 1002 is used for temporary storage of data and / or instructions. In some embodiments, system memory 1002 may be, for example, shared memory (SHM). Exemplarily, if electronic device 100 is a master device, then system memory 1002 may be the first system memory mentioned in this application.

[0132] The non-volatile memory 1003 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, the non-volatile memory 1003 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as a hard disk drive (HDD), a compact disc (CD), a digital versatile disc (DVD), a solid-state drive (SSD), etc. In some embodiments, the non-volatile memory 1003 may also be a removable storage medium, such as a secure digital (SD) memory card, etc.

[0133] Specifically, system memory 1002 and non-volatile memory 1003 may each include a temporary copy and a permanent copy of instruction 1007. Instruction 1007 may include, when executed by at least one of processors 1001, causing electronic device 100 to implement the time synchronization method provided in the embodiments of this application.

[0134] The communication interface 1004 may include a transceiver for providing a wired or wireless communication interface for the electronic device 100, thereby enabling communication with any other suitable device via one or more networks. In some embodiments, the communication interface 1004 may be integrated into other components of the electronic device 100, for example, the communication interface 1004 may be integrated into the processor 1001.

[0135] Input / output (I / O) device 1005 may include input devices such as keyboard and mouse, and output devices such as speaker system and monitor. Users can interact with electronic device 100 through input / output (I / O) device 1005.

[0136] System control logic 1006 may include any suitable interface controller to provide any suitable interface to other modules of electronic device 100. For example, in some embodiments, system control logic 1006 may include one or more memory controllers to provide an interface to system memory 1002 and non-volatile memory 1003.

[0137] Understandable. Figure 5 The structure of the electronic device 100 shown is merely an example. In other embodiments, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0138] This application also provides a computer-readable storage medium storing a program or instructions that, when executed by a master device or slave device, implement the time synchronization method mentioned in this application.

[0139] This application also provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are executed by a master device or a slave device, the time synchronization method mentioned in this application can be implemented.

[0140] Various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or combinations of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0141] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor, a microcontroller, an application-specific integrated circuit, or a microprocessor.

[0142] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. The mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0143] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, compact discread-only memory (CD-ROMs), magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other forms of propagated signals. Therefore, machine-readable media includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0144] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0145] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0146] It should be noted that in the examples and description of this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0147] Although this application has been illustrated and described with reference to certain embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A time synchronization method, characterized in that, This is applied to a distributed network system, which includes a master device and at least one slave device. The master device includes a master software clock and a master hardware clock, and the slave device includes a slave software clock and a slave hardware clock. The method includes: The master device sends a first time message to the slave device, wherein the first time message includes: the first hardware time of the master hardware clock when the master device sends the first time message, and the first UTC time of the master software clock when the master device sends the first time message; The slave device determines the transmission duration of the first time message based on the first hardware time in the received first time message and the second hardware time of the slave hardware clock in the slave device. Based on the first UTC time in the received first time message and the transmission duration of the first time message, the time from the software clock is adjusted to the second UTC time.

2. The time synchronization method according to claim 1, characterized in that, The transmission duration of the first time message is the time difference between the first hardware time in the first time message and the second hardware time of the slave hardware clock in the slave device, and... The second UTC time is the sum of the first UTC time in the first time message and the transmission duration of the first time message.

3. The time synchronization method according to claim 1, characterized in that, Before the master device sends the first time message to the slave device, the method further includes: The master device sends a second time message to the slave device. The second time message includes: the third hardware time of the master hardware clock when the master device sends the second time message, and the transmission link delay when transmitting the second time message. The slave device determines the target frequency of the slave hardware clock based on the third hardware time in the received second time message and the transmission link delay, and adjusts the frequency of the slave hardware clock to the target frequency so that the time of the slave hardware clock is synchronized with the time of the master hardware clock. or, The slave device determines the time difference between the third hardware time and the fourth hardware time based on the third hardware time in the received second time message, the transmission link delay, and the fourth hardware time of the slave hardware clock when the slave device receives the second time message. Based on the determined time difference, the slave hardware clock is adjusted to synchronize with the master hardware clock.

4. The time synchronization method according to any one of claims 1 to 3, characterized in that, The master device further includes a master monotonically increasing clock, and the slave device further includes a slave monotonically increasing clock; The time synchronization method further includes: The master device periodically calculates the first hardware time deviation between the master monotonically increasing clock and the master hardware clock, and writes the first hardware time deviation into the system memory of the master device. The system memory of the master device can be accessed by the data plane process. The data plane process of the master device is configured to determine the current time of the master hardware clock by reading the first hardware time deviation and the current time of the master monotonically increasing clock in the system memory of the master device. The slave device periodically calculates the second hardware time deviation between the slave monotonically increasing clock and the slave hardware clock, and writes the second hardware time deviation into the system memory of the slave device. The system memory of the slave device can be accessed by the data plane process. The data plane process of the slave device is configured to determine the current time of the slave hardware clock by reading the second hardware time deviation and the current time of the slave monotonically increasing clock from the system memory of the slave device.

5. The time synchronization method according to any one of claims 1 to 3, characterized in that, The management plane process of the master device is configured to determine the current UTC time by reading the current time of the master software clock in the master device, and the management plane process of the slave device is configured to determine the current UTC time by reading the current time of the slave software clock in the slave device.

6. The time synchronization method according to any one of claims 1 to 3, characterized in that, Both the master device and the slave device include third-party libraries; The third-party library in the master device is configured to determine the current UTC time by reading the current time of the master software clock in the master device. The third-party library in the slave device is configured to determine the current UTC time by reading the current time of the slave software clock in the slave device.

7. The time synchronization method according to claim 3, characterized in that, The first time message is sent via User Datagram Protocol (UDP), and the second time message is sent via Generalized Precision Clock Protocol (GPTP).

8. A distributed network system, characterized in that, include: A master device and at least one slave device, wherein the master device includes a master software clock and a master hardware clock, and the slave device includes a slave software clock and a slave hardware clock; The master device is used to send a first time message to the slave device. The first time message includes: the first hardware time of the master hardware clock when the master device sends the first time message, and the first UTC time of the master software clock when the master device sends the first time message. The slave device is configured to determine the transmission duration of the first time message based on the first hardware time in the received first time message and the second hardware time of the slave hardware clock in the slave device, and to adjust the time of the slave software clock to the second UTC time based on the first UTC time in the received first time message and the transmission duration of the first time message.

9. The distributed network system according to claim 8, characterized in that, The master device is also used to send a second time message to the slave device. The second time message includes: the third hardware time of the master hardware clock when the master device sends the second time message, and the transmission link delay when transmitting the second time message. The slave device is further configured to determine the target frequency of the slave hardware clock based on the third hardware time in the received second time message and the transmission link delay, and adjust the frequency of the slave hardware clock to the target frequency so that the time of the slave hardware clock is synchronized with the time of the master hardware clock. or, The slave device is further configured to determine the time difference between the third hardware time and the fourth hardware time based on the third hardware time in the received second time message, the transmission link delay, and the fourth hardware time of the slave hardware clock when the slave device receives the second time message, and to adjust the time of the slave hardware clock based on the determined time difference so that the time of the slave hardware clock is synchronized with the time of the master hardware clock.

10. An electronic device, characterized in that, It includes a processor and a memory, the memory storing computer programs or instructions executable by the processor, the processor executing the computer programs or instructions to implement the time synchronization method according to any one of claims 1 to 7.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program or instructions that, when executed by a master device or a slave device, implement the time synchronization method as described in any one of claims 1 to 7.

12. A computer program product, characterized in that, It includes a computer program or instructions that, when executed by a master device or slave device, cause the time synchronization method of any one of claims 1 to 7 to be implemented.

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