Multicast NoC Routing System and Implementation Method Based on Adaptive Routing Algorithm

Abstract

This invention discloses a multicast NoC routing system and its implementation method based on an adaptive routing algorithm, belonging to the field of Network-on-Chip (NoC) communication technology. The technical problem it addresses is that existing solutions, such as tree-structured virtual circuit multicast or parallel pipelines, fail to effectively balance dynamic obstacle avoidance and low-overhead requirements. The system includes an input control and routing arbitrator, used to receive data chips introduced by upstream nodes, extract the target address, compare the target address with the local address in X-Y dimension order, and generate direction selection signals Select1 / Select2 and a virtual circuit hold signal Keep_sel; a crossover selection switch, used to copy data packets according to the direction selection signals Select1 / Select2, filter irrelevant addresses, and distribute data in parallel to multiple directions; and an output buffer and controller, used to buffer data, handshake with downstream nodes, manage tail chip processing and virtual circuit release, and implement an anomaly recovery mechanism.

Description

Technical Field

[0001] This invention relates to the field of Network on-Chip (NoC) communication technology, specifically to a multicast NoC routing system and its implementation method based on an adaptive routing algorithm. Background Technology

[0002] As many-core chips become increasingly large-scale, traditional unicast communication tests require repeatedly sending the same data to homogeneous cores, resulting in long test times and high power consumption. Multicast technology can significantly improve test efficiency by serving multiple destination nodes with a single transmission. However, existing NoC routers mostly use fixed-order routing (such as XY routing), which has the following drawbacks:

[0003] (1) Hot spot problem: Dense data transmission causes local overheating;

[0004] (2) Insufficient flexibility: Fixed paths cannot avoid congested links;

[0005] (3) High hardware overhead: Virtual circuit multicast scheme requires additional storage resources.

[0006] Existing solutions, such as tree-structured virtual circuit multicast or parallel pipelines, have not effectively balanced dynamic obstacle avoidance with low overhead requirements, which is a technical problem that needs to be solved. Summary of the Invention

[0007] The technical objective of this invention is to address the above-mentioned shortcomings by providing a multicast NoC routing system and implementation method based on an adaptive routing algorithm, thereby solving the problem that existing solutions such as tree-structured virtual circuit multicast or parallel pipelines fail to effectively balance dynamic obstacle avoidance and low overhead requirements.

[0008] In a first aspect, the present invention provides a multicast NoC routing system based on an adaptive routing algorithm, comprising an input control and routing arbitrator, a cross-selection switch, and an output buffer and controller;

[0009] The input control and routing arbiter is used to receive data chips introduced by upstream nodes, extract the destination address and compare the destination address with the local address in XY dimension order, and generate direction selection signals Select1 / Select2 and virtual circuit hold signal Keep_sel. The data chip structure is segmented, and the data packet is divided into header chip, middle chip and tail chip. The header chip stores the first two destination addresses, the middle chip stores the remaining address or data payload, and the tail chip marks the end of transmission.

[0010] The cross selection switch is used to copy data packets according to the direction selection signals Select1 / Select2, filter irrelevant addresses, and distribute data in parallel to multiple directions;

[0011] The output buffer and controller are used to cache data, handshake with downstream nodes, manage tail chip processing and virtual circuit release, and implement an exception recovery mechanism.

[0012] Preferably, after receiving the data chip sent by the upstream node through the Data_in pin, the input control and routing arbiter is used to detect the header chip identifier bit. If the identifier bit shows that it is a header chip, the destination address stored in bits 3 to 10 is extracted. If the destination address exceeds the header chip capacity, the address is waited for to be supplemented by subsequent intermediate chips. The arbiter compares each destination address with the local address in XY dimension order.

[0013] The local address is preset via the ads pin;

[0014] The process of comparing each target address with the local address in XY dimension order includes the following steps:

[0015] X-direction priority: Compare the target X coordinate with the local X coordinate. If the target X coordinate > the local X coordinate, set the direction selection signal Select1 = "001", where 001 represents east; if the target X coordinate < the local X coordinate, set Select1 = "010", where 010 represents west.

[0016] The Y direction is next: when the target X coordinate is equal to the local X coordinate, compare the target Y coordinate with the local Y coordinate. If the target Y coordinate is greater than the local Y coordinate, set Select1="011", where 011 represents the south direction; if the target Y coordinate is less than the local Y coordinate, set Select1="100", where 100 represents the north direction.

[0017] Local processing: If the coordinates match perfectly, set Select1="000", where 000 represents the local IP core. At the same time, set the virtual circuit hold signal Keep_sel=1 to lock the current path until the tail chip arrives. This XY dimension comparison process must be completed within a single clock cycle to ensure low latency.

[0018] Preferably, the cross selection switch is used to perform the following operations:

[0019] Receive direction selection signals Select1 / Select2 and data packets from the input control and routing arbitrator. If the directions of the direction selection signals are consistent, the data chips are directly forwarded to the corresponding output ports. If the directions of the direction selection signals are inconsistent, the multicast splitting mechanism is activated.

[0020] The multicast splitting mechanism includes the following:

[0021] Packet copying and address filtering: Copy the original data packet to generate an independent copy, and remove destination addresses that are irrelevant to the direction of transmission;

[0022] Parallel distribution control: The replicas are sent to the Data_que signals in the east and north directions respectively, and a virtual circuit is established independently in each direction. Keep_sel = 1 to maintain the link.

[0023] Congestion avoidance mechanism: If a data port receives Ack_que=0, it suspends transmission in that direction and buffers data until Ack_que=1 and transmission resumes. During this stage, it is necessary to ensure that data copying and distribution are completed within 2-3 clock cycles to avoid pipeline blockage.

[0024] Preferably, when data arrives at the output buffer and controller, the output buffer and controller set Req_que = 1 to request writing to the buffer. If the buffer is free, Buffer_write = 1 is set to buffer the data, and then downstream transmission is started.

[0025] Downstream transmission includes the following operations:

[0026] Downstream node handshake: Set Req_out=1 to initiate a request to the downstream node, and after receiving the response Ack_in=1, send a data chip through the Data_out signal;

[0027] Tail chip processing: After the tail chip is successfully sent, set Ack_que = 1 to notify the cross switch and release the virtual circuit (Keep_sel = 0);

[0028] Anomaly recovery mechanism: If Ack_in=1 is not received in a certain direction within the predetermined period, the virtual circuit is forcibly released and the data is retransmitted to prevent deadlock. In multicast scenarios, the entire transmission process ends after all directions have completed the tail micro-pie confirmation.

[0029] Secondly, the present invention provides a multicast NoC routing implementation method based on an adaptive routing algorithm, applied to a routing system including an input control and routing arbitrator, a cross-selection switch, and an output buffer and controller. The method includes the following steps:

[0030] Data packet reception and multicast path decision: Data chips introduced by upstream nodes are received through input control and routing arbitrator, the destination address is extracted and compared with the local address in XY dimension order, and direction selection signals Select1 / Select2 and virtual circuit hold signal Keep_sel are generated. The data chip structure is segmented. The data packet is divided into header chip, middle chip and tail chip. The header chip stores the first two destination addresses, the middle chip stores the remaining address or data payload, and the tail chip marks the end of transmission.

[0031] Multicast data replication and dynamic distribution: Data packets are replicated based on direction selection signals Select1 / Select2 and cross-selection switches, irrelevant addresses are filtered, and data is distributed in parallel to multiple directions;

[0032] Output flow control and multicast transmission are completed by: buffering data in the output buffer and controller, handshaking with downstream nodes, managing tail chip processing and virtual circuit release, and implementing an anomaly recovery mechanism.

[0033] Preferably, after receiving the data fragments sent by the upstream node, the header fragment identifier is detected by input control. If the identifier indicates that it is a header fragment, the destination address stored in its 3rd to 10th bits is extracted. If the destination address exceeds the header fragment capacity, the address is waited for to be supplemented by subsequent intermediate fragments. Each destination address is compared with the local address in XY dimension order by the arbiter.

[0034] The local address is preset via the ads pin;

[0035] The process of comparing each target address with the local address in XY dimension order includes the following steps:

[0036] X-direction priority: Compare the target X coordinate with the local X coordinate. If the target X coordinate > the local X coordinate, set the direction selection signal Select1 = "001", where 001 represents east; if the target X coordinate < the local X coordinate, set Select1 = "010", where 010 represents west.

[0037] The Y direction is next: when the target X coordinate is equal to the local X coordinate, compare the target Y coordinate with the local Y coordinate. If the target Y coordinate is greater than the local Y coordinate, set Select1="011", where 011 represents the south direction; if the target Y coordinate is less than the local Y coordinate, set Select1="100", where 100 represents the north direction.

[0038] Local processing: If the coordinates match perfectly, set Select1="000", where 000 represents the local IP core. At the same time, set the virtual circuit hold signal Keep_sel=1 to lock the current path until the tail chip arrives. This XY dimension comparison process must be completed within a single clock cycle to ensure low latency.

[0039] As a preferred method, multicast data replication and dynamic distribution include the following operations:

[0040] The direction selection signals Select1 / Select2 and data packets are received through the cross selection switch. If the directions of the direction selection signals are consistent, the data chips are directly forwarded to the corresponding output ports. If the directions of the direction selection signals are inconsistent, the multicast splitting mechanism is activated.

[0041] The multicast splitting mechanism includes the following:

[0042] Packet copying and address filtering: Copy the original data packet to generate an independent copy, and remove destination addresses that are irrelevant to the direction of transmission;

[0043] Parallel distribution control: The replicas are sent to the Data_que signals in the east and north directions respectively, and a virtual circuit is established independently in each direction. Keep_sel = 1 to maintain the link.

[0044] Congestion avoidance mechanism: If a data port receives Ack_que=0, it suspends transmission in that direction and buffers data until Ack_que=1 and transmission resumes. During this stage, it is necessary to ensure that data copying and distribution are completed within 2-3 clock cycles to avoid pipeline blockage.

[0045] Preferably, when data arrives at the output buffer and controller, the output buffer and controller set Req_que = 1 to request writing to the buffer. If the buffer is free, Buffer_write = 1 is set to buffer the data, and then downstream transmission is started.

[0046] Downstream transmission includes the following operations:

[0047] Downstream node handshake: Set Req_out=1 to initiate a request to the downstream node, and after receiving the response Ack_in=1, send a data chip through the Data_out signal;

[0048] Tail chip processing: After the tail chip is successfully sent, set Ack_que = 1 to notify the cross switch and release the virtual circuit (Keep_sel = 0);

[0049] Anomaly recovery mechanism: If Ack_in=1 is not received in a certain direction within the predetermined period, the virtual circuit is forcibly released and the data is retransmitted to prevent deadlock. In multicast scenarios, the entire transmission process ends after all directions have completed the tail micro-pie confirmation.

[0050] The multicast NoC routing system and implementation method of the adaptive routing algorithm of the present invention have the following advantages:

[0051] 1. Adopting a modular three-component structure: The router consists of an input control and routing arbitrator, a cross-selection switch, and an output buffer and controller. The input control and routing arbitrator parses the destination address of the data packet and determines the direction. The cross-selection switch handles multi-directional data copying and forwarding. The output buffer and controller manages data buffering and downstream transmission. This structure simplifies the virtual channel design of traditional multicast routers and reduces hardware overhead.

[0052] 2. A special data micro-fragment format is introduced to support efficient multicast data transmission. It adopts a segmented micro-fragment structure: the data packet is divided into a header micro-fragment, a tail micro-fragment, a middle micro-fragment, and a micro-fragment. The header micro-fragment stores the first two destination addresses (such as coordinate information), the middle micro-fragment stores the remaining addresses or data payload, and the tail micro-fragment marks the end of transmission. This format avoids the overhead of traditional multicast protocols.

[0053] 3. Introducing a dynamic address expansion mechanism: When the head micro-chip cannot accommodate all destination addresses, subsequent intermediate micro-chips can continue to store additional addresses. This solves the flexibility problem in multi-destination address scenarios and significantly improves efficiency compared to fixed address formats. At the same time, a compact bit design is adopted: address information is encoded with 8 bits (the first 4 bits are the X coordinate and the last 4 bits are the Y coordinate), which is efficiently stored in the micro-chip and reduces bandwidth consumption.

[0054] 4. An extended algorithm based on dimension-order routing is proposed, employing a multi-destination address direction decision algorithm: using the XY dimension-order rule, the destination address is compared with the local address coordinates (the first 4 bits of the X coordinate and the last 4 bits of the Y coordinate); if the X coordinates differ, the direction is right (east) or left (west); if the Y coordinates differ, the direction is down (south) or up (north); if they are the same, it is determined to be a local node, and a multicast splitting and data replication mechanism is introduced. When the destination directions are inconsistent, the data packet is copied by cross-selection switch, irrelevant addresses are removed and sent to multiple directions, combined with virtual circuit hold (Keep_sel signal) to ensure that subsequent microchips use the same path;

[0055] 5. Supports deadlock avoidance mechanism: Prevents deadlock problems in multicast transmission through path preservation flag and timeout mechanism. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] The invention will be further described below with reference to the accompanying drawings.

[0058] Figure 1 This is a diagram illustrating the overall structure of a multicast NoC routing system based on an adaptive routing algorithm, as shown in Example 1.

[0059] Figure 2 This is a schematic diagram of the input control and routing arbitrator pins in a multicast NoC routing system based on an adaptive routing algorithm, as shown in Example 1.

[0060] Figure 3 This is a schematic diagram of the cross-selection switch pin in a multicast NoC routing system based on an adaptive routing algorithm, as shown in Example 1.

[0061] Figure 4 This is a schematic diagram of the output buffer and controller pins in a multicast NoC routing system based on an adaptive routing algorithm, as shown in Example 1.

[0062] Figure 5This is a schematic diagram of a special data micro-fragment format for a routing algorithm in a multicast NoC routing system based on an adaptive routing algorithm, as shown in Example 1.

[0063] Figure 6 This is a flowchart of a multicast dimension-order routing algorithm in a multicast NoC routing system based on an adaptive routing algorithm, as described in Example 1. Detailed Implementation

[0064] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments are not intended to limit the present invention. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0065] This invention provides a multicast NoC routing system and implementation method based on an adaptive routing algorithm, which solves the technical problem that existing solutions such as tree-structured virtual circuit multicast or parallel pipelines have not effectively balanced dynamic obstacle avoidance and low overhead requirements.

[0066] Example 1:

[0067] The present invention discloses a multicast NoC routing system based on an adaptive routing algorithm, comprising an input control and routing arbitrator, a cross-selection switch, and an output buffer and controller.

[0068] The input control and routing arbiter is used to receive data chips introduced by upstream nodes, extract the destination address and compare the destination address with the local address in XY dimension order, and generate direction selection signals Select1 / Select2 and virtual circuit hold signal Keep_sel. The data chip structure is segmented, and the data packet is divided into header chip, middle chip and tail chip. The header chip stores the first two destination addresses, the middle chip stores the remaining address or data payload, and the tail chip marks the end of transmission.

[0069] The local address is preset via the ads pin.

[0070] In this embodiment, when a data chip enters the input control and routing arbiter from the upstream node via the Data_in pin, the system first checks the header chip identifier. If it is a header chip, the destination address stored in bits 3-10 is extracted (e.g., "00011111" represents the destination coordinates X=1, Y=15). If the number of addresses exceeds the header chip capacity, the system waits for subsequent intermediate chips to supplement the addresses. Then, the arbiter compares the coordinates of each destination address with the local node coordinates (preset via the ads pin) in XY dimension order.

[0071] (1) X direction priority: compare the target X coordinate with the local X coordinate. If the target X coordinate > the local X coordinate, set the direction selection signal Select1 = "001", where 001 represents east; if the target X coordinate < the local X coordinate, set Select1 = "010", where 010 represents west.

[0072] (2) Y direction next: When the target X coordinate is equal to the local X coordinate, compare the target Y coordinate with the local Y coordinate. If the target Y coordinate is greater than the local Y coordinate, set Select1 = "011", where 011 represents the south direction; if the target Y coordinate is less than the local Y coordinate, set Select1 = "100", where 100 represents the north direction.

[0073] (3) Local processing: If the coordinates match perfectly, set Select1 = "000", where 000 represents the local IP core. At the same time, set the virtual circuit hold signal Keep_sel = 1 to lock the current path until the tail chip arrives. This XY dimension sequence comparison process needs to be completed within a single clock cycle to ensure low latency.

[0074] The cross selection switch is used to copy data packets according to the direction selection signals Select1 / Select2, filter irrelevant addresses, and distribute data in parallel to multiple directions.

[0075] In this embodiment, the cross-selection switch receives the Select1 / Select2 signals and data packets from the input control module. If Select1 and Select2 point in the same direction (e.g., both are "001"), the data slice is directly forwarded to the corresponding output port (e.g., eastbound Data_que). If multi-directional transmission is required (e.g., Select1 = "001" (eastbound), Select2 = "100" (northbound)), then the multicast splitting mechanism is activated.

[0076] (1) Data packet copying and address filtering: Copy the original data packet to generate an independent copy, and remove the destination address that is irrelevant to the transmission direction;

[0077] (2) Parallel distribution control: The replicas are sent to the Data_que signals in the east and north directions respectively, and virtual circuits are established independently in each direction. Keep_sel = 1 to maintain the link.

[0078] (3) Congestion avoidance mechanism: If a data port receives Ack_que=0, it will suspend sending in that direction and buffer the data until Ack_que=1 and transmission resumes. During this stage, it is necessary to ensure that data copying and distribution are completed within 2-3 clock cycles to avoid pipeline blockage.

[0079] The output buffer and controller are used to cache data, handshake with downstream nodes, manage tail chip processing and virtual circuit release, and implement an exception recovery mechanism.

[0080] In this embodiment, when data arrives at the output buffer and controller, the output buffer and controller set Req_que = 1 to request writing to the buffer. If the buffer is free, Buffer_write = 1 is set to buffer the data, and then downstream transmission is started.

[0081] (1) Downstream node handshake: Set Req_out=1 to initiate a request to the downstream node. After receiving the response Ack_in=1, send the data chip through the Data_out signal.

[0082] (2) Tail chip processing: After the tail chip is successfully sent, set Ack_que = 1 to notify the cross switch and release the virtual circuit (Keep_sel = 0);

[0083] (3) Abnormal recovery mechanism: If Ack_in=1 is not received in a certain direction within the predetermined period, the virtual circuit is forcibly released and the data is retransmitted to prevent deadlock. In the multicast scenario, the entire transmission process ends after all directions have completed the tail micro-chip confirmation.

[0084] This embodiment designs a NoC router hardware structure specifically for multicast communication, achieving modular design and an efficient data forwarding mechanism. It adopts a modular three-component structure: the router consists of an input control and routing arbitrator, a crossover selection switch, and an output buffer and controller. The input control and routing arbitrator parses the destination address of data packets and determines the direction; the crossover selection switch handles multi-directional data copying and forwarding; and the output buffer and controller manages data buffering and downstream transmission. This structure simplifies the virtual channel design of traditional multicast routers and reduces hardware overhead.

[0085] Secondly, this embodiment introduces a special data micro-fragment format to support efficient multicast data transmission. A segmented micro-fragment structure is adopted: data packets are divided into header micro-fragments, middle micro-fragments, and tail micro-fragments. The header micro-fragment stores the first two destination addresses (such as coordinate information); the middle micro-fragments store the remaining addresses or data payload; and the tail micro-fragment indicates the end of transmission. This format avoids the overhead of traditional multicast protocols. A dynamic address extension mechanism is introduced: when the header micro-fragment cannot accommodate all destination addresses, subsequent middle micro-fragments can continue to store additional addresses. This solves the flexibility problem in multi-destination address scenarios and significantly improves efficiency compared to fixed address formats. Simultaneously, a compact bit design is adopted: address information is encoded using 8 bits (the first 4 bits are the X coordinate, and the last 4 bits are the Y coordinate), efficiently stored in the micro-fragments, reducing bandwidth consumption.

[0086] Finally, this embodiment discloses an extended algorithm based on dimension-order routing, realizing direction judgment and multicast processing. A multi-destination address direction decision algorithm is adopted: (1) Using the XY dimension-order rule, the destination address is compared with the local address coordinates (first 4 bits of X coordinate, last 4 bits of Y coordinate); (2) If the X coordinates differ, the direction is right (east) or left (west); (3) If the Y coordinates differ, the direction is down (south) or up (north); (4) If they are the same: local node. More importantly, a multicast splitting and data replication mechanism is introduced: when the destination directions are inconsistent, the data packet is copied by cross-selection switch, irrelevant addresses are removed, and the packet is sent to multiple directions. Combined with virtual circuit holding (Keep_sel signal), it ensures that subsequent micro-chips use the same path. A deadlock avoidance mechanism is supported: deadlock problems in multicast transmission are prevented through path holding flags and timeout mechanisms.

[0087] The method in this embodiment has the following effects:

[0088] (1) Multicast parallel transmission: Routers can send the same data packets to multiple destination nodes simultaneously, reducing data duplication in many-core chip testing. For example, cross-selection switches copy data packets based on Select1 / Select2 signals.

[0089] (2) Test optimization mechanism: For homogeneous IP core testing, multicast transmission reduces test time by more than 30%, and load balancing alleviates hot spot problems.

[0090] (3) Low overhead implementation: The hardware only requires the area of ​​a standard on-chip router, which reduces resource consumption compared to the virtual circuit tree scheme.

[0091] Example 2:

[0092] This invention discloses a multicast NoC routing implementation method based on an adaptive routing algorithm, which is applied to a routing system including an input control and routing arbitrator, a cross-selection switch, and an output buffer and controller. The method includes three steps: packet reception and multicast path decision, multicast data replication and dynamic distribution, and output flow control and multicast transmission completion.

[0093] Step S100: Data packet reception and multicast path decision: The data slices introduced by the upstream node are received through the input control and routing arbiter. The destination address is extracted and compared with the local address in XY dimension order. Direction selection signals Select1 / Select2 and virtual circuit hold signal Keep_sel are generated. The data slice structure is segmented. The data packet is divided into header slice, middle slice and tail slice. The header slice stores the first two destination addresses, the middle slice stores the remaining address or data payload, and the tail slice marks the end of transmission.

[0094] The local address is preset via the ads pin.

[0095] In this embodiment, when a data chip enters the input control and routing arbiter from the upstream node via the Data_in pin, the header chip identifier is first detected. If it is a header chip, the destination address stored in bits 3-10 is extracted (e.g., "00011111" represents the destination coordinates X=1, Y=15). If the number of addresses exceeds the header chip capacity, the arbiter waits for subsequent intermediate chips to supplement the addresses. Then, the arbiter compares the coordinates of each destination address with the local node coordinates (preset via the ads pin) in XY dimension order.

[0096] (1) X direction priority: compare the target X coordinate with the local X coordinate. If the target X coordinate > the local X coordinate, set the direction selection signal Select1 = "001", where 001 represents east; if the target X coordinate < the local X coordinate, set Select1 = "010", where 010 represents west.

[0097] (2) Y direction next: When the target X coordinate is equal to the local X coordinate, compare the target Y coordinate with the local Y coordinate. If the target Y coordinate is greater than the local Y coordinate, set Select1 = "011", where 011 represents the south direction; if the target Y coordinate is less than the local Y coordinate, set Select1 = "100", where 100 represents the north direction.

[0098] (3) Local processing: If the coordinates match perfectly, set Select1 = "000", where 000 represents the local IP core. At the same time, set the virtual circuit hold signal Keep_sel = 1 to lock the current path until the tail chip arrives. This XY dimension sequence comparison process needs to be completed within a single clock cycle to ensure low latency.

[0099] Step S200: Multicast data copying and dynamic distribution: Copy data packets according to the direction selection signals Select1 / Select2 and through the cross selection switch, filter irrelevant addresses, and distribute data in parallel to multiple directions.

[0100] In this embodiment, the cross-selection switch receives the Select1 / Select2 signals and data packets from the input control module. If Select1 and Select2 point in the same direction (e.g., both are "001"), the data slice is directly forwarded to the corresponding output port (e.g., eastbound Data_que). If multi-directional transmission is required (e.g., Select1 = "001" (eastbound), Select2 = "100" (northbound)), then the multicast splitting mechanism is activated.

[0101] (1) Data packet copying and address filtering: Copy the original data packet to generate an independent copy, and remove the destination address that is irrelevant to the transmission direction;

[0102] (2) Parallel distribution control: The replicas are sent to the Data_que signals in the east and north directions respectively, and virtual circuits are established independently in each direction. Keep_sel = 1 to maintain the link.

[0103] (3) Congestion avoidance mechanism: If a data port receives Ack_que=0, it will suspend sending in that direction and buffer the data until Ack_que=1 and transmission resumes. During this stage, it is necessary to ensure that data copying and distribution are completed within 2-3 clock cycles to avoid pipeline blockage.

[0104] Step S300 output flow control and multicast transmission are completed: data is buffered by output buffer and controller buffer, handshake with downstream nodes, management of tail microchip processing and virtual circuit release, and an exception recovery mechanism is implemented.

[0105] In this embodiment, when data arrives at the output buffer and controller, the output buffer and controller set Req_que = 1 to request writing to the buffer. If the buffer is free, Buffer_write = 1 is set to buffer the data, and then downstream transmission is started.

[0106] (1) Downstream node handshake: Set Req_out=1 to initiate a request to the downstream node. After receiving the response Ack_in=1, send the data chip through the Data_out signal.

[0107] (2) Tail chip processing: After the tail chip is successfully sent, set Ack_que = 1 to notify the cross switch and release the virtual circuit (Keep_sel = 0);

[0108] (3) Abnormal recovery mechanism: If Ack_in=1 is not received in a certain direction within the predetermined period, the virtual circuit is forcibly released and the data is retransmitted to prevent deadlock. In the multicast scenario, the entire transmission process ends after all directions have completed the tail micro-chip confirmation.

[0109] The system in this embodiment can execute the method disclosed in Embodiment 1 to implement multicast NoC routing.

[0110] The above provides a detailed description of the multicast NoC routing system and implementation method based on adaptive routing algorithm provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A multicast NoC routing system based on an adaptive routing algorithm, characterized in that, This includes an input control and routing arbitrator, a cross selector switch, and an output buffer and controller; The input control and routing arbiter is used to receive data chips introduced by upstream nodes, extract the destination address and compare the destination address with the local address in XY dimension order, and generate direction selection signals Select1 / Select2 and virtual circuit hold signal Keep_sel. The data chip structure is segmented, and the data packet is divided into header chip, middle chip and tail chip. The header chip stores the first two destination addresses, the middle chip stores the remaining address or data payload, and the tail chip marks the end of transmission. The cross selection switch is used to copy data packets according to the direction selection signals Select1 / Select2, filter irrelevant addresses, and distribute data in parallel to multiple directions; The output buffer and controller are used to cache data, handshake with downstream nodes, manage tail chip processing and virtual circuit release, and implement an exception recovery mechanism.

2. The multicast NoC routing system based on adaptive routing algorithm according to claim 1, characterized in that, After receiving the data chip sent by the upstream node through the Data_in pin, the input control and routing arbiter is used to detect the header chip identifier bit. If the identifier bit shows that it is a header chip, the destination address stored in bits 3 to 10 is extracted. If the destination address exceeds the header chip capacity, the address is waited for to be supplemented by subsequent intermediate chips. The arbiter compares each destination address with the local address in XY dimension order. The local address is preset via the ads pin; The process of comparing each target address with the local address in XY dimension order includes the following steps: X-direction priority: Compare the target X coordinate with the local X coordinate. If the target X coordinate > the local X coordinate, set the direction selection signal Select1 = "001", where 001 represents east; if the target X coordinate < the local X coordinate, set Select1 = "010", where 010 represents west. The Y direction is next: when the target X coordinate is equal to the local X coordinate, compare the target Y coordinate with the local Y coordinate. If the target Y coordinate is greater than the local Y coordinate, set Select1="011", where 011 represents the south direction; if the target Y coordinate is less than the local Y coordinate, set Select1="100", where 100 represents the north direction. Local processing: If the coordinates match perfectly, set Select1="000", where 000 represents the local IP core. At the same time, set the virtual circuit hold signal Keep_sel=1 to lock the current path until the tail chip arrives. This XY dimension comparison process must be completed within a single clock cycle to ensure low latency.

3. The multicast NoC routing system based on adaptive routing algorithm according to claim 1, characterized in that, The cross selector switch is used to perform the following operations: Receive direction selection signals Select1 / Select2 and data packets from the input control and routing arbitrator. If the directions of the direction selection signals are consistent, the data chips are directly forwarded to the corresponding output ports. If the directions of the direction selection signals are inconsistent, the multicast splitting mechanism is activated. The multicast splitting mechanism includes the following: Packet copying and address filtering: Copy the original data packet to generate an independent copy, and remove destination addresses that are irrelevant to the direction of transmission; Parallel distribution control: The replicas are sent to the Data_que signals in the east and north directions respectively, and a virtual circuit is established independently in each direction. Keep_sel = 1 to maintain the link. Congestion avoidance mechanism: If a data port receives Ack_que=0, it suspends transmission in that direction and buffers data until Ack_que=1 and transmission resumes. During this stage, it is necessary to ensure that data copying and distribution are completed within 2-3 clock cycles to avoid pipeline blockage.

4. The multicast NoC routing system based on adaptive routing algorithm according to claim 1, characterized in that, When data arrives at the output buffer and controller, the output buffer and controller set Req_que = 1 to request writing to the buffer. If the buffer is free, Buffer_write = 1 is set to buffer the data, and then downstream transmission is started. Downstream transmission includes the following operations: Downstream node handshake: Set Req_out=1 to initiate a request to the downstream node, and after receiving the response Ack_in=1, send a data chip through the Data_out signal; Tail chip processing: After the tail chip is successfully sent, set Ack_que = 1 to notify the cross switch and release the virtual circuit (Keep_sel = 0); Anomaly recovery mechanism: If Ack_in=1 is not received in a certain direction within the predetermined period, the virtual circuit is forcibly released and the data is retransmitted to prevent deadlock. In multicast scenarios, the entire transmission process ends after all directions have completed the tail micro-pie confirmation.

5. A multicast NoC routing implementation method based on an adaptive routing algorithm, characterized in that, The method, applied to a routing system including an input control and routing arbitrator, a cross-selection switch, and an output buffer and controller, comprises the following steps: Data packet reception and multicast path decision: Data chips introduced by upstream nodes are received through input control and routing arbitrator, the destination address is extracted and compared with the local address in XY dimension order, and direction selection signals Select1 / Select2 and virtual circuit hold signal Keep_sel are generated. The data chip structure is segmented. The data packet is divided into header chip, middle chip and tail chip. The header chip stores the first two destination addresses, the middle chip stores the remaining address or data payload, and the tail chip marks the end of transmission. Multicast data replication and dynamic distribution: Data packets are replicated based on direction selection signals Select1 / Select2 and cross-selection switches, irrelevant addresses are filtered, and data is distributed in parallel to multiple directions; Output flow control and multicast transmission are completed by: buffering data in the output buffer and controller, handshaking with downstream nodes, managing tail chip processing and virtual circuit release, and implementing an anomaly recovery mechanism.

6. The multicast NoC routing implementation method of the adaptive routing algorithm according to claim 5, characterized in that, After receiving the data fragments sent by the upstream node, the header fragment identifier is detected by input control. If the identifier indicates that it is a header fragment, the destination address stored in its 3rd to 10th bits is extracted. If the destination address exceeds the header fragment capacity, the address is waited for to be supplemented by subsequent intermediate fragments. Each destination address is compared with the local address in XY dimension order by the arbiter. The local address is preset via the ads pin; The process of comparing each target address with the local address in XY dimension order includes the following steps: X-direction priority: Compare the target X coordinate with the local X coordinate. If the target X coordinate > the local X coordinate, set the direction selection signal Select1 = "001", where 001 represents east; if the target X coordinate < the local X coordinate, set Select1 = "010", where 010 represents west. The Y direction is next: when the target X coordinate is equal to the local X coordinate, compare the target Y coordinate with the local Y coordinate. If the target Y coordinate is greater than the local Y coordinate, set Select1="011", where 011 represents the south direction; if the target Y coordinate is less than the local Y coordinate, set Select1="100", where 100 represents the north direction. Local processing: If the coordinates match perfectly, set Select1="000", where 000 represents the local IP core. At the same time, set the virtual circuit hold signal Keep_sel=1 to lock the current path until the tail chip arrives. This XY dimension comparison process must be completed within a single clock cycle to ensure low latency.

7. The multicast NoC routing implementation method of the adaptive routing algorithm according to claim 5, characterized in that, Multicast data replication and dynamic distribution include the following operations: The direction selection signals Select1 / Select2 and data packets are received through the cross selection switch. If the directions of the direction selection signals are consistent, the data chips are directly forwarded to the corresponding output ports. If the directions of the direction selection signals are inconsistent, the multicast splitting mechanism is activated. The multicast splitting mechanism includes the following: Packet copying and address filtering: Copy the original data packet to generate an independent copy, and remove destination addresses that are irrelevant to the direction of transmission; Parallel distribution control: The replicas are sent to the Data_que signals in the east and north directions respectively, and a virtual circuit is established independently in each direction. Keep_sel = 1 to maintain the link. Congestion avoidance mechanism: If a data port receives Ack_que=0, it suspends transmission in that direction and buffers data until Ack_que=1 and transmission resumes. During this stage, it is necessary to ensure that data copying and distribution are completed within 2-3 clock cycles to avoid pipeline blockage.

8. The multicast NoC routing implementation method of the adaptive routing algorithm according to claim 5, characterized in that, When data arrives at the output buffer and controller, the output buffer and controller set Req_que = 1 to request writing to the buffer. If the buffer is free, Buffer_write = 1 is set to buffer the data, and then downstream transmission is started. Downstream transmission includes the following operations: Downstream node handshake: Set Req_out=1 to initiate a request to the downstream node, and after receiving the response Ack_in=1, send a data chip through the Data_out signal; Tail chip processing: After the tail chip is successfully sent, set Ack_que = 1 to notify the cross switch and release the virtual circuit (Keep_sel = 0); Anomaly recovery mechanism: If Ack_in=1 is not received in a certain direction within the predetermined period, the virtual circuit is forcibly released and the data is retransmitted to prevent deadlock. In multicast scenarios, the entire transmission process ends after all directions have completed the tail micro-pie confirmation.

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