Instruction scheduling method and device after register allocation, computer device and storage medium

Abstract

The application relates to the computer technical field, in particular to a register-allocated instruction scheduling method and device, a computer device and a storage medium. The method comprises the following steps: obtaining a machine instruction sequence to which a physical register has been allocated; determining scheduling dependency information and scheduling characteristic information of each instruction corresponding to the machine instruction sequence; constructing a global instruction scheduling model according to the scheduling dependency information and the scheduling characteristic information; the global instruction scheduling model comprises scheduling constraint information determined according to the scheduling characteristic information; solving the global instruction scheduling model to obtain target transmission periods corresponding to the instructions, with the scheduling constraint information being a solving condition, the transmission clock period of each instruction being a solving variable, and the earliest clock period in which all the instructions are executed completely being a solving target; and allocating and scheduling the instructions in a register-allocated instruction scheduling stage based on the target transmission periods. The application provides an instruction scheduling method with better scheduling effect.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to an instruction scheduling method, apparatus, computer device, and storage medium after register allocation. Background Technology

[0002] In modern compiler backend design, instruction scheduling is a crucial step in improving target code performance, especially in the PostRA (Post-Register Allocation) scheduling phase after register allocation. The compiler needs to process the MachineInstr (machine instruction) sequence that has already been allocated to physical registers. The core task of instruction scheduling in the PostRA phase is to mask instruction latency and maximize processor pipeline resource utilization by rearranging instructions, while strictly adhering to data dependencies, particularly the anti-dependency and output-dependency introduced by physical register reuse.

[0003] The traditional LLVM (Low Level Virtual Machine, an open-source compiler infrastructure project) PostRA scheduler relies on a heuristic list scheduling algorithm and a TBHR (Table-based HazardRecognizer, a static resource table) generated by TableGen (a meta-language and tool for describing how hardware and compiler information is described). List scheduling is essentially a greedy algorithm that makes the "best-performing" decision at each clock cycle based solely on the current system state. It struggles to support scheduling that breaks inverse dependencies, and if inverse dependencies are forcibly broken for scheduling, scheduling failures are likely, and effective backtracking is difficult.

[0004] Therefore, there is an urgent need for an instruction scheduling method with better scheduling performance. Summary of the Invention

[0005] This application provides an instruction scheduling method, apparatus, computer device, and storage medium after register allocation.

[0006] A first aspect of this application provides an instruction scheduling method after register allocation, comprising: During the instruction scheduling phase following register allocation, the sequence of machine instructions that have been allocated physical registers is obtained; Determine the scheduling dependency information and scheduling characteristic information of each instruction corresponding to the machine instruction sequence; A global instruction scheduling model is constructed based on the scheduling dependency information and the scheduling characteristic information; wherein, the global instruction scheduling model refers to a global scheduling model that performs linear programming scheduling on all instructions, and the global instruction scheduling model includes scheduling constraint information determined based on the scheduling characteristic information; Using the scheduling constraint information as the solution condition, the transmission clock period of each instruction as the solution variable, and the earliest clock period in which all instructions are completed as the solution objective, the global instruction scheduling model is solved to obtain the target transmission period corresponding to each instruction. Based on the target launch cycle, each instruction is allocated and scheduled during the instruction scheduling phase after register allocation.

[0007] In one optional embodiment of this application, the scheduling dependency information includes at least one of: data dependency information and sequence dependency information; and / or, The scheduling characteristic information includes at least one of the following: defined register information, used register information, instruction microarchitecture constraint information, and instruction resource call information.

[0008] In one optional embodiment of this application, the scheduling dependency information includes: data dependency information and order dependency information; wherein, The data dependency information includes at least one of the following: data read / write relationship and space occupied by data read / write of dependent registers; The sequence dependency information includes: an instruction execution dependency identifier, which indicates that the first instruction is executed after the second instruction, and / or the execution of the first instruction depends on the second instruction or depends on the execution result of the second instruction.

[0009] In an optional embodiment of this application, the scheduling characteristic information includes: defined register information, used register information, instruction microarchitecture constraint information, and instruction resource call information; wherein, The defined register information includes: the defined register identifier; The register usage information includes: register usage identifier; The instruction microarchitecture constraint information includes at least one of the following: slot, write port, path, bypass identifier (whether bypass is supported), and register file read / write port information; The instruction resource scheduling information includes: instruction resource occupancy information.

[0010] In an optional embodiment of this application, the instruction resource occupancy information includes: resource occupancy object, resource occupancy timing, and resource occupancy duration; before constructing the global instruction scheduling model based on the scheduling dependency information and the scheduling characteristic information, the method further includes: For each instruction, the scheduling constraint information of the instruction is determined based on the resource occupancy object, the resource occupancy timing, the resource occupancy duration, and the preset maximum launch cycle.

[0011] In one optional embodiment of this application, the step of determining the scheduling constraint information for each instruction based on the resource occupancy object, the resource occupancy timing, the resource occupancy duration, and the preset maximum launch period includes: If the third instruction occupies the target resource after N clock cycles following transmission, and the fourth instruction occupies the target resource after M clock cycles following transmission, then the scheduling constraint information for the third and fourth instructions is as follows: CycleA + N != CycleB + M; Wherein, A represents the third instruction, B represents the fourth instruction, and Cycle represents the clock cycle; the target resource includes at least one of the following: slot, data path resource, bypass resource, register file write port, and register file read port.

[0012] In one optional embodiment of this application, the step of determining the scheduling constraint information for each instruction based on the resource occupancy object, the resource occupancy timing, the resource occupancy duration, and the preset maximum launch period includes: If the data dependency of the preceding instruction and the following instruction is based on the same target register, and the preceding instruction is written to the target register after the following instruction is issued, then the scheduling constraint information for the preceding and following instructions is as follows: CycleUseMIA + UseLatA <CycleDefMIB + DefLatB || CycleUseMIB + UseLatB<CycleDefMIA + DefLatA; Wherein, Cycle represents clock cycle; CycleUseMIA represents the transmit clock cycle of instruction useA, UseLatA represents the delay clock cycle of instruction useA reading the target register, CycleDefMIB represents the transmit clock cycle of instruction DefB, and DefLatB represents the delay clock cycle of instruction DefB writing to the target register; "||" represents "OR"; CycleUseMIB represents the transmit clock cycle of instruction useB, UseLatB represents the delay clock cycle of instruction useB reading the target register, CycleDefMIA represents the transmit clock cycle of instruction DefA, and DefLatA represents the delay clock cycle of instruction DefA writing to the target register.

[0013] A second aspect of this application provides an instruction scheduling apparatus after register allocation, comprising: The acquisition module is used to acquire the sequence of machine instructions that have been allocated physical registers during the instruction scheduling phase after register allocation. The determination module is used to determine the scheduling dependency information and scheduling characteristic information of each instruction corresponding to the machine instruction sequence; The model building module is used to build a global instruction scheduling model based on the scheduling dependency information and the scheduling characteristic information; wherein, the global instruction scheduling model refers to a global scheduling model that performs linear programming scheduling on all instructions, and the global instruction scheduling model includes scheduling constraint information determined based on the scheduling characteristic information; The solution module is used to solve the global instruction scheduling model by taking the scheduling constraint information as the solution condition, the transmission clock period of each instruction as the solution variable, and the earliest clock period in which all instructions are completed as the solution objective, so as to obtain the target transmission period corresponding to each instruction. The instruction scheduling module is used to allocate and schedule each instruction during the instruction scheduling phase after register allocation based on the target launch cycle.

[0014] A third aspect of this application provides a computer device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above methods.

[0015] A fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the preceding claims.

[0016] The instruction scheduling method provided in this application after register allocation constructs a global instruction scheduling model based on the scheduling dependency information and the scheduling characteristic information. It uses the scheduling constraint information as the solution condition, the issue clock cycle of each instruction as the solution variable, and the earliest clock cycle in which all instructions are completed as the solution objective. The global instruction scheduling model is solved to obtain the target issue cycle for each instruction. Based on the target issue cycle, each instruction is allocated and scheduled during the instruction scheduling phase after register allocation. By modeling the instruction scheduling problem as a mathematical optimization problem through the global instruction scheduling model, the scheduling dependency information and the scheduling characteristic information are converted into solution variables for the global instruction scheduling model. This allows for finding local optima under complex microarchitectural constraints, breaking through the performance ceiling of traditional greedy algorithms and overcoming anti-dependency scheduling. The introduction of scheduling constraint information ensures that different types of instructions can be scheduled in an orderly manner, improving the concurrency of instruction execution without disrupting data dependencies or violating processor physical resource limitations, reducing or even eliminating instruction latency, and maximizing the resource utilization of the processor pipeline. Simultaneously, this global scheduling model also enables effective instruction backtracking, greatly improving the reliability and backtrackability of instruction scheduling after register allocation. In summary, the embodiments of this application provide a more effective instruction scheduling method.

[0017] Tests showed that integrating the instruction scheduling method after register allocation provided in this application into the MaPU compiler and performing approximately 1500 compilation tests, along with monitoring of over a dozen examples, improved launch cycle performance by tens or even hundreds of clock cycles. In particular, compared to heuristic algorithms based on list scheduling, taking MRattle3 as an example, there was an approximately 20% performance improvement, and other examples generally showed performance improvements of tens to nearly hundreds of clock cycles. For some scheduling regions, the performance improvement was even 100%, achieving 200% performance of list scheduling. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A flowchart illustrating an instruction scheduling method after register allocation provided in one embodiment of this application; Figure 2 A schematic diagram of the structure of an instruction scheduling device after register allocation provided in one embodiment of this application; Figure 3 This is a schematic diagram of a computer device structure provided in one embodiment of this application. Detailed Implementation

[0019] In the process of developing this application, the inventors discovered that there is an urgent need for an instruction scheduling method with better scheduling performance.

[0020] To address the aforementioned issues, this application provides an instruction scheduling method, apparatus, computer device, and storage medium after register allocation, in order to improve instruction scheduling performance.

[0021] The solutions in this application embodiment can be implemented using various computer languages, such as C++.

[0022] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0023] Please see Figure 1 The instruction scheduling method after register allocation provided in this application includes the following steps 101-105: Step 101: In the instruction scheduling phase after register allocation, obtain the machine instruction sequence that has been allocated physical registers; In the PostRA (Post Register Allocation) scheduling phase following register allocation, the compiler needs to process the MachineInstr (machine instruction) sequences that have already been allocated physical registers, with each machine instruction sequence corresponding to a different instruction.

[0024] Step 102: Determine the scheduling dependency information and scheduling characteristic information of each instruction corresponding to the machine instruction sequence; The scheduling dependency information refers to information that characterizes the correlation between instructions, including but not limited to: execution order, logical dependencies, resource sharing or exclusive relationships, etc., which will not be elaborated here and can be flexibly configured according to the actual situation. The scheduling characteristic information refers to information that characterizes the special or unique characteristics of the current instruction, such as register write information, register use information, instruction microarchitecture constraint information, and instruction resource call information, etc., which will not be exhaustively listed here and can be flexibly adjusted according to the actual situation.

[0025] Step 103: Construct a global instruction scheduling model based on the scheduling dependency information and the scheduling characteristic information; The global instruction scheduling model refers to a global scheduling model that uses linear programming (LP) to schedule all instructions. This global instruction scheduling model is a linear mathematical model transformed from traditional static resource tables and list scheduling to characterize the scheduling relationship of clock cycles between instructions. Since the types and numbers of instructions vary across different systems, the essential logic is the scheduling order and relationship between instructions. The input information includes scheduling dependency information and the aforementioned scheduling characteristic information, and the output information is the issue cycle of each instruction. The issue cycle refers to the relative clock cycle at which an operation (such as an instruction, micro-operation, or task) is scheduled to begin execution after scheduling. It is not a real clock cycle, but a logical sequence number or time slot. Correspondingly, the form and content of the global scheduling model in this application embodiment are not specifically limited. This application embodiment does not limit the specific form and content of the global scheduling model and can flexibly set it according to the actual situation, as long as it can express the scheduling relationship between instructions.

[0026] However, it should be clarified that the global instruction scheduling model includes scheduling constraint information determined based on the scheduling characteristic information; the scheduling constraint information may include constraints on the clock cycle, such as the maximum clock cycle, the minimum clock cycle, the dependency or cross slot between instructions, etc., which will not be exhaustively listed here, and can be flexibly configured according to the actual situation.

[0027] Step 104: Using the scheduling constraint information as the solution condition, the transmission clock period of each instruction as the solution variable, and the earliest clock period in which all instructions are completed as the solution objective, the global instruction scheduling model is solved to obtain the target transmission period corresponding to each instruction.

[0028] It should be explained that the clock cycle in which all instructions are completed was originally a concept relative to "late", rather than a concept of duration.

[0029] Step 105: Based on the target launch cycle, allocate and schedule each instruction during the instruction scheduling phase after register allocation.

[0030] The instruction scheduling method provided in this application after register allocation constructs a global instruction scheduling model based on the scheduling dependency information and the scheduling characteristic information. It uses the scheduling constraint information as the solution condition, the issue clock cycle of each instruction as the solution variable, and the earliest clock cycle in which all instructions are completed as the solution objective. The global instruction scheduling model is solved to obtain the target issue cycle for each instruction. Based on the target issue cycle, each instruction is allocated and scheduled during the instruction scheduling phase after register allocation. By modeling the instruction scheduling problem as a mathematical optimization problem through the global instruction scheduling model, the scheduling dependency information and the scheduling characteristic information are converted into solution variables for the global instruction scheduling model. This allows for finding local optima under complex microarchitectural constraints, breaking through the performance ceiling of traditional greedy algorithms and overcoming anti-dependency scheduling. The introduction of scheduling constraint information ensures that different types of instructions can be scheduled in an orderly manner, improving the concurrency of instruction execution without disrupting data dependencies or violating processor physical resource limitations, reducing or even eliminating instruction latency, and maximizing the resource utilization of the processor pipeline. Simultaneously, this global scheduling model also enables effective instruction backtracking, greatly improving the reliability and backtrackability of instruction scheduling after register allocation. In summary, the embodiments of this application provide a more effective instruction scheduling method.

[0031] Tests showed that integrating the instruction scheduling method after register allocation provided in this application into the MaPU compiler, executing approximately 1500 compilation tests and running approximately 1500 test cases, and monitoring more than a dozen examples, improved the launch cycle performance by tens or even hundreds of clock cycles. In particular, compared with heuristic algorithms based on list scheduling, taking MRattle3 as an example, there was an improvement of about 20%, and other examples generally showed a performance improvement of tens to nearly hundreds of clock cycles. For some scheduling regions, the performance could even be improved by 100%, achieving 200% performance of list scheduling.

[0032] In an optional embodiment of this application, the scheduling dependency information includes at least one of data dependency information and sequence dependency information. In this embodiment, data refers to data received, generated, or interacted with during instruction execution. Correspondingly, data dependency information refers to the dependency relationship between different data sets. For example, in the LLVM compiler, data dependency (DataDependency) refers to a constraint relationship between two instructions, specifying their execution order: for example, the calculation result of instruction A is written to the target register, and instruction B then reads the data from the target register; for example, if instruction B needs the calculation result of instruction A, then instruction B depends on instruction A. This relationship determines how the compiler performs instruction scheduling, parallelization, and loop transformation.

[0033] In an optional embodiment of this application, the scheduling characteristic information includes at least one of: defined register information, used register information, instruction microarchitecture constraint information, and instruction resource call information. Defined register information refers to the register identifier and register configuration information of the registers to which data is written; correspondingly, used register information refers to the register identifier and register configuration information of the registers to which data is read; instruction microarchitecture constraint information refers to the identifier and configuration information of data received, generated, or interacted with during instruction execution; instruction resource call information refers to the identifier information of the resources required to be called during instruction execution, as well as information that can characterize the call relationship.

[0034] In an optional embodiment of this application, the scheduling dependency information includes: data dependency information and sequence dependency information; wherein, the data dependency information includes at least one of: data read / write relationship and space occupancy for data read / write of dependent registers; the data read / write relationship refers to the data dependency relationship of registers: information on which instruction defines (writes) the register and which instruction uses (reads) it, and also includes instruction delay, such as a delay of 2 clock cycles, if the instruction is issued in the 10th clock cycle, the register will be actually written in the 12th clock cycle; the space occupancy for data read / write of dependent registers can be identified using mask information, indicating whether the data read and written is the entire register, half a register, or a word or even a half word in the register.

[0035] The sequence dependency information includes: an instruction execution dependency identifier, which indicates that the first instruction is executed after the second instruction, and / or the execution of the first instruction depends on the second instruction or depends on the execution result of the second instruction.

[0036] In an optional embodiment of this application, the scheduling characteristic information includes: defined register information, used register information, instruction microarchitecture constraint information, and instruction resource call information; wherein, The defined register information includes: a defined register identifier (used to characterize the delay clock cycle and mask of the defined register); the used register information includes: a used register identifier (the delay clock cycle and mask of the used register); the instruction microarchitecture constraint information includes at least one of the following: slot, write port, path, bypass identifier (whether bypass is supported), and MReg (Memory-mapped Register, register file) read / write port information; all instructions, each instruction defines the registers for writing to and using the registers for reading from, as well as the slot, write port, path, whether bypass is supported, read / write port information, and other special resource usage information.

[0037] The instruction resource scheduling information includes: instruction resource occupancy information. Instruction resource occupancy information refers to how many clock cycles of resources involved in the instruction execution process will be occupied after the instruction is issued, and may be occupied continuously for multiple clock cycles, such as how many clock cycles of reading registers will occur after the instruction is issued (possibly multiple readings), and how many clock cycles of writing registers will occur after the instruction is issued, etc.

[0038] In an optional embodiment of this application, the instruction resource occupancy information includes: resource occupancy object, resource occupancy timing, and resource occupancy duration; before step 103, and before constructing the global instruction scheduling model based on the scheduling dependency information and the scheduling characteristic information, the method further includes: For each instruction, the scheduling constraint information of the instruction is determined based on the resource occupancy object, the resource occupancy timing, the resource occupancy duration, and the preset maximum launch cycle.

[0039] The preset maximum launch period is determined based on the Depth of the directed acyclic graph. The greater the instruction execution depth, the larger the preset maximum launch period.

[0040] In one optional embodiment of this application, the step of determining the scheduling constraint information for each instruction based on the resource occupancy object, the resource occupancy timing, the resource occupancy duration, and the preset maximum launch period includes: If the third instruction occupies the target resource after N clock cycles following transmission, and the fourth instruction occupies the target resource after M clock cycles following transmission, then the scheduling constraint information for the third and fourth instructions is as follows: CycleA + N != CycleB + M; Where A represents the third instruction, B represents the fourth instruction, Cycle represents the clock cycle, and "!=" is a mathematical operator that means not equal to; the target resources include at least one of the following: slots, data path resources, bypass resources, register file write ports, and register file read ports.

[0041] This embodiment includes two instructions: Instruction A and Instruction B. If both Instruction A and Instruction B need to occupy the target resource R, Instruction A and Instruction B cannot occupy the target resource R in the same cycle and need to occupy it at different times. The constraints converted into linear programming are the scheduling constraint information mentioned above.

[0042] The issue cycle of each instruction ranges between the instruction's execution depth (Depth) and the preset maximum issue cycle. For example: If instruction A and instruction B occupy the same slot, then add the constraint CycleA != CycleB; If instruction A is issued and Cycle N occupies write port P after it is issued, and instruction B is issued and Cycle M occupies write port P after it is issued, then add the constraint CycleA + N != CycleB + M; If instruction A is issued and Cycle N occupies path DPA (Data Path Acceleration), and instruction B is issued and Cycle M occupies path DPB, and if DPA and DPB have an overlapping relationship, then the constraint CycleA + N != CycleB + M is added. If instruction A occupies bypass resources after launching Cycle N, and instruction B occupies the same bypass resources after launching Cycle M, and if the slot of A is equal to the slot of B, then add the constraint CycleA + N != CycleB + M; If instruction A needs to occupy the MReg write port BankA after transmitting N Cycles, and instruction B occupies the MReg write port BankB after transmitting M Cycles, and BankA and BankB are the same, then add the constraint CycleA + N != CycleB + M; If instruction A needs to occupy the MReg read port ClusterA after transmitting N cycles, and instruction B occupies the MReg read port ClusterB after transmitting M cycles, and ClusterA and ClusterB are the same, then add the constraint CycleA + N != CycleB + M.

[0043] In an optional embodiment of this application, for the case where multiple instructions occupy the same target register, taking four instructions—useA, DefA, useB, and DefB—as an example, instruction DefA writes to the target register, instruction useA reads the data written by instruction DefA from the target register, and instruction DefB writes to the target register while instruction useB reads the data written by instruction DefB. This requires that instruction useA reads the data before instruction DefB can start writing, or instruction useB reads the data before instruction DefA can start writing. If instruction DefA writes data before instruction useA reads it, and then instruction DefB writes data, then instruction useA will read incorrect data. Correspondingly, for each instruction, the scheduling constraint information for determining the instruction based on the resource occupancy object, the resource occupancy timing, the resource occupancy duration, and the preset maximum launch period includes: If the data dependency of the preceding instruction and the following instruction is based on the same target register, and the preceding instruction is written to the target register after the following instruction is issued, then the scheduling constraint information for the preceding and following instructions is as follows: CycleUseMIA + UseLatA <CycleDefMIB + DefLatB || CycleUseMIB + UseLatB<CycleDefMIA + DefLatA; Where Cycle represents clock cycle; CycleUseMIA represents the transmit clock cycle (variable) of instruction useA, UseLatA represents the delay clock cycle (fixed value) of instruction useA reading the target register, CycleDefMIB represents the transmit clock cycle (variable) of instruction DefB, and DefLatB represents the delay clock cycle (fixed value) of instruction DefB writing to the target register; "||" represents "OR"; CycleUseMIB represents the transmit clock cycle (variable) of instruction useB, UseLatB represents the delay clock cycle (fixed value) of instruction useB reading the target register, CycleDefMIA represents the transmit clock cycle (variable) of instruction DefA, and DefLatA represents the delay clock cycle (fixed value) of instruction DefA writing to the target register.

[0044] If there is an Order dependency between the preceding instruction A and the subsequent instruction B, then add the following constraint: CycleA <CycleB。

[0045] If there is a data dependency between the preceding instruction A and the following instruction B, where A defines register R and B uses register R, A writes data after N cycles of transmission and B reads register R after M cycles of transmission, then the following constraint is added: CycleA + N <= CycleB + M; If two data dependencies exist, SDepA and SDepB, based on the same register R, and the Define and Use of SDepA are DeMiA and UseMIA respectively, and the Define and Use of SDepB are DeMiB and UseMIB respectively, where DeMiA is written to register R after DefLatA following transmission, and DeMiB is written to register R after DefLatB, UseMIA is read from register R after UseLatA following transmission, and UseMIB is read from register R after UseLatB following transmission, and if DeMiA != DeMiB and UseMIA != UseMIB, then add the following constraint: CycleUseMIA + UseLatA <CycleDefMIB+ DefLatB || CycleUseMIB + UseLatB<CycleDefMIA + DefLat。

[0046] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0047] Please see Figure 2 One embodiment of this application provides an instruction scheduling device 200 after register allocation, including: an acquisition module 210, a determination module 220, a model building module 230, a solution module 240, and an instruction scheduling module 250, wherein: The acquisition module 210 is used to acquire the sequence of machine instructions that have been allocated physical registers during the instruction scheduling phase after register allocation. The determining module 220 is used to determine the scheduling dependency information and scheduling characteristic information of each instruction corresponding to the machine instruction sequence; The model building module 230 is used to build a global instruction scheduling model based on the scheduling dependency information and the scheduling characteristic information; wherein, the global instruction scheduling model refers to a global scheduling model that performs linear programming scheduling on all instructions, and the global instruction scheduling model includes scheduling constraint information determined based on the scheduling characteristic information; The solution module 240 is used to solve the global instruction scheduling model by taking the scheduling constraint information as the solution condition, the transmission clock period of each instruction as the solution variable, and the earliest clock period in which all instructions are completed as the solution objective, so as to obtain the target transmission period corresponding to each instruction. The instruction scheduling module 250 is used to allocate and schedule each instruction in the instruction scheduling phase after register allocation based on the target launch cycle.

[0048] In one optional embodiment of this application, the scheduling dependency information includes at least one of: data dependency information and sequence dependency information; and / or, The scheduling characteristic information includes at least one of the following: defined register information, used register information, instruction microarchitecture constraint information, and instruction resource call information.

[0049] In one optional embodiment of this application, the scheduling dependency information includes: data dependency information and order dependency information; wherein, The data dependency information includes at least one of the following: data read / write relationship and space occupied by data read / write of dependent registers; The sequence dependency information includes: an instruction execution dependency identifier, which indicates that the first instruction is executed after the second instruction, and / or the execution of the first instruction depends on the second instruction or depends on the execution result of the second instruction.

[0050] In an optional embodiment of this application, the scheduling characteristic information includes: defined register information, used register information, instruction microarchitecture constraint information, and instruction resource call information; wherein, The defined register information includes: a defined register identifier; the used register information includes: a used register identifier; the instruction microarchitecture constraint information includes at least one of: slot, write port, path, bypass identifier (whether bypass is supported), and register file read / write port information; and / or, The instruction resource scheduling information includes: instruction resource occupancy information.

[0051] In an optional embodiment of this application, the instruction resource occupancy information includes: resource occupancy object, resource occupancy timing, and resource occupancy duration; before constructing the global instruction scheduling model based on the scheduling dependency information and the scheduling characteristic information, the model construction module 230 is further configured to determine the scheduling constraint information of each instruction based on the resource occupancy object, the resource occupancy timing, the resource occupancy duration, and the preset maximum launch period.

[0052] In an optional embodiment of this application, the model building module 230 is further configured to, if the third instruction occupies the target resource after N clock cycles following transmission, and the fourth instruction occupies the target resource after M clock cycles following transmission, then add the scheduling constraint information of the third instruction and the fourth instruction as follows: CycleA + N != CycleB + M; Wherein, A represents the third instruction, B represents the fourth instruction, and Cycle represents the clock cycle; the target resource includes at least one of the following: slot, data path resource, bypass resource, register file write port, and register file read port.

[0053] In an optional embodiment of this application, the model building module 230 is further configured to, if the data dependency of the preceding instruction and the following instruction is based on the same target register, and the preceding instruction is issued after the following instruction is written into the target register, then add the scheduling constraint information for the preceding instruction and the following instruction as follows: CycleUseMIA + UseLatA <CycleDefMIB + DefLatB || CycleUseMIB + UseLatB<CycleDefMIA + DefLatA; Wherein, Cycle represents clock cycle; CycleUseMIA represents the transmit clock cycle of instruction useA, UseLatA represents the delay clock cycle of instruction useA reading the target register, CycleDefMIB represents the transmit clock cycle of instruction DefB, and DefLatB represents the delay clock cycle of instruction DefB writing to the target register; "||" represents "OR"; CycleUseMIB represents the transmit clock cycle of instruction useB, UseLatB represents the delay clock cycle of instruction useB reading the target register, CycleDefMIA represents the transmit clock cycle of instruction DefA, and DefLatA represents the delay clock cycle of instruction DefA writing to the target register.

[0054] Specific limitations regarding the instruction scheduling device 200 after register allocation can be found in the above description of the instruction scheduling method after register allocation, and will not be repeated here. Each module in the instruction scheduling device 200 after register allocation can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0055] In one embodiment, a computer device is provided, the internal structure of which can be as follows: Figure 3 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and the database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements the above-described register-allocated instruction scheduling method. It includes: memory and a processor; the memory stores the computer program; and the processor, when executing the computer program, implements any step of the above-described register-allocated instruction scheduling method.

[0056] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, can implement any step of the instruction scheduling method after register allocation as described above.

[0057] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0058] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0059] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0060] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0061] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0062] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for instruction scheduling after register allocation, characterized in that, include: During the instruction scheduling phase following register allocation, the sequence of machine instructions that have been allocated physical registers is obtained; Determine the scheduling dependency information and scheduling characteristic information of each instruction corresponding to the machine instruction sequence; A global instruction scheduling model is constructed based on the scheduling dependency information and the scheduling characteristic information; wherein, the global instruction scheduling model refers to a global scheduling model that performs linear programming scheduling on all instructions, and the global instruction scheduling model includes scheduling constraint information determined based on the scheduling characteristic information; Using the scheduling constraint information as the solution condition, the transmission clock period of each instruction as the solution variable, and the earliest clock period in which all instructions are completed as the solution objective, the global instruction scheduling model is solved to obtain the target transmission period corresponding to each instruction. Based on the target launch cycle, each instruction is allocated and scheduled during the instruction scheduling phase after register allocation.

2. The instruction scheduling method after register allocation according to claim 1, characterized in that, The scheduling dependency information includes at least one of data dependency information and sequence dependency information; and / or, The scheduling characteristic information includes at least one of the following: defined register information, used register information, instruction microarchitecture constraint information, and instruction resource call information.

3. The instruction scheduling method after register allocation according to claim 2, characterized in that, The scheduling dependency information includes: data dependency information and sequence dependency information; wherein... The data dependency information includes at least one of the following: data read / write relationship and space occupied by data read / write of dependent registers; The sequence dependency information includes: an instruction execution dependency identifier, which is used to indicate that the first instruction is executed after the second instruction, and / or the execution of the first instruction depends on the second instruction or depends on the execution result of the second instruction.

4. The instruction scheduling method after register allocation according to claim 2, characterized in that, The scheduling characteristic information includes: defined register information, used register information, instruction microarchitecture constraint information, and instruction resource call information; wherein... The defined register information includes: the defined register identifier; The register usage information includes: register usage identifier; The instruction microarchitecture constraint information includes at least one of the following: slot, write port, path, bypass identifier (whether bypass is supported), and register file read / write port information; The instruction resource scheduling information includes: instruction resource occupancy information.

5. The instruction scheduling method after register allocation according to claim 4, characterized in that, The instruction resource usage information includes: the resource-occupying object, the resource-occupying timing, and the resource-occupying duration; before constructing the global instruction scheduling model based on the scheduling dependency information and the scheduling characteristic information, the method further includes: For each instruction, the scheduling constraint information of the instruction is determined based on the resource occupancy object, the resource occupancy timing, the resource occupancy duration, and the preset maximum launch cycle.

6. The instruction scheduling method after register allocation according to claim 5, characterized in that, The scheduling constraint information for each instruction, determined based on the resource occupancy object, the resource occupancy timing, the resource occupancy duration, and the preset maximum launch period, includes: If the third instruction occupies the target resource after N clock cycles following transmission, and the fourth instruction occupies the target resource after M clock cycles following transmission, then the scheduling constraint information for the third and fourth instructions is as follows: CycleA + N != CycleB + M; Wherein, A represents the third instruction, B represents the fourth instruction, and Cycle represents the clock cycle; the target resource includes at least one of the following: slot, data path resource, bypass resource, register file write port, and register file read port.

7. The instruction scheduling method after register allocation according to claim 5, characterized in that, The scheduling constraint information for each instruction, determined based on the resource occupancy object, the resource occupancy timing, the resource occupancy duration, and the preset maximum launch period, includes: If the data dependency of the preceding instruction and the following instruction is based on the same target register, and the preceding instruction is written to the target register after the following instruction is issued, then the scheduling constraint information for the preceding and following instructions is as follows: CycleUseMIA + UseLatA < CycleDefMIB + DefLatB || CycleUseMIB + UseLatB <CycleDefMIA + DefLatA; Wherein, Cycle represents clock cycle; CycleUseMIA represents the transmit clock cycle of instruction useA, UseLatA represents the delay clock cycle of instruction useA reading the target register, CycleDefMIB represents the transmit clock cycle of instruction DefB, and DefLatB represents the delay clock cycle of instruction DefB writing to the target register; "||" represents "OR"; CycleUseMIB represents the transmit clock cycle of instruction useB, UseLatB represents the delay clock cycle of instruction useB reading the target register, CycleDefMIA represents the transmit clock cycle of instruction DefA, and DefLatA represents the delay clock cycle of instruction DefA writing to the target register.

8. An instruction scheduling device after register allocation, characterized in that, include: The acquisition module is used to acquire the sequence of machine instructions that have been allocated physical registers during the instruction scheduling phase after register allocation. The determination module is used to determine the scheduling dependency information and scheduling characteristic information of each instruction corresponding to the machine instruction sequence; The model building module is used to build a global instruction scheduling model based on the scheduling dependency information and the scheduling characteristic information; wherein, the global instruction scheduling model refers to a global scheduling model that performs linear programming scheduling on all instructions, and the global instruction scheduling model includes scheduling constraint information determined based on the scheduling characteristic information; The solution module is used to solve the global instruction scheduling model by taking the scheduling constraint information as the solution condition, the transmission clock period of each instruction as the solution variable, and the earliest clock period in which all instructions are completed as the solution objective, so as to obtain the target transmission period corresponding to each instruction. The instruction scheduling module is used to allocate and schedule each instruction during the instruction scheduling phase after register allocation based on the target launch cycle.

9. A computer device, comprising: A memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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