Memory design determination method and device, electronic equipment and storage medium
By acquiring eye diagram data of the initial memory design and using a dynamic transfer model to correlate performance data, the memory design was filtered and optimized, solving the problem that the memory design could not accurately match the server performance, and achieving a balance between cost control and performance assurance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUGON INFORMATION IND
- Filing Date
- 2026-01-12
- Publication Date
- 2026-05-29
AI Technical Summary
The lack of quantitative correlation analysis between eye diagram data and performance data in existing technologies makes it impossible for memory design to accurately match the performance requirements of the server, which can easily lead to excessive material investment and waste of resources.
By acquiring eye diagram data from various initial memory designs, a pre-defined dynamic transfer model is used to correlate the eye diagram data with performance data. Candidate memory designs that meet the pre-defined conditions are then selected, and the target memory design is determined in conjunction with material parameters. Software parameter tuning is used to replace hardware solution iteration, reducing trial and error costs and time.
This allows for precise control of material parameters while ensuring server performance meets requirements, eliminating resource waste and improving the accuracy and economy of memory design.
Smart Images
Figure CN122113825A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, electronic device, and storage medium for determining memory design. Background Technology
[0002] The hardware signal quality of server memory is an important factor affecting server performance, and eye diagram data is the core indicator for measuring the hardware signal quality of memory.
[0003] In related technologies, hardware adjustments such as upgrading the grade of the printed circuit board (PCB) material of the memory or increasing the number of PCB layers of the memory are used to improve eye diagram data, thereby improving the hardware signal quality of the memory and ultimately optimizing the performance of the server.
[0004] However, the lack of quantitative correlation analysis between eye diagram data and performance data in related technologies makes it impossible to accurately balance the material input of memory design with server performance, which can easily lead to memory design failing to accurately match the performance requirements of the server. Summary of the Invention
[0005] This application provides a method, apparatus, electronic device, and storage medium for determining memory design, in order to solve the technical problem that memory design cannot accurately match the performance requirements of the server.
[0006] In a first aspect, this application provides a method for determining a memory design, including:
[0007] Obtain eye diagram data corresponding to various initial memory designs. The eye diagram data is the hardware signal quality data obtained when performing eye diagram tests on memory using the initial memory design.
[0008] Based on multiple eye diagram data and a preset dynamic transfer model, multiple first performance data corresponding to various initial memory designs are determined. The dynamic transfer model is used to associate eye diagram data and performance data, and the performance data is the state data of the server running software.
[0009] Among multiple first performance data, multiple second performance data that meet preset conditions are identified, and multiple initial memory designs corresponding to multiple second performance data are identified as multiple candidate memory designs;
[0010] Determine the material parameters for multiple candidate memory designs;
[0011] Based on the material parameters of the material from multiple candidate memory designs, the target memory design is determined among the multiple candidate memory designs.
[0012] This solution collects eye diagram data (i.e., measured hardware signal quality data) from various initial memory designs. A pre-defined dynamic transfer model is used to accurately map the eye diagram data to the first performance data (server operating status data). Second performance data meeting pre-defined conditions and corresponding candidate memory designs are then selected. The target memory design is determined by combining the material parameters of the candidate memory designs. This approach ensures that the server's performance meets requirements while controlling the material parameters of the memory (i.e., controlling the cost of the memory), preventing resource waste caused by excessive material investment and significantly improving the accuracy and economy of server memory design.
[0013] In some embodiments, before determining a plurality of second performance data that satisfy preset conditions from a plurality of first performance data, the method further includes:
[0014] If there is at least one third performance data that does not meet the preset conditions among multiple first performance data, then at least one initial memory design corresponding to at least one third performance data is determined as at least one memory design to be tuned.
[0015] For any memory design to be tuned, adjust the software parameters in the memory design; obtain the eye diagram data corresponding to the adjusted memory design; and based on the eye diagram data and dynamic transfer model corresponding to the adjusted memory design, redetermine the first performance data corresponding to the adjusted memory design until the first performance data corresponding to the memory design meets the preset conditions or reaches the maximum number of adjustments.
[0016] In some embodiments, adjusting software parameters in the memory design to be tuned includes:
[0017] Determine the performance difference between the third performance data and the preset conditions;
[0018] Based on the performance difference, the direction and magnitude of the software parameter adjustment are determined in a preset parameter adjustment mapping table;
[0019] Adjust the software parameters in the memory design to be calibrated according to the direction and magnitude of the adjustment.
[0020] In this approach, for initial memory designs whose performance data does not meet preset conditions, software parameter tuning is used instead of hardware iteration, significantly reducing the trial-and-error cost and cycle of memory design. Performance is re-evaluated based on the tuned eye diagram data and dynamic transfer model until the preset conditions are met or the maximum number of adjustments is reached. This maximizes the performance potential of existing hardware designs without requiring additional hardware material investment, effectively expanding the range of candidate memory designs.
[0021] In some embodiments, based on material parameters of materials from multiple candidate memory designs, a target memory design is determined from among the multiple candidate memory designs, including:
[0022] Based on the sub-material parameters of each sub-material of multiple candidate memory designs and the preset material input coefficients of each sub-material, the input score of multiple candidate memory designs is determined. The material input coefficients indicate the processing difficulty of sub-materials in memory production.
[0023] Based on the input scoring of multiple candidate memory designs, the target memory design is determined among the multiple candidate memory designs.
[0024] In some embodiments, for any candidate memory design; based on the sub-material parameters of each sub-material of the materials of multiple candidate memory designs and the preset material input coefficients of each sub-material, the input score of multiple candidate memory designs is determined, including:
[0025] Obtain the preset material input coefficients for each sub-material;
[0026] The input score of the candidate memory design is obtained by weighting and summing the sub-material parameters of each sub-material of the material based on the candidate memory design with the preset material input coefficients of each sub-material.
[0027] In this scheme, the materials of the candidate memory design are broken down into sub-materials (such as PCB board material, number of PCB layers, etc.), and a material input coefficient is introduced (taking into account both the cost of sub-materials and the difficulty of production and processing). The input score is determined by the weighted sum of the sub-material parameters and the corresponding material input coefficient. This approach considers both the cost of the materials themselves and the implicit input caused by the difficulty of processing during production, so that the input score can comprehensively and realistically reflect the input cost of the memory design, thereby improving the economic efficiency of the memory design.
[0028] In some embodiments, based on the input scores of multiple candidate memory designs, a target memory design is determined from among the multiple candidate memory designs, including:
[0029] Based on the input scores of multiple candidate memory designs and the corresponding second performance data, the comprehensive score of multiple candidate memory designs is determined.
[0030] Among multiple candidate memory designs, the candidate memory design with the lowest overall score is selected as the target memory design.
[0031] In some embodiments, for any candidate memory design; based on the input scores of multiple candidate memory designs and the corresponding second performance data, a comprehensive score for multiple candidate memory designs is determined, including:
[0032] The product of the input score corresponding to the candidate memory design and the preset input weight is determined as the comprehensive score of material input corresponding to the candidate memory design.
[0033] The product of the second performance data corresponding to the memory design and the preset performance weight is determined as the comprehensive performance score corresponding to the candidate memory design.
[0034] The difference between the overall score for material input and the overall score for performance is determined as the overall score for memory design.
[0035] In this scheme, the input score of the candidate memory design (reflecting the input cost and processing difficulty) is combined with the second performance data (core performance indicators that have met the preset requirements). The weighted calculation is performed by preset input weight and performance weight. This avoids the problem of pursuing low cost while ignoring performance redundancy or stability, and also eliminates the waste of input caused by blindly pursuing high performance. This allows the target memory design to simultaneously meet the core requirements of cost control and performance assurance.
[0036] Secondly, this application provides a memory design determination apparatus, comprising:
[0037] The first processing module is used to obtain eye diagram data corresponding to various initial memory designs. The eye diagram data is the hardware signal quality data obtained when performing eye diagram testing on memory using the initial memory design.
[0038] The second processing module is used to determine multiple first performance data corresponding to multiple initial memory designs based on multiple eye diagram data and a preset dynamic transfer model. The dynamic transfer model is used to associate eye diagram data and performance data, and the performance data is the state data of the server running software.
[0039] The third processing module is used to determine multiple second performance data that meet preset conditions from multiple first performance data, and to determine multiple initial memory designs corresponding to multiple second performance data as multiple candidate memory designs.
[0040] The fourth processing module is used to determine the material parameters of materials for multiple candidate memory designs;
[0041] The fifth processing module is used to determine the target memory design from among the material parameters of multiple candidate memory designs.
[0042] The memory design determination device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.
[0043] In some embodiments, before determining a plurality of second performance data that satisfy preset conditions from a plurality of first performance data, the third processing module is further configured to:
[0044] If there is at least one third performance data that does not meet the preset conditions among multiple first performance data, then at least one initial memory design corresponding to at least one third performance data is determined as at least one memory design to be tuned.
[0045] For any memory design to be tuned, adjust the software parameters in the memory design; obtain the eye diagram data corresponding to the adjusted memory design; and based on the eye diagram data and dynamic transfer model corresponding to the adjusted memory design, redetermine the first performance data corresponding to the adjusted memory design until the first performance data corresponding to the memory design meets the preset conditions or reaches the maximum number of adjustments.
[0046] In some embodiments, the third processing module is further configured to:
[0047] Determine the performance difference between the third performance data and the preset conditions;
[0048] Based on the performance difference, the direction and magnitude of the software parameter adjustment are determined in a preset parameter adjustment mapping table;
[0049] Adjust the software parameters in the memory design to be calibrated according to the direction and magnitude of the adjustment.
[0050] In some embodiments, the fifth processing module is specifically used for:
[0051] Based on the sub-material parameters of each sub-material of multiple candidate memory designs and the preset material input coefficients of each sub-material, the input score of multiple candidate memory designs is determined. The material input coefficients indicate the processing difficulty of sub-materials in memory production.
[0052] Based on the input scoring of multiple candidate memory designs, the target memory design is determined among the multiple candidate memory designs.
[0053] In some embodiments, for any candidate memory design; the fifth processing module is specifically used for:
[0054] Obtain the preset material input coefficients for each sub-material;
[0055] The input score of the candidate memory design is obtained by weighting and summing the sub-material parameters of each sub-material of the material based on the candidate memory design with the preset material input coefficients of each sub-material.
[0056] In some embodiments, the fifth processing module is specifically used for:
[0057] Based on the input scores of multiple candidate memory designs and the corresponding second performance data, the comprehensive score of multiple candidate memory designs is determined.
[0058] Among multiple candidate memory designs, the candidate memory design with the lowest overall score is selected as the target memory design.
[0059] In some embodiments, for any candidate memory design; the fifth processing module is specifically used for:
[0060] The product of the input score corresponding to the candidate memory design and the preset input weight is determined as the comprehensive score of material input corresponding to the candidate memory design.
[0061] The product of the second performance data corresponding to the memory design and the preset performance weight is determined as the comprehensive performance score corresponding to the candidate memory design.
[0062] The difference between the overall score for material input and the overall score for performance is determined as the overall score for memory design.
[0063] The memory design determination device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.
[0064] Thirdly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;
[0065] The memory stores the instructions that the computer executes;
[0066] The processor executes computer-executable instructions stored in memory to implement the method as described in the first aspect.
[0067] The electronic device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be repeated here.
[0068] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method as described in the first aspect.
[0069] When the computer-executable instructions in the computer-readable storage medium provided in this application are executed by a processor, the technical solutions shown in the above method embodiments can be implemented. The implementation principle and beneficial effects are similar, and will not be repeated here.
[0070] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the method of the first aspect.
[0071] When the computer program in the computer program product provided in this application embodiment is executed by the processor, it can implement the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be repeated here.
[0072] The method, apparatus, electronic device, and storage medium for determining memory designs provided in this application acquire eye diagram data corresponding to multiple initial memory designs. The eye diagram data is hardware signal quality data obtained when performing eye diagram testing on memory using the initial memory designs. Based on multiple eye diagram data and a preset dynamic transfer model, multiple first performance data corresponding to the multiple initial memory designs are determined. The dynamic transfer model is used to associate the eye diagram data and performance data, and the performance data is state data when the server runs software. Among the multiple first performance data, multiple second performance data that meet preset conditions are determined, and the multiple initial memory designs corresponding to the multiple second performance data are determined as multiple candidate memory designs. Material parameters of the materials of the multiple candidate memory designs are determined. Based on the material parameters of the materials of the multiple candidate memory designs, a target memory design is determined among the multiple candidate memory designs. In the above method, eye diagram data (i.e., actual hardware signal quality measurement data) of various initial memory designs are collected. A preset dynamic transfer model is used to achieve accurate mapping of eye diagram data to first performance data (server operating status data). Second performance data and corresponding candidate memory designs that meet preset conditions are selected. The target memory design is determined by combining the material parameters of the candidate memory designs. This method can control the material parameters of memory (i.e., control the cost of memory) while ensuring that the server performance meets the requirements. It eliminates the waste of resources caused by excessive material investment and significantly improves the accuracy and economy of server memory design. Attached Figure Description
[0073] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0074] Figure 1 A flowchart illustrating a method for determining a memory design as provided in an embodiment of this application;
[0075] Figure 2 A flowchart illustrating a method for determining a target memory design provided in this application embodiment. Figure 1 ;
[0076] Figure 3 A flowchart illustrating a method for determining a target memory design provided in this application embodiment. Figure 2 ;
[0077] Figure 4 This is a schematic diagram of a memory design determination device provided in an embodiment of this application;
[0078] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.
[0079] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0080] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0081] The hardware signal quality of server memory is an important factor affecting server performance, and eye diagram data is the core indicator for measuring the hardware signal quality of memory.
[0082] In related technologies, hardware adjustments such as upgrading the grade of the printed circuit board (PCB) material of the memory or increasing the number of PCB layers of the memory are used to improve eye diagram data, thereby improving the hardware signal quality of the memory and ultimately optimizing the performance of the server.
[0083] However, the lack of quantitative correlation analysis between eye diagram data and performance data in related technologies makes it impossible to accurately balance the material input of memory design with server performance, which can easily lead to memory design not being accurately matched with the server's performance requirements. For example, when upgrading the grade of memory boards to improve server performance, because the correlation between the upgraded memory's eye diagram data and performance data is unclear, excessive investment in high-cost, high-grade boards may be made to meet the server's performance requirements, but only a small performance improvement is actually achieved, resulting in wasted resources.
[0084] Based on the above-mentioned technical problems, the technical concept of the embodiments of this application is as follows:
[0085] The process involves: acquiring eye diagram data for various initial memory designs, where eye diagram data represents hardware signal quality data obtained during eye diagram testing of memory using the initial memory designs; determining multiple first performance data points corresponding to the initial memory designs based on the multiple eye diagram data points and a preset dynamic transfer model, where the dynamic transfer model correlates the eye diagram data and performance data, which represents the state data of the server running software; identifying multiple second performance data points that meet preset conditions from among the multiple first performance data points, and defining the various initial memory designs corresponding to these second performance data points as multiple candidate memory designs; determining the material parameters of the materials for the multiple candidate memory designs; and determining the target memory design from among the multiple candidate memory designs based on the material parameters of the materials for the multiple candidate memory designs. In the above method, eye diagram data (i.e., actual hardware signal quality measurement data) of various initial memory designs are collected. A preset dynamic transfer model is used to achieve accurate mapping of eye diagram data to first performance data (server operating status data). Second performance data and corresponding candidate memory designs that meet preset conditions are selected. The target memory design is determined by combining the material parameters of the candidate memory designs. This method can control the material parameters of memory (i.e., control the cost of memory) while ensuring that the server performance meets the requirements. It eliminates the waste of resources caused by excessive material investment and significantly improves the accuracy and economy of server memory design.
[0086] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.
[0087] Figure 1 A flowchart illustrating a method for determining a memory design provided in an embodiment of this application is shown below. Figure 1 As shown, the method includes:
[0088] S101. Obtain eye diagram data corresponding to various initial memory designs. The eye diagram data is the hardware signal quality data obtained when performing eye diagram testing on memory using the initial memory design.
[0089] Initial memory design refers to a memory design proposed during the memory development stage that has not undergone performance verification and cost optimization. The differences between initial memory designs are reflected in the grade of the printed circuit board (PCB) material used and / or the number of PCB layers.
[0090] The grade of PCB board is a classification standard for measuring the electrical performance and transmission efficiency of PCB board. PCB board includes FR4 board, M2 board, M4 board, M6 board, M7 board and M8 board. The grade of PCA board from low to high is FR4 board, M2 board, M4 board, M6 board, M7 board and M8 board.
[0091] For example, several initial memory designs are Design A (using FR4 board and 2 power layers), Design B (using M2 board and 2 power layers), Design C (using M2 board and 4 power layers), Design D (using M4 board and 4 power layers), and Design E (using M6 board and 4 power layers).
[0092] Eye diagram testing is a method for evaluating the quality of hardware signal transmission. It can be implemented by: capturing the voltage changes of the signal at different time points using an oscilloscope to form an eye-like pattern, thereby obtaining eye diagram data; or by quantifying the safety margin of the signal within the open area of the eye diagram through margin testing, which is the maximum range of jitter, noise and other interference that the signal can withstand without bit errors.
[0093] Eye diagram data is the quantitative result of eye diagram testing, including but not limited to one or more of the following: eye width (duration of stable indicator signal), eye height (amplitude of indicator signal), jitter value (offset of indicator signal edge), and eye opening (quality of indicator signal).
[0094] In some embodiments, obtaining eye diagram data corresponding to multiple initial memory designs includes: determining multiple initial memory designs; fabricating multiple memory modules based on the multiple initial memory designs; performing eye diagram tests on the multiple memory modules to obtain eye diagram data corresponding to the multiple initial memory designs.
[0095] One initial memory design corresponds to one eye diagram data.
[0096] S102. Based on multiple eye diagram data and a preset dynamic transfer model, determine multiple first performance data corresponding to various initial memory designs. The dynamic transfer model is used to associate eye diagram data and performance data, and the performance data is the state data of the server running software.
[0097] The dynamic transfer model is a mapping model based on neural networks or mathematical statistics. It establishes a quantitative correlation between eye diagram data (input variable) and performance data (output variable) by designing corresponding sample eye diagram data and sample performance data through multiple historical memory designs.
[0098] For example, by using sample eye diagram data and sample performance data corresponding to multiple historical memory designs, a random forest algorithm is used to train the model and obtain a preset dynamic transfer model.
[0099] In some embodiments, based on multiple eye diagram data and a preset dynamic transfer model, multiple first performance data corresponding to various initial memory designs are determined, including:
[0100] For any initial memory design, the eye diagram data corresponding to the initial memory design is input into a preset dynamic transfer model to obtain the first performance data corresponding to the initial memory design.
[0101] The primary performance metrics can be data throughput, latency, bandwidth, or memory error rate.
[0102] S103. Among multiple first performance data, determine multiple second performance data that meet preset conditions, and determine multiple initial memory designs corresponding to multiple second performance data as multiple candidate memory designs.
[0103] The following is an example of determining multiple second performance data that meet preset conditions from multiple first performance data:
[0104] When the first performance data is bandwidth, it is determined whether multiple bandwidths are greater than or equal to a preset bandwidth threshold; when multiple bandwidths are greater than or equal to the preset bandwidth threshold, the multiple bandwidths are determined to be multiple second performance data that meet the preset conditions.
[0105] When the first performance data is data throughput, it is determined whether multiple data throughputs are greater than or equal to a preset data throughput threshold; when multiple data throughputs are greater than or equal to the preset data throughput threshold, these multiple data throughputs are determined to be multiple second performance data that meet preset conditions.
[0106] When the first performance data is latency, it is determined whether multiple latencies are less than or equal to a preset latency threshold; when multiple latencies are less than or equal to the preset latency threshold, these multiple latencies are determined to be multiple second performance data that meet preset conditions.
[0107] When the first performance data is the memory bit error rate, a safe threshold for the memory bit error rate is determined based on the relationship between the memory bit error rate and bandwidth. When multiple memory bit error rates are lower than the safe threshold, these multiple memory bit error rates are determined as multiple second performance data that meet preset conditions. Among them, when the memory bit error rate is lower than the safe threshold, the impact of the memory bit error rate on the server performance is negligible. When the memory bit error rate is greater than or equal to the safe threshold, the memory bit error rate will reduce the server performance.
[0108] The preset bandwidth threshold, data throughput threshold, and latency threshold can be flexibly adjusted according to the server's business performance requirements.
[0109] The preset bandwidth threshold is, for example, 25GB / s, the preset data throughput threshold is, for example, 1.8GB / s, and the preset latency threshold is, for example, 6ms.
[0110] In some embodiments, before determining a plurality of second performance data that satisfy preset conditions from a plurality of first performance data, the method further includes:
[0111] If there is at least one third performance data that does not meet the preset conditions among multiple first performance data, then at least one initial memory design corresponding to at least one third performance data is determined as at least one memory design to be tuned.
[0112] For any memory design to be tuned, adjust the software parameters in the memory design; obtain the eye diagram data corresponding to the adjusted memory design; and based on the eye diagram data and dynamic transfer model corresponding to the adjusted memory design, redetermine the first performance data corresponding to the adjusted memory design until the first performance data corresponding to the memory design meets the preset conditions or reaches the maximum number of adjustments.
[0113] In some embodiments, adjusting software parameters in the memory design to be tuned includes:
[0114] Determine the performance difference between the third performance data and the preset conditions;
[0115] Based on the performance difference, the direction and magnitude of the software parameter adjustment are determined in a preset parameter adjustment mapping table;
[0116] Adjust the software parameters in the memory design to be calibrated according to the direction and magnitude of the adjustment.
[0117] The following is an example of how to determine the performance difference between the third performance data and the preset conditions:
[0118] When the third performance data is bandwidth, the difference between the bandwidth and the preset bandwidth threshold is determined as the performance difference.
[0119] When the third performance data is data throughput, the difference between the data throughput and the preset data throughput threshold is determined as the performance difference.
[0120] When the third performance data is latency, the difference between the latency and the preset latency threshold is determined as the performance difference.
[0121] When the third performance data is the memory bit error rate, the difference between the memory bit error rate and the preset security threshold is determined as the performance difference.
[0122] The adjustment direction indicates whether the software parameter has increased or decreased, while the adjustment range indicates the specific amount of change in the software parameter (how much it has increased or decreased).
[0123] The preset parameter adjustment mapping table includes the correspondence between multiple performance differences and multiple adjustment directions and multiple adjustment magnitudes.
[0124] S104. Determine the material parameters of materials for multiple candidate memory designs.
[0125] In some embodiments, the material may include PCB board material and PCB layer number, and each sub-material of the material is respectively PCB board material and PCB layer number.
[0126] The sub-material parameter of PCB board material is the cost of PCB board material, and the sub-material parameter of PCB layer number is the cost of PCB layer number.
[0127] In some embodiments, the material parameters for determining the materials of multiple candidate memory designs can be:
[0128] For any candidate memory design, based on the number of PCB layers corresponding to the candidate memory design, the cost of the PCB material is obtained from a preset material cost table; based on the number of PCB layers corresponding to the candidate memory design, the cost of the number of PCB layers is obtained from a preset layer cost table; the sum of the cost of the PCB material and the cost of the number of PCB layers is determined as the material parameter of the candidate memory design.
[0129] The board material cost table includes the correspondence between the costs of multiple PCB boards, and the layer cost table includes the correspondence between the costs of multiple PCB layers.
[0130] S105. Based on the material parameters of the material with multiple candidate memory designs, determine the target memory design among the multiple candidate memory designs.
[0131] In some embodiments, determining the target memory design from among multiple candidate memory designs based on the material parameters of the material in multiple candidate memory designs can be as follows:
[0132] Among multiple candidate memory designs, the candidate memory design with the lowest material parameters is selected as the target memory design.
[0133] The beneficial effects of this embodiment are as follows: In this embodiment, eye diagram data corresponding to multiple initial memory designs are obtained. The eye diagram data is the hardware signal quality data obtained when performing eye diagram testing on memory using the initial memory design. Based on multiple eye diagram data and a preset dynamic transfer model, multiple first performance data corresponding to multiple initial memory designs are determined. The dynamic transfer model is used to associate the eye diagram data and performance data. The performance data is the state data when the server runs the software. Among the multiple first performance data, multiple second performance data that meet preset conditions are determined, and the multiple initial memory designs corresponding to the multiple second performance data are determined as multiple candidate memory designs. The material parameters of the materials for the multiple candidate memory designs are determined. Based on the material parameters of the materials for the multiple candidate memory designs, the target memory design is determined among the multiple candidate memory designs. In the above method, eye diagram data (i.e., actual hardware signal quality measurement data) of various initial memory designs are collected. A preset dynamic transfer model is used to achieve accurate mapping of eye diagram data to first performance data (server operating status data). Second performance data and corresponding candidate memory designs that meet preset conditions are selected. The target memory design is determined by combining the material parameters of the candidate memory designs. This method can control the material parameters of memory (i.e., control the cost of memory) while ensuring that the server performance meets the requirements. It eliminates the waste of resources caused by excessive material investment and significantly improves the accuracy and economy of server memory design.
[0134] Hereinafter, based on any of the above embodiments, by... Figure 2 The document further explains the material parameters of materials based on multiple candidate memory designs, and how to determine the target memory design among multiple candidate memory designs.
[0135] Figure 2 A flowchart illustrating a method for determining a target memory design provided in this application embodiment. Figure 1 ,like Figure 2 As shown, the method includes:
[0136] S201. Based on the sub-material parameters of each sub-material of the materials for multiple candidate memory designs and the preset material input coefficients of each sub-material, determine the input score of multiple candidate memory designs, wherein the material input coefficients indicate the processing difficulty of sub-materials in memory production.
[0137] In some embodiments, for any candidate memory design, based on the sub-material parameters of each sub-material of the materials in the multiple candidate memory designs and the preset material input coefficients of each sub-material, an input score for the multiple candidate memory designs is determined, including:
[0138] Obtain the preset material input coefficients for each sub-material;
[0139] The input score of the candidate memory design is obtained by weighting and summing the sub-material parameters of each sub-material of the material based on the candidate memory design with the preset material input coefficients of each sub-material.
[0140] For example, taking the sub-materials of the candidate memory design material, including PCB board material and PCB layer number, as an example, the input score of the candidate memory design is obtained by weighted summing the sub-material parameters of each sub-material based on the candidate memory design material with the preset material input coefficients of each sub-material:
[0141] The first product is determined by multiplying the cost of the PCB board material by the material input coefficient of the PCB board material.
[0142] The second product is determined by multiplying the cost of the number of PCB layers by the material input coefficient of the number of PCB layers.
[0143] The sum of the first and second products is used as the input score for the candidate memory design.
[0144] S202. Based on the input scoring of multiple candidate memory designs, determine the target memory design among the multiple candidate memory designs.
[0145] In some embodiments, among a plurality of candidate memory designs, the candidate memory design with the lowest input score is determined as the target memory design.
[0146] The beneficial effects of this embodiment are as follows: In this embodiment, based on the sub-material parameters of each sub-material of multiple candidate memory designs and the preset material input coefficients of each sub-material, the input score of multiple candidate memory designs is determined. The material input coefficient indicates the processing difficulty of the sub-materials in memory production. Based on the input score of multiple candidate memory designs, the target memory design is determined among multiple candidate memory designs. In the above method, the materials of the candidate memory design are decomposed into sub-materials (such as PCB board, number of PCB layers, etc.), and a material input coefficient is introduced (taking into account both the cost of sub-materials and the difficulty of production and processing). The input score is determined by the weighted sum of the sub-material parameters and the corresponding material input coefficients. This method considers both the cost of the materials themselves and the implicit input brought about by the processing difficulty in the production process, so that the input score can comprehensively and realistically reflect the input cost of the memory design, thereby improving the economic efficiency of the memory design.
[0147] Hereinafter, based on any of the above embodiments, by... Figure 3 The document further explains the process of “scoring multiple candidate memory designs and determining the target memory design from among them”.
[0148] Figure 3 A flowchart illustrating a method for determining a target memory design provided in this application embodiment. Figure 2 ,like Figure 3 As shown, the method includes:
[0149] S301. Based on the input scores of multiple candidate memory designs and the corresponding second performance data, determine the comprehensive score of multiple candidate memory designs.
[0150] In some embodiments, for any candidate memory design; based on the input scores of multiple candidate memory designs and the corresponding second performance data, a comprehensive score for multiple candidate memory designs is determined, including:
[0151] The product of the input score corresponding to the candidate memory design and the preset input weight is determined as the comprehensive score of material input corresponding to the candidate memory design.
[0152] The product of the second performance data corresponding to the memory design and the preset performance weight is determined as the comprehensive performance score corresponding to the candidate memory design.
[0153] The difference between the overall score for material input and the overall score for performance is determined as the overall score for memory design.
[0154] When the second performance data is data throughput or bandwidth, the preset performance weight is positive.
[0155] When the second performance data is latency or memory error rate, the preset performance weight is negative.
[0156] S302. Among multiple candidate memory designs, the candidate memory design with the lowest comprehensive score is determined as the target memory design.
[0157] The lower the overall score, the better the memory design can simultaneously meet the core requirements of cost control and performance assurance.
[0158] The beneficial effects of this embodiment are as follows: In this embodiment, a comprehensive score for multiple candidate memory designs is determined based on the input scores and corresponding second performance data. Among the multiple candidate memory designs, the candidate memory design with the lowest comprehensive score is determined as the target memory design. In the above method, the input score of the candidate memory design (reflecting input cost and processing difficulty) is combined with the second performance data (core performance indicators that have met preset requirements). By performing weighted calculations using preset input weights and performance weights, the problem of pursuing low cost while ignoring performance redundancy or stability is avoided, and the waste of input caused by blindly pursuing high performance is eliminated. This allows the target memory design to simultaneously meet the core requirements of cost control and performance assurance.
[0159] Figure 4 This is a schematic diagram of a memory design determination device provided in an embodiment of this application. Figure 4As shown, the memory design determination device 40 includes a first processing module 401, a second processing module 402, a third processing module 403, a fourth processing module 404, and a fifth processing module 405.
[0160] The first processing module 401 is used to obtain eye diagram data corresponding to various initial memory designs. The eye diagram data is the hardware signal quality data obtained when performing eye diagram testing on memory using the initial memory design.
[0161] The second processing module 402 is used to determine multiple first performance data corresponding to multiple initial memory designs based on multiple eye diagram data and a preset dynamic transfer model. The dynamic transfer model is used to associate the eye diagram data and the performance data, and the performance data is the state data of the server running the software.
[0162] The third processing module 403 is used to determine multiple second performance data that meet preset conditions from multiple first performance data, and to determine multiple initial memory designs corresponding to multiple second performance data as multiple candidate memory designs.
[0163] The fourth processing module 404 is used to determine the material parameters of materials for multiple candidate memory designs;
[0164] The fifth processing module 405 is used to determine the target memory design from among the multiple candidate memory designs, based on the material parameters of the material based on multiple candidate memory designs.
[0165] The memory design determination device 40 provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.
[0166] In some embodiments, before determining a plurality of second performance data that satisfy preset conditions from a plurality of first performance data, the third processing module 403 is further configured to:
[0167] If there is at least one third performance data that does not meet the preset conditions among multiple first performance data, then at least one initial memory design corresponding to at least one third performance data is determined as at least one memory design to be tuned.
[0168] For any memory design to be tuned, adjust the software parameters in the memory design; obtain the eye diagram data corresponding to the adjusted memory design; and based on the eye diagram data and dynamic transfer model corresponding to the adjusted memory design, redetermine the first performance data corresponding to the adjusted memory design until the first performance data corresponding to the memory design meets the preset conditions or reaches the maximum number of adjustments.
[0169] In some embodiments, the third processing module 403 is further configured to:
[0170] Determine the performance difference between the third performance data and the preset conditions;
[0171] Based on the performance difference, the direction and magnitude of the software parameter adjustment are determined in a preset parameter adjustment mapping table;
[0172] Adjust the software parameters in the memory design to be calibrated according to the direction and magnitude of the adjustment.
[0173] In some embodiments, the fifth processing module 405 is specifically used for:
[0174] Based on the sub-material parameters of each sub-material of multiple candidate memory designs and the preset material input coefficients of each sub-material, the input score of multiple candidate memory designs is determined. The material input coefficients indicate the processing difficulty of sub-materials in memory production.
[0175] Based on the input scoring of multiple candidate memory designs, the target memory design is determined among the multiple candidate memory designs.
[0176] In some embodiments, for any candidate memory design; the fifth processing module 405 is specifically used for:
[0177] Obtain the preset material input coefficients for each sub-material;
[0178] The input score of the candidate memory design is obtained by weighting and summing the sub-material parameters of each sub-material of the material based on the candidate memory design with the preset material input coefficients of each sub-material.
[0179] In some embodiments, the fifth processing module 405 is specifically used for:
[0180] Based on the input scores of multiple candidate memory designs and the corresponding second performance data, the comprehensive score of multiple candidate memory designs is determined.
[0181] Among multiple candidate memory designs, the candidate memory design with the lowest overall score is selected as the target memory design.
[0182] In some embodiments, for any candidate memory design; the fifth processing module 405 is specifically used for:
[0183] The product of the input score corresponding to the candidate memory design and the preset input weight is determined as the comprehensive score of material input corresponding to the candidate memory design.
[0184] The product of the second performance data corresponding to the memory design and the preset performance weight is determined as the comprehensive performance score corresponding to the candidate memory design.
[0185] The difference between the overall score for material input and the overall score for performance is determined as the overall score for memory design.
[0186] The memory design determination device 40 provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.
[0187] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 5 As shown, the electronic device 50 includes a processor 501 and a memory 502. The processor 501 is communicatively connected to the memory 502, which stores computer execution instructions. The processor 501 is configured to execute the technical solutions in any of the aforementioned method embodiments by executing the computer execution instructions stored in the memory 502.
[0188] Optionally, the memory 502 can be either independent or integrated with the processor 501. Optionally, when the memory 502 is a device independent of the processor 501, the electronic device 50 may further include a bus 503 for connecting the aforementioned devices.
[0189] The electronic device is used to execute the technical solutions in any of the foregoing method embodiments. Its implementation principle and technical effect are similar, and will not be described again here.
[0190] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the technical solutions provided in any of the foregoing method embodiments.
[0191] This application also provides a computer program product, including a computer program, which, when executed by a processor, is used to implement the technical solutions provided in the foregoing method embodiments.
[0192] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.
[0193] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.
[0194] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.
[0195] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.
[0196] When integrated units / modules are implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. Unless otherwise specified, the processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the storage unit can be any suitable magnetic or magneto-optical storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.
[0197] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.
[0198] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.
[0199] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0200] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A method for determining memory design, characterized in that, The method includes: Eye diagram data corresponding to various initial memory designs are obtained. The eye diagram data is the hardware signal quality data obtained when performing eye diagram testing on memory using the initial memory design. Based on multiple eye diagram data and a preset dynamic transfer model, multiple first performance data corresponding to the various initial memory designs are determined. The dynamic transfer model is used to associate the eye diagram data and the performance data, and the performance data is the state data of the server running software. Among the plurality of first performance data, a plurality of second performance data that meet preset conditions are determined, and a plurality of initial memory designs corresponding to the plurality of second performance data are determined as a plurality of candidate memory designs; Determine the material parameters of the materials for the various candidate memory designs; Based on the material parameters of the materials in the multiple candidate memory designs, the target memory design is determined among the multiple candidate memory designs.
2. The method according to claim 1, characterized in that, Before determining a plurality of second performance data that satisfy preset conditions from the plurality of first performance data, the method further includes: If at least one third performance data does not meet the preset condition among the plurality of first performance data, at least one initial memory design corresponding to at least one third performance data is determined as at least one memory design to be tuned. For any memory design to be tuned, adjust the software parameters in the memory design to be tuned; obtain the eye diagram data corresponding to the adjusted memory design to be tuned, and based on the eye diagram data corresponding to the adjusted memory design to be tuned and the dynamic transfer model, redetermine the first performance data corresponding to the adjusted memory design to be tuned, until the first performance data corresponding to the memory design to be tuned meets the preset conditions or reaches the maximum number of adjustments.
3. The method according to claim 2, characterized in that, The adjustment of software parameters in the memory design to be tuned includes: Determine the performance difference between the third performance data and the preset conditions; Based on the performance difference, the adjustment direction and adjustment range of the software parameters are determined in a preset parameter adjustment mapping table; Adjust the software parameters in the memory design to be tuned according to the adjustment direction and the adjustment range.
4. The method according to claim 1, characterized in that, The material parameters of the material based on the multiple candidate memory designs, in determining the target memory design from among the multiple candidate memory designs, include: Based on the sub-material parameters of each sub-material of the various candidate memory designs and the preset material input coefficients of each sub-material, the input score of the various candidate memory designs is determined, and the material input coefficients indicate the processing difficulty of the sub-materials in memory production; Based on the input scores of the multiple candidate memory designs, the target memory design is determined from among the multiple candidate memory designs.
5. The method according to claim 4, characterized in that, For any candidate memory design; based on the sub-material parameters of each sub-material of the materials in the multiple candidate memory designs and the preset material input coefficients of each sub-material, determine the input score of the multiple candidate memory designs, including: Obtain the preset material input coefficient for each sub-material; The input score of the candidate memory design is obtained by weighting and summing the sub-material parameters of each sub-material of the material based on the candidate memory design with the preset material input coefficient of each sub-material.
6. The method according to claim 4, characterized in that, The evaluation of the input based on the multiple candidate memory designs, and the determination of the target memory design from the multiple candidate memory designs, includes: Based on the input scores of the various candidate memory designs and the corresponding second performance data, a comprehensive score for the various candidate memory designs is determined. Among the various candidate memory designs, the candidate memory design with the lowest overall score is determined as the target memory design.
7. The method according to claim 6, characterized in that, For any candidate memory design; the comprehensive score of the candidate memory designs is determined based on the input scores and corresponding second performance data, including: The product of the input score corresponding to the candidate memory design and the preset input weight is determined as the comprehensive material input score corresponding to the candidate memory design. The product of the second performance data corresponding to the memory design and the preset performance weight is determined as the comprehensive performance score corresponding to the candidate memory design. The difference between the overall score of the material input and the overall performance score is determined as the overall score of the memory design.
8. A memory design determination device, characterized in that, include: The first processing module is used to acquire eye diagram data corresponding to various initial memory designs. The eye diagram data is the hardware signal quality data obtained when performing eye diagram testing on memory using the initial memory design. The second processing module is used to determine multiple first performance data corresponding to the multiple initial memory designs based on multiple eye diagram data and a preset dynamic transfer model. The dynamic transfer model is used to associate the eye diagram data and the performance data. The performance data is the state data of the server running software. The third processing module is used to determine, from the plurality of first performance data, a plurality of second performance data that meet preset conditions, and to determine the plurality of initial memory designs corresponding to the plurality of second performance data as a plurality of candidate memory designs; The fourth processing module is used to determine the material parameters of the materials for the various candidate memory designs; The fifth processing module is used to determine the target memory design from among the multiple candidate memory designs based on the material parameters of the materials in the multiple candidate memory designs.
9. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 7.