A p-type topcon cell and a preparation method thereof

Abstract

The application discloses a P-type TOPCon cell and a preparation method thereof. The P-type TOPCon cell takes P-type crystalline silicon as a substrate, and the front surface of the P-type TOPCon cell comprises, from inside to outside, a tunneling oxide layer, a phosphorus-doped polysilicon stack and a front composite passivation layer. The phosphorus-doped polysilicon stack comprises, from inside to outside, a first phosphorus-doped polysilicon film, a first silicon oxide film, a second phosphorus-doped polysilicon film, a second silicon oxide film and a third phosphorus-doped polysilicon film. The phosphorus doping concentration and the thickness of the third phosphorus-doped polysilicon film are greater than those of the first phosphorus-doped polysilicon film. The preparation method comprises preparing the tunneling oxide layer, the phosphorus-doped polysilicon stack and the front composite passivation layer on the front surface of the P-type crystalline silicon. The P-type TOPCon cell has the advantages of excellent anti-space radiation capability, high conversion efficiency, long service life and the like. As a novel solar cell with excellent performance, the P-type TOPCon cell can adapt to a harsh space environment and meet the demand of modern spacecraft for high-performance power supplies.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology and relates to a P-type TOPCon cell and its preparation method. Background Technology

[0002] Existing cadmium telluride solar modules are expensive, and with the increasing number of commercial satellites, there are growing demands for both cost and performance of space power supplies. Conventional N-type crystalline silicon cells have high conversion efficiency, but their resistance to ultraviolet and high-energy particle radiation is poor. Electrons, which are the charge carriers, are easily trapped by lattice defects generated by high-energy radiation, and these defects are difficult to repair through thermal processes. Under long-term radiation, performance degradation continues to accelerate, and the minority carrier lifetime decreases rapidly, making them unsuitable for long-term space service. Traditional P-type cells (BSF and PERC) have stronger radiation resistance, but their low conversion efficiency makes them unsuitable for the high-performance power requirements of modern spacecraft.

[0003] P-type TOPCon solar cells include front junction cells and back junction cells. In the front junction cell, the pn junction is located on the light-receiving surface (front N-type doped layer), while in the back junction cell, the pn junction is located on the back side (back N-type doped layer). However, existing P-type TOPCon front junction cells require the use of masks, which is cumbersome and costly. For example, one existing method for fabricating a P-type TOPCon front junction cell requires first fabricating a tunneling oxide layer and a boron-doped amorphous silicon layer on the back side (through high-temperature annealing or high-temperature boron expansion), followed by phosphorus expansion after front-side treatment. This process is complex and carries the risk of edge leakage. Alternatively, a silicon oxide layer can be grown on the textured surface of the silicon wafer and a phosphosilicate glass layer (P2O5) can be deposited before covering it with a silicon nitride mask. Existing P-type TOPCon back-junction solar cells lack an effective PN junction on the front side, resulting in low short-wavelength quantum efficiency. Mass production conversion efficiency is significantly lower than that of N-type TOPCon cells. Furthermore, silicon wafer quality (minority carrier lifetime) significantly impacts performance, making stability difficult to guarantee. If only a single n-poly layer is used for passivation on the front side, the parasitic absorption of light by the polycrystalline silicon layer is heavy, affecting the cell's power performance. For example, a method for fabricating a P-type TOPCon back-junction solar cell has been proposed in the prior art, which can replace N-type silicon wafers in conventional TOPCon cell production lines with P-type silicon wafers with minimal changes to other aspects. However, this approach suffers from low carrier separation efficiency and heavy recombination on the cell surface due to the lack of a PN junction on the front side (limited high-low junction effect), resulting in low short-wavelength quantum efficiency and slightly lower mass production efficiency.

[0004] For the reasons stated above, this invention is proposed. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a P-type TOPCon battery that has excellent resistance to space radiation, high conversion efficiency and long service life, as well as a P-type TOPCon battery preparation method with simple process and high production line compatibility.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A P-type TOPCon solar cell uses P-type crystalline silicon as a substrate. The front side of the substrate, from the inside out, includes: a tunneling oxide layer, a phosphorus-doped polycrystalline silicon stack, and a front composite passivation layer. The phosphorus-doped polycrystalline silicon stack, from the inside out, consists of a first phosphorus-doped polycrystalline silicon film, a first silicon oxide film, a second phosphorus-doped polycrystalline silicon film, a second silicon oxide film, and a third phosphorus-doped polycrystalline silicon film. The phosphorus doping concentration in the third phosphorus-doped polycrystalline silicon film is greater than that in the first phosphorus-doped polycrystalline silicon film. The thickness of the third phosphorus-doped polycrystalline silicon film is greater than that of the first phosphorus-doped polycrystalline silicon film. The front side of the substrate also includes a front metal electrode; the front metal electrode penetrates the front composite passivation layer and forms an ohmic contact with the third phosphorus-doped polycrystalline silicon thin film.

[0007] In a further improvement of the aforementioned P-type TOPCon battery, the thickness of the phosphorus-doped polycrystalline silicon stack is 40 nm to 180 nm.

[0008] In a further improvement of the aforementioned P-type TOPCon cell, the thickness of the first phosphorus-doped polycrystalline silicon film is 10 nm to 30 nm; the thickness of the first silicon oxide film is 0.3 nm to 2 nm; the thickness of the second phosphorus-doped polycrystalline silicon film is 10 nm to 30 nm; the thickness of the second silicon oxide film is 0.3 nm to 2 nm; and the thickness of the third phosphorus-doped polycrystalline silicon film is 30 nm to 120 nm.

[0009] In a further improvement of the aforementioned P-type TOPCon cell, the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon thin film is 1×10⁻⁶. 19 / cm 3 ~5×10 19 / cm 3 The phosphorus doping concentration in the second phosphorus-doped polycrystalline silicon thin film is 5 × 10⁻⁶. 19 / cm 3 ~10×10 19 / cm 3 The phosphorus doping concentration in the third phosphorus-doped polycrystalline silicon thin film is 1×10⁻⁶. 20 / cm 3 ~5×10 20 / cm 3 .

[0010] In a further improvement of the aforementioned P-type TOPCon battery, the P-type crystalline silicon is a P-type gallium-doped monocrystalline silicon wafer; the resistivity of the P-type gallium-doped monocrystalline silicon wafer is 0.6 Ω. cm~50 Ω cm; the minority carrier lifetime of the P-type gallium-doped single-crystal silicon wafer is above 300 µs.

[0011] In a further improvement of the aforementioned P-type TOPCon battery, the tunneling oxide layer is a SiO2 thin film; the thickness of the tunneling oxide layer is 1 nm to 2.5 nm.

[0012] In a further improvement of the aforementioned P-type TOPCon battery, the front composite passivation layer consists of an AlOx thin film and a SixNy stacked film from the inside out; the thickness of the AlOx thin film is 4.5 nm to 10 nm; the total thickness of the SixNy stacked film is 65 nm to 80 nm, and the refractive index is 2.0 to 2.3; the SixNy stacked film consists of a SixNy thin film, a SiNOx thin film, and a SiOx thin film from the inside out.

[0013] In a further improvement to the aforementioned P-type TOPCon battery, the front metal electrode is a silver electrode.

[0014] The aforementioned P-type TOPCon cell is further improved in that the back side of the substrate includes, from the inside out, a boron-doped polycrystalline silicon layer and a back composite passivation layer.

[0015] In a further improvement to the aforementioned P-type TOPCon battery, the back side of the substrate also includes a back metal electrode; the back metal electrode penetrates the back composite passivation layer and forms an ohmic contact with the boron-doped polycrystalline silicon layer.

[0016] In a further improvement of the aforementioned P-type TOPCon battery, the back composite passivation layer consists of an AlOx thin film and a SixNy stacked film from the inside out; the thickness of the AlOx thin film is 4.5 nm to 10 nm; the thickness of the SixNy stacked film is 65 nm to 80 nm, and the refractive index is 2.0 to 2.3; the SixNy stacked film consists of a SixNy thin film, a SiNOx thin film, and a SiOx thin film from the inside out.

[0017] In a further improvement to the aforementioned P-type TOPCon battery, the back metal electrode is a silver-aluminum electrode.

[0018] As a general technical concept, the present invention also provides a method for preparing a P-type TOPCon battery, comprising the following steps: S1. Pretreatment of P-type crystalline silicon; S2. With the back side of the P-type crystalline silicon facing upwards, perform boron diffusion on the back side of the P-type crystalline silicon to form a boron-doped polycrystalline silicon layer and a BSG layer on the back side of the P-type crystalline silicon. S3. The front side of the P-type crystalline silicon is cleaned, polished, and texturized in sequence to remove the BSG layer and boron-doped polycrystalline silicon layer on the front side and edges, and to form a textured surface on the front side. S4. A tunneling oxide layer is deposited on the front side of the P-type crystalline silicon, and an intrinsic polycrystalline silicon thin film and a silicon oxide thin film are alternately deposited on the tunneling oxide layer to form a silicon oxide thin film / intrinsic polycrystalline silicon passivation stack; the silicon oxide thin film / intrinsic polycrystalline silicon passivation stack consists of, from the inside to the outside, a first intrinsic polycrystalline silicon thin film, a first silicon oxide thin film, a second intrinsic polycrystalline silicon thin film, a second silicon oxide thin film, and a third intrinsic polycrystalline silicon thin film; S5. Thin and oxidize the polysilicon layer in the non-gate area, and grow an oxide layer on the surface of the polysilicon layer. S6. Phosphorus diffusion is performed on the front side of the P-type crystalline silicon, and a phosphorus-doped polycrystalline silicon layer and a PSG layer are formed by plating polycrystalline silicon around the front, edge and back of the P-type crystalline silicon, and a BPSG layer is formed at the back edge. S7. Laser SE heavy doping is performed on the gate line region on the front side of P-type crystalline silicon to form a phosphorus-doped polycrystalline silicon stack in the gate line region on the front side of P-type crystalline silicon. S8. Remove the PSG and BPSG layers on the back and sides of the P-type crystalline silicon. S9. Remove the phosphorus-doped polysilicon layer on the back and sides of the P-type crystalline silicon, and remove the BSG layer on the back and the PSG layer on the front. S10. With the back side of the P-type crystalline silicon facing down, deposit AlOx thin films on the front and back sides of the P-type crystalline silicon respectively. S11. Deposit SixNy stacked films on the AlOx thin films on the front and back sides of P-type crystalline silicon, respectively, and form a front composite passivation layer and a back composite passivation layer on the front and back sides of P-type crystalline silicon, respectively. S12. Prepare front metal electrodes and back metal electrodes on the front and back sides of P-type crystalline silicon, respectively; S13. Laser-assisted sintering is performed on the back side of the P-type crystalline silicon to form a low-resistance contact in the back metal electrode area.

[0019] In a further improvement to the above preparation method, step S1 includes the following pretreatment: alkaline washing of the front and back sides of the P-type crystalline silicon with an alkaline solution, and texturing of the front and back sides of the P-type crystalline silicon with an alkaline solution containing a texturing additive; the alkaline solution is a KOH solution or a NaOH solution; the mass concentration of the alkaline solution is 3%–5%; the texturing is performed at a temperature of 30℃–98℃; the texturing time is 100s–600s; the P-type crystalline silicon is a P-type gallium-doped single-crystal silicon wafer; the resistivity of the P-type gallium-doped single-crystal silicon wafer is 0.6 Ω. cm~50 Ω cm; the minority carrier lifetime of the P-type gallium-doped single-crystal silicon wafer is above 300 µs.

[0020] In a further improvement to the above preparation method, in step S2, the process parameters for boron diffusion are as follows: temperature is 960℃~1050℃, boron source is BCl3, flow rate is 200sccm~500sccm, O2 flow rate is 10000sccm~30000sccm; the thickness of the BSG layer is 80 nm~130 nm; and the diffusion sheet resistance of the BSG layer is 200Ω / sq~300Ω / sq.

[0021] In a further improvement to the above preparation method, in step S3, the front side of the P-type crystalline silicon is cleaned with an HF solution, polished with an alkaline solution containing additives, and texturized with an alkaline solution containing texturing additives; the mass concentration of the HF solution is 10% to 50%; the alkaline solution is a KOH solution or a NaOH solution; and the mass concentration of the alkaline solution is 3% to 5%.

[0022] In a further improvement to the above preparation method, step S4 involves depositing a tunneling oxide layer, an intrinsic polycrystalline silicon thin film, and a silicon oxide thin film using an LPCVD device. The deposition process parameters for the tunneling oxide layer are: O2 as the introduced gas, a gas flow rate of 5000 sccm to 20000 sccm, a deposition time of 120 s to 1800 s, and a deposition temperature of 550℃ to 650℃. The deposition process parameters for the intrinsic polycrystalline silicon thin film are: SiH4 as the introduced gas, a flow rate of 200 sccm to 2000 sccm, a deposition time of 1000 s to 2000 s, and a deposition temperature of 550℃ to 650℃. The deposition process parameters for the silicon oxide thin film are: O2 as the introduced gas, a gas flow rate of 5000 sccm to 20000 sccm, and a deposition time of 120 s to 1800 s. The deposition time is 120s to 1800s, and the deposition temperature is 550℃ to 650℃. The tunneling oxide layer is a SiO2 thin film. The thickness of the tunneling oxide layer is 1 nm to 2.5 nm. The thickness of the silicon oxide thin film / intrinsic polycrystalline silicon passivation stack is 50 nm to 180 nm. The thickness of the first intrinsic polycrystalline silicon thin film is 10 nm to 30 nm. The thickness of the first silicon oxide thin film is 0.3 nm to 2 nm. The thickness of the second intrinsic polycrystalline silicon thin film is 10 nm to 30 nm. The thickness of the second silicon oxide thin film is 0.3 nm to 2 nm. The thickness of the third intrinsic polycrystalline silicon thin film is 30 nm to 120 nm.

[0023] In a further improvement to the above preparation method, step S5 involves using a laser to thin and oxidize the polycrystalline silicon layer in the non-gateline region.

[0024] In a further improvement to the above preparation method, in step S6, the process parameters for phosphorus diffusion are as follows: the phosphorus source is POCl3, the diffusion temperature is 800℃~930℃, and the time is 1000s~2400s; the total thickness of the phosphorus-doped polycrystalline silicon layer is 40 nm~150 nm; and the thickness of the PSG layer is 20 nm~60 nm.

[0025] In a further improvement to the above preparation method, in step S8, an HF solution is used in a chain cleaning machine to clean the back and sides of the P-type crystalline silicon to remove the PSG layer and BPSG layer on the back and sides of the P-type crystalline silicon; the mass concentration of the HF solution is 3% to 40%.

[0026] In a further improvement to the above preparation method, in step S9, an alkaline solution is used to perform alkaline washing on the back and sides of the P-type crystalline silicon in a tank cleaning machine to remove the phosphorus-doped polycrystalline silicon layer on the back and sides of the P-type crystalline silicon; the alkaline solution is a KOH solution or a NaOH solution; the mass concentration of the alkaline solution is 3% to 5%; an HF solution is used to perform acid washing on the P-type crystalline silicon to remove the BSG layer on the back and the PSG layer on the front; the mass concentration of the HF solution is 5% to 40%.

[0027] In a further improvement to the above preparation method, in step S10, an atomic layer deposition process is used to deposit AlOx thin films on the front and back sides of the P-type crystalline silicon, respectively; the deposition process parameters of the AlOx thin film are: trimethylaluminum as the aluminum source, water vapor as the oxygen source, and the process temperature is 250℃~300℃; the thickness of the AlOx thin film is 4.5 nm~10 nm.

[0028] In a further improvement to the above preparation method, in step S11, a SixNy multilayer film is deposited on the AlOx thin film on both the front and back sides of the P-type crystalline silicon using a PECVD process. When depositing the SixNy multilayer film on the AlOx thin film on both sides of the P-type crystalline silicon, the deposition process parameters for the SixNy multilayer film are: a SiH4 flow rate of 500 sccm to 3000 sccm, an NH3 flow rate of 5000 sccm to 18000 sccm, and a N2O flow rate of 8000 sccm to 15000 sccm; a deposition temperature of 380℃ to 500℃; and a film thickness of 65 nm to 80 nm with a refractive index of 2.0 to 2.3.

[0029] In a further improvement to the above preparation method, in step S12, silver paste and silver-aluminum paste are printed on the front and back sides of P-type crystalline silicon using screen printing technology, then dried, sintered, and photo-injected to prepare front and back metal electrodes on the front and back sides of the P-type crystalline silicon, respectively.

[0030] The above-described fabrication method is further improved in that the P-type TOPCon cell includes a positive junction structure. The positive junction structure uses P-type crystalline silicon as a substrate. The front side of the substrate, from the inside out, includes: a tunneling oxide layer, a phosphorus-doped polycrystalline silicon stack, and a front composite passivation layer. The phosphorus-doped polycrystalline silicon stack, from the inside out, consists of a first phosphorus-doped polycrystalline silicon film, a first silicon oxide film, a second phosphorus-doped polycrystalline silicon film, a second silicon oxide film, and a third phosphorus-doped polycrystalline silicon film. The phosphorus doping concentration in the third phosphorus-doped polycrystalline silicon film is greater than that in the first phosphorus-doped polycrystalline silicon film. The thickness of the third phosphorus-doped polycrystalline silicon film is greater than that of the first phosphorus-doped polycrystalline silicon film. The front side of the substrate also includes a front metal electrode; the front metal electrode penetrates the front composite passivation layer and forms an ohmic contact with the third phosphorus-doped polycrystalline silicon thin film.

[0031] In a further improvement to the above preparation method, the front metal electrode is a silver electrode.

[0032] In a further improvement to the above preparation method, the thickness of the phosphorus-doped polycrystalline silicon stack is 40 nm to 180 nm.

[0033] In a further improvement to the above preparation method, the thickness of the first phosphorus-doped polycrystalline silicon film is 10 nm to 30 nm; the thickness of the first silicon oxide film is 0.3 nm to 2 nm; the thickness of the second phosphorus-doped polycrystalline silicon film is 10 nm to 30 nm; the thickness of the second silicon oxide film is 0.3 nm to 2 nm; and the thickness of the third phosphorus-doped polycrystalline silicon film is 30 nm to 120 nm.

[0034] A further improvement to the above preparation method is that the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon thin film is 1×10⁻⁶. 19 / cm 3 ~5×10 19 / cm 3 The phosphorus doping concentration in the second phosphorus-doped polycrystalline silicon thin film is 5 × 10⁻⁶. 19 / cm 3 ~10×10 19 / cm 3 The phosphorus doping concentration in the third phosphorus-doped polycrystalline silicon thin film is 1×10⁻⁶. 20 / cm 3 ~5×10 20 / cm 3 .

[0035] In a further improvement to the above-described preparation method, the back side of the substrate comprises, from the inside out, a boron-doped polycrystalline silicon layer and a back composite passivation layer.

[0036] In a further improvement to the above-described preparation method, the back side of the substrate further includes a back metal electrode; the back metal electrode penetrates the back composite passivation layer and forms an ohmic contact with the boron-doped polycrystalline silicon layer.

[0037] In a further improvement to the above preparation method, the back metal electrode is a silver-aluminum electrode.

[0038] Compared with the prior art, the advantages of the present invention are as follows: (1) In the P-type TOPCon battery of the present invention, a tunneling oxide layer, a phosphorus-doped polycrystalline silicon stack, and a front composite passivation layer are disposed on the front side of the battery to form a positive junction structure. On the one hand, as a positive junction battery, it can take into account the radiation decay resistance advantage of P-type crystalline silicon batteries. On the other hand, the phosphorus-doped polycrystalline silicon stack used is a polycrystalline silicon stack structure constructed from phosphorus-doped polycrystalline silicon thin films of different thicknesses and doping concentrations. It can not only reduce the polycrystalline silicon layer (removing 50-80%), but also reduce the parasitic absorption and surface light reflection loss of the polycrystalline silicon layer. More importantly, the polycrystalline silicon stack structure can effectively suppress metal growth and block the penetration of the silver metal electrode into the interface oxide layer, thereby suppressing the risk of metal puncture. It can not only significantly reduce metal recombination loss and improve battery efficiency, but also improve the long-term reliability of the battery and make the battery life longer. In addition, under the combined action of the tunneling oxide layer, the phosphorus-doped polycrystalline silicon stack, and the front composite passivation layer, the contact area can be increased to fully neutralize the surface dangling bonds, improve minority carrier lifetime and reduce carrier recombination, and significantly improve the battery efficiency. Furthermore, the fabrication process of this battery is highly compatible with the conventional N-type TOPCon battery route, requiring no additional mask deposition, which helps reduce production costs and facilitates large-scale industrial production. The P-type TOPCon battery of this invention combines excellent resistance to space radiation, high conversion efficiency, and long lifespan. As a high-performance novel solar cell, it can adapt to the harsh space environment and meet the high-performance power requirements of modern spacecraft.

[0039] (2) In the P-type TOPCon cell of the present invention, the thickness of the phosphorus-doped polycrystalline silicon stack is optimized to be 40 nm to 180 nm, wherein the thickness of the first phosphorus-doped polycrystalline silicon film is 10 nm to 30 nm, the thickness of the first silicon oxide film is 0.3 nm to 2 nm, the thickness of the second phosphorus-doped polycrystalline silicon film is 10 nm to 30 nm, the thickness of the second silicon oxide film is 0.3 nm to 2 nm, and the thickness of the third phosphorus-doped polycrystalline silicon film is 30 nm to 120 nm. By optimizing the total thickness of the phosphorus-doped polycrystalline silicon stack and the thickness of each film, the useless absorption of near-infrared light can be reduced. Combined with the textured reflective structure, the overall light utilization rate can be improved by about 2% to 3%, and the passivation performance, conductivity and resistance to metal penetration are balanced, ultimately ensuring that a solar cell with better performance is obtained. However, if the silicon oxide film is too thin (below 0.3 nm), the oxide layer is incomplete, the pinhole defect density increases significantly, minority carrier recombination is exacerbated, J0 (dark saturation current density) increases by 2-3 times, and Voc (open circuit voltage) decreases by 10-20 mV. Conversely, if the silicon oxide film is too thick (above 2 nm), carrier transport resistance increases, contact resistivity increases by more than an order of magnitude, and the FF (fade angle) decreases by 3%-5%, leading to a significant decrease in battery efficiency. Furthermore, if the first and second phosphorus-doped polycrystalline silicon films are too thick, the total thickness of the low-doped layer becomes too large, increasing overall parasitic absorption, lengthening the lateral carrier transport path, and increasing series resistance. If the first and second phosphorus-doped polycrystalline silicon films are too thin, an effective low-doped buffer layer cannot be formed, allowing high-concentration impurities to easily diffuse to the tunneling oxide interface, reducing passivation effect. Moreover, if the third phosphorus-doped polycrystalline silicon film is too thin, it leads to insufficient resistance to metal corrosion, a significantly increased risk of silver paste burn-through, increased contact resistance, and exacerbated metal recombination. Simultaneously, if the third phosphorus-doped polycrystalline silicon film is too thick, it significantly increases optical loss.

[0040] (3) In the P-type TOPCon cell of the present invention, the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon thin film is optimized to be 1×10⁻⁶. 19 / cm 3 ~5×10 19 / cm 3 The phosphorus doping concentration in the second phosphorus-doped polycrystalline silicon thin film is 5 × 10⁻⁶. 19 / cm 3 ~10×10 19 / cm 3 The phosphorus doping concentration in the third phosphorus-doped polycrystalline silicon thin film is 1×10⁻⁶. 20 / cm 3 ~5×10 20 / cm 3In this process, the first phosphorus-doped polycrystalline silicon thin film, employing a lower doping concentration, can reduce high-doping recombination losses while ensuring a sufficient majority carrier concentration to achieve efficient carrier tunneling and transport. This, combined with the tunneling oxide layer, results in excellent interface passivation. However, if the doping concentration in the first phosphorus-doped polycrystalline silicon thin film is lower than 1×10⁻⁶, the... 19 / cm 3 This will lead to an increase in the polysilicon layer resistance, an increase in carrier transport resistance, and an increase in contact resistance, especially when the concentration is higher than 5×10⁻⁶. 19 / cm 3 The first phosphorus-doped polycrystalline silicon film, acting as an intermediate transition layer, has a doping concentration between the first and third layers, forming a gradient doping structure. This reduces the barrier for carrier transport between layers and further suppresses recombination, improving passivation. The third phosphorus-doped polycrystalline silicon film, in direct contact with the front metal electrode, uses a high doping concentration to effectively reduce contact resistance and form a good ohmic contact. High doping concentration also prevents silver atoms in the metal electrode from diffusing into the stack, suppressing the risk of metal puncture and improving the long-term reliability of the battery. However, the doping concentration in the contact area of ​​the third phosphorus-doped polycrystalline silicon film generally needs to reach 1×10⁻⁶. 20 / cm 3 Only the above can achieve low contact resistance, while concentrations higher than 5×10 20 / cm 3 This can lead to enhanced parasitic absorption in the polycrystalline silicon layer, reducing the quantum efficiency of short-wavelength light, and potentially causing a decrease in the crystal quality of the polycrystalline silicon layer and an increase in defects. Therefore, optimizing the phosphorus doping concentration in the first, second, and third phosphorus-doped polycrystalline silicon films yields the following benefits: low doping in the inner layer ensures passivation, while high doping in the outer layer ensures contact performance, improving the open-circuit voltage and fill factor of the battery; low doping in the inner layer reduces light absorption by high-concentration impurities, improving the utilization efficiency of short-wavelength light and optimizing the short-circuit current; and the high doping and thick film structure in the outer layer effectively blocks the diffusion of metal atoms, improving the long-term operational stability of the battery.

[0041] (4) In the P-type TOPCon battery of the present invention, the front and back composite passivation layers are AlOx thin film and SixNy stacked film from the inside to the outside. At the same time, by optimizing the thickness of each film, the problem of ultraviolet degradation of the battery can be significantly improved.

[0042] (5) This invention also provides a method for fabricating a P-type TOPCon cell, which innovatively proposes a P-type substrate combined with a TOPCon structure, a back junction flipped to a front junction, a simplified process without a mask, aluminum grid lines on the back side replacing silver grids, a poly-finger thinning polycrystalline silicon layer on the front side plus a textured light-trapping structure, and a polycrystalline silicon stacked structure. This effectively solves the problems of poor radiation resistance of existing N-type TOPCon cells, low conversion efficiency and poor bifaciality of traditional P-type cells, cumbersome and costly masking process of conventional P-type TOPCon, low quantum efficiency of back junction cells in the short-wavelength band, poor stability due to the large impact of silicon wafer quality, and high risk of parasitic absorption and metal puncture in polycrystalline silicon layers. It not only retains the radiation resistance advantage of P-type cells, but also greatly optimizes the fabrication process and performance of P-type TOPCon cells, as detailed below: (a) By innovatively converting the back junction cell into a front junction cell, replacing the masking process of the traditional front junction P-type TOPCon, the process is simplified and the stability is improved. The flip design eliminates the masking process, reduces production steps, reduces process pollution, and lowers equipment investment and manufacturing costs.

[0043] (b) The front side adopts a poly-finger thinned polycrystalline silicon layer combined with a textured surface light trapping design, which replaces the traditional thick polycrystalline silicon layer structure, reduces the parasitic absorption and light reflection loss of the polycrystalline silicon layer, and indirectly improves the short-circuit current.

[0044] (c) The front side adopts a polycrystalline silicon stacked structure, which can effectively suppress metal growth and block the penetration of the silver metal electrode into the interface oxide layer. This can suppress the risk of metal puncture, which can not only significantly reduce metal recombination loss and improve battery efficiency, but also improve the long-term reliability of the battery and make the battery life longer.

[0045] (d) The back side uses silver aluminum grid lines instead of silver grid lines to reduce the cost of using precious metals.

[0046] (e) By depositing a tunnel oxide layer + polysilicon stack structure on the textured surface using an LPCVD device, the contact area is increased to fully neutralize the surface dangling bonds, improve minority carrier lifetime and reduce carrier recombination.

[0047] (f) By combining laser-assisted sintering process, low-resistance contact is formed in the electrode area, improving carrier collection efficiency and effectively solving the problem of bifaciality difference in traditional P-type batteries, which is suitable for the needs of high-reflectivity space scenarios. Attached Figure Description

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0049] Figure 1 This is a schematic diagram of the cross-sectional structure of the P-type TOPCon battery in Embodiment 1 of the present invention.

[0050] Figure 2 This is a process flow diagram of the P-type TOPCon battery fabrication in Embodiment 1 of the present invention.

[0051] Legend: 1. P-type crystalline silicon; 2. Tunneling oxide layer; 3. Phosphorus-doped polycrystalline silicon stack; 4. AlOx thin film; 5. SixNy stack film; 6. Front metal electrode; 7. Boron-doped polycrystalline silicon layer; 8. Back metal electrode. Detailed Implementation

[0052] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.

[0053] In the following embodiments of the present invention, unless otherwise specified, the materials and instruments used are commercially available, the equipment used is conventional equipment, and the data obtained are the average values ​​of more than three repeated experiments.

[0054] Example 1: like Figure 1 As shown, a P-type TOPCon cell uses P-type crystalline silicon 1 as a substrate. On the front side of the substrate, from the inside out, it includes: a tunneling oxide layer 2, a phosphorus-doped polycrystalline silicon stack 3, and a front composite passivation layer. The phosphorus-doped polycrystalline silicon stack 3 consists of a first phosphorus-doped polycrystalline silicon film, a first silicon oxide film, a second phosphorus-doped polycrystalline silicon film, a second silicon oxide film, and a third phosphorus-doped polycrystalline silicon film from the inside out. The phosphorus doping concentration in the third phosphorus-doped polycrystalline silicon film is greater than that in the first phosphorus-doped polycrystalline silicon film, and the thickness in the third phosphorus-doped polycrystalline silicon film is greater than that in the first phosphorus-doped polycrystalline silicon film. The front side of the substrate also includes a front metal electrode 6, which penetrates the front composite passivation layer and forms an ohmic contact with the third phosphorus-doped polycrystalline silicon thin film.

[0055] In conventional P-type TOPCon cells, the passivation level of the monolayer poly-Si on the back is typically only 3-5 fA / cm. 2 The bilayer polycrystalline silicon structure can effectively improve the n+ passivation quality to 1.5-2 fA / cm. 2 In this invention, the phosphorus-doped polycrystalline silicon stack 3 has a multi-layer oxide polycrystalline silicon structure, and the passivation limit level can reach <1 fA / cm. 2By reducing the phosphorus concentration in the interface silicon oxide region and increasing the overall hydrogen content of poly, the passivation quality is improved. Moreover, it can inhibit the growth of silver crystals, block the penetration of electrode silver into the interface oxide layer, significantly reduce metal recombination loss, and increase short-circuit current density (Jsc) and open-circuit voltage (Voc). At the same time, poly-Si has high absorption of short-wavelength light, and the superimposed poly-Si / SiOx is not easily damaged by hot carriers, thus improving the battery's UV resistance.

[0056] In this embodiment, the total thickness of the phosphorus-doped polycrystalline silicon stack 3 is 142 nm.

[0057] In this embodiment, the thickness of the first phosphorus-doped polycrystalline silicon film is 20 nm, the thickness of the first silicon oxide film is 1 nm, the thickness of the second phosphorus-doped polycrystalline silicon film is 20 nm, the thickness of the second silicon oxide film is 1 nm, and the thickness of the third phosphorus-doped polycrystalline silicon film is 100 nm.

[0058] In other embodiments, the thickness of the first phosphorus-doped polycrystalline silicon thin film may also be 10 nm, 12 nm, 14 nm, 15 nm, 18 nm, 22 nm, 25 nm, 27 nm, 28 nm, or 30 nm, but is not limited thereto.

[0059] In other embodiments, the thickness of the first silicon oxide film may also be 0.3 nm, 0.5 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1.1 nm, 1.3 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, or 2 nm, but is not limited thereto.

[0060] In other embodiments, the thickness of the second phosphorus-doped polycrystalline silicon film may also be 10 nm, 12 nm, 14 nm, 15 nm, 18 nm, 22 nm, 25 nm, 27 nm, 28 nm, or 30 nm, but is not limited thereto.

[0061] In other embodiments, the thickness of the second silicon oxide film may also be 0.3 nm, 0.5 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1.1 nm, 1.3 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, or 2 nm, but is not limited thereto.

[0062] In other embodiments, the thickness of the third phosphorus-doped polycrystalline silicon film may also be 10 nm, 12 nm, 14 nm, 15 nm, 18 nm, 22 nm, 25 nm, 27 nm, 28 nm, 30 nm, 32 nm, 35 nm, 40 nm, 48 nm, 52 nm, 55 nm, 57 nm, 60 nm, 65 nm, 70 nm, 78 nm, 82 nm, 85 nm, 87 nm, 90 nm, 95 nm, 105 nm, 108 nm, 112 nm, 115 nm, 117 nm, or 120 nm, but is not limited to these.

[0063] In this embodiment, the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon thin film is 2×10⁻⁶. 19 / cm 3 The phosphorus doping concentration in the second phosphorus-doped polycrystalline silicon thin film is 7 × 10⁻⁶. 19 / cm 3 The phosphorus doping concentration in the third phosphorus-doped polycrystalline silicon thin film is 3×10⁻⁶. 20 / cm 3 .

[0064] In other embodiments, the phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon thin film is 1×10⁻⁶. 19 / cm 3 1.5×10 19 / cm 3 2.5×10 19 / cm 3 3×10 19 / cm 3 4.5×10 19 / cm 3 4×10 19 / cm 3 4.5×10 19 / cm 3 5×10 19 / cm 3 However, it is not limited to this.

[0065] In other embodiments, the phosphorus doping concentration in the second phosphorus-doped polycrystalline silicon thin film is 5 × 10⁻⁶. 19 / cm 3 5.5×10 19 / cm 3 6×10 19 / cm 3 6.5×10 19 / cm 3 7.5×10 19 / cm 3 8×10 19 / cm3 8.5×10 19 / cm 3 9×10 19 / cm 3 9.5×10 19 / cm 3 10×10 19 / cm 3 However, it is not limited to this.

[0066] In other embodiments, the phosphorus doping concentration in the third phosphorus-doped polycrystalline silicon thin film is 1×10⁻⁶. 20 / cm 3 1.5×10 20 / cm 3 2×10 20 / cm 3 2.5×10 20 / cm 3 3.5×10 20 / cm 3 4×10 20 / cm 3 4.5×10 20 / cm 3 5×10 20 / cm 3 However, it is not limited to this.

[0067] In this embodiment, the P-type crystalline silicon 1 used is a P-type gallium-doped single-crystal silicon wafer, and the resistivity of this P-type gallium-doped single-crystal silicon wafer is 0.6 Ω. cm~50 Ω cm, minority carrier lifetime is above 300us, for example, minority carrier lifetime is 500us-2ms.

[0068] In this embodiment, the tunneling oxide layer 2 is a SiO2 thin film with a thickness of 2nm.

[0069] In other embodiments, the thickness of the tunneling oxide layer 2 may also be 1 nm, 1.1 nm, 1.3 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.9 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, or 2.5 nm, but is not limited thereto.

[0070] In this embodiment, the front composite passivation layer consists of an AlOx thin film 4 and a SixNy stacked film 5 from the inside out.

[0071] In this embodiment, the AlOx thin film 4 used in the front composite passivation layer has a thickness of 6 nm.

[0072] In other embodiments, the thickness of the AlOx thin film 4 may also be 4.5 nm, 4.8 nm, 5.0 nm, 5.2 nm, 5.5 nm, 5.8 nm, 6.2 nm, 6.5 nm, 6.8 nm, 7.2 nm, 7.5 nm, 8.0 nm, 8.2 nm, 8.5 nm, 8.8 nm, 9.2 nm, 9.5 nm, or 10 nm, but is not limited to these.

[0073] In this embodiment, the SixNy stacked film 5 used in the front composite passivation layer has a thickness of 77 nm.

[0074] In other embodiments, the thickness of the SixNy stacked film 5 may be 65 nm, 67 nm, 68 nm, 70 nm, 72 nm, 75 nm, or 80 nm, but is not limited to these.

[0075] In this embodiment, the SixNy stacked film 5 used in the front composite passivation layer consists of a SixNy film, a SiNOx film, and a SiOx film from the inside out. Specifically, from the inside out, the layers are: a first SixNy film (28nm, refractive index 2.3) / a second SixNy film (12nm, refractive index 2.2) / a third SixNy film (12nm, refractive index 2.1) / a SiNOx film (15nm, refractive index 2.0) / a SiOx film (10nm, refractive index 1.85), with a total film thickness controlled at 77nm and a refractive index of 2.08.

[0076] In this embodiment, the front metal electrode 6 is a silver electrode.

[0077] In this embodiment, the back side of the substrate includes, from the inside out: a boron-doped polycrystalline silicon layer 7 and a back composite passivation layer.

[0078] In this embodiment, a back metal electrode 8 is also included on the back side of the substrate. After penetrating the back composite passivation layer, the back metal electrode 8 forms an ohmic contact with the boron-doped polycrystalline silicon layer 7. In this embodiment, the back composite passivation layer consists of an AlOx thin film 4 and a SixNy stacked film 5 from the inside out.

[0079] In this embodiment, the AlOx thin film 4 used in the back composite passivation layer has a thickness of 6 nm.

[0080] In this embodiment, the SixNy stacked film 5 used in the back composite passivation layer has a thickness of 77 nm.

[0081] In other embodiments, the thickness of the SixNy stacked film 5 may be 65 nm, 67 nm, 68 nm, 70 nm, 72 nm, 75 nm, or 80 nm, but is not limited to these.

[0082] In this embodiment, the SixNy stacked film 5 used in the back composite passivation layer consists of a SixNy film, a SiNOx film, and a SiOx film from the inside out. Specifically, from the inside out, the layers are: a first SixNy film (28nm, refractive index 2.3) / a second SixNy film (12nm, refractive index 2.2) / a third SixNy film (12nm, refractive index 2.1) / a SiNOx film (15nm, refractive index 2.0) / a SiOx film (10nm, refractive index 1.85), with a total film thickness controlled at 77nm and a refractive index of 2.08.

[0083] In this embodiment, the back metal electrode used is a silver-aluminum electrode.

[0084] A method for preparing a P-type TOPCon battery according to the above embodiments of the present invention is shown in the following process flow diagram. Figure 2 As shown, it includes the following steps: S1. Pretreatment of P-type crystalline silicon, specifically: S11. The front and back sides of the P-type crystalline silicon are washed with an alkaline solution to remove the damaged layer. The alkaline solution is a KOH solution with a mass concentration of 4%.

[0085] S12. Texturing is performed on the front and back sides of P-type crystalline silicon using an alkaline solution containing texturing additives to form a textured surface on both sides of the silicon wafer. The texturing is performed at a temperature of 35°C for 200 seconds. The alkaline solution containing texturing additives used is a KOH solution with a mass concentration of 4%.

[0086] In other embodiments, the texturing can also be carried out at temperatures of 30°C, 40°C, 45°C, 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, 80°C, 85°C, 90°C, 95°C, and 98°C, but is not limited thereto.

[0087] In other embodiments, the texturing time may also be 100s, 150s, 220s, 280s, 320s, 400s, 450s, 520s, 580s, or 600s, but is not limited to these.

[0088] In this embodiment, the texturing additive is a commercially available product, a composite system of multiple functional components, also known as a "single-crystal texturing additive." Its main components include surfactants, texturing catalysts, and texturing corrosion inhibitors. The texturing principle is as follows: surfactants reduce the surface tension of the solution, increase the reaction rate, remove surface impurities, and dissolve organic matter; the texturing catalyst slows down the reaction rate between Si and -OH, increasing the pyramid nucleation density and forming a large number of small pyramids; finally, the texturing corrosion inhibitor increases various factors, with a fast reaction rate on the 100-facet and a slow reaction rate on the 111-facet, ultimately completing pyramid growth.

[0089] In this invention, the mass concentration of the texturing additive in the KOH alkaline solution is 0.5%-1.5%. Specifically, in this embodiment, the mass concentration of the texturing additive in the KOH alkaline solution is 1%. In other embodiments, it can also be 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1.1%, 1.2%, 1.3%, 1.5%, or 1.5%, but is not limited thereto.

[0090] In this embodiment, the P-type crystalline silicon is a P-type gallium-doped single-crystal silicon wafer, and the resistivity of this P-type gallium-doped single-crystal silicon wafer is 0.6 Ω. cm~50 Ω cm, minority carrier lifetime is above 300us, for example, minority carrier lifetime is 500us-2ms.

[0091] S2. With the back side of the P-type silicon facing upwards, perform boron diffusion on the back side of the P-type silicon to form a boron-doped polycrystalline silicon layer (P+ layer) and a BSG layer on the back side of the P-type silicon. Specifically: A shallow boron-diffused emitter is formed on the back side of P-type crystalline silicon using high-temperature boron diffusion and oxidation, and BSG layers are formed on the sides and front edges. The BSG layer thickness is 100 nm, and the diffusion sheet resistance is 200 Ω / sq (using N-type resistivity of 0.6-2 Ω). (cm silicon wafer monitoring), the process parameters for boron diffusion are: diffusion oxidation temperature of 1000℃, boron source of BCl3 with a flow rate of 400 sccm, O2 oxidation flow rate of 20000 sccm, and wet oxygen oxidation can appropriately reduce the oxidation temperature and oxygen flow rate.

[0092] S3. The front side of the P-type crystalline silicon is cleaned, polished, and texturized sequentially to remove the BSG layer and boron-doped polycrystalline silicon layer on the front side and edges, and to form a textured surface on the front side, as detailed below: A chain cleaning machine was used to perform alkaline polishing and edge separation on the front side of the P-type crystalline silicon wafer. A 20% HF solution was used to remove the BSG layer on the front side and the edges of the silicon wafer, achieving an overall hydrophobic effect on the front side. The wafer was then placed in a tank machine and polished in a 3% KOH solution containing alkaline polishing additives to remove excess P+ layers on the front side and edges, while retaining the BSG layer on the back side. Finally, the wafer was placed in a 3% KOH solution containing texturing additives to texturize the front side, creating a textured surface.

[0093] In this embodiment, the alkaline polishing additive is a commercially available product. Its function is to slow down the corrosion rate of KOH and enhance the anisotropy of corrosion. Some components of the additive bind to the oxide layer surface, further increasing the protective properties of the oxide layer and extending the time before oxide layer degradation. This achieves front-side polishing while protecting the back side within the set process time. The mass concentration of the alkaline polishing additive in the KOH solution is 0.6%. In this embodiment, the texturing additive is a commercially available product, a composite system of multiple functional components, also known as a "single-crystal texturing additive." Its main components include surfactants, texturing catalysts, and texturing corrosion inhibitors. The texturing principle is as follows: surfactants reduce the surface tension of the solution, increase the reaction rate, remove surface impurities, and dissolve organic matter; the texturing catalyst slows down the reaction rate between Si and -OH, increasing the pyramid nucleation density and forming a large number of small pyramids; finally, the texturing corrosion inhibitor increases various factors, with a fast reaction rate on the 100-facet and a slow reaction rate on the 111-facet, ultimately completing pyramid growth.

[0094] In this invention, the mass concentration of the texturing additive in the KOH alkaline solution is 0.5%-1.5%. Specifically, in this embodiment, the mass concentration of the texturing additive in the KOH alkaline solution is 1%. In other embodiments, it can also be 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1.1%, 1.2%, 1.3%, 1.5%, or 1.5%, but is not limited thereto.

[0095] S4. A tunneling oxide layer is deposited on the front side of the P-type crystalline silicon. Intrinsic polycrystalline silicon thin films and silicon oxide thin films are alternately deposited on the tunneling oxide layer to form a silicon oxide thin film / intrinsic polycrystalline silicon passivation stack. This silicon oxide thin film / intrinsic polycrystalline silicon passivation stack, from the inside out, consists of a first intrinsic polycrystalline silicon thin film, a first silicon oxide thin film, a second intrinsic polycrystalline silicon thin film, a second silicon oxide thin film, and a third intrinsic polycrystalline silicon thin film, as detailed below: The tunneling oxide layer, intrinsic polycrystalline silicon thin film, and silicon oxide thin film were deposited using LPCVD equipment.

[0096] In this embodiment, the deposition process parameters for the tunneling oxide layer are as follows: the introduced gas is O2, the gas flow rate is 10000 sccm, the deposition time is 200s, and the deposition temperature is 580℃.

[0097] In this embodiment, the deposition process parameters for the intrinsic polycrystalline silicon thin film are as follows: the introduced gas is SiH4, the flow rate is 800 sccm, the deposition time is 1000 s to 2000 s, and the deposition temperature is 580℃. The deposition time is adjusted according to the different thickness requirements of the intrinsic polycrystalline silicon thin film.

[0098] In this embodiment, the deposition process parameters for the silicon oxide thin film are as follows: the introduced gas is O2, the gas flow rate is 10000 sccm, the deposition time is 200 s, and the deposition temperature is 580 ℃.

[0099] In this embodiment, the tunneling oxide layer is a SiO2 thin film with a thickness of 1 nm.

[0100] In this embodiment, the total thickness of the silicon oxide thin film / intrinsic polysilicon passivation stack is 142 nm.

[0101] In this embodiment, the thickness of the first intrinsic polycrystalline silicon thin film is 20 nm.

[0102] In this embodiment, the thickness of the first silicon oxide film is 1 nm.

[0103] In this embodiment, the thickness of the second intrinsic polycrystalline silicon thin film is 20 nm.

[0104] In this embodiment, the thickness of the second silicon oxide film is 1 nm.

[0105] In this embodiment, the thickness of the third intrinsic polycrystalline silicon thin film is 100 nm.

[0106] S5. Thinning and oxidizing the polysilicon layer (third intrinsic polysilicon thin film) in the non-gate area on the front side, and growing an oxide layer on the surface of the polysilicon layer, as follows: Lasers are used to ablate and thin the polycrystalline silicon layer in the non-metallic region or to modify the polycrystalline silicon. Then, laser thermal oxidation is used to grow an oxide layer on the thinned polycrystalline silicon surface, which reduces the subsequent phosphorus diffusion doping in this region.

[0107] In this step, the polysilicon in the non-gateway region is thinned and oxidized by laser, which reduces the thickness of the polysilicon while hindering phosphorus diffusion doping in the region.

[0108] S6. Phosphorus diffusion is performed on the front side of the P-type crystalline silicon. A phosphorus-doped polycrystalline silicon layer (N+ layer) and a PSG layer are formed by coating polycrystalline silicon around the front, edge, and back sides of the P-type crystalline silicon, and a BPSG layer is formed at the back edge, as detailed below: Phosphorus diffusion is performed on the front side of P-type crystalline silicon. An n-Poly layer (phosphorus-doped polysilicon layer) and a PSG layer (a BPSG layer is formed on the back edge) are formed by depositing polysilicon around the front, edge, and back surfaces of the silicon wafer. An N+ region is formed on the front side of the P-type crystalline silicon. The process parameters for phosphorus diffusion are as follows: the phosphorus source is POCl3, the diffusion temperature is 850℃, and the time is 1300s; the thickness of the deposited PSG layer is 40nm, and the total thickness of the n-Poly layer is 142nm. Due to the obstruction of the oxide layer in the non-gate area, the doping concentration is lower than that in the gate area.

[0109] S7. Laser SE heavy doping is performed on the gate line region on the front side of P-type crystalline silicon to increase the phosphorus doping concentration in the gate line contact region and form an N++ region. At the same time, an oxide protective film will still grow on the surface under thermal action. Thus, a thick and thin high and low phosphorus doped polycrystalline silicon stack is formed in the gate line region on the front side of P-type crystalline silicon, optimizing the contact and carrier transport, thereby improving the front electron collection efficiency and light utilization.

[0110] In this invention, forming a thick and thin polycrystalline silicon stack with high and low phosphorus doping in the gate line region on the front side of P-type crystalline silicon can bring the following advantages: Thin polycrystalline silicon (non-gateway region): Thinning to 70 nm can significantly reduce long-wavelength parasitic absorption of the polycrystalline silicon layer and improve the short-circuit current of the cell; at the same time, the surface oxide layer hinders subsequent phosphorus diffusion and reduces the doping concentration in this region.

[0111] Thick polycrystalline silicon (gate region): retains an initial thickness of 142 nm. This prevents subsequent metal paste from burning through, ensures low-ohmic contact with the metal electrode, and allows for high doping concentration in this region as there is no oxide layer obstruction.

[0112] Low doping concentration (non-gateline region): Due to oxide layer obstruction, phosphorus doping concentration is 1×10⁻⁶. 18 / cm 3 ~5×10 18 / cm 3 The sheet resistance is greater than 150 Ω / □. This reduces free carrier absorption in the polycrystalline silicon layer, further reducing optical loss and improving surface passivation.

[0113] High doping concentration (gate line region): No oxide layer obstruction, phosphorus diffuses fully, and the concentration can reach 1×10⁻⁶. 20 / cm 3 The sheet resistance is less than 80 Ω / □.

[0114] S8. Remove the PSG and BPSG layers on the back and sides of the P-type crystalline silicon, as follows: In the chain cleaning machine, a 35% HF solution is used to clean the back and sides of the P-type crystalline silicon, removing the PSG and BPSG layers on the back and sides of the P-type crystalline silicon, while the PSG on the front protects the front poly.

[0115] S9. Remove the phosphorus-doped polysilicon layers on the back and sides of the P-type crystalline silicon, and remove the BSG and PSG layers on the front and back sides, as follows: The silicon wafer is placed in a tank cleaning machine and cleaned with a 4% KOH solution (containing 6% RCA cleaning additive) to remove the phosphorus-doped polysilicon layer on the back edge and sides of the silicon wafer. Then, a 15% HF solution is used to remove the surface SiO2, the BSG layer on the back and the PSG layer on the front.

[0116] S10. With the back side of the P-type crystalline silicon facing down, deposit AlOx thin films on the front and back sides of the P-type crystalline silicon respectively. Specifically: AlOx thin films were deposited on the front and back surfaces of p-type crystalline silicon using atomic layer deposition (ALD). The deposition parameters for the AlOx thin films were as follows: trimethylaluminum (TMA) was used as the aluminum source, water vapor as the oxygen source, and the AlOx thin films were generated through the reaction of TMA with water vapor at a process temperature of 260°C. In this embodiment, the thickness of the AlOx thin films on both the front and back surfaces was 6 nm.

[0117] S11. Deposit SixNy stacked films on the AlOx thin films on the front and back sides of the P-type crystalline silicon, respectively, to form a front composite passivation layer and a back composite passivation layer on the front and back sides of the P-type crystalline silicon, respectively. Specifically: SixNy multilayer films are deposited on AlOx thin films on both the front and back sides of p-type crystalline silicon using PECVD. This process mainly involves preparing composite multilayer films (commonly referred to in the industry as silicon nitride or SixNy multilayer films) in the same equipment through stepwise deposition using formula editing. The SixNy portion of the multilayer film is formed by depositing a mixture of SiH4 and NH3 gases; the SiOx layer is formed by depositing a mixture of SiH4 and N2O gases; or the SiNOx layer is formed by depositing a mixture of all three gases. The refractive index of each single layer in the composite film is adjusted by changing the mixing ratio of two or three gases, and the thickness of each layer is adjusted by changing the deposition time, as detailed below: In this embodiment, when depositing a SixNy stacked film on the AlOx thin film on the front and back sides of P-type crystalline silicon, the deposition process parameters of the SixNy stacked film are: SiH4 flow rate of 1200 sccm, NH3 flow rate of 5200 sccm and N2O flow rate of 7400 sccm, and deposition temperature of 450℃.

[0118] S12. Prepare front-side metal electrodes and back-side metal electrodes on the front and back sides of P-type crystalline silicon, respectively. Specifically: Metal electrodes are fabricated on both the front and back sides using screen printing. Silver-aluminum paste is printed onto the P-region on the back side and silver paste onto the N-region on the front side using screen patterning technology. After printing, the pastes are dried. The silicon wafer with the printed electrode patterns is then rapidly sintered to achieve good ohmic contact between the metal electrodes and the phosphorus-doped polycrystalline silicon, and point contact with the boron-doped silicon (similar to the low-temperature sintering of N-type TOPCon). In the later stage of sintering, the cell is activated by photoinjection at medium to low temperatures to reduce the interface defect density.

[0119] S13. Laser precision scanning combined with deflection voltage is used to perform laser-assisted sintering (LECO) on the back side of P-type crystalline silicon, forming a low-resistance contact in the back metal electrode region and improving carrier collection efficiency.

[0120] Sorting test: By testing the current-voltage characteristic curve, key parameters such as battery conversion efficiency, short-circuit current, and open-circuit voltage are obtained, and efficiency classification is completed.

[0121] Table 1. Electrical performance of the P-type TOPCon battery prepared in Example 1

[0122] As shown in Table 1, compared with conventional P-type TOPCon batteries, the P-type TOPCon batteries prepared in this invention have superior electrical performance, with the photoelectric conversion efficiency (Eta) increased to 24.92%.

[0123] The three types of batteries in Table 1 were packaged into 2278×1134mm 144-pane double-glass modules using conventional POE+EVA. Their degradation under ultraviolet aging conditions was tested and compared. The results are shown in Table 2: Table 2 Comparison of degradation effects of different battery components

[0124] Note: UVID test: Under short-circuit conditions at 60℃, the front of the module is exposed to 60 / 120 kWh / m² of UV (280-400 nm), with the total UV dose equivalent to 1-2 years of outdoor exposure. The UVID test setup complies with IEC61215:2021MQT10 requirements, using metal halide lamps with UVB content in the range of 3-9%. This test assesses the power degradation risk of the module under ultraviolet radiation to ensure its reliability.

[0125] As can be seen from Tables 1 and 2, the P-type TOPCon battery of the present invention has the advantages of excellent resistance to space radiation, high conversion efficiency, and long service life. As a new type of high-performance solar cell, it can adapt to the harsh space environment and meet the needs of modern spacecraft for high-performance power.

[0126] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the spirit and technical essence of the present invention. Therefore, any simple modifications, equivalent substitutions, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall still fall within the protection scope of the technical solutions of the present invention.

Claims

1. A P-type TOPCon battery, using P-type crystalline silicon as a substrate, characterized in that, The front side of the substrate, from the inside out, includes: a tunneling oxide layer, a phosphorus-doped polycrystalline silicon stack, and a front composite passivation layer; the phosphorus-doped polycrystalline silicon stack, from the inside out, consists of a first phosphorus-doped polycrystalline silicon film, a first silicon oxide film, a second phosphorus-doped polycrystalline silicon film, a second silicon oxide film, and a third phosphorus-doped polycrystalline silicon film; the phosphorus doping concentration in the third phosphorus-doped polycrystalline silicon film is greater than that in the first phosphorus-doped polycrystalline silicon film; the thickness of the third phosphorus-doped polycrystalline silicon film is greater than that of the first phosphorus-doped polycrystalline silicon film; The front side of the substrate also includes a front metal electrode; the front metal electrode penetrates the front composite passivation layer and forms an ohmic contact with the third phosphorus-doped polycrystalline silicon thin film.

2. The P-type TOPCon battery according to claim 1, characterized in that, The thickness of the phosphorus-doped polycrystalline silicon stack is 40 nm to 180 nm. The thickness of the first phosphorus-doped polycrystalline silicon film is 10 nm to 30 nm; the thickness of the first silicon oxide film is 0.3 nm to 2 nm; the thickness of the second phosphorus-doped polycrystalline silicon film is 10 nm to 30 nm; the thickness of the second silicon oxide film is 0.3 nm to 2 nm; and the thickness of the third phosphorus-doped polycrystalline silicon film is 30 nm to 120 nm. The phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon thin film is 1×10⁻⁶. 19 / cm 3 ~5×10 19 / cm 3 The phosphorus doping concentration in the second phosphorus-doped polycrystalline silicon thin film is 5 × 10⁻⁶. 19 / cm 3 ~10×10 19 / cm 3 The phosphorus doping concentration in the third phosphorus-doped polycrystalline silicon thin film is 1×10⁻⁶. 20 / cm 3 ~5×10 20 / cm 3 .

3. The P-type TOPCon battery according to claim 2, characterized in that, The P-type crystalline silicon is a P-type gallium-doped monocrystalline silicon wafer; the resistivity of the P-type gallium-doped monocrystalline silicon wafer is 0.6 Ω. cm~50 Ω cm; The minority carrier lifetime of the P-type gallium-doped single-crystal silicon wafer is above 300 µs; The tunneling oxide layer is a SiO2 thin film; the thickness of the tunneling oxide layer is 1 nm to 2.5 nm. The front composite passivation layer consists of an AlOx thin film and a SixNy stacked film from the inside out; the thickness of the AlOx thin film is 4.5 nm to 10 nm; the total thickness of the SixNy stacked film is 65 nm to 80 nm, and the refractive index is 2.0 to 2.3; the SixNy stacked film consists of a SixNy thin film, a SiNOx thin film, and a SiOx thin film from the inside out. The front metal electrode is a silver electrode.

4. The P-type TOPCon battery according to any one of claims 1 to 3, characterized in that, The back side of the substrate, from the inside out, includes: a boron-doped polycrystalline silicon layer and a back composite passivation layer; The back side of the substrate also includes a back metal electrode; the back metal electrode penetrates the back composite passivation layer and forms an ohmic contact with the boron-doped polycrystalline silicon layer; The back composite passivation layer consists of an AlOx thin film and a SixNy stacked film from the inside out; the thickness of the AlOx thin film is 4.5 nm to 10 nm; the thickness of the SixNy stacked film is 65 nm to 80 nm, and the refractive index is 2.0 to 2.3; the SixNy stacked film consists of a SixNy thin film, a SiNOx thin film, and a SiOx thin film from the inside out. The back metal electrode is a silver-aluminum electrode.

5. A method for preparing a P-type TOPCon battery, characterized in that, Includes the following steps: S1. Pretreatment of P-type crystalline silicon; S2. With the back side of the P-type crystalline silicon facing upwards, perform boron diffusion on the back side of the P-type crystalline silicon to form a boron-doped polycrystalline silicon layer and a BSG layer on the back side of the P-type crystalline silicon. S3. The front side of the P-type crystalline silicon is cleaned, polished, and texturized in sequence to remove the BSG layer and boron-doped polycrystalline silicon layer on the front side and edges, and to form a textured surface on the front side. S4. A tunneling oxide layer is deposited on the front side of the P-type crystalline silicon, and an intrinsic polycrystalline silicon thin film and a silicon oxide thin film are alternately deposited on the tunneling oxide layer to form a silicon oxide thin film / intrinsic polycrystalline silicon passivation stack; the silicon oxide thin film / intrinsic polycrystalline silicon passivation stack consists of, from the inside to the outside, a first intrinsic polycrystalline silicon thin film, a first silicon oxide thin film, a second intrinsic polycrystalline silicon thin film, a second silicon oxide thin film, and a third intrinsic polycrystalline silicon thin film; S5. Thinning and oxidizing the polysilicon layer in the non-gate area, and growing an oxide layer on the surface of the polysilicon layer; S6. Phosphorus diffusion is performed on the front side of the P-type crystalline silicon. A phosphorus-doped polycrystalline silicon layer and a PSG layer are formed by coating polycrystalline silicon around the front, edge and back sides of the P-type crystalline silicon, and a BPSG layer is formed at the back edge. S7. Laser SE heavy doping is performed on the gate line region on the front side of P-type crystalline silicon to form a phosphorus-doped polycrystalline silicon stack in the gate line region on the front side of P-type crystalline silicon. S8. Remove the PSG and BPSG layers on the back and sides of the P-type crystalline silicon. S9. Remove the phosphorus-doped polysilicon layer on the back and sides of the P-type crystalline silicon, and remove the BSG layer on the back and the PSG layer on the front. S10. With the back side of the P-type crystalline silicon facing down, deposit AlOx thin films on the front and back sides of the P-type crystalline silicon respectively. S11. Deposit SixNy stacked films on the AlOx thin films on the front and back sides of P-type crystalline silicon, respectively, and form a front composite passivation layer and a back composite passivation layer on the front and back sides of P-type crystalline silicon, respectively. S12. Prepare front metal electrodes and back metal electrodes on the front and back sides of P-type crystalline silicon, respectively; S13. Laser-assisted sintering is performed on the back side of the P-type crystalline silicon to form a low-resistance contact in the back metal electrode area.

6. The preparation method according to claim 5, characterized in that, In step S1, the pretreatment includes: alkaline washing of the front and back sides of the P-type crystalline silicon with an alkaline solution, and texturing of the front and back sides of the P-type crystalline silicon with an alkaline solution containing a texturing additive; the alkaline solution is a KOH solution or a NaOH solution; the mass concentration of the alkaline solution is 3% to 5%; the texturing is performed at a temperature of 30℃ to 98℃; the texturing time is 100s to 600s; the P-type crystalline silicon is a P-type gallium-doped single-crystal silicon wafer; the resistivity of the P-type gallium-doped single-crystal silicon wafer is 0.6 Ω. cm~50 Ω cm; The minority carrier lifetime of the P-type gallium-doped single-crystal silicon wafer is above 300 µs; In step S2, the process parameters for boron diffusion are as follows: temperature is 960℃~1050℃, boron source is BCl3, flow rate is 200sccm~500sccm, O2 flow rate is 10000 sccm~30000sccm; the thickness of the BSG layer is 80 nm~130 nm; and the diffusion sheet resistance of the BSG layer is 200Ω / sq~300Ω / sq. In step S3, the front side of the P-type crystalline silicon is cleaned with HF solution, polished with an alkaline solution containing additives, and texturized with an alkaline solution containing texturing additives; the mass concentration of the HF solution is 10%–50%; the alkaline solution is KOH solution or NaOH solution; the mass concentration of the alkaline solution is 3%–5%. In step S4, an LPCVD device is used to deposit a tunneling oxide layer, an intrinsic polycrystalline silicon thin film, and a silicon oxide thin film. The deposition process parameters for the tunneling oxide layer are: O2 as the introduced gas, a gas flow rate of 5000 sccm to 20000 sccm, a deposition time of 120 s to 1800 s, and a deposition temperature of 550℃ to 650℃. The deposition process parameters for the intrinsic polycrystalline silicon thin film are: SiH4 as the introduced gas, a flow rate of 200 sccm to 2000 sccm, a deposition time of 1000 s to 2000 s, and a deposition temperature of 550℃ to 650℃. The deposition process parameters for the silicon oxide thin film are: O2 as the introduced gas, a gas flow rate of 5000 sccm to 20000 sccm, a deposition time of 120 s to 1800 s, and a deposition temperature of 550℃ to 650℃. The tunneling oxide layer is a SiO2 thin film. The thickness of the tunneling oxide layer is 1 mm. The thickness of the silicon oxide film / intrinsic polycrystalline silicon passivation stack is 50 nm to 2.5 nm; the thickness of the first intrinsic polycrystalline silicon film is 10 nm to 30 nm; the thickness of the first silicon oxide film is 0.3 nm to 2 nm; the thickness of the second intrinsic polycrystalline silicon film is 10 nm to 30 nm; the thickness of the second silicon oxide film is 0.3 nm to 2 nm; and the thickness of the third intrinsic polycrystalline silicon film is 30 nm to 120 nm. In step S5, a laser is used to thin and oxidize the polysilicon layer in the non-gateline region; In step S6, the process parameters for phosphorus diffusion are as follows: the phosphorus source is POCl3, the diffusion temperature is 800℃~930℃, and the time is 1000s~2400s; the total thickness of the phosphorus-doped polycrystalline silicon layer is 40 nm~150 nm; and the thickness of the PSG layer is 20 nm~60 nm. In step S8, an HF solution is used in a chain cleaning machine to clean the back and sides of the P-type crystalline silicon, removing the PSG and BPSG layers from the back and sides of the P-type crystalline silicon; the mass concentration of the HF solution is 3% to 40%. In step S9, in a tank cleaning machine, an alkaline solution is used to perform alkaline washing on the back and sides of the P-type crystalline silicon to remove the phosphorus-doped polycrystalline silicon layer on the back and sides of the P-type crystalline silicon; the alkaline solution is a KOH solution or a NaOH solution; the mass concentration of the alkaline solution is 3% to 5%; HF solution is used to perform acid washing on the P-type crystalline silicon to remove the BSG layer on the back and the PSG layer on the front; the mass concentration of the HF solution is 5% to 40%. In step S10, an atomic layer deposition process is used to deposit AlOx thin films on the front and back sides of a P-type crystalline silicon. The deposition process parameters for the AlOx thin film are: trimethylaluminum as the aluminum source, water vapor as the oxygen source, and a process temperature of 250℃~300℃. The thickness of the AlOx thin film is 4.5 nm~10 nm. In step S11, a SixNy multilayer film is deposited on the AlOx thin film on both the front and back sides of the P-type crystalline silicon using a PECVD process. The deposition process parameters for the SixNy multilayer film are as follows: SiH4 flow rate of 500 sccm–3000 sccm, NH3 flow rate of 5000 sccm–18000 sccm, and N2O flow rate of 8000 sccm–15000 sccm; deposition temperature of 380℃–500℃; and the film thickness of the SixNy multilayer film is controlled at 65 nm–80 nm, with a refractive index of 2.0–2.

3. In step S12, silver paste and silver-aluminum paste are printed on the front and back sides of P-type crystalline silicon using screen printing technology. After drying, sintering, and light injection, front metal electrodes and back metal electrodes are prepared on the front and back sides of the P-type crystalline silicon, respectively.

7. The preparation method according to claim 5 or 6, characterized in that, The P-type TOPCon cell includes a positive junction structure. The positive junction structure uses P-type crystalline silicon as a substrate. The front side of the substrate, from the inside out, includes: a tunneling oxide layer, a phosphorus-doped polycrystalline silicon stack, and a front composite passivation layer. The phosphorus-doped polycrystalline silicon stack, from the inside out, consists of a first phosphorus-doped polycrystalline silicon film, a first silicon oxide film, a second phosphorus-doped polycrystalline silicon film, a second silicon oxide film, and a third phosphorus-doped polycrystalline silicon film. The phosphorus doping concentration in the third phosphorus-doped polycrystalline silicon film is greater than that in the first phosphorus-doped polycrystalline silicon film. The thickness of the third phosphorus-doped polycrystalline silicon film is greater than that of the first phosphorus-doped polycrystalline silicon film. The front side of the substrate also includes a front metal electrode; the front metal electrode penetrates the front composite passivation layer and forms an ohmic contact with the third phosphorus-doped polycrystalline silicon thin film; The front metal electrode is a silver electrode.

8. The preparation method according to claim 7, characterized in that, The thickness of the phosphorus-doped polycrystalline silicon stack is 40 nm to 180 nm. The thickness of the first phosphorus-doped polycrystalline silicon film is 10 nm to 30 nm; the thickness of the first silicon oxide film is 0.3 nm to 2 nm; the thickness of the second phosphorus-doped polycrystalline silicon film is 10 nm to 30 nm; the thickness of the second silicon oxide film is 0.3 nm to 2 nm; and the thickness of the third phosphorus-doped polycrystalline silicon film is 30 nm to 120 nm. The phosphorus doping concentration in the first phosphorus-doped polycrystalline silicon thin film is 1×10⁻⁶. 19 / cm 3 ~5×10 19 / cm 3 The phosphorus doping concentration in the second phosphorus-doped polycrystalline silicon thin film is 5 × 10⁻⁶. 19 / cm 3 ~10×10 19 / cm 3 The phosphorus doping concentration in the third phosphorus-doped polycrystalline silicon thin film is 1×10⁻⁶. 20 / cm 3 ~5×10 20 / cm 3 .

9. The preparation method according to claim 8, characterized in that, The back side of the substrate, from the inside out, includes: a boron-doped polycrystalline silicon layer and a back composite passivation layer; The back side of the substrate also includes a back metal electrode; the back metal electrode penetrates the back composite passivation layer and forms an ohmic contact with the boron-doped polycrystalline silicon layer; The back metal electrode is a silver-aluminum electrode.

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