A calibration method of a test chip and a test device

Abstract

The calibration method and the test equipment for the detection chip provided by the embodiments of the present disclosure comprise the following steps: controlling a target detection chip to continuously generate a trigger signal according to a preset rule; and controlling the target detection chip to output a logic test signal until the logic test signal flips between a high level and a low level; determining the value of the trigger signal; calibrating the target detection chip by using a calibration algorithm according to the determined value of the trigger signal; wherein an internal calibration circuit is configured to provide a calibration channel between the detection chip and a sampling element in the internal calibration circuit; and the internal calibration circuit is configured to establish a target calibration channel according to a control instruction. The embodiments of the present disclosure adopt a linear search method to find the value of the trigger signal, and then calibrate the level comparator of the detection chip by using a preset calibration algorithm according to the value of the trigger signal. Thus, the problem that the level comparator cannot be calibrated in the related art is solved. The integration of the ATE equipment is improved, and the dependence on external equipment is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of chip testing, and in particular to a calibration method and testing equipment for testing chips. Background Technology

[0002] In a chip testing system, the test chip is responsible for providing precise voltage and current signals to the device under test. The accuracy of its output DC signal directly determines the test quality, so calibrating the test chip is an essential step.

[0003] However, comparators in existing detection chips typically have their threshold levels designed as internal nodes. This means the actual threshold level of the comparator cannot be directly obtained, nor can it be directly read and quantized by the chip's internal acquisition circuitry, thus posing significant challenges to comparator calibration. Current conventional solutions often rely on external testing equipment for intervention. This not only leads to inefficient calibration processes for detection chips but also significantly increases costs, ultimately impacting mass production testing.

[0004] In summary, existing comparator calibration methods for detection chips suffer from several drawbacks: the threshold level cannot be directly acquired, leading to difficult and inefficient calibration, and the calibration equipment has low integration and relies on external devices. Therefore, a new calibration method is urgently needed to accurately and quickly calibrate the comparator. Summary of the Invention

[0005] This disclosure provides a calibration method and testing equipment for a detection chip, which solves the problems of low comparator calibration efficiency and reliance on external equipment in existing detection chips.

[0006] In view of the above problems, firstly, embodiments of this disclosure provide a calibration method for a detection chip, comprising: The target detection chip is controlled to continuously generate trigger signals according to preset rules; and The target detection chip is controlled to output a logic test signal when triggered by a trigger signal, until the logic test signal flips between high and low levels, and the logic test signal is continuously sampled by a sampling element; Determine the value of the trigger signal that causes the logic test signal to flip; Based on the determined value of the trigger signal, the target detection chip is calibrated using a first preset calibration algorithm; The detection chip and the internal calibration circuit are located in the test circuit. The detection chip is connected to the internal calibration circuit through a corresponding external signal channel. The internal calibration circuit is used to provide a calibration channel between the detection chip and the sampling element in the internal calibration circuit. The internal calibration circuit includes a relay array and switches the conduction state of the relay array according to the control command to establish a target calibration channel between the signal output terminal of the target detection chip and the sampling element.

[0007] In conjunction with the first aspect, in one possible implementation, the target detection chip continuously generates trigger signals according to preset rules; and controls the target detection chip to output logic test signals upon triggering by the trigger signals, until the logic test signals toggle between high and low levels, and continuously samples the logic test signals through sampling elements, including: The target detection chip is controlled to generate a trigger signal, which is then input as an input signal to the level comparator within the target detection chip. The trigger signal is changed in the direction of the threshold level set for the level comparator according to a preset step value until the first sampled value of the logic test signal sampled by the sampling element indicates that the logic test signal has flipped between high and low levels.

[0008] In conjunction with the first aspect, in one possible implementation, calibrating the target detection chip according to the determined value of the trigger signal using a first preset calibration algorithm includes: The value of the trigger signal that flips the logic test signal from high to low is determined as the first toggle value of the level comparator. The value of the trigger signal that flips the logic test signal from low to high is determined as the second flip value of the level comparator. The actual trigger value of the level comparator is determined based on the average of the first and second flip values. Based on the actual trigger value and the first set electrical signal value of the threshold level of the level comparator, a plurality of first calibration points are determined in the first coordinate system; wherein, the horizontal coordinate of the first calibration point is the actual trigger value, and the vertical coordinate of the first calibration point is the first set electrical signal value; The first calibration equation is obtained by fitting the first calibration point; wherein the first calibration equation is a linear equation in two variables with the actual trigger value as the independent variable and the first set electrical signal value as the dependent variable. The threshold level of the target detection chip is calibrated using the first calibration equation.

[0009] In conjunction with the first aspect, in one possible implementation, before controlling the target detection chip to continuously generate trigger signals according to a preset rule, the method further includes: The target detection chip is controlled to output a level test signal to the target calibration channel, and the electrical signal value of the level test signal is sampled by a sampling element. Based on the sampled electrical signal value and the corresponding set electrical signal value, the level output of the target detection chip is calibrated using a second preset calibration algorithm; the set electrical signal value includes a high level set value and a low level set value.

[0010] In conjunction with the first aspect, in one possible implementation, controlling the target detection chip to output a level test signal to the target calibration channel, and sampling the electrical signal value of the level test signal through a sampling element, includes: Different preset electrical signal values ​​are set for the target detection chip; The target detection chip is controlled to output a corresponding level test signal to the target calibration channel according to the different set electrical signal values, and the sampled value of the level test signal output by the sampling element is obtained respectively; The step of calibrating the level output of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a second preset calibration algorithm includes: Based on the second sample value of the level test signal and the second set electrical signal value corresponding to the level test signal, a plurality of second calibration points are determined in the second coordinate system; wherein, the horizontal coordinate of the second calibration point is the second sample value, and the vertical coordinate of the second calibration point is the second set electrical signal value; The second calibration equation is obtained by fitting the second calibration point; wherein the second calibration equation is a linear equation in two variables with the second sampled value as the independent variable and the second set electrical signal value as the dependent variable. The level output of the target detection chip is calibrated using a second calibration equation.

[0011] In conjunction with the first aspect, in one possible implementation, the set electrical signal value further includes a reference level set value; The step of controlling the target detection chip to output a level test signal to the target calibration channel, and sampling the electrical signal value of the level test signal through a sampling element, includes: Different reference level settings are set for the target detection chip; The target detection chip is controlled to output a corresponding reference signal to the target calibration channel according to the different reference level settings, and the sampled value of the reference signal output by the sampling element is obtained respectively; The step of calibrating the level output of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a second preset calibration algorithm includes: Based on the third sample value of the reference signal and the third set electrical signal value corresponding to the reference signal, multiple third calibration points are determined in the third coordinate system; wherein, the horizontal coordinate of the third calibration point is the third sample value, and the vertical coordinate of the third calibration point is the third set electrical signal value; The third calibration equation is obtained by fitting the third calibration point; wherein the third calibration equation is a linear equation in two variables with the third sampled value as the independent variable and the third set electrical signal value as the dependent variable. The reference level output of the target detection chip is calibrated using the third calibration equation.

[0012] In conjunction with the first aspect, in one possible implementation, after calibrating the threshold level of the target detection chip using the first calibration equation, the method further includes: A first verification equation is established based on the first calibration equation, the calibrated level comparator is verified, and the error percentage corresponding to the threshold level is determined based on the verification result. The error percentage is compared with a first threshold. If the error percentage is less than the first threshold, the level comparator is determined to have passed calibration.

[0013] In conjunction with the first aspect, in one possible implementation, after calibrating the level output of the target detection chip using a second preset calibration algorithm based on the sampled electrical signal value and the corresponding set electrical signal value, the method further includes: A second verification equation is established based on the second calibration equation, the calibrated level output is verified, and the error percentage corresponding to the level setting value is determined based on the verification result. The error percentage is compared with a second threshold. If the error percentage is less than the second threshold, the level output calibration is determined to be successful.

[0014] In conjunction with the first aspect, in one possible implementation, the external signal channels are multiple; the test circuit further includes: a signal controller array and a signal channel controller array; The signal controllers in the signal controller array are connected to the signal input terminals of the detection chip; the signal channel controllers in the signal channel controller array are respectively connected to the signal output terminals of the detection chip and the corresponding external signal channels. The method further includes: The target detection chip is determined based on the received control signal, and the target detection chip is controlled by the signal controller; and / or Based on the received control signal, the conduction relationship of the target detection chip corresponding to the external signal channel is controlled.

[0015] In conjunction with the first aspect, in one possible implementation, the internal calibration circuit further includes: at least one resistor with a preset resistance value and a test signal interface provided for connection to an external signal channel. The relays in the relay array are respectively set at the connection nodes between the resistor, the test signal interface and the sampling element, and are used to switch the conduction relationship according to the control command to establish a calibration channel between the test signal interface, the resistor and the sampling element.

[0016] In conjunction with the first aspect, in one possible implementation, the internal calibration circuit includes a preset number of resistors; one end of each resistor is connected to a common connection point and a sampling element, and the other end of the resistor is connected to a ground point; each common connection point is connected to at least one test signal interface; the conduction relationship between each resistor and the test signal interface is switched by a relay array to determine the test signal interface connected to the resistor.

[0017] Secondly, embodiments of this disclosure provide a testing device for performing the calibration method for the detection chip as described in any of the first aspects.

[0018] The beneficial effects of the embodiments disclosed herein include: This disclosure provides a calibration method and testing equipment for a detection chip, comprising: controlling a target detection chip to continuously generate a trigger signal according to a preset rule; controlling the target detection chip to output a logic test signal under the trigger signal until the logic test signal flips between a high level and a low level, and continuously sampling the logic test signal through a sampling element; determining the value of the trigger signal that causes the logic test signal to flip; calibrating the target detection chip according to the determined value of the trigger signal using a first preset calibration algorithm; wherein the detection chip is connected to an internal calibration circuit through a corresponding external signal channel; the internal calibration circuit is used to provide a calibration channel between the detection chip and the sampling element in the internal calibration circuit; the internal calibration circuit includes a relay array, and switches the conduction state of the relay array according to a control command to establish a target calibration channel between the signal output terminal of the target detection chip and the sampling element. This disclosure uses a linear search method to find the level judgment threshold of the level comparator, thereby obtaining the actual trigger value of the level comparator according to the value of the trigger signal, and then calibrating the level comparator of the detection chip according to the value of the trigger signal using a preset calibration algorithm. This solves the problem that related technologies have difficulty in acquiring the level judgment threshold and cannot calibrate the level comparator. Furthermore, by integrating the calibration circuit and the detection chip into the ATE equipment, the integration level of the ATE equipment is improved, and the dependence on external equipment is reduced. Attached Figure Description

[0019] Figure 1A schematic flowchart illustrating the calibration method for the detection chip provided in this embodiment of the disclosure; Figure 2 This is a schematic diagram of the structure of a test circuit provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of the level comparator calibration process provided in an embodiment of the present disclosure; Figure 4 This is a schematic diagram of the internal calibration circuit structure provided in an embodiment of the present disclosure; Figure 5 A schematic diagram of the driver calibration process provided in this embodiment of the disclosure; Figure 6 This is a schematic diagram of the resistor wiring structure provided in an embodiment of this disclosure. Detailed Implementation

[0020] This disclosure provides a calibration method and testing equipment for a detection chip. Preferred embodiments of this disclosure are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of this disclosure. Furthermore, the embodiments and features described herein can be combined with each other unless otherwise specified.

[0021] This disclosure provides a calibration method for a detection chip, such as... Figure 1 As shown, it includes: S101. Control the target detection chip to continuously generate trigger signals according to preset rules; and control the target detection chip to output logic test signals under the trigger of the trigger signals until the logic test signals flip between high level and low level, and continuously sample the logic test signals through the sampling element; S102. Determine the value of the trigger signal that causes the logic test signal to flip; S103. Based on the determined value of the trigger signal, calibrate the target detection chip using a first preset calibration algorithm; The detection chip and the internal calibration circuit are located in the test circuit. The detection chip is connected to the internal calibration circuit through a corresponding external signal channel. The internal calibration circuit is used to provide a calibration channel between the detection chip and the sampling element in the internal calibration circuit. The internal calibration circuit includes a relay array and switches the conduction state of the relay array according to the control command to establish a target calibration channel between the signal output terminal of the target detection chip and the sampling element.

[0022] In this embodiment, the execution entity can be a control terminal in a test circuit. This test circuit can be implemented as a circuit used in Automatic Test Equipment (ATE) for testing chips. The circuit includes a detection chip that outputs an electrical signal to the chip under test (DUT). Based on the DUT's response to the electrical signal, the performance of the DUT is detected, thus achieving the test. In a preferred embodiment, the detection chip can be a PE (Pin Electronics) chip. To calibrate the detection chip in this circuit, the test circuit of this disclosure also integrates an internal calibration circuit and a main control chip for calibrating the detection chip. This allows the ATE equipment to calibrate the detection chip without requiring an additional calibration device.

[0023] The main control chip can be the control terminal in the test circuit. This main control chip can communicate with the lower-level machine, receive control signals from the lower-level machine, and perform calibration calculations based on a pre-set algorithm. It should be noted that the lower-level machine referred to in this disclosure is relative to the upper-level machine used for overall control of the ATE equipment. The lower-level machine in this disclosure can be a computer device capable of controlling the main control chip and other devices, and acquiring the data it collects (e.g., the values ​​of collected logic test signals). As needed, the lower-level machine can also execute corresponding calibration algorithms based on this data. The upper-level machine in this disclosure can communicate with the lower-level machine and can send corresponding control signals to control the main control chip through the lower-level machine.

[0024] Specifically, such as Figure 2 As shown, the main control chip 1 can be connected to the data transfer unit board (DTU) via a signal backplane. Signal connectors are located at both ends of the signal backplane; one connector connects to the main control chip 1, and the other connects to the DTU board. The DTU board can communicate with the lower-level machine via an optical module or other network protocols. It can convert control signals from the lower-level machine and send them to the main control chip 1. The main control chip 1 can parse the control signals into control commands to control the internal calibration circuit 2 and the detection chip 3, and send the data acquired by the main control chip 1 to the lower-level machine.

[0025] The main control chip 1 can be implemented as a programmable system-on-a-chip. Embedded software can be pre-installed within the main control chip 1. Based on the instructions of the control signals, the main control chip 1 can output corresponding signals through extended interfaces such as integrated circuit bus (I2C), serial peripheral interface (SPI), or local bus. Specifically, the main control chip 1 can include a processing system (PS) section and a programmable logic (PL) section.

[0026] In addition, the test circuit can be equipped with multiple detection chips 3. Each detection chip 3 can integrate multiple channels for outputting logic signals. In the actual chip testing process, each channel can correspond to a pin of the chip under test, so as to test the chip under test.

[0027] like Figure 2 The test circuit shown can include 144 detection chips 3, each of which can include two channels (i.e., detection chips 3#0 to 3#287 in the diagram, totaling 288 channels). The number of detection chips 3 in the test circuit can be set according to the actual situation of the target chip under test. If the chip under test has a large number of pins, more detection chips 3 can be set accordingly. This is for illustration only and is not a limitation.

[0028] The sampling element 21 can acquire the electrical signal value in the internal calibration circuit 2 and is connected to the main control chip 1. It can upload the acquired value to the main control chip 1, which then transmits it to the lower-level machine for calibration calculation and data recording. During the calibration process of the detection chip 3, a calibration channel from the target detection chip 3 to the sampling element 21 can be established in the internal calibration circuit 2. Through this calibration channel, the logic test signal output by the detection chip 3 can be transmitted to the corresponding sampling element 21, which then acquires the signal value output by the detection chip 3. Specifically, the sampling element 21 can be implemented as an analog-to-digital converter (ADC).

[0029] The circuit described above can acquire the electrical signals output by the detection chip 3 within the ATE equipment and calibrate the detection chip 3 based on these electrical signals, thereby achieving the goal of integrating the calibration function of the detection chip 3 into the ATE equipment and improving the integration level of the ATE equipment.

[0030] Furthermore, since multiple detection chips 3 can be set in a test circuit, the number of control channels of the main control chip 1 cannot correspond one-to-one with the number of detection chips 3. Therefore, a signal controller array 4 can be set to expand the control channels of the main control chip 1 to control more detection chips 3. Specifically, the signal controller 41 can be implemented as a field-programmable gate array (FPGA). Figure 2 As shown, each FPGA can expand the main control chip 1 with 24 control channels, meaning that one FPGA can control 24 detection chips 3 and 48 channels. In practical applications, the number of FPGAs can be flexibly configured according to the control capabilities of the main control chip 1, the control capabilities of the FPGA, and the number of detection chips 3. This is for illustrative purposes only and is not a limitation.

[0031] The main control chip 1 can send a second control command carrying specific address information or following specific timing information, which allows it to locate and independently drive a specific detection chip 3 to generate logic test signals via the signal controller 41 in the signal controller array 4. This enables the main control chip 1 to control a large number of detection chips 3 even with a limited number of interfaces.

[0032] The signal channel controller array 5 can be located at the signal output terminal of the detection chip 3. By responding to a third control command issued by the main control chip 1, it selectively connects or disconnects the loop between the signal output terminal of the detection chip 3 and the external signal channel, thereby controlling the signal output terminal of the detection chip 3. This ensures that only the logic test signal generated by the target detection chip 3 is transmitted to the designated external signal channel, thus isolating non-target logic test signals from entering the internal calibration circuit 2. This prevents signal interference and guarantees the accuracy of the calibration process.

[0033] Specifically, the signal channel controller 51 can be implemented as an optocoupler relay, and each optocoupler relay can be connected to the signal output terminal of a detection chip 3 to control the conduction relationship between the signal output terminal and the external signal channel. Figure 1 For example, each external signal channel can be connected to 48 optocoupler relays, i.e., 48 channels, which can be aggregated into one external signal channel. During each calibration process, only the optocoupler relay of the target detection chip 3 among the 48 optocoupler relays connected to this external signal channel is turned on. The main control chip 1 can control the on / off state of the signal channel controllers 51 in the signal channel controller matrix through the signal channel controller 51 driver. Specifically, if the signal channel controller 51 is an optocoupler relay, the driver can be implemented as an optocoupler relay driver.

[0034] The number of external signal channels can be determined based on the number of resistors 23 in the internal calibration circuit 2. The number of resistors 23 determines the number of detection chips 3 that can be calibrated simultaneously. Figure 1 For example, the internal calibration circuit 2 may include three resistors 23 with preset resistance values. Each resistor 23 is connected to a sampling element 21 and connected to the channels of 96 detection chips 3 through two test signal interfaces 24. That is, this test circuit can calibrate three channels at the same time. This is for illustration only and is not a limitation.

[0035] This embodiment provides a method for calibrating the comparator of a detection chip, specifically a method for calibrating the comparator's level judgment threshold. and Calibration is performed. During comparator calibration, the high-level comparator and low-level comparator of the detection chip can be calibrated separately by obtaining the level of the trigger signal that causes the logic test signal output by the comparator to toggle between high and low levels and the error of the set threshold level.

[0036] In this process, the main control chip first selects any detection chip in the test circuit as the target detection chip, and then controls the chip to generate a trigger signal internally according to certain preset rules, which is then input into the level comparator of the chip channel of the detection chip. The level comparator compares the value of the trigger signal with the designed threshold level value. Based on the relationship between the two, the level comparator can output different levels, thereby triggering the preset mechanism inside the detection chip, so that the logic test signal output by the detection chip to the external signal channel through the signal output terminal presents a corresponding high or low level. It should be noted that, in this disclosure, a high level refers to a relatively high voltage state, which can represent "1" in the output logic of the detection chip; a low level refers to a relatively low voltage state (e.g., close to 0V or ground), which can represent "0" in the output logic of the detection chip; this logic test signal can be output by the driver function of the detection chip.

[0037] Due to the level judgment threshold of the level comparator and Since the actual value cannot be collected, this method continuously samples the toggling of the logic test signal to obtain the comparator's output. It then uses a linear search to find the level comparator's level judgment threshold, thereby obtaining the actual trigger value of the level comparator based on the trigger signal value. Finally, a preset calibration algorithm is used to calibrate the level comparator of the detection chip based on the trigger signal value. This solves the problem of related technologies struggling to collect the level judgment threshold and thus unable to calibrate the level comparator.

[0038] In another embodiment provided in this disclosure, the step S101 above, "controlling the target detection chip to continuously generate trigger signals according to preset rules; and controlling the target detection chip to output logic test signals under the trigger of the trigger signals until the logic test signals flip between high and low levels, and continuously sampling the logic test signals through sampling elements," can be implemented as follows: S1011 controls the target detection chip to generate a trigger signal, which is then input as an input signal to the level comparator within the target detection chip; S1012 changes the trigger signal in the direction of the threshold level set for the level comparator according to a preset step value, until the first sampled value of the logic test signal sampled by the sampling element indicates that the logic test signal has flipped between high level and low level.

[0039] In this embodiment of the disclosure, the preset rule can be a step-by-step linear search rule, that is, the trigger signal is generated in a step-by-step manner, so that the value of the trigger signal gradually approaches and finds the threshold level judgment threshold, so as to finally obtain the threshold.

[0040] In one possible implementation, the lower-level computer can send a corresponding calibration command as a control signal to the main control chip 1 for each detection chip. The main control chip 1 controls the relay switching of the internal calibration circuit 2 according to the control signal, thereby obtaining a target calibration channel for the target detection chip. This allows the signal output terminal of the target detection chip to be connected to the sampling element through the external signal channel and the target calibration channel.

[0041] Furthermore, a threshold level can be set for the level comparator of the target detection chip. This threshold level can be achieved through the source voltage (FV, Force Voltage) function of the Parametric Measurement Unit (PMU) in the detection chip. Specifically, the PMU provides a preset voltage signal to the reference signal input terminal of the level comparator as a reference signal input, and the level of this reference signal is the threshold level. For both the high-level and low-level comparators, the reference signal input terminal is a non-inverting input terminal, and the input signal is input to the inverting input terminal of the comparator. The trigger signal used as the input signal can also be a signal with a certain voltage value provided by the PMU to the level comparator. The value of the PMU's trigger signal can be adjusted according to the control of the main control chip 1. Each detection chip can include multiple chip channels (e.g., two signal channels), and each chip channel can include two comparators (i.e., the aforementioned high-level comparator and low-level comparator).

[0042] For a high-level comparator, when the input signal from the inverting input is less than the voltage value of the reference signal, the high-level comparator outputs a high level. As the input signal gradually rises and reaches the set threshold level, the output of the high-level comparator flips from high to low. When the input signal from the inverting input is greater than the voltage value of the reference signal, the high-level comparator outputs a low level. As the input signal gradually falls and reaches the set threshold level, the output of the high-level comparator flips from low to high.

[0043] Similarly, for a low-level comparator, when the voltage value of the input signal input from the inverting input terminal rises to the set threshold level, the output of the low-level comparator flips from high to low; when it falls to the set threshold level, it flips from low to high.

[0044] It should be noted that the signals received by the inverting and non-inverting inputs of the high-level and low-level comparators mentioned above can be set according to actual needs, and there are no restrictions here.

[0045] To determine the actual level threshold at which the output of each level comparator flips, the initial value of the trigger signal can be set to a value close to the threshold level. The generated trigger signal value is gradually changed to approach the threshold level until the first sampled value of the logic test signal sampled by the sampling element flips between high and low levels. This indicates that the output level of the level comparator has flipped, and the level output of the driver of the detection chip is flipped through the internal mechanism of the detection chip. The trigger signal value reaches the level threshold, and the current trigger signal value is recorded as the flip value.

[0046] In another embodiment provided in this disclosure, the step S103 above, "calibrating the target detection chip according to the determined value of the trigger signal using a first preset calibration algorithm," can be implemented as follows: S1031. The value of the trigger signal that flips the logic test signal from high level to low level is determined as the first flip value of the level comparator. S1032. The value of the trigger signal that flips the logic test signal from low to high level is determined as the second flip value of the level comparator. S1033. Determine the actual trigger value of the level comparator based on the average of the first and second flip values; S1034. Based on the actual trigger value and the first set electrical signal value of the threshold level of the level comparator, determine a plurality of first calibration points in the first coordinate system; wherein, the horizontal coordinate of the first calibration point is the actual trigger value, and the vertical coordinate of the first calibration point is the first set electrical signal value; S1035. A first calibration equation is obtained by fitting the first calibration point; wherein, the first calibration equation is a linear equation in two variables with the actual trigger value as the independent variable and the first set electrical signal value as the dependent variable. S1036. The threshold level of the target detection chip is calibrated using the first calibration equation.

[0047] In this embodiment of the disclosure, for the high-level comparator, when the sampling element samples the high level output of the corresponding channel of the detection chip and it flips to a low level, the value of the input signal at the inverting input terminal of the high-level comparator is the first flip value of the high-level comparator; when the sampling element samples the low level and it flips to a high level, the value of the input signal at the inverting input terminal of the high-level comparator is the second flip value of the high-level comparator.

[0048] Similarly, for a low-level comparator, when the sampling element samples the high level output of the corresponding channel of the detection chip and it flips to a low level, the value of the input signal at the inverting input terminal of the low-level comparator is the first flip value of the low-level comparator; when the sampling element samples the low level and it flips to a high level, the value of the input signal at the inverting input terminal of the low-level comparator is the second flip value of the low-level comparator.

[0049] The actual trigger value for the level flip position of each level comparator can be obtained by averaging the first and second flip values.

[0050] After acquiring multiple actual trigger values ​​and corresponding first-set electrical signal values ​​for threshold levels, multiple first calibration points can be obtained in a first coordinate system, with the actual trigger values ​​as the x-axis and the first-set electrical signal values ​​as the y-axis. By performing fitting operations on these first calibration points through the control terminal of the test circuit, a linear equation in two variables can be obtained, which is the first calibration equation. Furthermore, the slope and intercept of the linear equation in two variables can be determined as correction coefficients for the first calibration equation. Based on these correction coefficients, the judgment threshold of the comparator threshold level of the detection chip can be calibrated.

[0051] In one possible implementation, the above calibration process can be carried out as follows: Figure 3 The flowchart shown here is for reference only. Figure 3 Taking this as an example, the process of calibrating the comparator described above will be explained.

[0052] by Figure 2 Taking the test circuit shown as an example, if the comparator of the detection chip needs to be calibrated, the lower-level machine can first send a control signal to the main control chip 1, and the main control chip 1 will first initialize the calibration process.

[0053] The main control chip 1 can first traverse all the channels of the detection chips through the signal controller array 4, shutting down the output of these signal channels to prevent any detection chips from still being in the output state and directly outputting upon power-up, which could damage the circuit. After shutting down all signal channels, the comparator calibration process can be initialized. Then, the judgment program can be entered to determine whether the signal channels of the detection chips to be calibrated have been calibrated. If the selected channels have been calibrated, the comparator calibration process can end. If there are any uncalibrated signal channels among the selected signal channels, the subsequent calibration program will be executed.

[0054] Furthermore, the test circuit can be switched to a specific calibration mode depending on the calibration content to be performed. Figure 2 Taking the test circuit in the example, through the formula The on-board calibration mode corresponding to a channel can be obtained based on the signal output terminal number. The channel number of the detection chip is used; within the channel number range of the detection chip, six possible modes, modes 46 to 51, can be calculated. The lower-level computer, through the instructions contained in the control signals, can control the main control chip 1 to enter the corresponding calibration mode and activate the corresponding circuit structure using these six values ​​(46 to 51). These modes can each represent a calibration mode, namely, a calibration mode for calibrating the comparators of different groups of detection chips. The on-board calibration mode here is a pre-set program for calibrating various functions of the detection chip; different programs can be called according to the values ​​of different modes. In this disclosure, the on-board calibration mode is relative to the system calibration mode, which is a mode for calibrating other components in the test circuit besides the detection chip.

[0055] Furthermore, the type of electrical signal that the sampling element corresponding to the target channel of the detection chip to be calibrated needs to measure can be set. For comparator calibration, the value of the logic test signal to be acquired can be set to determine whether it is high or low level. The PMU can also be set to enter the corresponding mode to cooperate with the calibration process.

[0056] After the measurement value is set, the correction coefficients of the comparator for the detection chip that are pre-stored in the storage space of the main control chip 1 can be reset. The reset process is to reset the correction coefficients (i.e. the slope and intercept of the two linear equations) to 1 and 0 respectively.

[0057] After the reset is complete, the output voltage of the target signal output terminal of the target detection chip can be set to 0V via signal controller 41. Then, the signal channel controller of the signal output terminal is turned on via relay driver. After completing the above procedure, the judgment process can be further entered. If all the set threshold voltage points have been tested, the correction coefficient calculation process can be performed. If the tests have not been completed, the threshold level setting procedure is entered.

[0058] Set the FV output value of the detection chip's PMU as the threshold level input comparator, and set another FV as the input signal input comparator. The value of this input signal can be slightly smaller than the threshold level.

[0059] For example, with a threshold level of 2V, the initial input signal can be set to 1.8V. This input signal is then controlled to increase in a preset step value, for example, 10mV. After each increase, the output state of the test chip is detected by a sampling element. For a high-level comparator, the initial state is a high-level output. When it flips to a low-level output, a corresponding mechanism is triggered, causing the logic test signal of the detection chip to flip from high to low. The current input signal value is recorded as the first flip value of the high-level comparator. Similarly, for a low-level comparator, the initial state is a high-level output. When it flips to a low level, a corresponding mechanism is triggered, causing the logic test signal of the detection chip to flip between high and low levels. The current input signal value is recorded as the first flip value of the low-level comparator. Similarly, the initial input signal is set to 2.2V again, and this input signal is controlled to decrease downwards according to a preset step value (e.g., 10mV). For the high-level comparator, when the output of the detection chip flips between high and low levels (i.e., when the low-level output of the high-level comparator flips to a high-level output), the corresponding mechanism is triggered to cause the logic test signal of the detection chip to flip from low to high. The value of the input signal of the high-level comparator is the second flip value of the high-level comparator.

[0060] Similarly, for the low-level comparator, when the output of the detection chip flips between high and low levels (i.e. when the low-level output of the low-level comparator flips to a high-level output), the corresponding mechanism is triggered to cause the logic test signal of the detection chip to flip from low to high. The value of the input signal of the low-level comparator is the second flip value of the low-level comparator.

[0061] The target detection chip is controlled by setting different threshold levels and repeatedly acquiring the toggling values ​​of the high-level comparator and the low-level comparator.

[0062] After sampling the flip values, the output of the detection chip's channel can be restored to 0V, and the optocoupler relay corresponding to the signal output terminal can be turned off. The sampled first and second flip values ​​are used to calculate the actual trigger values, which are then uploaded to the control terminal of the test circuit (e.g., a lower-level machine). The lower-level machine calculates the correction values ​​and sends them to the non-volatile storage space connected to the main control chip 1. The circuit then switches to the next signal output terminal of the target detection chip until the threshold correction values ​​of the high-level comparators and low-level comparators for all signal output terminals of all detection chips in the test circuit are obtained. These values ​​are then matched with each signal output terminal and recorded, completing the calibration of the detection chip comparators.

[0063] Assuming the first and second toggles of the high-level comparator are 2.09V and 1.97V respectively, then an actual trigger value for the high-level comparator can be obtained. Then, by combining the set threshold level value (i.e., the first set electrical signal value), the coordinates of a first calibration point of the high-level comparator (2.03, 2) can be obtained. Similarly, the coordinates of the first calibration points of multiple high-level comparators can be obtained, and then a first calibration equation can be fitted. The comparator can be calibrated according to the slope and intercept (i.e., correction coefficient) of the first calibration equation.

[0064] In another embodiment provided in this disclosure, the step S101 above, "before controlling the target detection chip to continuously generate trigger signals according to preset rules," further includes the following step: Step 1: Control the target detection chip to output a level test signal to the target calibration channel, and sample the electrical signal value of the level test signal through a sampling element; Step 2: Based on the sampled electrical signal value and the corresponding set electrical signal value, calibrate the level output of the target detection chip using the second preset calibration algorithm; the set electrical signal value includes a high level set value and a low level set value.

[0065] In this embodiment of the disclosure, before calibrating the comparator, the driver of the detection chip can also be calibrated, that is, the high level output of the driver needs to be calibrated. low level and reference level Perform calibration.

[0066] During driver calibration, the main control chip 1 can send a set control command to the detection chip to control the target detection chip to output a specific level test signal (e.g., high level, low level, and reference level). The signal channel controller 51 can select the circuit between the signal output terminal of the detection chip and the external signal channel, and transmit the signal through the external signal channel to the target calibration channel corresponding to the logic test signal in the internal calibration circuit 2. The main control chip 1 can sample the value of the logic test signal through the internal calibration circuit 2, and calculate the error of each signal by combining it with the set value of the logic test signal level, thereby determining the correction value of the detection chip in the output function of each logic test signal.

[0067] In another embodiment provided in this disclosure, step 1 above, "controlling the target detection chip to output a level test signal to the target calibration channel, and sampling the electrical signal value of the level test signal through a sampling element," can be implemented as follows: Step 1A1: Set different preset electrical signal values ​​for the target detection chip; Step 1A2: Control the target detection chip to output a corresponding level test signal to the target calibration channel according to the different set electrical signal values, and obtain the sampled value of the level test signal output by the sampling element respectively; Step 2 above, "calibrating the level output of the target detection chip according to the sampled electrical signal value and the corresponding set electrical signal value through the second preset calibration algorithm," can be implemented as follows: Step 2A1: Based on the second sample value of the level test signal and the second set electrical signal value corresponding to the level test signal, determine a plurality of second calibration points in the second coordinate system; wherein, the horizontal coordinate of the second calibration point is the second sample value, and the vertical coordinate of the second calibration point is the second set electrical signal value; Step 2A2: Fit the second calibration equation based on the second calibration point; wherein, the second calibration equation is a linear equation in two variables with the second sampled value as the independent variable and the second set electrical signal value as the dependent variable; Step 2A3: Calibrate the level output of the target detection chip using the second calibration equation.

[0068] In this embodiment, the process is a calibration process for the high-level and low-level output functions of the detection chip. In this process, the lower-level machine can send a corresponding calibration command as a control signal to the main control chip 1 for each detection chip. The main control chip 1 controls the I / O expansion chip in the internal calibration circuit 2 according to the control signal. The I / O expansion chip further controls the relay to switch on and off, obtaining a target calibration channel for that detection chip. Furthermore, the main control chip 1 can control the signal channel controller 51 in the signal channel controller array 5, making the signal output terminal of the detection chip connected to the external signal channel. Furthermore, the signal controller 41 corresponding to the detection chip in the signal controller array 4 controls the output level test signal of the detection chip.

[0069] The specific voltage value of this level test signal is preset for the driver of the detection chip. When the main control chip 1 controls the detection chip to output a high level, the detection chip can output a high-level level test signal with that voltage value through the corresponding signal output terminal. When the main control chip 1 controls the detection chip to output a low level, the detection chip can output a low-level level test signal with that voltage value through the corresponding signal output terminal.

[0070] The level test signal is output to the internal calibration circuit 2, where it is sampled by the sampling element. The sampling element transmits the sampled electrical signal value as the second sampled value of the level test signal to the main control chip 1. The main control chip 1 combines the second preset electrical signal value set for the level test signal with the second sampled value, and uses a preset calibration algorithm to calibrate the high-level and low-level output functions of the detection chip.

[0071] It should be noted that the sampling element in the internal calibration circuit 2 has been calibrated. The second sampled value can be considered as the value of the electrical signal actually output by the signal output terminal of the detection chip. By determining the deviation between this value and the set value, the deviation between the high-level and low-level output capability of the detection chip and the set value can be obtained, and the high-level signal output can be calibrated.

[0072] In one possible implementation, such as Figure 4 As shown, the internal calibration circuit 2 can be equipped with multiple sampling elements and corresponding resistors. During the calibration process, multiple non-interfering target calibration channels can be turned on simultaneously to calibrate multiple detection chips at the same time, thereby improving calibration efficiency.

[0073] After acquiring multiple second sampled values ​​and their corresponding second set electrical signal values, multiple second calibration points can be obtained in a second coordinate system, with the second sampled values ​​as the abscissa and the second set electrical signal values ​​as the ordinate. By fitting these second calibration points using a lower-level computer, a linear equation in two variables can be obtained; this equation is the second calibration equation. Furthermore, the slope and intercept of this linear equation can be determined as correction coefficients for the second calibration equation, thereby calibrating the high-level and low-level output capabilities of the detection chip.

[0074] In another embodiment provided in this disclosure, the set electrical signal value further includes a reference level set value; In step 1 above, "controlling the target detection chip to output a level test signal to the target calibration channel, and sampling the electrical signal value of the level test signal through a sampling element" can be implemented as follows: Step 1B1: Set different reference level settings for the target detection chip; Step 1B2: Control the target detection chip to output corresponding reference signals to the target calibration channel according to the different reference level settings, and obtain the sampled values ​​of the reference signals output by the sampling element respectively; Step 2 above, "calibrating the level output of the target detection chip according to the sampled electrical signal value and the corresponding set electrical signal value through the second preset calibration algorithm," can be implemented as follows: Step 2B1: Based on the third sample value of the reference signal and the third set electrical signal value corresponding to the reference signal, determine multiple third calibration points in the third coordinate system; wherein, the horizontal coordinate of the third calibration point is the third sample value, and the vertical coordinate of the third calibration point is the third set electrical signal value; Step 2B2: Fit the third calibration equation based on the third calibration point; wherein the third calibration equation is a linear equation in two variables with the third sampled value as the independent variable and the third set electrical signal value as the dependent variable. Step 2B3: Calibrate the reference level output of the target detection chip using the third calibration equation.

[0075] In this embodiment, the process is for calibrating the reference signal output function of the detection chip. Similar to the high-level and low-level output calibration process, in this process, the lower-level computer can issue a corresponding calibration command as a control signal to the main control chip 1 for each detection chip. The main control chip 1 switches the on / off state of the control relay to obtain a target calibration channel for the target detection chip. It also controls the corresponding signal channel controller 51 to be turned on, and controls the corresponding signal controller 41 to control the output of the reference signal of the detection chip.

[0076] The specific voltage value of the reference signal is preset for the driver of the detection chip. When the main control chip 1 controls the detection chip to output a reference level, the detection chip can output a reference signal with that voltage value through the corresponding signal output terminal. When the detection chip tests the chip under test, this reference signal can be used as the threshold level input to the chip under test.

[0077] The reference signal is output to the sampling element in the internal calibration circuit 2 for sampling. The sampling element transmits the value of the sampled electrical signal as the third sampled value of the reference signal to the main control chip 1. The main control chip 1 combines the third preset electrical signal value set for the reference signal with the third sampled value, and uses a preset calibration algorithm to calibrate the reference signal output function of the detection chip.

[0078] After acquiring multiple third sample values ​​and their corresponding third set electrical signal values, multiple third calibration points can be obtained in a third coordinate system, with the third sample values ​​as the abscissa and the third set electrical signal values ​​as the ordinate. By performing fitting operations on these third calibration points using a lower-level computer, a linear equation in two variables can be obtained; this equation is the third calibration equation. Furthermore, the slope and intercept of the linear equation in two variables can be determined as correction coefficients for the third calibration equation, thereby calibrating the reference level output capability of the detection chip.

[0079] In one possible implementation, the above calibration process can be carried out as follows: Figure 5 The flowchart shown here is for reference only. Figure 5 Taking this as an example, the process of calibrating the driver in the detection chip will be explained.

[0080] by Figure 2 Taking the test circuit shown as an example, to calibrate the driver of the detection chip, the lower-level machine first sends a control signal to the main control chip 1, which then initializes the calibration process. Next, it enters the judgment program to determine whether the signal channels of the detection chip to be calibrated have been calibrated. If the selected signal channels are calibrated, the driver calibration process can end. If there are uncalibrated output signal channels among the selected signal channels, the subsequent calibration program is executed.

[0081] The main control chip 1 can first traverse all the channels of the detection chips through the signal controller array 4, shutting down the output of these channels to prevent any detection chips from still being in the output state during the previous calibration and directly outputting upon power-up, which could damage the circuit. After shutting down all signal channels, the driver calibration process is initialized.

[0082] Furthermore, the test circuit can be switched to a specific calibration mode depending on the calibration content to be performed. Figure 1Regarding the test circuit, since the external signal channel has 6 signal lines, while the internal calibration circuit 2 only has 3 resistors and 3 sampling elements, only 3 detection chips can be calibrated at the same time. To avoid interference between nearby chips and data lines, [the following can be done]: Figure 1 The 288 channels of the 144 detection chips are divided into 6 groups, namely, numbers 0-47, 48-95, 96-143, 144-191, 192-239, and 240-287, which are groups 1, 2, 3, 4, 5, and 6 respectively. Detection chips in groups 1, 3, and 5 are calibrated simultaneously, as are those in groups 2, 4, and 6. Calibration of groups 1, 3, and 5 can be performed using one calibration mode, while calibration of groups 2, 4, and 6 can be performed using another. This is achieved through the formula... The calibration mode corresponding to a channel can be obtained based on the channel number of the detection chip. This refers to the channel number of the detection chip. Within the channel number range of the detection chip, two possible modes, mode 29 and mode 30, can be calculated. The lower-level computer, in the instructions contained in the control signal, can use these two values ​​(29 and 30) to control the main control chip 1 to enter the corresponding calibration mode. Mode 29 and mode 30 can each represent an internal voltage calibration mode, that is, a calibration mode that uses sampling elements to collect voltage values ​​for calibration.

[0083] The calibration mode here refers to controlling the switching devices (e.g., relays) in the test circuit to establish a target calibration channel between the sampling element and the signal output terminal of the target detection chip, thereby receiving and acquiring the electrical signal value of the output terminal through the sampling element. The different numbered modes are pre-set control logics for the switching devices that establish different calibration channels. These control logics are pre-stored in a storage space connected to the main control chip 1. The main control chip 1 can read the corresponding control logic according to the number and control the switching devices in the test circuit to establish the calibration channel. The mode numbers can be set according to actual conditions and are not limited here.

[0084] Furthermore, the type of electrical signal that the sampling element corresponding to the channel of the detection chip to be calibrated needs to measure can be set. For the calibration of the detection chip driver, it can be set to require the sampling element to measure the voltage value of the logic test signal. In addition, if the measurement voltage (MV) function of the detection chip has been calibrated, this function can also be used to sample the voltage value of the logic test signal.

[0085] After setting the measurement value, the calibration value of the driver for the target channel of the detection chip, which is pre-stored in the storage space of the main control chip 1, can be reset. Specifically, the high-level signal can be reset. low-level signal and reference level The correction coefficients (i.e., the slope and intercept of the two linear equations) are reset to 1 and 0, respectively.

[0086] After the reset is complete, the output voltage of the target channel of the target detection chip can be set to 0V first through the signal controller 41. Then, the optocoupler relay of that channel can be turned on through the relay driver.

[0087] Different high-level voltage values, low-level voltage values, and reference voltage values ​​are set for the drivers of the target channel. The target detection chip is then controlled to output corresponding logic test signals through the target channel, and these signals are sampled by sampling elements until a preset number of sample values ​​have been acquired for each of the high-level voltage value, low-level voltage value, and reference voltage value. For example, 10 voltage points can be set for each of the high-level voltage value, low-level voltage value, and reference voltage value to acquire the corresponding sample values.

[0088] After sampling is complete, the output of the channel can be restored to 0V, and the corresponding optocoupler relay can be turned off. The sampled values ​​are uploaded to the lower-level computer, which calculates the correction coefficient and sends it to the non-volatile storage space connected to the main control chip 1 for storage.

[0089] Then, the circuit can switch to the next channel of the target detection chip until the high and low levels of the selected signal channel in the test circuit are calculated, along with the correction coefficient for the reference level output. After each channel is mapped and recorded, the driver calibration is completed.

[0090] In another embodiment provided in this disclosure, after step S1036 "calibrating the threshold level of the target detection chip using the first calibration equation", the following step is further included: Step 1: Establish a first verification equation based on the first calibration equation, verify the calibrated level comparator, and determine the error percentage corresponding to the threshold level based on the verification result; Step 2: Compare the error percentage with the first threshold. If the error percentage is less than the first threshold, the level comparator calibration is deemed successful.

[0091] In this embodiment of the disclosure, after calibration is completed, the calibration effect needs to be verified to determine whether the calibration result meets the accuracy requirements.

[0092] The first threshold can be set to 100%, and the deviation after calibration can meet the corresponding accuracy requirements. The value of the first threshold can be adjusted according to actual needs to adapt to different calibration accuracy requirements.

[0093] The first verification equation can be a linear equation in two variables constructed based on the slope and intercept of the correction coefficients in the first calibration equation, with the actual trigger value of the level comparator as the independent variable and the calculated trigger value as the dependent variable. Specifically, when verification is required, the main control chip 1 can load the corresponding verification equation, output the verification equation with the actual trigger value as the independent variable, and obtain the corresponding calculated value.

[0094] The calibration effect can be verified based on the first verification equation. Assuming the accuracy specification of the high-level comparator is ±100mV, after applying the correction coefficient to the high-level comparator, setting the threshold level to 2V, and changing the preset step value to 5mV, the calculated trigger value is 1.995V. Therefore, the trigger error of the high-level comparator is... The percentage of error is calculated based on the accuracy index. If the percentage error does not exceed the preset threshold of 100%, then the correction value is verified. Similarly, the calibration effect of the low-level comparator can also be verified.

[0095] In another embodiment provided in this disclosure, step 2, "after calibrating the level output of the target detection chip according to the sampled electrical signal value and the corresponding set electrical signal value using a second preset calibration algorithm," further includes: Step 1: Establish a second verification equation based on the second calibration equation, verify the calibrated level output, and determine the error percentage corresponding to the level setting value based on the verification result; Step 2: Compare the error percentage with the second threshold. If the error percentage is less than the second threshold, the level output calibration is deemed successful.

[0096] In this embodiment of the disclosure, the second threshold can be set to 100%, and the deviation after calibration can meet the corresponding accuracy requirements. The value of the second threshold can be adjusted according to actual needs to adapt to different calibration accuracy requirements.

[0097] The second verification equation can be a linear equation in two variables constructed based on the slope and intercept of the correction coefficients in the second calibration equation, with the actual value of the driver's output level as the independent variable and the calculated output level as the dependent variable. Specifically, when verification is required, the main control chip 1 can load the corresponding verification equation, output the verification equation with the actual value of the output level as the independent variable, and obtain the corresponding calculated value.

[0098] Then, the calibration effect of the level output function is verified based on the second verification equation. Assume that the accuracy index for the high-level signal is... After applying the correction factor to the high-level output of the driver, the high-level signal is set to 2V, controlling the channel output of the detection chip to be high. Assuming the calculated voltage is 1.99909V, the maximum accuracy error can be obtained according to the accuracy specifications. The actual error is The error percentage was then calculated as follows: If the percentage of error does not exceed the preset threshold of 100%, the calibration verification is considered successful. Similarly, the reference level output and the low level output can be verified separately.

[0099] In another embodiment provided in this disclosure, there are multiple external signal channels; the test circuit further includes: a signal controller array and a signal channel controller array; The signal controllers in the signal controller array are connected to the signal input terminals of the detection chip; the signal channel controllers in the signal channel controller array are respectively connected to the signal output terminals of the detection chip and the corresponding external signal channels. The method further includes: The target detection chip is determined based on the received control signal, and the target detection chip is controlled by the signal controller; and / or Based on the received control signal, the conduction relationship of the target detection chip corresponding to the external signal channel is controlled.

[0100] In this embodiment, the main control chip 1 can independently or in conjunction with the generated control signals to adjust the switching states of the signal controller 41 and the signal channel controller 51. When a specific target detection chip needs to be operated, on the one hand, the corresponding signal controller 41 can be used to control the chip to output a logic test signal or a level test signal; on the other hand, the corresponding signal channel controller 51 can be controlled to be in a conducting state to establish an electrical connection between the output terminal of the target detection chip and a designated external signal channel. At this time, the signal channel controller 51 corresponding to a non-target detection chip can remain disconnected to avoid signal crosstalk. Based on the setting of multiple external signal channels, this embodiment can support a multi-channel parallel detection mode, that is, the main control chip 1 can simultaneously control different groups of signal controllers 41 and signal channel controllers 51 to be on, so that multiple target detection chips can occupy different external signal channels to transmit data simultaneously, improving calibration efficiency.

[0101] In another embodiment provided in this disclosure, the internal calibration circuit further includes: at least one resistor 23 with a preset resistance value and a test signal interface 24 provided for connection to an external signal channel; The relays in the relay array 22 are respectively set at the connection nodes between the resistor 23, the test signal interface 24 and the sampling element 21, and are used to switch the conduction relationship according to the control command to establish a calibration channel between the test signal interface, the resistor and the sampling element.

[0102] In this embodiment of the disclosure, each component in the internal calibration circuit 2 can be a pre-calibrated component. By calibrating these components, the accuracy of the calibration of the detection chip 3 can be improved, thereby improving the accuracy of subsequent testing of the chip under test.

[0103] The internal calibration circuit 2 may include multiple resistors 23 with preset resistance values, so as to... Figure 4 For example, Figure 4 The device includes three resistors 23 with the same preset resistance value. These resistors 23 can serve as loads. By applying the logic test signal output by the detection chip 3 to these loads, the electrical signal value of the logic test signal can be further obtained, thereby calibrating the detection chip 3. The number of resistors 23 can be set according to the number of signal output channels of the detection chip 3 to be calibrated, and each resistor 23 can correspond to multiple signal output terminals in the detection chip 3. As an example, it can be seen that... Figure 4 The resistors R1, R6, and R11 are all 2.5MΩ resistors.

[0104] Multiple relays can be installed on the connection lines between each resistor 23, the sampling element, and the test signal interface 24. These relays form a relay array 22, which may also include an input / output (I / O) expansion chip. This expansion chip is connected to the I2C interface of each relay and the main control chip 1. Under the control of the main control chip 1, the expansion chip switches the conduction state of different relays, thereby forming different signal paths as calibration channels for the output signal of the measurement and detection chip 3.

[0105] Test signal interface 24 is the interface for inputting the logic test signal output from the detection chip 3 into the internal calibration circuit 2. Test signal interface 24 can establish a connection with the signal output terminal of the detection chip 3 through the external signal channel of the internal calibration circuit 2. The signal output terminal of the detection chip 3 can be the interface of the channel for the output logic signal of each detection chip 3.

[0106] Depending on the actual situation, each external signal channel can be connected to multiple signal output terminals and connected to a corresponding test signal interface 24. The external signal channel can be implemented as a load board, on which multiple signal lines can be configured. Figure 1Taking the load board as an example, it can include 6 signal lines. Each signal line can be connected to a test signal interface 24 in the internal calibration channel, thereby realizing the purpose of transmitting the logic test signal output by the detection chip 3 to the internal calibration circuit 2.

[0107] In another embodiment provided in this disclosure, the internal calibration circuit includes a preset number of resistors; one end of each resistor is connected to a common connection point of the resistor and a sampling element, and the other end of the resistor is connected to a ground point; each common connection point is connected to at least one test signal interface; the conduction relationship between each resistor and the test signal interface is switched by a relay array to determine the test signal interface connected to the resistor.

[0108] In this embodiment of the present disclosure, since the logic test signal input from the detection chip 3 to the internal calibration circuit 2 requires a resistor 23 load to generate a current to ground in order to be collected by the sampling element during the calibration process of the detection chip 3, multiple resistors 23 with preset resistance values ​​need to be set in the internal calibration circuit 2.

[0109] In one possible implementation, the preset resistance value of resistor 23 can be... .

[0110] Depending on the number of signal output terminals of the detection chip 3, multiple resistors 23 can be set in the internal calibration circuit 2. Each resistor 23 can be responsible for receiving logic test signals output from multiple signal output terminals of the detection chip 3. In practical applications, multiple resistors 23 can be calibrated simultaneously to reduce calibration time and improve calibration efficiency.

[0111] Each set of resistors 23 in the internal calibration circuit 2 can be connected to at least one test signal interface 24. That is, the set of resistors 23 can measure the logic test signal of the signal output terminal of the test chip connected to the test signal interface 24, and then calibrate these channels.

[0112] like Figure 6 As shown, one end of each resistor 23 in each group of resistors 23 is connected to a common connection point and a sampling element, respectively. The common connection point is connected to at least one test signal interface 24. A relay is installed on the connection line between each resistor 23 and the connection point. By controlling the conduction of the relay, the continuity of that connection line can be controlled. Furthermore, a relay is also installed between the common connection point and the test signal interface 24 to control the conduction relationship between the resistor 23 and different test signal interfaces 24.

[0113] This disclosure also provides a testing apparatus for performing the calibration method for the detection chip as described in any of the above embodiments.

[0114] Through the above description of the embodiments, those skilled in the art can clearly understand that the embodiments of this disclosure can be implemented in hardware or by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions of the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, mobile hard drive, etc.) and includes several instructions to cause a computer device (such as a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of this disclosure.

[0115] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes in the drawings are not necessarily essential for implementing this disclosure.

[0116] Those skilled in the art will understand that the modules in the apparatus of the embodiments can be distributed in the apparatus of the embodiments as described in the embodiments, or they can be located in one or more devices different from this embodiment with corresponding changes. The modules of the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0117] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0118] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A calibration method for a detection chip, characterized in that, include: The target detection chip is controlled to continuously generate trigger signals according to preset rules; and The target detection chip is controlled to output a logic test signal when triggered by a trigger signal, until the logic test signal flips between high and low levels, and the logic test signal is continuously sampled by a sampling element; Determine the value of the trigger signal that causes the logic test signal to flip; Based on the determined value of the trigger signal, the target detection chip is calibrated using a first preset calibration algorithm; The detection chip and the internal calibration circuit are disposed in the test circuit. The detection chip is connected to the internal calibration circuit through a corresponding external signal channel. The internal calibration circuit is used to provide a calibration channel between the detection chip and the sampling element in the internal calibration circuit. The internal calibration circuit includes a relay array, and switches the conduction state of the relay array according to control commands to establish a target calibration channel between the signal output terminal of the target detection chip and the sampling element.

2. The method as described in claim 1, characterized in that, The target detection chip is controlled to continuously generate trigger signals according to preset rules; and the target detection chip is controlled to output logic test signals when triggered by the trigger signals, until the logic test signals flip between high and low levels, and the logic test signals are continuously sampled by sampling elements, including: The target detection chip is controlled to generate a trigger signal, which is then input as an input signal to the level comparator within the target detection chip. The trigger signal is changed in the direction of the threshold level set for the level comparator according to a preset step value until the first sampled value of the logic test signal sampled by the sampling element indicates that the logic test signal has flipped between high and low levels.

3. The method as described in claim 1, characterized in that, The step of calibrating the target detection chip according to the determined trigger signal value using a first preset calibration algorithm includes: The value of the trigger signal that flips the logic test signal from high to low is determined as the first toggle value of the level comparator. The value of the trigger signal that flips the logic test signal from low to high is determined as the second flip value of the level comparator. The actual trigger value of the level comparator is determined based on the average of the first and second flip values. Based on the actual trigger value and the first set electrical signal value of the threshold level of the level comparator, a plurality of first calibration points are determined in the first coordinate system; wherein, the horizontal coordinate of the first calibration point is the actual trigger value, and the vertical coordinate of the first calibration point is the first set electrical signal value; The first calibration equation is obtained by fitting the first calibration point; wherein the first calibration equation is a linear equation in two variables with the actual trigger value as the independent variable and the first set electrical signal value as the dependent variable. The threshold level of the target detection chip is calibrated using the first calibration equation.

4. The method as described in claim 1, characterized in that, Before the target detection chip continuously generates trigger signals according to preset rules, the following steps are also included: The target detection chip is controlled to output a level test signal to the target calibration channel, and the electrical signal value of the level test signal is sampled by a sampling element. Based on the sampled electrical signal value and the corresponding set electrical signal value, the level output of the target detection chip is calibrated using a second preset calibration algorithm; the set electrical signal value includes a high level set value and a low level set value.

5. The method as described in claim 4, characterized in that, The step of controlling the target detection chip to output a level test signal to the target calibration channel, and sampling the electrical signal value of the level test signal through a sampling element, includes: Different preset electrical signal values ​​are set for the target detection chip; The target detection chip is controlled to output a corresponding level test signal to the target calibration channel according to the different set electrical signal values, and the sampled value of the level test signal output by the sampling element is obtained respectively; The step of calibrating the level output of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a second preset calibration algorithm includes: Based on the second sample value of the level test signal and the second set electrical signal value corresponding to the level test signal, a plurality of second calibration points are determined in the second coordinate system; wherein, the horizontal coordinate of the second calibration point is the second sample value, and the vertical coordinate of the second calibration point is the second set electrical signal value; The second calibration equation is obtained by fitting the second calibration point; wherein the second calibration equation is a linear equation in two variables with the second sampled value as the independent variable and the second set electrical signal value as the dependent variable. The level output of the target detection chip is calibrated using a second calibration equation.

6. The method as described in claim 4, characterized in that, The set electrical signal value also includes a reference level set value; The step of controlling the target detection chip to output a level test signal to the target calibration channel, and sampling the electrical signal value of the level test signal through a sampling element, includes: Different reference level settings are set for the target detection chip; The target detection chip is controlled to output a corresponding reference signal to the target calibration channel according to the different reference level settings, and the sampled value of the reference signal output by the sampling element is obtained respectively; The step of calibrating the level output of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a second preset calibration algorithm includes: Based on the third sample value of the reference signal and the third set electrical signal value corresponding to the reference signal, multiple third calibration points are determined in the third coordinate system; wherein, the horizontal coordinate of the third calibration point is the third sample value, and the vertical coordinate of the third calibration point is the third set electrical signal value; The third calibration equation is obtained by fitting the third calibration point; wherein the third calibration equation is a linear equation in two variables with the third sampled value as the independent variable and the third set electrical signal value as the dependent variable. The reference level output of the target detection chip is calibrated using the third calibration equation.

7. The method as described in claim 3, characterized in that, After calibrating the threshold level of the target detection chip using the first calibration equation, the method further includes: A first verification equation is established based on the first calibration equation, the calibrated level comparator is verified, and the error percentage corresponding to the threshold level is determined based on the verification result. The error percentage is compared with a first threshold. If the error percentage is less than the first threshold, the level comparator is determined to have passed calibration.

8. The method as described in claim 5, characterized in that, After calibrating the level output of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a second preset calibration algorithm, the process further includes: A second verification equation is established based on the second calibration equation, the calibrated level output is verified, and the error percentage corresponding to the level setting value is determined based on the verification result. The error percentage is compared with a second threshold. If the error percentage is less than the second threshold, the level output calibration is determined to be successful.

9. The method as described in claim 1, characterized in that, The external signal channels are multiple; the test circuit also includes: a signal controller array and a signal channel controller array; The signal controllers in the signal controller array are connected to the signal input terminals of the detection chip; the signal channel controllers in the signal channel controller array are respectively connected to the signal output terminals of the detection chip and the corresponding external signal channels. The method further includes: The target detection chip is determined based on the received control signal, and the target detection chip is controlled by the signal controller; and / or Based on the received control signal, the conduction relationship of the target detection chip corresponding to the external signal channel is controlled.

10. The method as described in claim 1, characterized in that, The internal calibration circuit further includes: at least one resistor with a preset resistance value and a test signal interface provided for connection to an external signal channel. The relays in the relay array are respectively set at the connection nodes between the resistor, the test signal interface and the sampling element, and are used to switch the conduction relationship according to the control command to establish a calibration channel between the test signal interface, the resistor and the sampling element.

11. The method as described in claim 10, characterized in that, The internal calibration circuit includes a preset number of resistors; one end of each resistor is connected to the common connection point of the resistor and the sampling element respectively, and the other end of the resistor is connected to the ground point; each common connection point is connected to at least one test signal interface; the conduction relationship between each resistor and the test signal interface is switched by a relay array to determine the test signal interface connected to the resistor.

12. A testing device, characterized in that, Perform the calibration method for the detection chip as described in any one of claims 1-11.

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