A method for controlling random constraints based on simulation command line parameters or files
By passing random constraint control information through simulation command-line parameters or files, the problem of recompiling the verification environment caused by random constraint modification in SystemVerilog is solved, achieving efficient random constraint iteration and improving verification efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2026-02-11
- Publication Date
- 2026-06-02
AI Technical Summary
In the random verification process of SystemVerilog, changes in random constraints can lead to excessively long recompilation times in the verification environment, affecting the efficiency of verification iterations. In particular, in large-scale chip design, compilation time may exceed one hour or even half a day.
By passing preset-formatted random constraint control information through simulation command-line parameters or files, random constraints can be dynamically adjusted without modifying the verification environment code, thus enabling iterative adjustment of random constraints.
It reduces recompilation time introduced by random constraint modifications, improves verification iteration efficiency, and saves significant time, especially in large verification projects.
Smart Images
Figure CN122132306A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of verification methodology technology of SystemVerilog language, and specifically relates to a method for controlling random constraints based on simulation command line parameters or files, specifically a SystemVerilog method for controlling random constraints based on simulation command line parameters or files without compilation. Background Technology
[0002] In SystemVerilog-based stochastic verification methods, verifiers perform functional coverage testing on the Design Under Test (DUT) by defining constrained stochastic stimuli. As verification iterations progress, the initial constraint model often fails to cover newly discovered boundary scenarios or complex interaction paths, leading to stagnant coverage growth. To improve verification completeness, it is necessary to continuously analyze coverage gaps and stochastic test cases, and dynamically expand or adjust stochastic constraints accordingly to guide the generation of more targeted test stimuli. This process involves iterative modification of constraint logic, priority adjustment, and combinatorial optimization, and is a crucial step in achieving high coverage and efficient verification convergence.
[0003] In SystemVerilog-based stochastic verification, continuously expanding and modifying stochastic constraints is not only a common practice but also a core element in ensuring the adequacy of verification. Common constraint iteration methods include directly modifying the stochastic constraint block in the environment code, extending data classes and modifying or overloading the stochastic constraint block, enabling or disabling the stochastic constraint block through code, and supplementing stochastic constraint content through random calls. All these methods involve modifying the verification environment code, which necessitates recompiling the verification environment to achieve the desired stochastic constraint modification effect during simulation. With the continuous increase in chip design scale, the size of verification simulation environments has also exploded, with a single compilation potentially taking more than an hour or even half a day.
[0004] Therefore, exploring a method to pass in random constraint control information in a preset format through simulation command line parameters or file transfer or invocation has become an urgent problem to be solved in order to improve the efficiency of verification iteration. Summary of the Invention
[0005] The purpose of this invention is to provide a method for controlling random constraints based on simulation command line parameters or files, eliminating the recompilation time of the verification environment caused by the modification of random constraint content, and supporting a more efficient random constraint iteration method while retaining the original random constraint iteration.
[0006] To address the aforementioned technical problems, this invention provides a method for controlling random constraints based on simulation command-line parameters or files, comprising: Step S1: In a verification environment implemented using the SystemVerilog language, declare at least one random variable, at least one preset parameter variable associated with the random variable, and at least one random constraint controlled by the preset parameter variable. Step S2: Independently compile the verification environment containing the content described in Step S1 to generate compilation results; Step S3: Start the simulation based on the compilation result, and pass the random constraint control information in a preset format to the simulation tool through the simulation command line. The control information is used to specify the target value of the preset parameter variable. Step S4: During the simulation execution, the random constraint control information passed in by the simulation command line is automatically parsed; if a target value for a specific preset parameter variable is parsed, the target value is assigned to the corresponding preset parameter variable; if no target value is parsed, the preset parameter variable is kept at the specific default value. Step S5: When verifying the randomization of the environment, the system determines the constraint activation mode based on the current value of the preset parameter variable.
[0007] Preferably, in step S1, the preset parameter variable is set with a specific default value indicating that it is not subject to external constraints; the random constraint controlled by the preset parameter variable is configured as a condition constraint, and when the value of the preset parameter variable is not equal to the specific default value, the condition constraint is activated and exerts a constraint effect on the random variable.
[0008] Preferably, the specific default value is -1; the random constraint based on the preset parameter variable is configured to constrain the corresponding random variable to the value of the preset parameter variable when the preset parameter variable is not equal to -1.
[0009] Preferably, in step S2, the verification environment implemented in SystemVerilog language is compiled and simulated in stages, with the environment compilation completed first.
[0010] Preferably, in step S3, the preset format random constraint control information is directly passed in through a command line parameter in the format "+<preset parameter variable name>=<target value>", or passed in through a command line parameter in the format "-f<file name>" referencing a configuration file containing the content in the format "+<preset parameter variable name>=<target value>"; wherein, the <target value> is a single numerical value, a closed interval, or a set of discrete values.
[0011] Preferably, in step S4, the automatic parsing includes: identifying whether there are constraint parameters identified by a specific prefix in the command line or a specified configuration file; if so, extracting the parameter name and parameter value, and matching the parameter name with the corresponding preset parameter variable in the verification environment, and assigning the parameter value to the preset parameter variable after format conversion.
[0012] Preferably, in step S5, when the preset parameter variable remains at the specific default value, the random constraint controlled by the preset parameter variable becomes invalid because its condition is not met, and the random variable is only controlled by traditional random constraints, and the system operates in traditional random mode. When the preset parameter variable is assigned a non-default target value, the random constraint controlled by the preset parameter variable takes effect because its condition is met. The random variable is controlled by this effective constraint, and its randomization result is dynamically guided to a specific value or range defined by the target value, thereby achieving the purpose of controlling random constraints without compilation through simulation command line parameters or files.
[0013] Preferably, the traditional random constraint defines a basic, broad, or general random value range for the random variable; the random constraint based on preset parameter variable control is used to cover, tighten, or specialize the basic value range when an external command is received, so as to generate targeted test stimuli.
[0014] Preferably, the method is applied in the convergence iteration of digital chip functional verification. By inputting the constraints of test stimuli dynamically through an external command line or fine-tuning the random range, the convergence of functional coverage is accelerated, while avoiding the need to recompile the verification environment due to constraint modifications.
[0015] The present invention also provides a computer-readable storage medium storing SystemVerilog code for implementing a digital chip verification environment. When the SystemVerilog code is compiled and used for simulation, it can implement a method based on simulation command line parameters or file-controlled random constraints as described above.
[0016] Compared with the prior art, the present invention has the following beneficial effects: This invention, in the simulation process of a verification methodology based on SystemVerilog, transmits random constraints related to verification environment stimuli to the simulation tool via simulation command-line parameters or files. This allows modification of the random constraints of the verification environment stimuli without modifying the verification environment source code or recompiling the verification environment. This invention effectively reduces the time spent modifying random constraints and recompiling during the verification convergence process, which is necessary to further constrain the random range to support rapid convergence. The time savings are even more significant in large-scale verification projects. Attached Figure Description
[0017] Figure 1 This is a flowchart of a method for controlling random constraints based on simulation command line parameters or files according to the present invention. Detailed Implementation
[0018] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0019] like Figure 1 As shown, this embodiment of the invention specifically provides a method for controlling random constraints based on simulation command line parameters or files, including: Step S1: In a verification environment implemented using the SystemVerilog language, declare at least one random variable, at least one preset parameter variable associated with the random variable, and at least one random constraint controlled by the preset parameter variable. Step S2: Independently compile the verification environment containing the content described in Step S1 to generate compilation results; Step S3: Start the simulation based on the compilation result, and pass the random constraint control information in a preset format to the simulation tool through the simulation command line. The control information is used to specify the target value of the preset parameter variable. Step S4: During the simulation execution, the random constraint control information passed in by the simulation command line is automatically parsed; if a target value for a specific preset parameter variable is parsed, the target value is assigned to the corresponding preset parameter variable; if no target value is parsed, the preset parameter variable is kept at the specific default value. Step S5: When verifying the randomization of the environment, the system determines the constraint activation mode based on the current value of the preset parameter variable.
[0020] As a further preferred embodiment of the present invention, in step S1, the preset parameter variable is set with a specific default value indicating that it is not subject to external constraints; the random constraint controlled by the preset parameter variable is configured as a condition constraint, and when the value of the preset parameter variable is not equal to the specific default value, the condition constraint is activated and exerts a constraint effect on the random variable.
[0021] As a further preferred embodiment of the present invention, the specific default value is -1; the random constraint based on the preset parameter variable is configured to constrain the corresponding random variable to a value equal to the preset parameter variable when the preset parameter variable is not equal to -1.
[0022] As a further preferred embodiment of the present invention, in step S2, the verification environment implemented in SystemVerilog language is compiled and simulated stepwise, and the environment compilation is completed first.
[0023] As a further preferred embodiment of the present invention, in step S3, the preset format random constraint control information is directly passed in through a command line parameter in the format "+<preset parameter variable name>=<target value>", or passed in through a command line parameter in the format "-f<file name>" referencing a configuration file containing the content in the format "+<preset parameter variable name>=<target value>"; wherein, the <target value> is a single numerical value, a closed interval, or a set of discrete values.
[0024] As a further preferred embodiment of the present invention, in step S4, the automatic parsing includes: identifying whether there are constraint parameters identified by a specific prefix in the command line or a specified configuration file; if so, extracting the parameter name and parameter value, and matching the parameter name with the corresponding preset parameter variable in the verification environment, and assigning the parameter value to the preset parameter variable after format conversion.
[0025] As a further preferred embodiment of the present invention, in step S5, when the preset parameter variable remains at the specific default value, the random constraint controlled by the preset parameter variable fails because its condition is not met, and the random variable is only controlled by the traditional random constraint, and the system operates in the traditional random mode. When the preset parameter variable is assigned a non-default target value, the random constraint controlled by the preset parameter variable takes effect because its condition is met. The random variable is controlled by this effective constraint, and its randomization result is dynamically guided to a specific value or range defined by the target value, thereby achieving the purpose of controlling random constraints without compilation through simulation command line parameters or files.
[0026] As a further preferred embodiment of the present invention, the conventional random constraint defines a basic, broad, or general random value range for the random variable; the random constraint based on preset parameter variable control is used to cover, tighten, or specialize the basic value range when receiving external commands, so as to generate targeted test stimuli.
[0027] As a further preferred embodiment of the present invention, the method is applied in the convergence iteration of digital chip functional verification. By inputting the constraints of dynamically switching test stimuli or fine-tuning the random range through an external command line, the convergence of functional coverage is accelerated, while avoiding recompiling the verification environment due to constraint modifications.
[0028] To further elaborate on the embodiments of the present invention, the following implementation examples are also disclosed, with specific steps as follows: S1: The implementation of random constraints in the verification environment based on the SystemVerilog language includes "random constraints controlled by preset parameter variables".
[0029] Example of a stochastic constraint model: Example of a random variable: Declare a random variable of type integer rand_v, as shown in the code example below: rand intrand_v.
[0030] Example of a preset parameter variable: Corresponding to the random variable rand_v, declare a preset parameter variable rand_v_from_cmd_line of type integer, with a default value of -1. Code example: int rand_v_from_cmd_line = -1.
[0031] Example of implementing traditional random constraints: The code implements a constraint that limits the random variable `rand_v` to a range of 0 to 10. Example code is shown below: cosntraint normal { rand_v inside {[0:10]};} Example of random constraints controlled by preset parameter variables: The code implements the random constraint of the random variable rand_v_from_cmd_line by applying the preset parameter variable rand_v_from_cmd_line, as shown in the following example: constraint controlled_by_cmd_line { (rand_v_from_cmd_line != -1) ->rand_v == rand_v_from_cmd_line; } S2: The verification environment, implemented using SystemVerilog, uses step-by-step compilation and simulation, with the environment compilation completed first.
[0032] S3: Start the verification simulation based on the compilation results of S2 and pass in the random constraints of the preset format through the command line.
[0033] Example of a pre-defined random constraint: Example of constructing random constraint parameters in a preset format passed to the simulation command line: Command-line arguments: +rand_v=5 or +rand_v=[0:5] or +rand_v=[1,3] Example of a simulation command line inputting a pre-formatted random constraint file: Command line argument: -f constraint.cfg Example of the constraint.cfg file content structure: +rand_v=5 or +rand_v=[0:5] or +rand_v=[1,3] S4: When the verification environment simulation is executed, it first automatically parses the random constraint information in the preset format passed through the command line, and converts the constraint information into the preset parameter variables described in S1.
[0034] Example of parsing random constraint information in a preset format passed through the command line: 1) Determine if the +rand_v parameter was passed as an argument or from a file in the command line; 2) If parameters are passed in, parse the parameter values and assign them to rand_v_from_cmd_line; 3) If no parameters are passed in, rand_v_from_cmd_line retains its default value.
[0035] S5: Verify that the environment is randomly constrained by the preset parameter variables described in S1. The random constraints described in S1 based on the preset parameter variables are effective. The preset parameter variables described in S1 are derived from the simulation command line parsing, thus achieving the effect of controlling random constraints through command line parameters or file transfer without compilation.
[0036] Examples of random control effects: 1) Without the +rand_v parameter, rand_v_from_cmd_line retains its default value of -1. Random constraint branches controlled by preset parameter variables are invalid, and only traditional random constraints are valid, which is equivalent to the traditional random implementation method. 2) When the +rand_v parameter is passed in, rand_v_from_cmd_line obtains a valid value. The random constraints controlled by the preset parameter variable are valid, realizing the purpose of controlling the random result of the random variable rand_v through command line parameters or files.
[0037] This invention also provides a computer-readable storage medium storing SystemVerilog code for implementing a digital chip verification environment. When the SystemVerilog code is compiled and used for simulation, it can implement a method based on simulation command line parameters or file-controlled random constraints as described above.
[0038] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for controlling random constraints based on simulation command-line parameters or files, characterized in that, include: Step S1: In a verification environment implemented using the SystemVerilog language, declare at least one random variable, at least one preset parameter variable associated with the random variable, and at least one random constraint controlled by the preset parameter variable. Step S2: Independently compile the verification environment containing the content described in Step S1 to generate compilation results; Step S3: Start the simulation based on the compilation result, and pass the random constraint control information in a preset format to the simulation tool through the simulation command line. The control information is used to specify the target value of the preset parameter variable. Step S4: During the simulation execution, automatically parse the random constraint control information passed in by the simulation command line; If a target value for a specific preset parameter variable is parsed, the target value is assigned to the corresponding preset parameter variable; if no target value is parsed, the preset parameter variable is kept at the specific default value. Step S5: When verifying the randomization of the environment, the system determines the constraint activation mode based on the current value of the preset parameter variable.
2. The method for random constraints based on simulation command-line parameters or file control as described in claim 1, characterized in that, In step S1, the preset parameter variable is set with a specific default value indicating that it is not subject to external constraints; the random constraint controlled by the preset parameter variable is configured as a condition constraint, and when the value of the preset parameter variable is not equal to the specific default value, the condition constraint is activated and exerts a constraint effect on the random variable.
3. The method for controlling random constraints based on simulation command-line parameters or files as described in claim 2, characterized in that, The specific default value is -1; the random constraint based on the preset parameter variable is configured to constrain the corresponding random variable to the value of the preset parameter variable when the preset parameter variable is not equal to -1.
4. The method for controlling random constraints based on simulation command-line parameters or files as described in claim 1, characterized in that, In step S2, the verification environment, implemented in SystemVerilog, is compiled first using step-by-step compilation and simulation.
5. The method for controlling random constraints based on simulation command-line parameters or files as described in claim 1, characterized in that, In step S3, the preset format random constraint control information is directly passed in through a command line parameter in the format "+<preset parameter variable name>=<target value>", or passed in through a command line parameter in the format "-f <file name>" referencing a configuration file containing the content in the format "+<preset parameter variable name>=<target value>"; wherein, the <target value> is a single numerical value, a closed interval, or a set of discrete values.
6. The method for controlling random constraints based on simulation command-line parameters or files as described in claim 1, characterized in that, In step S4, the automatic parsing includes: identifying whether there are constraint parameters identified by a specific prefix in the command line or a specified configuration file; if so, extracting the parameter name and parameter value, matching the parameter name with the corresponding preset parameter variable in the verification environment, and assigning the parameter value to the preset parameter variable after format conversion.
7. The method for random constraints based on simulation command-line parameters or file control as described in claim 1, characterized in that, In step S5, when the preset parameter variable remains at the specific default value, the random constraint controlled by the preset parameter variable becomes invalid because its condition is not met, and the random variable is only controlled by the traditional random constraint, and the system operates in the traditional random mode. When the preset parameter variable is assigned a non-default target value, the random constraint controlled by the preset parameter variable takes effect because its condition is met. The random variable is controlled by this effective constraint, and its randomization result is dynamically guided to a specific value or range defined by the target value, thereby achieving the purpose of controlling random constraints without compilation through simulation command line parameters or files.
8. The method for random constraints based on simulation command-line parameters or file control as described in claim 7, characterized in that, The traditional random constraint defines a basic, broad, or general random value range for the random variable; the random constraint based on preset parameter variable control is used to cover, tighten, or specialize the basic value range when an external command is received, so as to generate targeted test stimuli.
9. The method for controlling random constraints based on simulation command-line parameters or files as described in claim 1, characterized in that, The method is applied in the convergence iteration of digital chip functional verification. By inputting the constraints of test stimuli through an external command line or fine-tuning the random range, the convergence of functional coverage is accelerated, while avoiding the need to recompile the verification environment due to constraint modifications.
10. A computer-readable storage medium storing SystemVerilog code for implementing a digital chip verification environment, characterized in that, When the SystemVerilog code is compiled and used for simulation, it enables a method for controlling random constraints based on simulation command-line parameters or files, as described in any one of claims 1 to 9.