Multi-mode detection single photon avalanche diode front-end circuit

Abstract

The application relates to a single photon avalanche diode front-end circuit for multi-mode detection, which integrates a quenching, delay control and self-resetting module composed of basic MOS tubes, inverters and logic gates. Three control signals are output by a controller to configure modes: in a synchronous gating mode, the related MOS tubes are sequentially controlled to be turned on and turned off in a gating mode; in an asynchronous free-running mode, the related control levels are fixed, and the reset delay is linearly controlled by adjusting the third control signal. The application realizes dual-mode detection by using a single circuit structure, shares the core quenching path, has the advantages of small area, low power consumption and wide adjustable range of dead time, and is suitable for large-scale SPAD array integration.

Description

Technical Field

[0001] This invention relates to the field of lidar, and in particular to a front-end circuit for a multi-mode detection single-photon avalanche diode. Background Technology

[0002] Single-photon avalanche diodes (SPADs) have been widely used in various high-sensitivity optoelectronic detection scenarios, such as LiDAR, Time-of-Flight (ToF) imaging, biofluorescence detection, and event-driven vision, due to their single-photon level detection capability, picosecond-level time resolution, and good compatibility with CMOS technology.

[0003] Depending on the control method, SPADs typically operate in either synchronous gated mode or asynchronous free-running mode. Synchronous gated mode utilizes external timing or pulse signals to generate a narrow-time gating window, ensuring the SPAD is in an avalanche-like state only within the expected return time interval of the laser pulse. This effectively suppresses background noise and improves the signal-to-noise ratio. For example, Chinese patent application CN106338339A discloses a compact detection quenching circuit for array-type single-photon avalanche diodes. It uses two MOSFETs to connect the diode's anode to the positive and negative terminals of the power supply, respectively, achieving control based on the gated timing. However, this mode is not suitable for detecting continuous photon streams or random events with unknown arrival times.

[0004] Asynchronous free-running mode does not require external timing drive and can provide higher detection coverage in applications where photon arrival time is uncertain or continuous event monitoring is required. For example, the relevant paper "SPAD Pixel With Sub-NS Dead-Time for High-Count Rate Applications" discloses a front-end circuit that uses the inverted anode level of the diode to control the connection between the positive terminal of the power supply and the anode of the diode, thereby achieving rapid quenching after photon detection.

[0005] In existing systems, SPAD front-ends typically select a single operating mode to construct the circuitry based on the specific application. For example, in outdoor scenarios with large fluctuations in light intensity in urban environments, the free-running mode may trigger saturation due to excessive background noise; while in applications requiring the detection of random or temporally unstable signals, the time window limitation of the fixed-gated mode is insufficient to meet the detection requirements. Due to the clear applicability boundaries between modes, systems employing a single mode struggle to cope with complex and ever-changing operating environments.

[0006] While some studies have attempted to achieve dual-mode detection through external switching circuits or mode splicing, such as the hybrid quenching circuit and operating method disclosed in Chinese patent CN120274878B for gated quenching and fast active quenching, this requires multiple high-speed comparators, whose circuit structures are very large, undoubtedly increasing the area. In contrast, the solutions provided in Chinese patent application CN106338339A and "SPAD Pixel With Sub-NS Dead-Time for High-Count Rate Applications," which use a single switch to connect to the anode of the diode respectively, can significantly reduce the chip size compared to the solution in Chinese patent CN120274878B.

[0007] However, this method of using a switching switch to select the signal path cannot achieve the reuse of the quenching path, and still suffers from increased area occupation and control complexity, which is not conducive to high-density arraying and system integration. Therefore, a SPAD front-end architecture is needed that can flexibly switch between synchronous gating and asynchronous free operation modes without relying on complex large-sized components, while sharing the quenching path. This would adapt to multimodal detection requirements, improve the detection performance, stability, and intelligence level of the system in complex scenarios, and minimize the area of ​​the detection chip. Summary of the Invention

[0008] The purpose of this invention is to provide a multi-mode detection single-photon avalanche diode front-end circuit to overcome the shortcomings of the prior art.

[0009] The objective of this invention can be achieved through the following technical solutions: A multi-mode detection single-photon avalanche diode front-end circuit includes a first P-channel MOSFET, a first N-channel MOSFET, and a quenching path unit. The source of the first P-channel MOSFET is connected to the positive terminal of the power supply, the drain is connected to the anode of the single-photon avalanche diode, and the gate is connected to the first control signal output terminal of the controller. The source of the first N-channel MOSFET is connected to the negative terminal of the power supply, the drain is connected to the anode of the single-photon avalanche diode, and the gate is connected to the second control signal output terminal of the controller. The quenching path unit includes a first inverter, an OR gate, and a second P-channel MOSFET. The front-end circuit also includes a delay control module and a self-reset module. The input terminal of the first inverter... The anode of the single-photon avalanche diode is connected to the output terminal, which is connected to the first input terminal of the OR gate and the second input terminal of the delay control module. The second input terminal of the OR gate is connected to the second control signal output terminal of the controller, and the output terminal is connected to the gate of the second P-channel MOSFET. The source of the second P-channel MOSFET is connected to the positive terminal of the power supply, and the drain is connected to the anode of the single-photon avalanche diode. The first input terminal of the delay control module is connected to the third control signal output terminal of the controller, and the output terminal is connected to the second input terminal of the self-reset module. The self-reset module is located between the anode of the single-photon avalanche diode and the negative terminal of the power supply, and its first input terminal is connected to the first control signal output terminal of the controller. When operating in synchronous gating mode, the controller maintains a high level at its third control signal output terminal, and after a pre-configured gating duration, controls the first control signal output terminal to first output a low level and then a high level, and then controls the second control signal output terminal to first output a high level and then a low level. When operating in asynchronous free-running mode, the first control signal output terminal of the controller is maintained at a high level, the second control signal output terminal is maintained at a low level, and the third control signal output terminal is maintained at a first set level.

[0010] The first set level corresponds to different delay times.

[0011] The delay control module includes an inverting transistor and a third inverter. The gate of the inverting transistor is connected to the third control signal output terminal of the controller, the drain is connected to the positive input terminal of the power supply of the reverse camera, and the source is connected to the positive terminal of the power supply. The input terminal of the third inverter serves as the second input terminal of the delay control module and is connected to the output terminal of the first inverter. The output terminal serves as the output terminal of the delay control module and is connected to the second input terminal of the self-reset module.

[0012] The mathematical expressions for the delay time and the first set level are: in: t dTo delay time, C L For load capacitance, This is the toggling level of the third inverter. This is the operating current of the delay control module. The carrier mobility of the inverting diode, For the gate oxide capacitance of the inverter transistor, W The width of the channel is the inverted ratio pipe. L The channel length of the inverted ratio tube. The first set level, This is the threshold voltage of the inverting transistor.

[0013] The self-reset module includes an AND gate and a second N-channel MOS transistor. The first input terminal of the AND gate is connected to the first control signal output terminal of the controller as the first input terminal of the self-reset module. The second input terminal is connected to the output terminal of the third inverter as the second input terminal of the self-reset module. The output terminal is connected to the gate of the second N-channel MOS transistor. The drain of the second N-channel MOS transistor is connected to the anode of a single-photon avalanche diode, and the source is connected to the negative terminal of the power supply.

[0014] The third inverter includes a third P-channel MOSFET and a third N-channel MOSFET. The gates of both the third P-channel MOSFET and the third N-channel MOSFET are connected to the output terminal of the first inverter, and their drains are connected to the second input terminal of the self-reset module. The source of the third P-channel MOSFET serves as the positive input terminal of the power supply for the third inverter and is connected to the drain of the inverting transistor. The gate of the third N-channel MOSFET serves as the negative input terminal of the power supply for the third inverter and is connected to the negative power supply terminal.

[0015] The front-end circuit also includes a signal output module, the input of which is connected to the output of the first inverter, and the output is connected to an external signal receiving device.

[0016] The signal output module is a second inverter.

[0017] The first P-channel MOSFET and the second P-channel MOSFET have the same specifications.

[0018] The first N-channel MOSFET and the second N-channel MOSFET have the same specifications.

[0019] Compared with the prior art, the present invention has the following beneficial effects: 1. A single circuit structure composed of basic electronic components is used to realize dual-mode detection of synchronous gating mode and asynchronous free operation, and the quenching path is shared, which further reduces the area occupation, has low power consumption, and a wide dead zone adjustment range. It is suitable for large-scale SPAD arrays and integrated applications of photon counting and three-dimensional imaging detection.

[0020] 2. This allows for flexible and linear control of the dead time or quench reset timing via an adjustable voltage / level signal in asynchronous free-running mode, without requiring changes to the hardware circuitry. This enhances the system's adaptability to different detection scenarios and allows for optimization of detection efficiency and noise performance through software or simple external control.

[0021] 3. Using an inverting transistor to power the third inverter is a simple and area-efficient method for achieving variable delay. By changing the voltage applied to the gate of the inverting transistor, its on-resistance can be linearly adjusted, thereby changing the supply voltage and switching speed of the third inverter, ultimately achieving continuous adjustment of the signal path delay. This solution eliminates the need for complex clock or digital delay circuits, achieving the key delay adjustment function with minimal overhead, aligning with the core objective of this invention: reducing area.

[0022] 4. Precise quantitative relationships are provided, offering a theoretical basis for circuit design, simulation, and performance prediction. This enables engineers to quantitatively design and adjust circuit parameters to achieve specific delay targets. While the document does not detail the specific form of this expression, based on my knowledge, such mathematical relationships typically ensure the predictability and repeatability of timing control, which is beneficial for performance consistency in large-scale production.

[0023] 5. One input of the AND gate receives a signal from the delay control module, and the other input receives the first control signal from the controller. This ensures that the second N-channel MOSFET will only turn on and pull the SPAD anode low to complete the reset when both conditions of "delay end" and "controller reset enabled" are met simultaneously. This provides a reliable and safe reset mechanism, preventing inappropriate reset operations from interfering with the normal avalanche detection or quenching process, and enhancing the stability and reliability of the circuit under various operating conditions.

[0024] 6. The core unit of the delay control module is clearly defined as the most basic CMOS gate circuit. This design not only greatly simplifies the circuit structure and reduces power consumption and area, but also makes delay adjustment entirely dependent on the control of the gate voltage of the inverting transistor. The principle is clear and easy to implement. Connecting the inverting transistor in series with the PMOS transistor power supply path of the third inverter is a clever solution that utilizes the linear region of the MOS transistor for analog voltage regulation to achieve digital path delay, demonstrating the ingenuity of the design.

[0025] 7. A dedicated signal output buffer channel has been added. This module isolates and drives the avalanche detection signal reflecting the arrival of photons before outputting it to an external counting or time-to-digital conversion circuit. This avoids interference from the back-end load to the high-sensitivity avalanche detection node at the front end, improves the integrity and driving capability of the output signal, ensures the time accuracy and stability of the detection system, and makes this front-end circuit easier to integrate with different subsequent processing systems.

[0026] 8. The inverter can further shape and restore the amplitude of the probe signal, providing full-amplitude output from rail to rail, and enhancing the noise margin of the signal. At the same time, as the most basic standard CMOS unit, the inverter has good characteristic consistency and low power consumption, which perfectly matches the core pursuit of this invention to reduce chip area and reduce complexity, and is very conducive to the integration of each pixel in a large-scale SPAD array. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of the present invention; Figure 2 This is a simplified circuit diagram for operation in synchronous gating mode. Figure 3 A simplified circuit diagram for operation in asynchronous free-running mode; Where: V SPAD Cathode voltage, SPAD, single-photon avalanche diode, TG, gating signal, RST, reset signal, VB, delay control signal, M1, first P-channel MOSFET, M2, second P-channel MOSFET, M3, first N-channel MOSFET, M4, second N-channel MOSFET, M5, inverting diode, M6, third P-channel MOSFET, M7, third N-channel MOSFET, OR, AND, V NODE Anode node voltage, INV1, first inverter, INV2, second inverter, TRRIGER, event trigger signal, VDD, positive power supply. Detailed Implementation

[0028] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0029] A multi-mode detection single-photon avalanche diode front-end circuit, such as Figure 1As shown, the circuit includes a first P-channel MOSFET M1, a first N-channel MOSFET M3, and a quenching path unit. The source of the first P-channel MOSFET M1 is connected to the positive power supply VDD, the drain is connected to the anode of the single-photon avalanche diode SPAD, and the gate is connected to the first control signal output terminal of the controller. The source of the first N-channel MOSFET M3 is connected to the negative power supply, the drain is connected to the anode of the single-photon avalanche diode SPAD, and the gate is connected to the second control signal output terminal of the controller. The quenching path unit includes a first inverter INV1, an OR gate, and a second P-channel MOSFET M2. The front-end circuit also includes a delay control module and a self-reset module. The input terminal of the first inverter INV1 is connected to the single-photon avalanche diode SPAD. The anode of the avalanche diode SPAD is connected to the first input of the OR gate and the second input of the delay control module. The second input of the OR gate is connected to the second control signal output of the controller, and the output is connected to the gate of the second P-channel MOSFET M2. The source of the second P-channel MOSFET M2 is connected to the positive power supply VDD, and the drain is connected to the anode of the single-photon avalanche diode SPAD. The first input of the delay control module is connected to the third control signal output of the controller, and the output is connected to the second input of the self-reset module. The self-reset module is located between the anode of the single-photon avalanche diode SPAD and the negative power supply, and its first input is connected to the first control signal output of the controller. When operating in synchronous gating mode, the controller's third control signal output remains high, and after a pre-configured gating duration, it controls the first control signal output to first output a low level and then a high level. Subsequently, it controls the second control signal output to first output a high level and then a low level. When operating in asynchronous free-running mode, the controller's first control signal output terminal remains at a high level, the second control signal output terminal remains at a low level, and the third control signal output terminal remains at the first set level.

[0030] The first set level corresponds to different delay times.

[0031] A single circuit structure composed of basic electronic components enables dual-mode detection, including synchronous gating and asynchronous free operation, and shares a quenching path, further reducing the area footprint, resulting in low power consumption and a wide dead zone adjustment range. It is suitable for large-scale SPAD arrays and integrated applications of photon counting and three-dimensional imaging detection.

[0032] In most embodiments, the delay control module includes an inverter transistor M5 and a third inverter. The gate of the inverter transistor M5 is connected to the third control signal output terminal of the controller, the drain is connected to the positive power input terminal of the reverse camera, and the source is connected to the positive power supply VDD. The input terminal of the third inverter serves as the second input terminal of the delay control module and is connected to the output terminal of the first inverter INV1. The output terminal serves as the output terminal of the delay control module and is connected to the second input terminal of the self-reset module.

[0033] Specifically, the mathematical expressions for the delay time and the first set level are: in: t d To delay time, C L For load capacitance, This is the toggling level of the third inverter. This is the operating current of the delay control module. The carrier mobility of the inverting diode M5, The gate oxide capacitance of the inverting transistor M5, W The channel width is the inverted ratio of pipe M5. L The channel length of the inverted pipe M5 is given. The first set level, This is the threshold voltage of the inverting transistor M5.

[0034] In this embodiment, the self-reset module includes an AND gate and a second N-channel MOSFET M4. The first input terminal of the AND gate serves as the first input terminal of the self-reset module and is connected to the first control signal output terminal of the controller. The second input terminal serves as the second input terminal of the self-reset module and is connected to the output terminal of the third inverter. The output terminal is connected to the gate of the second N-channel MOSFET M4. The drain of the second N-channel MOSFET M4 is connected to the anode of the single-photon avalanche diode SPAD, and the source is connected to the negative terminal of the power supply.

[0035] In this embodiment, the third inverter includes a third P-channel MOSFET M6 and a third N-channel MOSFET M7. The gates of both the third P-channel MOSFET M6 and the third N-channel MOSFET M7 are connected to the output terminal of the first inverter INV1, and their drains are connected to the second input terminal of the self-reset module. The source of the third P-channel MOSFET M6 serves as the positive input terminal of the power supply for the third inverter and is connected to the drain of the inverting transistor M5. The gate of the third N-channel MOSFET M7 serves as the negative input terminal of the power supply for the third inverter and is connected to the negative power supply terminal.

[0036] In this embodiment, the front-end circuit also includes a signal output module. The input terminal of the signal output module is connected to the output terminal of the first inverter INV1, and the output terminal is connected to an external signal receiving device.

[0037] In this embodiment, the signal output module is the second inverter INV2.

[0038] Generally, the first P-channel MOSFET M1 and the second P-channel MOSFET M2 have the same specifications, and the first N-channel MOSFET M3 and the second N-channel MOSFET M4 have the same specifications.

[0039] The control signal output from the first control signal output terminal of the controller is called the gate signal TG, the control signal output from the second control signal output terminal is called the reset signal RST, and the control signal output from the third control signal output terminal is the delay control signal VB. The cathode of the single-electron diode SPAD is connected to the cathode voltage VS. PAD .

[0040] The first P-channel MOSFET M1 is controlled by the gate signal TG. When the gate signal TG is 0V (low level), the first P-channel MOSFET M1 is always on, and the anode node voltage V of the single-photon avalanche diode SPAD is... NODE The gate signal TG is always at a high level of 3.3V, which represents the quenching stage. When the gate signal TG is at a high level of 3.3V, the first P-channel MOSFET M1 is turned off, which means the quenching is over.

[0041] The first N-channel MOSFET M3 is controlled by the reset signal RST. When the reset signal RST is a high level of 3.3V, the first N-channel MOSFET M3 remains on, and the anode node voltage V of the single-photon avalanche diode SPAD is... NODE The voltage level is always 0V low, which represents the reset phase. When the reset signal RST is 0V low, the first N-channel MOSFET M3 is turned off, which means the reset is over.

[0042] The first inverter, INV1, is used for rapid detection of photon events. When the single-photon avalanche diode (SPAD) detects a photon signal, the device undergoes an avalanche. The avalanche current charges the parasitic capacitance at the anode node of the SPAD, and the anode node voltage V... NODE Starting from a low level of 0V, the voltage rises until it reaches the toggling level of the first inverter INV1. Then, the first inverter INV1 quickly toggles, causing the output to change from a high level of 3.3V to a low level of 0V.

[0043] When the device is not avalanche-prone, the output of the OR gate is a high level of 3.3V, and the second P-channel MOSFET M2 remains off. When a photon event is detected and the device avalanche occurs, the output of the OR gate becomes a low level of 0V, the second P-channel MOSFET M2 turns on, and the anode node voltage V of the device increases.NODE Forced clamping to a high level of 3.3V puts the device in a quenched state.

[0044] The input of the AND gate is the gate control signal TG and the output of the delay control module, while the output is the control signal for the second N-channel MOSFET M4. When the second N-channel MOSFET M4 is turned on, the anode node voltage V of the device... NODE Force clamping to low level 0V, in reset state.

[0045] In this embodiment, to prevent a direct path from creating a large current that could damage the circuit, the first P-channel MOSFET M1 and the first N-channel MOSFET M3 cannot be turned on simultaneously. Figure 2 As shown, in synchronous gating mode, the delay control signal VB received by the delay control module is a high level of 3.3V, and the delay control module does not work. In this embodiment, the first P-channel MOSFET M1 is turned on first and then turned off, and the anode node voltage V of the single-photon avalanche diode SPAD is... NODE Clamped at a high level of 3.3V, after the first P-channel MOSFET M1 is turned off, the first N-channel MOSFET M3 also turns on first and then turns off. At this time, the anode node voltage V of the single-photon avalanche diode SPAD is... NODE When the voltage level switches from a high level of 3.3V to a low level of 0V, the voltage across the single-photon avalanche diode (SPAD) reaches the avalanche voltage bias. During this period, the SPAD can receive and respond to photon-triggered avalanche events. When the SPAD detects a photon signal, an avalanche occurs, and the avalanche current charges the parasitic capacitance at the anode node of the SPAD, increasing the anode node voltage V. NODE Starting from a low level of 0V, the output of the first inverter INV1 quickly changes from a high level of 3.3V to a low level of 0V. The OR gate outputs a low level of 0V, turning on the second P-channel MOSFET M2 in the module, and the anode node voltage V... NOD E is forced to clamp to a high level of 3.3V. At this time, the single-photon avalanche diode SPAD is quickly quenched, and the front-end circuit quickly outputs an event trigger signal TRRIGER to the external signal receiving device.

[0046] like Figure 3 As shown, in this embodiment, when the front-end circuit operates in asynchronous free-running mode, the gate signal TG is always a high level of 3.3V, and the reset signal RST is always a low level of 0V. When the single-photon avalanche diode SPAD detects a photon signal, the device undergoes avalanche. The avalanche current charges the parasitic capacitance at the anode node of the single-photon avalanche diode SPAD, and the anode node voltage V... NODEStarting from a low level of 0V, the output of the first inverter INV1 quickly changes from a high level of 3.3V to a low level of 0V. The OR gate outputs a low level of 0V, turning on the second P-channel MOSFET M2, and the anode node voltage V... NODE The diode is forced to a high level of 3.3V, at which point the single-photon avalanche diode (SPAD) is rapidly quenched. Simultaneously, the bias-controlled delay module begins operation. After a controllable dead time, the output of the delay module is a high level of 3.3V, triggering the AND gate output of the self-reset module to also be a high level of 3.3V. This turns on the second N-channel MOSFET M4. At this point, the pull-down second N-channel MOSFET M4 has a strong driving capability, reducing the anode node voltage V of the SPAD. NODE The circuit is clamped to a low level of 0V. The output of the delay control circuit quickly drops from a high level of 3.3V to a low level of 0V. After a short loop delay, the single-photon avalanche diode (SPAD) device resumes its detection function. This process realizes the periodic quenching and reset of the single-photon avalanche diode (SPAD) device, enabling the circuit to continuously perform single-photon detection.

Claims

1. A front-end circuit for a multi-mode detection single-photon avalanche diode, comprising a first P-channel MOSFET, a first N-channel MOSFET, and a quenching path unit, wherein the source of the first P-channel MOSFET is connected to the positive terminal of a power supply, the drain is connected to the anode of the single-photon avalanche diode, and the gate is connected to a first control signal output terminal of a controller; the source of the first N-channel MOSFET is connected to the negative terminal of a power supply, the drain is connected to the anode of the single-photon avalanche diode, and the gate is connected to a second control signal output terminal of the controller, characterized in that... The quenching path unit includes a first inverter, an OR gate, and a second P-channel MOSFET. The front-end circuit also includes a delay control module and a self-reset module. The input terminal of the first inverter is connected to the anode of the single-photon avalanche diode, and the output terminal is connected to the first input terminal of the OR gate and the second input terminal of the delay control module. The second input terminal of the OR gate is connected to the second control signal output terminal of the controller, and the output terminal is connected to the gate of the second P-channel MOSFET. The source of the second P-channel MOSFET is connected to the positive terminal of the power supply, and the drain is connected to the anode of the single-photon avalanche diode. The first input terminal of the delay control module is connected to the third control signal output terminal of the controller, and the output terminal is connected to the second input terminal of the self-reset module. The self-reset module is located between the anode of the single-photon avalanche diode and the negative terminal of the power supply, and its first input terminal is connected to the first control signal output terminal of the controller. When operating in synchronous gating mode, the controller maintains a high level at its third control signal output terminal, and after a pre-configured gating duration, controls the first control signal output terminal to first output a low level and then a high level, and then controls the second control signal output terminal to first output a high level and then a low level. When operating in asynchronous free-running mode, the first control signal output terminal of the controller is maintained at a high level, the second control signal output terminal is maintained at a low level, and the third control signal output terminal is maintained at a first set level.

2. The front-end circuit of a multi-mode detection single-photon avalanche diode according to claim 1, characterized in that, The first set level corresponds to different delay times.

3. The front-end circuit of a multi-mode detection single-photon avalanche diode according to claim 2, characterized in that, The delay control module includes an inverting transistor and a third inverter. The gate of the inverting transistor is connected to the third control signal output terminal of the controller, the drain is connected to the positive input terminal of the power supply of the reverse camera, and the source is connected to the positive terminal of the power supply. The input terminal of the third inverter serves as the second input terminal of the delay control module and is connected to the output terminal of the first inverter. The output terminal serves as the output terminal of the delay control module and is connected to the second input terminal of the self-reset module.

4. The front-end circuit of a multi-mode detection single-photon avalanche diode according to claim 3, characterized in that, The mathematical expressions for the delay time and the first set level are: in: t d To delay time, C L For load capacitance, This is the toggling level of the third inverter. This is the operating current of the delay control module. The carrier mobility of the inverting diode, For the gate oxide capacitance of the inverter transistor, W The width of the channel is the inverted ratio pipe. L The channel length of the inverted ratio tube. The first set level, This is the threshold voltage of the inverting transistor.

5. The front-end circuit of a multi-mode detection single-photon avalanche diode according to claim 3, characterized in that, The self-reset module includes an AND gate and a second N-channel MOS transistor. The first input terminal of the AND gate is connected to the first control signal output terminal of the controller as the first input terminal of the self-reset module. The second input terminal is connected to the output terminal of the third inverter as the second input terminal of the self-reset module. The output terminal is connected to the gate of the second N-channel MOS transistor. The drain of the second N-channel MOS transistor is connected to the anode of a single-photon avalanche diode, and the source is connected to the negative terminal of the power supply.

6. The front-end circuit of a multi-mode detection single-photon avalanche diode according to claim 3, characterized in that, The third inverter includes a third P-channel MOSFET and a third N-channel MOSFET. The gates of both the third P-channel MOSFET and the third N-channel MOSFET are connected to the output terminal of the first inverter, and their drains are connected to the second input terminal of the self-reset module. The source of the third P-channel MOSFET serves as the positive input terminal of the power supply for the third inverter and is connected to the drain of the inverting transistor. The gate of the third N-channel MOSFET serves as the negative input terminal of the power supply for the third inverter and is connected to the negative power supply terminal.

7. The front-end circuit of a multi-mode detection single-photon avalanche diode according to claim 1, characterized in that, The front-end circuit also includes a signal output module, the input of which is connected to the output of the first inverter, and the output is connected to an external signal receiving device.

8. The front-end circuit of a multi-mode detection single-photon avalanche diode according to claim 7, characterized in that, The signal output module is a second inverter.

9. The front-end circuit of a multi-mode detection single-photon avalanche diode according to claim 1, characterized in that, The first P-channel MOSFET and the second P-channel MOSFET have the same specifications.

10. The front-end circuit of a multi-mode detection single-photon avalanche diode according to claim 1, characterized in that, The first N-channel MOSFET and the second N-channel MOSFET have the same specifications.

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