Analog integrated circuit automatic layout method and related device

Abstract

The application discloses an automatic layout method of an analog integrated circuit and related devices, and the method comprises the following steps: obtaining circuit netlist information, device library information and layout canvas size data corresponding to an analog integrated circuit to be laid out; constructing a circuit hierarchical structure model based on the circuit netlist information, and performing sorting processing on the layout sequence of devices and sub-circuits through the circuit connection relationship in the circuit hierarchical structure model to form a corresponding layout sequence; performing layout processing on the current device and sub-circuit to be placed according to the layout sequence to obtain layout state information; generating a placement strategy of the current device and sub-circuit to be placed based on the layout state information and an available layout region set, and placing the current device and sub-circuit to be placed in the selected layout region according to the placement strategy until the top-level circuit layout is completed, so as to complete the automatic layout of the analog integrated circuit to be laid out. In the embodiment of the application, the layout quality and design efficiency are improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design automation technology, and in particular to an automatic placement method and related apparatus for analog integrated circuits. Background Technology

[0002] Automated placement of analog integrated circuits (ICs) has long been a key challenge in the field of electronic design automation (EDA). Unlike the highly automated processes of digital ICs, the performance of analog ICs is intricately coupled with the physical implementation details of the layout, exhibiting complex nonlinear relationships. Analog ICs are extremely sensitive to relative device positions, geometric relationships, symmetry, matching, and parasitic effects. The quality of their placement directly determines the chip's noise performance, phase margin, reliability, area, and power consumption. The core objective of automated placement of analog ICs is to achieve multi-objective optimization, such as maximizing area utilization and minimizing total wiring length, while meeting stringent design rule constraints (DRC), physical constraints, and parasitic effect requirements. However, this field still faces many unresolved technical bottlenecks.

[0003] In the field of digital integrated circuits, automated processes based on standard cell libraries are highly mature. However, this paradigm faces significant challenges in the analog field, where existing analog integrated circuit placement methods primarily rely on manual experience or rule-based automated approaches. Manual placement methods have long design cycles, heavily depend on designer experience, and are ill-suited for complex circuit scales. Traditional automated placement methods based on heuristic rules or mathematical optimization typically require simplified assumptions about the circuit structure, making it difficult to simultaneously consider multiple objectives such as area, interconnect length, symmetry, matching, and design rule constraints. Furthermore, with the widespread use of non-rectangular devices, irregularly shaped devices, and polygonal structures in analog circuits, traditional placement models that abstract devices into simple rectangles can no longer accurately reflect the actual physical structure, easily leading to problems such as device overlap and spacing violations in subsequent layout implementation stages.

[0004] In recent years, while machine learning methods have made breakthroughs in digital macrocell placement, their core ideas are difficult to directly transfer to the analog domain. First, these methods generally rely on a gridded placement space, but the size and spacing requirements of analog devices are often not integer multiples of the grid step size. This can lead to physical overlap or violations of Design Rules (DRC) during forced alignment, severely impacting the accuracy of analog circuits. Second, abstracting devices as rigid rectangular bounding boxes, ignoring the actual non-rectangular contours of the device placement itself, also creates a large number of "dead zones" at the sub-circuit level, severely restricting area utilization. Third, multi-objective optimization is difficult. Analog placement requires balancing multiple conflicting objectives such as line length, area, symmetry, and signal integrity. Traditional analog annealing or analytical methods struggle to find the global optimum in complex constraint spaces. While some dedicated AI algorithms have been explored and achieved some success in addressing the unique characteristics of analog circuits, they have not fundamentally solved the accuracy problems caused by discretization operations and the area waste caused by spatial fragmentation.

[0005] In summary, existing automatic placement schemes for analog integrated circuits suffer from problems such as long design cycles, low area utilization, accuracy loss, device overlap risk, and weak multi-objective optimization capabilities. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides an automatic layout method and related apparatus for analog integrated circuits, which solves the accuracy loss problem of traditional grid-based methods. By using polygon contour perception, it effectively recovers the dead space inside and at the edges of sub-circuits. While meeting the complex physical constraints of analog circuits, it significantly improves the area utilization and layout quality of the layout. It can reduce the dependence of analog integrated circuit layout on human experience, improve layout quality and design efficiency, and is suitable for automatic layout design of complex analog integrated circuits.

[0007] To address the aforementioned technical problems, embodiments of the present invention provide an automatic placement method for analog integrated circuits, the method comprising: Obtain the circuit netlist information, device library information, and layout size data corresponding to the simulated integrated circuit to be laid out; Based on the circuit netlist information, a hierarchical circuit structure model is constructed, and the layout order of devices and sub-circuits is sorted according to the circuit connection relationship in the hierarchical circuit structure model to form the corresponding layout order. The devices and sub-circuits to be placed are laid out according to the layout order to obtain layout status information, which includes available layout area information, geometric size information of the currently placed object, and global layout indicators. Based on the layout status information and the set of available layout areas, a placement strategy is generated for the devices and sub-circuits to be placed. The devices and sub-circuits to be placed are then placed in the selected layout areas according to the placement strategy until the top-level circuit layout is completed, thereby completing the automatic placement of the analog integrated circuit to be placed.

[0008] Optionally, the step of constructing a hierarchical circuit structure model based on the circuit netlist information, and sorting the placement order of devices and sub-circuits according to the circuit connection relationships in the hierarchical circuit structure model to form a corresponding placement order, includes: The device type, device parameters, and connection relationships between devices of the analog integrated circuit to be laid out are analyzed based on the circuit netlist information and the device library information. Based on the analysis results, the analog integrated circuit to be laid out is gradually split into multiple hierarchical structures from low to high to form a circuit hierarchical structure model. The layout order is adjusted based on the area size and connection relationship of the devices or sub-circuits in each layer of the hierarchical circuit structure to form the layout order of each layer in the hierarchical circuit structure.

[0009] Optionally, the step of generating a placement strategy for the devices and sub-circuits to be placed based on the layout state information and the set of available layout areas includes: The layout canvas corresponding to the layout canvas size data is taken as a complete available space rectangular area, and the available space rectangular area is added to the layout area set to form an available layout area set; The layout state information and the set of available layout regions are input into the reinforcement learning decision model, and the placement decision probability distribution of the device and sub-circuit to be placed is output. The placement decision probability is the probability that each candidate blank rectangle in the set of available layout regions is the target placement area corresponding to the device and sub-circuit to be placed. Based on the placement decision probability, the method of selecting the device and sub-circuit to be placed at the moment with the highest probability is used to determine the target blank rectangular area and placement direction of the device and sub-circuit to be placed in the set of available layout areas, thus forming a placement strategy.

[0010] Optionally, the reinforcement learning decision model is run using a policy gradient-based near-end optimization algorithm to adaptively determine the placement position and orientation of devices and sub-circuits under the premise of satisfying design rule constraints; and the reinforcement learning decision model uses the reward feedback information generated by the evaluation results after each placement according to the placement strategy for reinforcement learning.

[0011] Optionally, placing the currently selected device and sub-circuit into the selected layout area according to the placement strategy until the top-level circuit layout is completed includes: According to the placement strategy, the devices and sub-circuits to be placed are placed in the selected layout area to form a layout placement result, and the circuit netlist information is used to determine whether there are still unplaced devices and sub-circuits of the analog integrated circuit to be laid out. If there are unlaid devices and sub-circuits, the available layout area set is divided and updated based on the layout placement result to form an updated available layout area set. Return to the layout process for the currently placed devices and sub-circuits according to the layout order, until the top-level circuit layout is completed.

[0012] Optionally, after segmenting and updating the set of available layout areas based on the layout placement result to form the first updated set of available layout areas, the process further includes: When the object to be placed is a sub-circuit, the geometric contour of the sub-circuit is calculated, and the polygonal blank space within the geometric contour is segmented to obtain the polygonal blank space region within the geometric contour. The polygonal blank space region within the geometric contour is updated to the available layout region set after the first update, forming the available layout region set after the second update.

[0013] Optionally, after placing the device and sub-circuit to be placed in the selected layout area according to the placement strategy, the method further includes: The evaluation results are generated by comprehensively evaluating the area occupied by the devices and sub-circuits to be placed, the compactness of the layout, and the compliance of the distance between devices.

[0014] In addition, embodiments of the present invention also provide an automatic placement apparatus for analog integrated circuits, the apparatus comprising: Acquisition module: used to acquire the circuit netlist information, device library information, and layout size data corresponding to the analog integrated circuit to be laid out; The layout order acquisition module is used to construct a hierarchical circuit structure model based on the circuit netlist information, and sort the layout order of devices and sub-circuits through the circuit connection relationship in the hierarchical circuit structure model to form the corresponding layout order. The layout status module is used to perform layout processing on the devices and sub-circuits to be placed according to the layout order to obtain layout status information, which includes available layout area information, geometric dimension information of the currently placed object, and global layout indicators. Placement strategy module: used to generate placement strategies for the devices and sub-circuits to be placed based on the layout status information and the set of available layout areas, and place the devices and sub-circuits to be placed in the selected layout areas according to the placement strategies until the top-level circuit layout is completed, so as to complete the automatic placement of the analog integrated circuit to be placed.

[0015] In addition, embodiments of the present invention also provide an electronic device, including a processor and a memory, wherein the processor runs a computer program or code stored in the memory to implement the automatic placement method for analog integrated circuits as described in any of the above embodiments.

[0016] In addition, embodiments of the present invention also provide a computer-readable storage medium for storing a computer program or code, which, when executed by a processor, implements the automatic placement method for analog integrated circuits as described above.

[0017] In this embodiment of the invention, a multi-stage layout decision-making approach decomposes the complex analog integrated circuit layout problem, improving the stability and controllability of the layout process. Through continuous layout space management and a dynamic update mechanism for available areas, space utilization is improved, and layout dead zones are reduced. By calculating the geometric contours of sub-circuit modules and releasing polygonal blank spaces, internal fragmented space is effectively reclaimed, enhancing the overall layout compactness. Under the premise of meeting design rule constraints, the degree of manual intervention is reduced, improving the quality and efficiency of automatic layout of analog integrated circuits. This solves the accuracy loss problem of traditional mesh-based methods and effectively reclaims dead zone space inside and at the edges of sub-circuits through polygon contour perception. While meeting the complex physical constraints of analog circuits, it significantly improves the area utilization and layout quality of the layout. It reduces the dependence of analog integrated circuit layout on human experience, improves layout quality and design efficiency, and is suitable for automatic layout design of complex analog integrated circuits. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the automatic placement method for analog integrated circuits in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structural composition of the automatic placement device for analog integrated circuits in an embodiment of the present invention; Figure 3This is a schematic diagram of the structural composition of the electronic device in an embodiment of the present invention; Figure 4 This is a schematic diagram of the hierarchical division and layout sequence of sub-circuits in an embodiment of the present invention; Figure 5 This is a flowchart illustrating the polygon perception blank area recycling strategy in an embodiment of the present invention. Figure 6 This is a schematic diagram showing the comparison of blank areas before and after polygon processing of the sub-circuit in an embodiment of the present invention, as well as the polygon generation strategy. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Example 1, please refer to Figure 1 , Figure 1 This is a flowchart illustrating the automatic placement method for analog integrated circuits in an embodiment of the present invention.

[0022] like Figure 1 As shown, an automatic placement method for analog integrated circuits includes: S101: Obtain the circuit netlist information, device library information, and layout size data corresponding to the analog integrated circuit to be laid out; In the specific implementation of this invention, the first step is to initialize the simulated integrated circuit to be laid out in order to obtain the circuit netlist information, device library information, and layout size data corresponding to the simulated integrated circuit to be laid out. During initialization, the circuit netlist information of the simulated integrated circuit to be laid out is parsed to obtain the corresponding device library information and layout size data. The circuit netlist information is used to describe the electrical connection relationships between various devices and sub-circuits in the simulated integrated circuit to be laid out. The device library is used to provide the geometric dimensions, pin positions, and corresponding layout constraint attributes of various analog devices (such as transistors, resistors, capacitors, etc.). The layout size data is used to limit the physical boundary range during the entire layout process, providing a unified spatial reference for subsequent layout operations in continuous layout space.

[0023] S102: Construct a hierarchical circuit structure model based on the circuit netlist information, and sort the layout order of devices and sub-circuits through the circuit connection relationship in the hierarchical circuit structure model to form a corresponding layout order; In the specific implementation of this invention, the step of constructing a hierarchical circuit structure model based on the circuit netlist information, and sorting the placement order of devices and sub-circuits through the circuit connection relationships in the hierarchical circuit structure model to form a corresponding placement order, includes: parsing the device type, device parameters, and connection relationships between the analog integrated circuit to be placed according to the circuit netlist information and the device library information, and gradually splitting the analog integrated circuit to be placed into multiple hierarchical structures from low to high according to the parsing results to form a hierarchical circuit structure model; and sorting and adjusting the placement order based on the area size and connection relationships of the devices or sub-circuits in each layer of the hierarchical circuit structure to form the placement order of each layer in the hierarchical circuit structure.

[0024] Specifically, such as Figure 4 As shown, after obtaining the circuit netlist information, it is necessary to analyze the device types, device parameters, and connection relationships between the devices of the integrated circuit to be laid out using the circuit netlist information and device library information. Then, based on the analysis results, the integrated circuit to be laid out is gradually divided into multiple hierarchical structures from low to high to form a hierarchical circuit structure model. Finally, the layout order is sorted and adjusted according to the area size and connection relationship of the devices or sub-circuits in each layer of the hierarchical circuit structure to form the layout order of each layer in the hierarchical circuit structure.

[0025] Based on this, according to the connection relationships and functional divisions between devices, the circuit is gradually broken down into multiple hierarchical structures. First, the most basic circuit building units, namely individual transistors, resistors, capacitors, and other basic devices, are identified through the circuit netlist and device library information, and these are taken as the bottom layer structure. Then, according to the connection relationships between these basic devices, several basic devices are combined into functionally related sub-circuits according to the sub-circuit affiliation relationships in the circuit netlist information. Further, multiple sub-circuits are combined into higher-level circuit structures until a complete top-level circuit is formed.

[0026] By using the above method, the analog integrated circuit to be laid out is divided into a multi-layered structure from low to high, so that each layer contains only a limited number of devices or sub-circuits, thereby reducing the complexity of subsequent layout processing.

[0027] The layout sequence corresponds to the hierarchical structure described above, adopting a layout strategy from low to high. First, the basic components at the bottom layer are laid out. After the layout of the components at this level is completed, the entire circuit is regarded as a sub-circuit with a fixed external size and port position. Then, the sub-circuit is used as a whole in the layout process of the next level. The above process is executed layer by layer until the overall layout of the top-level circuit is completed.

[0028] To improve the overall layout quality, within the same level, the order of objects to be laid out will be adjusted according to the size of the device or sub-circuit, the type of device, and the number of connections between it and other devices or sub-circuits, so that devices or sub-circuit modules that have a greater impact on performance are placed first.

[0029] S103: Perform layout processing on the devices and sub-circuits to be placed according to the layout order to obtain layout status information, which includes available layout area information, geometric size information of the currently placed object, and global layout indicators. In the specific implementation of this invention, after obtaining the layout order, the devices and sub-circuits to be placed will be laid out according to the layout order. At each layout stage, the corresponding layout status information needs to be obtained first. The layout status information includes, but is not limited to: the geometric feature parameters of each blank rectangular area in the current available layout area set, the geometric size information of the device or sub-circuit to be laid out, and global index information reflecting the overall layout progress and space utilization. By comprehensively acquiring the above status information, the system can form a complete and accurate description of the current layout environment.

[0030] S104: Based on the layout status information and the set of available layout areas, generate a placement strategy for the devices and sub-circuits to be placed, and place the devices and sub-circuits to be placed in the selected layout area according to the placement strategy until the top-level circuit layout is completed, so as to complete the automatic layout of the analog integrated circuit to be laid out.

[0031] In a specific implementation of this invention, the step of generating a placement strategy for the device and sub-circuit to be placed based on the layout state information and the set of available layout regions includes: taking the layout canvas corresponding to the layout canvas size data as a complete available space rectangular area, and adding the available space rectangular area to the layout region set to form an available layout region set; inputting the layout state information and the set of available layout regions into a reinforcement learning decision model, and outputting the placement decision probability distribution of the device and sub-circuit to be placed, wherein the placement decision probabilities are the probabilities of each candidate blank rectangular area in the set of available layout regions being the target placement area corresponding to the device and sub-circuit to be placed; selecting the method with the highest probability corresponding to the device and sub-circuit to be placed based on the placement decision probabilities, determining the target blank rectangular area and placement direction of the device and sub-circuit to be placed in the set of available layout regions, and forming a placement strategy.

[0032] Furthermore, the reinforcement learning decision model is run using a policy gradient-based proximal optimization algorithm to adaptively determine the placement position and orientation of devices and sub-circuits under the premise of satisfying design rule constraints; and the reinforcement learning decision model uses the reward feedback information generated by the evaluation results after each placement according to the placement strategy for reinforcement learning.

[0033] Furthermore, the step of placing the currently placed devices and sub-circuits in the selected layout area according to the placement strategy until the top-level circuit layout is completed includes: placing the currently placed devices and sub-circuits in the selected layout area according to the placement strategy to form a layout placement result, and determining whether there are still unplaced devices and sub-circuits of the analog integrated circuit to be placed based on the circuit netlist information; if there are unplaced devices and sub-circuits, dividing and updating the set of available layout areas based on the layout placement result to form an updated set of available layout areas; and returning to the step of placing the currently placed devices and sub-circuits according to the layout order until the top-level circuit layout is completed.

[0034] Furthermore, after segmenting and updating the available layout area set based on the layout placement result to form the first updated available layout area set, the process further includes: when the current placement object is a sub-circuit, calculating the geometric contour of the sub-circuit, and segmenting the polygonal blank space within the geometric contour to obtain the polygonal blank space region within the geometric contour; updating the polygonal blank space region within the geometric contour to the first updated available layout area set to form the second updated available layout area set.

[0035] Furthermore, after placing the device and sub-circuit to be placed in the selected layout area according to the placement strategy, the process further includes: performing a comprehensive evaluation based on the area ratio occupied by the device and sub-circuit to be placed, the compactness of the layout, and the compliance of the distance between the devices, to form an evaluation result.

[0036] Specifically, in response to the requirements for device distance accuracy and layout connectivity during the layout of the simulated integrated circuit, a layout environment is constructed in a continuous two-dimensional coordinate space. A complete layout canvas can be obtained through the layout canvas size data, and this layout canvas is regarded as a complete available blank rectangular area, which is added to the canvas set as the initial set of available layout areas in the subsequent layout process.

[0037] The corresponding device and sub-circuit placement decisions are generated and executed in the continuous layout space. The placement decisions mainly involve the selection of the target blank rectangular area and the determination of the placement direction of the device or sub-circuit.

[0038] This is achieved through a reinforcement learning decision model, which employs a policy gradient-based proximal optimization algorithm to adaptively determine the placement position and orientation of devices and sub-circuits while satisfying design rule constraints. Furthermore, the reinforcement learning decision model utilizes the reward feedback information generated from the evaluation results of each placement according to the placement strategy for reinforcement learning.

[0039] In each placement decision process, the current layout state information and the set of available layout areas are input into the reinforcement learning decision model, and a set of placement decision probability distributions are output. The probability distributions correspond to: the probability that each candidate blank rectangular area is selected as the target placement area; the probability of the current device or sub-circuit under different placement directions; based on the probability distributions, the target blank rectangular area and its placement direction of the current device or sub-circuit are determined by the maximum probability selection method, and the corresponding placement operation is performed in the continuous coordinate space.

[0040] After the placement operation is completed, the space management is called to update the set of available blank rectangles, and the layout evaluation module is called to evaluate the current layout result. The evaluation result is used to generate reward feedback information corresponding to the current placement decision.

[0041] After the corresponding components and sub-circuits are placed, the set of currently available layout areas will be updated based on their geometry and placement location; for details, please refer to [link / reference needed]. Figure 5 In this embodiment, a space management method based on the largest rectangle is adopted to segment the blank rectangular area that overlaps with the newly placed object. Specifically, along the boundary of the newly placed object, the original blank rectangle is divided into up to four new candidate blank rectangles. Subsequently, a trimming operation is performed on the newly generated blank rectangles. If a rectangle is completely contained by other rectangles, it is removed from the set of available layout areas. Through the above segmentation and trimming process, it is ensured that only the largest blank rectangle is retained in the set of available layout areas, thereby avoiding space waste caused by grid alignment or rounding errors, and ensuring that the device spacing meets the design rule requirements.

[0042] For systems consisting of multiple devices or sub-circuits, after completing the overall layout, a polygon-aware empty space reclamation operation is further performed. Please refer to [link to relevant documentation]. Figure 6 The device obtains the geometric coordinate information of each placed device in the sub-circuit, and calculates the polygonal outline of the closely surrounding device geometry using the geometric coordinate information, in order to more accurately describe the actual occupied area of ​​the sub-circuit.

[0043] Subsequently, the geometric difference region between the polygonal outline and the outer rectangular border of the sub-circuit is calculated to identify the blank space located inside the rectangular bounding box but not actually occupied by the sub-circuit. Then, for this difference region, it is further divided into several rectangular blank regions that conform to the definition of the largest rectangle, and added to the set of available layout regions as the set of available layout regions for subsequent layout processes. Then, the layout processing steps for the devices and sub-circuits to be placed are repeated according to the layout order until all devices and sub-circuits are laid out. At this point, the layout of the top-level circuit is completed, that is, the automatic layout of the analog integrated circuit to be laid out is completed.

[0044] After each layout stage is completed, the placement result and layout status information need to be updated, and the current layout result is comprehensively evaluated. The evaluation result is used to generate reward feedback information corresponding to the current placement decision. The reward feedback information comprehensively reflects the impact of this placement operation on space utilization efficiency, layout compactness, and the satisfaction of design rule constraints. The reward feedback information, together with the corresponding layout status information and placement decision information, constitute an interaction sample of the reinforcement learning algorithm and is stored as experience for subsequent policy updates.

[0045] In this embodiment of the invention, a multi-stage layout decision-making approach decomposes the complex analog integrated circuit layout problem, improving the stability and controllability of the layout process. Through continuous layout space management and a dynamic update mechanism for available areas, space utilization is improved, and layout dead zones are reduced. By calculating the geometric contours of sub-circuit modules and releasing polygonal blank spaces, internal fragmented space is effectively reclaimed, enhancing the overall layout compactness. Under the premise of meeting design rule constraints, the degree of manual intervention is reduced, improving the quality and efficiency of automatic layout of analog integrated circuits. This solves the accuracy loss problem of traditional mesh-based methods and effectively reclaims dead zone space inside and at the edges of sub-circuits through polygon contour perception. While meeting the complex physical constraints of analog circuits, it significantly improves the area utilization and layout quality of the layout. It reduces the dependence of analog integrated circuit layout on human experience, improves layout quality and design efficiency, and is suitable for automatic layout design of complex analog integrated circuits.

[0046] Example 2, please refer to Figure 2 , Figure 2 This is a schematic diagram of the structural composition of the automatic placement device for analog integrated circuits in an embodiment of the present invention.

[0047] like Figure 2 As shown, an automatic placement device for analog integrated circuits includes: Acquisition module 201: used to acquire the circuit netlist information, device library information and layout size data corresponding to the analog integrated circuit to be laid out; In the specific implementation of this invention, the first step is to initialize the simulated integrated circuit to be laid out in order to obtain the circuit netlist information, device library information, and layout size data corresponding to the simulated integrated circuit to be laid out. During initialization, the circuit netlist information of the simulated integrated circuit to be laid out is parsed to obtain the corresponding device library information and layout size data. The circuit netlist information is used to describe the electrical connection relationships between various devices and sub-circuits in the simulated integrated circuit to be laid out. The device library is used to provide the geometric dimensions, pin positions, and corresponding layout constraint attributes of various analog devices (such as transistors, resistors, capacitors, etc.). The layout size data is used to limit the physical boundary range during the entire layout process, providing a unified spatial reference for subsequent layout operations in continuous layout space.

[0048] The layout order acquisition module 202 is used to construct a circuit hierarchical structure model based on the circuit netlist information, and sort the layout order of devices and sub-circuits through the circuit connection relationship in the circuit hierarchical structure model to form a corresponding layout order. In the specific implementation of this invention, the step of constructing a hierarchical circuit structure model based on the circuit netlist information, and sorting the placement order of devices and sub-circuits through the circuit connection relationships in the hierarchical circuit structure model to form a corresponding placement order, includes: parsing the device type, device parameters, and connection relationships between the analog integrated circuit to be placed according to the circuit netlist information and the device library information, and gradually splitting the analog integrated circuit to be placed into multiple hierarchical structures from low to high according to the parsing results to form a hierarchical circuit structure model; and sorting and adjusting the placement order based on the area size and connection relationships of the devices or sub-circuits in each layer of the hierarchical circuit structure to form the placement order of each layer in the hierarchical circuit structure.

[0049] Specifically, such as Figure 4 As shown, after obtaining the circuit netlist information, it is necessary to analyze the device types, device parameters, and connection relationships between the devices of the integrated circuit to be laid out using the circuit netlist information and device library information. Then, based on the analysis results, the integrated circuit to be laid out is gradually divided into multiple hierarchical structures from low to high to form a hierarchical circuit structure model. Finally, the layout order is sorted and adjusted according to the area size and connection relationship of the devices or sub-circuits in each layer of the hierarchical circuit structure to form the layout order of each layer in the hierarchical circuit structure.

[0050] Based on this, according to the connection relationships and functional divisions between devices, the circuit is gradually broken down into multiple hierarchical structures. First, the most basic circuit building units, namely individual transistors, resistors, capacitors, and other basic devices, are identified through the circuit netlist and device library information, and these are taken as the bottom layer structure. Then, according to the connection relationships between these basic devices, several basic devices are combined into functionally related sub-circuits according to the sub-circuit affiliation relationships in the circuit netlist information. Further, multiple sub-circuits are combined into higher-level circuit structures until a complete top-level circuit is formed.

[0051] By using the above method, the analog integrated circuit to be laid out is divided into a multi-layered structure from low to high, so that each layer contains only a limited number of devices or sub-circuits, thereby reducing the complexity of subsequent layout processing.

[0052] The layout sequence corresponds to the hierarchical structure described above, adopting a layout strategy from low to high. First, the basic components at the bottom layer are laid out. After the layout of the components at this level is completed, the entire circuit is regarded as a sub-circuit with a fixed external size and port position. Then, the sub-circuit is used as a whole in the layout process of the next level. The above process is executed layer by layer until the overall layout of the top-level circuit is completed.

[0053] To improve the overall layout quality, within the same level, the order of objects to be laid out will be adjusted according to the size of the device or sub-circuit, the type of device, and the number of connections between it and other devices or sub-circuits, so that devices or sub-circuit modules that have a greater impact on performance are placed first.

[0054] The layout status module 203 is used to perform layout processing on the devices and sub-circuits to be placed according to the layout order to obtain layout status information, which includes available layout area information, geometric size information of the currently placed object, and global layout indicators. In the specific implementation of this invention, after obtaining the layout order, the devices and sub-circuits to be placed will be laid out according to the layout order. At each layout stage, the corresponding layout status information needs to be obtained first. The layout status information includes, but is not limited to: the geometric feature parameters of each blank rectangular area in the current available layout area set, the geometric size information of the device or sub-circuit to be laid out, and global index information reflecting the overall layout progress and space utilization. By comprehensively acquiring the above status information, the system can form a complete and accurate description of the current layout environment.

[0055] Placement strategy module 204: is used to generate a placement strategy for the device and sub-circuit to be placed based on the layout status information and the set of available layout areas, and place the device and sub-circuit to be placed in the selected layout area according to the placement strategy until the top-level circuit layout is completed, so as to complete the automatic placement of the analog integrated circuit to be placed.

[0056] In a specific implementation of this invention, the step of generating a placement strategy for the device and sub-circuit to be placed based on the layout state information and the set of available layout regions includes: taking the layout canvas corresponding to the layout canvas size data as a complete available space rectangular area, and adding the available space rectangular area to the layout region set to form an available layout region set; inputting the layout state information and the set of available layout regions into a reinforcement learning decision model, and outputting the placement decision probability distribution of the device and sub-circuit to be placed, wherein the placement decision probabilities are the probabilities of each candidate blank rectangular area in the set of available layout regions being the target placement area corresponding to the device and sub-circuit to be placed; selecting the method with the highest probability corresponding to the device and sub-circuit to be placed based on the placement decision probabilities, determining the target blank rectangular area and placement direction of the device and sub-circuit to be placed in the set of available layout regions, and forming a placement strategy.

[0057] Furthermore, the reinforcement learning decision model is run using a policy gradient-based proximal optimization algorithm to adaptively determine the placement position and orientation of devices and sub-circuits under the premise of satisfying design rule constraints; and the reinforcement learning decision model uses the reward feedback information generated by the evaluation results after each placement according to the placement strategy for reinforcement learning.

[0058] Furthermore, the step of placing the currently placed devices and sub-circuits in the selected layout area according to the placement strategy until the top-level circuit layout is completed includes: placing the currently placed devices and sub-circuits in the selected layout area according to the placement strategy to form a layout placement result, and determining whether there are still unplaced devices and sub-circuits of the analog integrated circuit to be placed based on the circuit netlist information; if there are unplaced devices and sub-circuits, dividing and updating the set of available layout areas based on the layout placement result to form an updated set of available layout areas; and returning to the step of placing the currently placed devices and sub-circuits according to the layout order until the top-level circuit layout is completed.

[0059] Furthermore, after segmenting and updating the available layout area set based on the layout placement result to form the first updated available layout area set, the process further includes: when the current placement object is a sub-circuit, calculating the geometric contour of the sub-circuit, and segmenting the polygonal blank space within the geometric contour to obtain the polygonal blank space region within the geometric contour; updating the polygonal blank space region within the geometric contour to the first updated available layout area set to form the second updated available layout area set.

[0060] Furthermore, after placing the device and sub-circuit to be placed in the selected layout area according to the placement strategy, the process further includes: performing a comprehensive evaluation based on the area ratio occupied by the device and sub-circuit to be placed, the compactness of the layout, and the compliance of the distance between the devices, to form an evaluation result.

[0061] Specifically, in response to the requirements for device distance accuracy and layout connectivity during the layout of the simulated integrated circuit, a layout environment is constructed in a continuous two-dimensional coordinate space. A complete layout canvas can be obtained through the layout canvas size data, and this layout canvas is regarded as a complete available blank rectangular area, which is added to the canvas set as the initial set of available layout areas in the subsequent layout process.

[0062] The corresponding device and sub-circuit placement decisions are generated and executed in the continuous layout space. The placement decisions mainly involve the selection of the target blank rectangular area and the determination of the placement direction of the device or sub-circuit.

[0063] This is achieved through a reinforcement learning decision model, which employs a policy gradient-based proximal optimization algorithm to adaptively determine the placement position and orientation of devices and sub-circuits while satisfying design rule constraints. Furthermore, the reinforcement learning decision model utilizes the reward feedback information generated from the evaluation results of each placement according to the placement strategy for reinforcement learning.

[0064] In each placement decision process, the current layout state information and the set of available layout areas are input into the reinforcement learning decision model, and a set of placement decision probability distributions are output. The probability distributions correspond to: the probability that each candidate blank rectangular area is selected as the target placement area; the probability of the current device or sub-circuit under different placement directions; based on the probability distributions, the target blank rectangular area and its placement direction of the current device or sub-circuit are determined by the maximum probability selection method, and the corresponding placement operation is performed in the continuous coordinate space.

[0065] After the placement operation is completed, the space management is called to update the set of available blank rectangles, and the layout evaluation module is called to evaluate the current layout result. The evaluation result is used to generate reward feedback information corresponding to the current placement decision.

[0066] After the corresponding components and sub-circuits are placed, the set of currently available layout areas will be updated based on their geometry and placement location; for details, please refer to [link / reference needed]. Figure 5 In this embodiment, a space management method based on the largest rectangle is adopted to segment the blank rectangular area that overlaps with the newly placed object. Specifically, along the boundary of the newly placed object, the original blank rectangle is divided into up to four new candidate blank rectangles. Subsequently, a trimming operation is performed on the newly generated blank rectangles. If a rectangle is completely contained by other rectangles, it is removed from the set of available layout areas. Through the above segmentation and trimming process, it is ensured that only the largest blank rectangle is retained in the set of available layout areas, thereby avoiding space waste caused by grid alignment or rounding errors, and ensuring that the device spacing meets the design rule requirements.

[0067] For systems consisting of multiple devices or sub-circuits, after completing the overall layout, a polygon-aware empty space reclamation operation is further performed. Please refer to [link to relevant documentation]. Figure 6 The device obtains the geometric coordinate information of each placed device in the sub-circuit, and calculates the polygonal outline of the closely surrounding device geometry using the geometric coordinate information, in order to more accurately describe the actual occupied area of ​​the sub-circuit.

[0068] Subsequently, the geometric difference region between the polygonal outline and the outer rectangular border of the sub-circuit is calculated to identify the blank space located inside the rectangular bounding box but not actually occupied by the sub-circuit. Then, for this difference region, it is further divided into several rectangular blank regions that conform to the definition of the largest rectangle, and added to the set of available layout regions as the set of available layout regions for subsequent layout processes. Then, the layout processing steps for the devices and sub-circuits to be placed are repeated according to the layout order until all devices and sub-circuits are laid out. At this point, the layout of the top-level circuit is completed, that is, the automatic layout of the analog integrated circuit to be laid out is completed.

[0069] After each layout stage is completed, the placement result and layout status information need to be updated, and the current layout result is comprehensively evaluated. The evaluation result is used to generate reward feedback information corresponding to the current placement decision. The reward feedback information comprehensively reflects the impact of this placement operation on space utilization efficiency, layout compactness, and the satisfaction of design rule constraints. The reward feedback information, together with the corresponding layout status information and placement decision information, constitute an interaction sample of the reinforcement learning algorithm and is stored as experience for subsequent policy updates.

[0070] In this embodiment of the invention, a multi-stage layout decision-making approach decomposes the complex analog integrated circuit layout problem, improving the stability and controllability of the layout process. Through continuous layout space management and a dynamic update mechanism for available areas, space utilization is improved, and layout dead zones are reduced. By calculating the geometric contours of sub-circuit modules and releasing polygonal blank spaces, internal fragmented space is effectively reclaimed, enhancing the overall layout compactness. Under the premise of meeting design rule constraints, the degree of manual intervention is reduced, improving the quality and efficiency of automatic layout of analog integrated circuits. This solves the accuracy loss problem of traditional mesh-based methods and effectively reclaims dead zone space inside and at the edges of sub-circuits through polygon contour perception. While meeting the complex physical constraints of analog circuits, it significantly improves the area utilization and layout quality of the layout. It reduces the dependence of analog integrated circuit layout on human experience, improves layout quality and design efficiency, and is suitable for automatic layout design of complex analog integrated circuits.

[0071] This invention provides a computer-readable storage medium storing a computer program. When executed by a processor, this program implements the analog integrated circuit automatic placement method of any of the above embodiments. The computer-readable storage medium includes, but is not limited to, any type of disk (including floppy disk, hard disk, optical disk, CD-ROM, and magneto-optical disk), ROM (Read-Only Memory), RAM (Random Access Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, magnetic cards, or optical cards. In other words, the storage device includes any medium that stores or transmits information in a readable form by a device (e.g., a computer, a mobile phone), and can be a read-only memory, a disk, or an optical disk, etc.

[0072] This invention also provides a computer application running on a computer, which is used to execute the analog integrated circuit automatic placement method of any of the above embodiments.

[0073] also, Figure 3 This is a schematic diagram of the structural composition of the electronic device in an embodiment of the present invention.

[0074] This invention also provides an electronic device, such as... Figure 3As shown. The electronic device includes a processor 302, a memory 303, an input unit 304, and a display unit 305, among other devices. Those skilled in the art will understand that... Figure 3 The structural components of the illustrated electronic device do not constitute a limitation on all devices and may include more or fewer components than illustrated, or combine certain components. Memory 303 can be used to store application program 301 and various functional modules. Processor 302 runs application program 301 stored in memory 303, thereby performing various functional applications and data processing of the device. Memory can be internal memory or external memory, or both. Internal memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or random access memory. External memory may include hard disks, floppy disks, ZIP disks, USB flash drives, magnetic tapes, etc. The memory disclosed in this invention includes, but is not limited to, these types of memory. The memory disclosed in this invention is only an example and not a limitation.

[0075] Input unit 304 is used to receive signal input and user-input keywords. Input unit 304 may include a touch panel and other input devices. The touch panel can collect user touch operations on or near it (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touch panel) and drive the corresponding connection device according to a pre-set program; other input devices may include, but are not limited to, one or more of physical keyboards, function keys (such as play control buttons, power buttons, etc.), trackballs, mice, joysticks, etc. Display unit 305 can be used to display user-input information or information provided to the user, as well as various menus of the terminal device. Display unit 305 may be in the form of a liquid crystal display, organic light-emitting diode, etc. Processor 302 is the control center of the terminal device, connecting various parts of the entire device through various interfaces and lines, and performing various functions and processing data by running or executing software programs and / or modules stored in memory 303, and calling data stored in memory.

[0076] As one embodiment, the electronic device includes: one or more processors 302, a memory 303, and one or more application programs 301, wherein the one or more application programs 301 are stored in the memory 303 and configured to be executed by the one or more processors 302, and the one or more application programs 301 are configured to perform the corresponding analog integrated circuit automatic placement method in any of the above embodiments.

[0077] In this embodiment of the invention, a multi-stage layout decision-making approach decomposes the complex analog integrated circuit layout problem, improving the stability and controllability of the layout process. Through continuous layout space management and a dynamic update mechanism for available areas, space utilization is improved, and layout dead zones are reduced. By calculating the geometric contours of sub-circuit modules and releasing polygonal blank spaces, internal fragmented space is effectively reclaimed, enhancing the overall layout compactness. Under the premise of meeting design rule constraints, the degree of manual intervention is reduced, improving the quality and efficiency of automatic layout of analog integrated circuits. This solves the accuracy loss problem of traditional mesh-based methods and effectively reclaims dead zone space inside and at the edges of sub-circuits through polygon contour perception. While meeting the complex physical constraints of analog circuits, it significantly improves the area utilization and layout quality of the layout. It reduces the dependence of analog integrated circuit layout on human experience, improves layout quality and design efficiency, and is suitable for automatic layout design of complex analog integrated circuits.

[0078] Furthermore, the above provides a detailed description of an automatic placement method and related apparatus for analog integrated circuits provided by the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An automatic placement method for analog integrated circuits, characterized in that, The method includes: Obtain the circuit netlist information, device library information, and layout size data corresponding to the simulated integrated circuit to be laid out; Based on the circuit netlist information, a hierarchical circuit structure model is constructed, and the layout order of devices and sub-circuits is sorted according to the circuit connection relationship in the hierarchical circuit structure model to form the corresponding layout order. The devices and sub-circuits to be placed are laid out according to the layout order to obtain layout status information, which includes available layout area information, geometric size information of the currently placed object, and global layout indicators. Based on the layout status information and the set of available layout areas, a placement strategy is generated for the devices and sub-circuits to be placed. The devices and sub-circuits to be placed are then placed in the selected layout areas according to the placement strategy until the top-level circuit layout is completed, thereby completing the automatic placement of the analog integrated circuit to be placed.

2. The automatic placement method for analog integrated circuits according to claim 1, characterized in that, The process of constructing a hierarchical circuit structure model based on the circuit netlist information, and sorting the placement order of devices and sub-circuits according to the circuit connection relationships in the hierarchical circuit structure model to form a corresponding placement order, includes: The device type, device parameters, and connection relationships between devices of the analog integrated circuit to be laid out are analyzed based on the circuit netlist information and the device library information. Based on the analysis results, the analog integrated circuit to be laid out is gradually split into multiple hierarchical structures from low to high to form a circuit hierarchical structure model. The layout order is adjusted based on the area size and connection relationship of the devices or sub-circuits in each layer of the hierarchical circuit structure to form the layout order of each layer in the hierarchical circuit structure.

3. The automatic placement method for analog integrated circuits according to claim 1, characterized in that, The step of generating a placement strategy for the current devices and sub-circuits based on the layout state information and the set of available layout areas includes: The layout canvas corresponding to the layout canvas size data is taken as a complete available space rectangular area, and the available space rectangular area is added to the layout area set to form an available layout area set; The layout state information and the set of available layout regions are input into the reinforcement learning decision model, and the placement decision probability distribution of the device and sub-circuit to be placed is output. The placement decision probability is the probability that each candidate blank rectangle in the set of available layout regions is the target placement area corresponding to the device and sub-circuit to be placed. Based on the placement decision probability, the method of selecting the device and sub-circuit to be placed at the moment with the highest probability is used to determine the target blank rectangular area and placement direction of the device and sub-circuit to be placed in the set of available layout areas, thus forming a placement strategy.

4. The automatic placement method for analog integrated circuits according to claim 3, characterized in that, The reinforcement learning decision model is run using a policy gradient-based near-end optimization algorithm, which adaptively determines the placement position and orientation of devices and sub-circuits while satisfying design rule constraints. Furthermore, the reinforcement learning decision model utilizes the reward feedback information generated from the evaluation results of each placement according to the placement strategy to perform reinforcement learning.

5. The automatic placement method for analog integrated circuits according to claim 1, characterized in that, The step of placing the currently selected device and sub-circuit into the selected layout area according to the placement strategy until the top-level circuit layout is completed includes: According to the placement strategy, the devices and sub-circuits to be placed are placed in the selected layout area to form a layout placement result, and the circuit netlist information is used to determine whether there are still unplaced devices and sub-circuits of the analog integrated circuit to be laid out. If there are unlaid devices and sub-circuits, the available layout area set is divided and updated based on the layout placement result to form an updated available layout area set. Return to the layout process for the currently placed devices and sub-circuits according to the layout order, until the top-level circuit layout is completed.

6. The automatic placement method for analog integrated circuits according to claim 5, characterized in that, After dividing and updating the set of available layout areas based on the layout placement result to form the first updated set of available layout areas, the process further includes: When the object to be placed is a sub-circuit, the geometric contour of the sub-circuit is calculated, and the polygonal blank space within the geometric contour is segmented to obtain the polygonal blank space region within the geometric contour. The polygonal blank space region within the geometric contour is updated to the available layout region set after the first update, forming the available layout region set after the second update.

7. The automatic placement method for analog integrated circuits according to claim 1, characterized in that, After placing the device and sub-circuit to be placed in the selected layout area according to the placement strategy, the method further includes: The evaluation results are generated by comprehensively evaluating the area occupied by the devices and sub-circuits to be placed, the compactness of the layout, and the compliance of the distance between devices.

8. An automatic placement device for analog integrated circuits, characterized in that, The device includes: Acquisition module: used to acquire the circuit netlist information, device library information, and layout size data corresponding to the analog integrated circuit to be laid out; The layout order acquisition module is used to construct a hierarchical circuit structure model based on the circuit netlist information, and sort the layout order of devices and sub-circuits through the circuit connection relationship in the hierarchical circuit structure model to form the corresponding layout order. The layout status module is used to perform layout processing on the devices and sub-circuits to be placed according to the layout order to obtain layout status information, which includes available layout area information, geometric dimension information of the currently placed object, and global layout indicators. Placement strategy module: used to generate placement strategies for the devices and sub-circuits to be placed based on the layout status information and the set of available layout areas, and place the devices and sub-circuits to be placed in the selected layout areas according to the placement strategies until the top-level circuit layout is completed, so as to complete the automatic placement of the analog integrated circuit to be placed.

9. An electronic device comprising a processor and a memory, characterized in that, The processor runs a computer program or code stored in the memory to implement the automatic placement method for analog integrated circuits as described in any one of claims 1 to 7.

10. A computer-readable storage medium for storing computer programs or code, characterized in that, When the computer program or code is executed by a processor, the automatic placement method for analog integrated circuits as described in any one of claims 1 to 7 is implemented.

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