A delay-locked loop reusable in a memory controller
By designing a reusable delay-locked loop in the memory controller, the problem of increased logic area and power consumption caused by repeated instantiation of DLLs in read-write scenarios is solved, realizing time-division multiplexing of DLLs and improving chip integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU XINSHENG INTELLIGENT TECH CO LTD
- Filing Date
- 2026-03-02
- Publication Date
- 2026-06-05
AI Technical Summary
In existing technologies, the design of latency-locked loops (DLLs) for read and write scenarios in storage controllers leads to increased logic area and power consumption, as well as poor integration. This is because DLLs are instantiated separately for read and write scenarios, resulting in reduced DLL utilization.
Design a reusable delay phase-locked loop (PLL), including an input signal selection circuit, a delay PLL device, and an output signal selection circuit. It achieves selective input and output of Tx/Rx scene signals through a scene type selection signal, replacing the traditional TxDLL and RxDLL, reducing redundant instantiation, and realizing time-division multiplexing of the delay PLL.
It reduces internal logic area and power consumption, improves chip integration, and solves the problems of logic simplicity and resource waste in read and write scenarios by reusing a DLL structure.
Smart Images
Figure CN122159862A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of delay phase-locked loop (PLL) technology, and more specifically to a reusable delay phase-locked loop in a storage controller. Background Technology
[0002] In current traditional designs, the data transmission and sampling circuits for ONFI PHY write (Tx) and read (Rx) scenarios, such as... Figure 1 and Figure 2 As shown, a standalone instantiated DLL structure is used. For Figure 1 In the Rx scenario shown, if it is DDR transmission (double-edge data transmission), the NAND Flash will synchronously transmit DQS and DQ[7:0] to the ONFI IO interface. The signals will be sent to the sampling logic in the ONFI PHY for processing after entering the chip (Figure 103). Among them, the DQ signal will be sent to the input of the rising and falling edge asynchronous FIFO to wait for sampling, and the DQS signal will be delayed and latched through the DLL circuit in the Rx direction (Figure 102) to meet the 90° phase difference between DQ and DQS on the FIFO sampling interface, thereby maximizing the signal quality of the NAND Flash receiver. After that, the DQS clock will be split into two and used as the write clock for the rising and falling edge asynchronous FIFO to trigger sampling. To meet the falling edge sampling requirement, the DQS signal is reversed and then used as the write clock for the falling edge asynchronous FIFO. If it is SDR transmission (single-edge data transmission), the NAND Flash will receive the falling edge of the RE signal from the chip and then return the DQ data. The RE signal is transmitted back to the chip for sampling by the ONFI PHY, and is also delayed and latched by the DLL (Figure 102) circuit in the Rx direction, finally serving as the sampling clock for the asynchronous FIFO.
[0003] for Figure 2In the Tx scenario shown, the NFC & ONFI PHY typically use the FLH_CLK (Flash Clock) generated by the internal PLL to drive the relevant circuits. After processing by the NFC's internal DMA logic, the data from the same rising edge and falling edge are given together to the ONFI PHY for processing and then transmitted to the ONFI IO interface. To optimize the sampling window of the DQS signal at the NAND Flash end, a TxDLL is added to the DQS clock transmission path to delay and latch the transmitted FLH_CLK signal, ensuring a 90° phase difference between the NAND Flash's final clock sampling edge and the data, thus optimizing the signal quality at the NAND Flash receiver. After this, the sampled data is driven by the FLH_CLK (Flash Clock) generated by the internal PLL and transmitted to the NFC and other logic of the ONFI PHY for further processing.
[0004] As the above analysis shows, the DLLs handling read and write scenarios are independent, resulting in a clean and clear processing flow and relatively simple logic. However, this design inevitably requires instantiating the DLLs separately on both the read and write sides, reducing DLL utilization by half. While the control logic of this structure is simple and easy to implement, repeated instantiation increases logic area and power consumption, leading to relatively poor integration. Summary of the Invention
[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a reusable delay-locked loop in a memory controller, which reduces internal logic, avoids redundant instantiation, reduces logic area and power consumption, and improves chip integration.
[0006] The objective of this invention is achieved through the following technical solution:
[0007] A reusable delay phase-locked loop in a storage controller includes: an input signal selection circuit, a delay phase-locked loop device, and an output signal selection circuit, and further includes a Tx scene input node, an Rx scene input node, a Tx scene output node, an Rx scene output node, and a scene type selection signal terminal;
[0008] The first and second input terminals of the input signal selection circuit are connected to the Tx scene input node and the Rx scene input node, respectively. The third input terminal of the input signal selection circuit is connected to the scene type selection signal terminal. The output terminal of the input signal selection circuit is connected to the input terminal of the delay phase-locked loop device. The output terminal of the delay phase-locked loop device is connected to the first input terminal of the output signal selection circuit. The second input terminal of the output signal selection circuit is connected to the scene type selection signal terminal. The first and second output terminals of the output signal selection circuit are connected to the Tx scene output node and the Rx scene output node, respectively.
[0009] The input signal selection circuit is used to selectively input the signals of the Tx scene input node and the Rx scene input node according to the scene type selection signal, and the output signal selection circuit is used to output the signals of the Tx scene output node and the Rx scene output node respectively according to the scene type selection signal.
[0010] Furthermore, the input signal selection circuit includes a first two-way selector MUX1, a second two-way selector MUX2, and a third two-way selector MUX3. The first input terminal of the first two-way selector MUX1 is connected to the Tx scene input node, and the second input terminal of the second two-way selector MUX2 is connected to the Rx scene input node. The second input terminals of the first two-way selector MUX1 and the first input terminals of the second two-way selector MUX2 are both set to low level. The output terminal of the first two-way selector MUX1 is connected to the first input terminal of the third two-way selector MUX3, and the output terminal of the second two-way selector MUX2 is connected to the second input terminal of the third two-way selector MUX3. The control terminals of the first two-way selector MUX1, the second two-way selector MUX2, and the third two-way selector MUX3 are all connected to the scene type selection signal terminal. The output terminal of the third two-way selector MUX3 is connected to the input terminal of the delay phase-locked loop device.
[0011] Furthermore, the output signal selection circuit includes a fourth two-way selector MUX4, a fifth two-way selector MUX5, and an inverter. The second input terminal of the fourth two-way selector MUX4 and the first input terminal of the fifth two-way selector MUX5 are both connected to the output terminal of the delay phase-locked loop device. The first input terminal of the fourth two-way selector MUX4 and the second input terminal of the fifth two-way selector MUX5 are both set to low level. The output terminals of the fourth two-way selector MUX4 and the fifth two-way selector MUX5 are respectively connected to the Tx scene output node and the Rx scene output node. The control terminals of the fourth two-way selector MUX4 and the fifth two-way selector MUX5 are both connected to the output terminal of the inverter, and the input terminal of the inverter is connected to the scene type selection signal terminal.
[0012] Furthermore, it also includes a glitch filter circuit connected between the input signal selection circuit and the delay phase-locked loop device. The glitch filter circuit includes a clock gating module and a control logic module. The input terminal of the clock gating module is connected to the output terminal of the input signal selection circuit, the output terminal of the clock gating module is connected to the input terminal of the delay phase-locked loop device, the enable control terminal of the clock gating module is connected to the output terminal of the control logic module, and the input terminal of the control logic module is connected to the scene type selection signal terminal. The control logic module is used to output a pulse signal when it detects that the scene type selection signal has flipped. The clock gating module is used to cut off the path between the input signal selection circuit and the delay phase-locked loop device according to the pulse signal of the enable control terminal, and to open the path again after a delay according to the frequency of the signals of the Tx scene input node and the Rx scene input node.
[0013] Furthermore, it also includes a configuration selector MUXa, used to input DLL configuration information under Tx / Rx scenarios, including DLL phase information; the first and second input terminals of the configuration selector MUXa are respectively connected to the Tx scenario configuration information terminal and the Rx scenario configuration information terminal, the output terminal of the configuration selector MUXa is connected to the delay phase-locked loop device, and the control terminal of the configuration selector MUXa is connected to the scenario type selection signal terminal.
[0014] Furthermore, the Tx scene input node is connected to the FLH_CLK signal generated by the internal PLL, the Tx scene output node is connected to the DQS PAD, the Rx scene input node is connected to the DQS / RE signal transmitted from the chip, and the Rx scene output node is connected to the Rx sampling circuit on the ONFI PHY; the Rx scene output node is connected to the NFC output Tx / Rx DLL sourceselect signal, and its value is set to 0 to indicate that the Tx write scene is selected, and its value is set to 1 to indicate that the Rx read scene is selected.
[0015] The beneficial effects of this invention are:
[0016] The delay-locked loop (PLL) structure provided by this invention replaces the TxDLL and RxDLL in the traditional ONFI PHY chip digital architecture for write (Tx) and read (Rx) scenarios, achieving time-division multiplexing of the PLL. This allows a single DLL to be reused in both Tx and Rx scenarios, reducing internal logic, avoiding redundant instantiation, and to some extent reducing logic area and power consumption, while improving chip integration. Attached Figure Description
[0017] Figure 1 This is a data transmission circuit for the write (Tx) scenario of the ONFI PHY in traditional designs;
[0018] Figure 2This is a sampling circuit for ONFI PHY read (Rx) scenarios in traditional designs;
[0019] Figure 3 This is a circuit schematic of a reusable delay phase-locked loop in a storage controller. Detailed Implementation
[0020] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0021] See Figures 1-3 The present invention provides a technical solution:
[0022] A reusable delay-locked loop in a memory controller, such as Figure 3 As shown, it includes: an input signal selection circuit 1, a delay phase-locked loop device 2, and an output signal selection circuit 3, as well as a Tx scene input node A, an Rx scene input node B, a Tx scene output node C, an Rx scene output node D, and a scene type selection signal terminal S;
[0023] The first and second input terminals of the input signal selection circuit 1 are connected to the Tx scene input node A and the Rx scene input node B, respectively. The third input terminal of the input signal selection circuit 1 is connected to the scene type selection signal terminal S. The output terminal of the input signal selection circuit 1 is connected to the input terminal of the delay phase-locked loop device 2. The output terminal of the delay phase-locked loop device 2 is connected to the first input terminal of the output signal selection circuit 3. The second input terminal of the output signal selection circuit 3 is connected to the scene type selection signal terminal S. The first and second output terminals of the output signal selection circuit 3 are connected to the Tx scene output node C and the Rx scene output node D, respectively.
[0024] The input signal selection circuit 1 is used to selectively input the signals of the Tx scene input node and the Rx scene input node according to the scene type selection signal, and the output signal selection circuit 3 is used to output the signals of the Tx scene output node and the Rx scene output node respectively according to the scene type selection signal.
[0025] In one specific embodiment, the input signal selection circuit 1 includes a first two-way selector MUX1, a second two-way selector MUX2, and a third two-way selector MUX3. The first input terminal of the first two-way selector MUX1 is connected to the Tx scene input node, and the second input terminal of the second two-way selector MUX2 is connected to the Rx scene input node. The second input terminals of the first two-way selector MUX1 and the first input terminals of the second two-way selector MUX2 are both set to low level. The output terminal of the first two-way selector MUX1 is connected to the first input terminal of the third two-way selector MUX3, and the output terminal of the second two-way selector MUX2 is connected to the second input terminal of the third two-way selector MUX3. The control terminals of the first two-way selector MUX1, the second two-way selector MUX2, and the third two-way selector MUX3 are all connected to the scene type selection signal terminal. The output terminal of the third two-way selector MUX3 is connected to the input terminal of the delay phase-locked loop device.
[0026] In one specific embodiment, the output signal selection circuit 3 includes a fourth two-way selector MUX4, a fifth two-way selector MUX5, and an inverter. The second input terminal of the fourth two-way selector MUX4 and the first input terminal of the fifth two-way selector MUX5 are both connected to the output terminal of the delay phase-locked loop device. The first input terminal of the fourth two-way selector MUX4 and the second input terminal of the fifth two-way selector MUX5 are both set to low level. The output terminals of the fourth two-way selector MUX4 and the fifth two-way selector MUX5 are respectively connected to the Tx scene output node and the Rx scene output node. The control terminals of the fourth two-way selector MUX4 and the fifth two-way selector MUX5 are both connected to the output terminal of the inverter, and the input terminal of the inverter is connected to the scene type selection signal terminal.
[0027] Furthermore, the Tx scene input node A is connected to the FLH_CLK signal generated by the internal PLL, the Tx scene output node C is connected to the DQS PAD, the Rx scene input node B is connected to the DQS / RE signal transmitted from the chip, and the Rx scene output node D is connected to the Rx sampling circuit on the ONFI PHY; the Rx scene output node is connected to the NFC output Tx / Rx DLL sourceselect signal, whose value is set to 0 to indicate selection of the Tx write scene, and whose value is set to 1 to indicate selection of the Rx read scene. As can be seen from the above connection method, the delay-locked loop structure provided by this invention is used to replace the chip digital architecture in the traditional ONFI PHY in the write (Tx) and read (Rx) scenes. Figure 1 and Figure 2 The TxDLL and RxDLL in the ) are used to implement time-division multiplexing of the delay phase-locked loop.
[0028] It needs to be explained that, Figure 1 and Figure 2 The NFC & ONFI PHY modules in the diagram represent the control circuit (NFC) and other digital logic of the ONFI PHY used for NAND Flash (non-volatile memory) control in the SSD controller chip. Since the entire NAND Flash control circuit and ONFI PHY are quite complex, and the other functions are not very relevant to this work, the relevant parts are omitted in this diagram for the sake of simplicity.
[0029] In an optional embodiment, a glitch filter circuit 4 is further included, connected between the input signal selection circuit and the delay phase-locked loop device. The glitch filter circuit 4 includes a clock gating module and a control logic module. The input terminal of the clock gating module is connected to the output terminal of the input signal selection circuit, the output terminal of the clock gating module is connected to the input terminal of the delay phase-locked loop device, the enable control terminal of the clock gating module is connected to the output terminal of the control logic module, and the input terminal of the control logic module is connected to the scene type selection signal terminal. The control logic module is used to output a pulse signal when a scene type selection signal flip is detected. The clock gating module is used to cut off the path between the input signal selection circuit and the delay phase-locked loop device according to the pulse signal of the enable control terminal, and to delay and then reopen the path according to the frequency of the signals of the Tx scene input node and the Rx scene input node.
[0030] When the scene type selection signal SELECT toggles, the clock gating module triggers a few clock cycles to turn off, in the following sequence: clock off, clock switching, clock on. Its switching logic is synchronized with the chip's FSH_CLK frequency, therefore, there will be no FSH_CLK glitches during switching. Since the DQS in the Rx direction is not generated at the moment of switching, and an internal cnt counter is configured to delay switching back after the DQS signal is received, there will be no glitches when switching from Tx to Rx or back from Rx.
[0031] In an optional embodiment, a configuration selector MUXa is further included for inputting DLL configuration information under the Tx / Rx scenario, including DLL phase information; the first input terminal and the second input terminal of the configuration selector MUXa are respectively connected to the Tx scenario configuration information terminal and the Rx scenario configuration information terminal; the output terminal of the configuration selector MUXa is connected to the delay phase-locked loop device; and the control terminal of the configuration selector MUXa is connected to the scenario type selection signal terminal.
[0032] like Figure 3 The operating logic of the reusable delay phase-locked loop shown is as follows:
[0033] Tx Write Scenario: NFC output Tx / Rx DLL source select=0 indicates that a Tx scenario is currently in progress. The TxDLL configuration is entered through the configuration register into the A0 terminal of MUXa and then into the DLL. Since Tx / Rx DLL source select serves as the control terminal for the first two-way selector MUX1, the second two-way selector MUX2, and the third two-way selector MUX3, when Tx / Rx DLL source select=0, MUX1, MUX2, and MUX3 all select the signal input from their A0 ports for output. Therefore, in the current situation, the FLH_CLK input from the Tx scenario input node can be input through the A0 terminal of MUX1, and after passing through MUX3, it enters the clock gating module of the glitch filter circuit. After dynamic switching filtering, the clock gating is enabled, and the clock passes through the gating to enter the DLL input terminal. The DLL outputs the delayed latched clock. Similarly, the Tx / Rx DLL source select signal, after being inverted, controls the fourth two-way selector MUX4 and the fifth two-way selector MUX5 of the output signal selection circuit. When Tx / Rx DLL source select=0, the clock signal is entered through the A0 terminal of MUX1, MUX2, and MUX3 for output. With select=0, both MUX4 and MUX5 select the signal input from their A1 ports for output. Therefore, in the current case, the clock after delay and latching can be input through the A1 port of MUX4 and eventually transmitted from the Tx output node to the DQS PAD.
[0034] Rx Read Scenario: NFC output Tx / Rx DLL source select=1 indicates that the current scenario is Rx. The RxDLL configuration is entered through the configuration register into the A1 terminal of MUXa and then into the DLL. When Tx / Rx DLL source select=1, MUX1, MUX2, and MUX3 all select the signal input from their A1 ports for output. Therefore, in the current case, DQS / RE enters the chip through the PAD, is input through the A1 terminal of MUX2, and then enters the clock gating module of the glitch filter circuit through MUX3. After dynamic switching filtering, the clock gating is enabled, and the clock enters the DLL input terminal through the gating. The DLL outputs a delayed latched clock, which is input through the A0 terminal of MUX5 and finally transmitted from the Rx output node, ultimately providing the Rx sampling circuit on the ONFI PHY to drive the asynchronous FIFO read clock.
[0035] This invention introduces relevant digital logic design, enabling the reuse of a DLL in Tx / Rx scenarios, reducing internal logic, avoiding redundant instantiation, and to some extent reducing logic area and power consumption, thereby improving chip integration.
[0036] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. A reusable delay-locked loop in a storage controller, characterized in that, include: The input signal selection circuit, the delay phase-locked loop device, and the output signal selection circuit also include a Tx scene input node, an Rx scene input node, a Tx scene output node, an Rx scene output node, and a scene type selection signal terminal; The first and second input terminals of the input signal selection circuit are connected to the Tx scene input node and the Rx scene input node, respectively. The third input terminal of the input signal selection circuit is connected to the scene type selection signal terminal. The output terminal of the input signal selection circuit is connected to the input terminal of the delay phase-locked loop device. The output terminal of the delay phase-locked loop device is connected to the first input terminal of the output signal selection circuit. The second input terminal of the output signal selection circuit is connected to the scene type selection signal terminal. The first and second output terminals of the output signal selection circuit are connected to the Tx scene output node and the Rx scene output node, respectively. The input signal selection circuit is used to selectively input the signals of the Tx scene input node and the Rx scene input node according to the scene type selection signal, and the output signal selection circuit is used to output the signals of the Tx scene output node and the Rx scene output node respectively according to the scene type selection signal.
2. The reusable delay-locked loop in a storage controller according to claim 1, characterized in that: The input signal selection circuit includes a first two-way selector MUX1, a second two-way selector MUX2, and a third two-way selector MUX3. The first input terminal of the first two-way selector MUX1 is connected to the Tx scene input node, and the second input terminal of the second two-way selector MUX2 is connected to the Rx scene input node. The second input terminals of the first two-way selector MUX1 and the first input terminals of the second two-way selector MUX2 are both set to low level. The output terminal of the first two-way selector MUX1 is connected to the first input terminal of the third two-way selector MUX3, and the output terminal of the second two-way selector MUX2 is connected to the second input terminal of the third two-way selector MUX3. The control terminals of the first two-way selector MUX1, the second two-way selector MUX2, and the third two-way selector MUX3 are all connected to the scene type selection signal terminal. The output terminal of the third two-way selector MUX3 is connected to the input terminal of the delay phase-locked loop device.
3. A reusable delay-locked loop in a storage controller according to claim 1, characterized in that: The output signal selection circuit includes a fourth two-way selector MUX4, a fifth two-way selector MUX5, and an inverter. The second input terminal of the fourth two-way selector MUX4 and the first input terminal of the fifth two-way selector MUX5 are both connected to the output terminal of the delay phase-locked loop device. The first input terminal of the fourth two-way selector MUX4 and the second input terminal of the fifth two-way selector MUX5 are both set to low level. The output terminals of the fourth two-way selector MUX4 and the fifth two-way selector MUX5 are respectively connected to the Tx scene output node and the Rx scene output node. The control terminals of the fourth two-way selector MUX4 and the fifth two-way selector MUX5 are both connected to the output terminal of the inverter, and the input terminal of the inverter is connected to the scene type selection signal terminal.
4. A reusable delay-locked loop in a storage controller according to claim 1, characterized in that: It also includes a glitch filter circuit connected between the input signal selection circuit and the delay phase-locked loop device. The glitch filter circuit includes a clock gating module and a control logic module. The input terminal of the clock gating module is connected to the output terminal of the input signal selection circuit, the output terminal of the clock gating module is connected to the input terminal of the delay phase-locked loop device, the enable control terminal of the clock gating module is connected to the output terminal of the control logic module, and the input terminal of the control logic module is connected to the scene type selection signal terminal. The control logic module is used to output a pulse signal when it detects that the scene type selection signal has flipped. The clock gating module is used to cut off the path between the input signal selection circuit and the delay phase-locked loop device according to the pulse signal of the enable control terminal, and to open the path after a delay according to the frequency of the signals of the Tx scene input node and the Rx scene input node.
5. A reusable delay-locked loop in a storage controller according to claim 1, characterized in that: It also includes a configuration selector MUXa, which is used to input DLL configuration information under Tx / Rx scenarios, including DLL phase information; the first and second input terminals of the configuration selector MUXa are connected to the Tx scenario configuration information terminal and the Rx scenario configuration information terminal, respectively; the output terminal of the configuration selector MUXa is connected to the delay phase-locked loop device; and the control terminal of the configuration selector MUXa is connected to the scenario type selection signal terminal.
6. A reusable delay-locked loop in a storage controller according to claim 1, characterized in that: The Tx scene input node is connected to the FLH_CLK signal generated by the internal PLL, the Tx scene output node is connected to the DQS PAD, the Rx scene input node is connected to the DQS / RE signal transmitted from the chip, and the Rx scene output node is connected to the Rx sampling circuit on the ONFI PHY. The Rx scene output node is connected to the NFC output Tx / Rx DLL source select signal, and its value is set to 0 to indicate that the Tx write scene is selected, and its value is set to 1 to indicate that the Rx read scene is selected.