An EPC tunneling encoding method and system for improving RFID tag identification reliability

Abstract

The application provides an EPC tunneling encoding method and system for improving the identification reliability of an RFID tag. The method comprises the following steps: performing lightweight forward error correction encoding on standard EPC information to obtain redundant error correction EPC data containing a redundant protection structure; writing the data into an RFID tag; performing an interactive process between a reader and the RFID tag to read the redundant error correction EPC data and perform decoding operation, and recovering the standard EPC information by using the redundant information; performing cyclic redundancy check on the standard EPC information, and if the check is passed, uploading the standard EPC information to an upper application, otherwise, retriggering the interactive process. By using the EPC tunneling encoding method, the EPC transmission reliability is improved without modifying the protocol and the tag hardware, and the energy consumption of the tag retransmission, the system communication overhead and the throughput are reduced.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency identification technology, specifically relating to an EPC tunneling coding method and system for improving the reliability of RFID tag identification. Background Technology

[0002] Radio Frequency Identification (RFID) technology, a non-contact automatic identification technology based on radio waves, has been widely used in numerous fields such as logistics warehousing, supply chain management, retail settlement, industrial manufacturing, and the Internet of Things since the late 20th century, and is one of the key supporting technologies for the Industrial Internet. A typical RFID system consists of readers, tags, middleware, and backend systems. Each tag stores a unique Electronic Product Code (EPC) to identify its corresponding physical object.

[0003] In passive RFID systems operating in the Ultra-High Frequency (UHF) band (860-960MHz), the communication protocol typically follows the EPCglobal Class-1 Generation-2 (Gen2) standard. This protocol achieves multi-tag collision avoidance through a time-slotted ALOHA mechanism and uses a 16-bit CRC (Cyclic Redundancy Check) for error detection, but it lacks error correction capabilities. Passive tags rely on electromagnetic waves emitted by the reader for energy, resulting in extremely low power budgets for their communication links. This limits the design of tag antennas and rectifier circuits, making them sensitive to environmental noise, electromagnetic interference, and multipath reflections. In complex industrial environments, RF signals are often attenuated or distorted due to interference from metal equipment, liquid media, and other wireless systems.

[0004] Existing UHF RFID systems suffer from deficiencies in the reliability of EPC data transmission. On one hand, due to the lack of effective forward error correction (FEC), if channel noise interference causes bit flipping, the entire EPC data packet will be deemed invalid, requiring retransmission to recover the data. However, passive tags have extremely low power budgets, and retransmission operations not only significantly increase communication overhead and energy consumption, but also lead to frequent error retransmissions in low signal-to-noise ratio environments, resulting in decreased system throughput and a significant increase in read latency. On the other hand, while traditional FEC algorithms can solve the error correction problem, they require adding redundant data bits, thus altering the data frame structure or transmission timing. Furthermore, the EPC Gen2 protocol defines strict data packet formats and field lengths; any change in code length will lead to incompatibility with existing readers, chips, and middleware systems, making it difficult to introduce these algorithms to improve the reliability of EPC data transmission without changing the protocol. Summary of the Invention

[0005] In view of this, the present invention provides an EPC tunneling coding method and system to improve the reliability of RFID tag identification, aiming to solve the reliability problem of existing UHF RFID systems in EPC data transmission.

[0006] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0007] In a first aspect, the present invention provides an EPC tunneling coding method for improving the reliability of RFID tag identification, comprising the following steps:

[0008] Lightweight forward error correction coding is performed on standard EPC information. By introducing redundant information into the standard EPC information, redundant error correction EPC data containing a redundant protection structure is constructed. The redundant information is used to provide error correction constraints for decoding and recovering the standard EPC information.

[0009] Write redundant error correction EPC data into the RFID tag; the length of the redundant error correction EPC data is within the range of EPC field length specified in the EPCglobal Gen2 standard.

[0010] The interaction process between the reader and the RFID tag is carried out so that the reader receives redundant error correction EPC data and performs decoding operation corresponding to the lightweight forward error correction code, and recovers the standard EPC information using the redundant information.

[0011] Perform cyclic redundancy check on the standard EPC information. If the check passes, upload the standard EPC information to the upper layer application. If the check fails, re-trigger the interaction process.

[0012] Furthermore, the lightweight forward error correction coding is polar coding, and polar coding is only performed once when the RFID tag is first written. The polar coding process includes:

[0013] Using a 96-bit standard EPC as the information source, a 128-bit input bit vector is constructed. The first 96 bits of the input bit vector are standard EPC information bits, and the last 32 bits are frozen bits that are fixed to zero. The frozen bits are redundant information.

[0014] Construct the polarization generation matrix;

[0015] The input bit vector is multiplied by the polarization generation matrix to obtain 128-bit redundant error correction EPC data; the 128-bit polarization EPC data is the redundant error correction EPC data.

[0016] Furthermore, the polarization generation matrix is:

[0017]

[0018] In the formula, It is an N×N dimensional generating matrix. It is the basic kernel matrix, and , For Kronecker exponentiation, This represents the number of operations performed by the Kronecker exponentiation.

[0019] Furthermore, the decoding process includes:

[0020] Demodulate the 128-bit polarized EPC data to obtain the log-likelihood ratio of each bit.

[0021] According to the polar coding freeze bit construction rules, the position of the corresponding freeze bit in the demodulated data is forcibly set to zero;

[0022] Based on the log-likelihood ratio, perform SC decoding recursive operation bit by bit to obtain the estimated information bit sequence;

[0023] By removing the frozen bits from the estimated information bit sequence, the 96-bit standard EPC information is recovered.

[0024] Furthermore, the interaction process follows the EPCglobal Gen2 standard. Redundant error-correcting EPC data is carried in communication frames to implement the interaction process. The structure of the communication frame includes:

[0025] The field includes a preamble, a protocol control field, a redundancy correction EPC data field, and a CRC field, wherein the content of the redundancy correction EPC data field is the redundancy correction EPC data.

[0026] All protocol commands in the interaction process remained unchanged.

[0027] Furthermore, the decoding operation is implemented through software or hardware modules on the reader / writer side, specifically as follows:

[0028] The software module is a decoding module added to the reader firmware; the decoding module is used to complete the decoding operation by using a lookup table method and an integer approximation of the log-likelihood ratio.

[0029] The hardware module is a decoder built on an FPGA with a parallel pipeline structure. The decoder's decoding depth matches the length of the redundant error correction EPC data. The bit path uses the Min-Sum approximation algorithm to reduce the number of multipliers. It is connected to the original reader / writer system through an AXI bus to realize the streaming input and output of data during the decoding process, thereby completing the decoding operation.

[0030] Furthermore, redundant error correction EPC data is written into the EPC or User storage area of ​​the RFID tag.

[0031] Secondly, the present invention provides an EPC tunneling coding system for improving the reliability of RFID tag identification, comprising:

[0032] The encoding unit is used to perform lightweight forward error correction coding on the standard EPC information. By introducing redundant information into the standard EPC information, redundant error-corrected EPC data containing a redundant protection structure is constructed. The redundant information is used to provide error correction constraints for decoding and recovering the standard EPC information.

[0033] The writing unit is used to write redundant error correction EPC data into the RFID tag; the length of the redundant error correction EPC data is within the range of EPC field length specified in the EPCglobal Gen2 standard.

[0034] The decoding unit is used to perform an interaction process between the reader and the RFID tag, so that the reader receives redundant error correction EPC data and performs a decoding operation corresponding to the lightweight forward error correction code, and recovers the standard EPC information using the redundant information.

[0035] The verification unit is used to perform cyclic redundancy verification on the standard EPC information. If the verification passes, the standard EPC information is uploaded to the upper-layer application; if the verification fails, the interaction process is retried.

[0036] Thirdly, the present invention provides a computer device, the device including a processor and a memory:

[0037] The memory is used to store computer programs and send the instructions of the computer programs to the processor;

[0038] The processor executes, according to the instructions of the computer program, an EPC tunneling coding method for improving the reliability of RFID tag identification, as described in the first aspect.

[0039] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements an EPC tunneling coding method for improving the reliability of RFID tag identification as described in the first aspect.

[0040] In summary, this invention provides an EPC tunneling coding method and system for improving the reliability of RFID tag identification. The method includes the following steps: performing lightweight forward error correction coding on standard EPC information; constructing redundant error-correcting EPC data with a redundancy protection structure by introducing redundant information into the standard EPC information; using the redundant information to provide error correction constraints for decoding and recovering the standard EPC information; writing the redundant error-correcting EPC data into the RFID tag; ensuring the length of the redundant error-correcting EPC data is within the EPC field length range specified in the EPCglobal Gen2 standard; executing an interaction process between a reader and the RFID tag, enabling the reader to receive the redundant error-correcting EPC data and perform decoding operations corresponding to the lightweight forward error correction coding, recovering the standard EPC information using the redundant information; performing cyclic redundancy check on the standard EPC information; if the check passes, uploading the standard EPC information to the upper-layer application; if the check fails, re-triggering the interaction process. This invention, by employing the EPC tunneling coding method, improves EPC transmission reliability without modifying the protocol or tag hardware, while simultaneously reducing tag retransmission energy consumption, reducing system communication overhead, and increasing throughput. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A flowchart of an EPC tunneling coding method for improving the reliability of RFID tag identification is provided in an embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram of EPC tunneling encoding provided in an embodiment of the present invention;

[0044] Figure 3 A comparison chart of transmission throughput between Polar EPC and traditional EPC provided for embodiments of the present invention;

[0045] Figure 4 A comparison chart of data reception delay between the Polar EPC scheme and the traditional EPC scheme provided in this embodiment of the invention;

[0046] Figure 5 This invention provides a block diagram of an EPC tunneling coding system for improving the reliability of RFID tag identification.

[0047] Figure 6This is a block diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0048] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0049] The background technology of this invention will be further introduced below.

[0050] Radio Frequency Identification (RFID) is a non-contact automatic identification technology based on radio waves, used to identify objects and collect data without human intervention. Since the late 20th century, this technology has been widely used in logistics warehousing, supply chain management, retail settlement, industrial manufacturing, and the Internet of Things (IoT), and is one of the key supporting technologies for the Industrial Internet of Things (IIoT). A typical RFID system consists of three parts: a reader, a tag, and middleware and backend systems. The reader is responsible for transmitting radio frequency signals and receiving data returned by the tag; the tag is usually a passive device that obtains energy from the electromagnetic waves emitted by the reader through an internal rectification and energy harvesting module to drive its circuitry. Each tag stores a unique Electronic Product Code (EPC) to identify its corresponding physical object.

[0051] In passive RFID systems operating in the Ultra-High Frequency (UHF) band (860–960 MHz), the communication protocol typically follows the EPCglobal Class-1 Generation-2 (Gen2) standard. This protocol achieves multi-tag collision avoidance through a slotted ALOHA mechanism and performs error detection using a 16-bit CRC, but it lacks error correction capabilities. The data transmission process includes the following steps:

[0052] 1. The reader sends a Query command to establish communication;

[0053] 2. The tag responds with a 16-bit random number (RN16) based on a random time slot;

[0054] 3. After confirmation, the reader requests the tag to return its EPC code;

[0055] 4. The tag will send back the EPC (96-bit) along with the verification code.

[0056] Because passive tags rely entirely on the energy of the reader's excitation signal for power, their communication link power budget is extremely low, typically only in the microwatt range. The design of the tag antenna and rectifier circuitry is severely constrained, making them highly sensitive to environmental noise, electromagnetic interference, and multipath reflections. In complex industrial environments, RF signals are often attenuated or distorted due to interference from metal equipment, liquid media, and other wireless systems, leading to bit errors or read failures in tag responses.

[0057] The power budget limitations of passive tags not only affect signal reception sensitivity but also directly restrict the logic operation capabilities and storage capacity of the tag chip. To control cost and power consumption, the number of logic gates in commercial passive RFID tag chips is typically limited to 500-2000, enabling only basic functions such as signal demodulation, CRC check, and random number generation, and cannot handle complex signal processing or encoding operations. Simultaneously, the EPC storage area of ​​the tag is usually 96-bit or 128-bit, with some low-cost tags even supporting only a fixed 96-bit length, unable to expand storage for redundant information. This makes it difficult to directly apply traditional FEC technology, which requires a large number of redundant bits and complex calculations, to passive RFID tags. Furthermore, the EPCglobal Gen2 standard, as the mainstream protocol in the current UHF RFID field, has been widely adopted by the vast majority of readers, tag chips, and backend systems worldwide. Its defined data packet format, field length, and communication timing have strong universality and compatibility; any modification to the protocol will result in incompatibility with existing equipment, increasing system upgrade costs, which is also a significant factor restricting the improvement of RFID system reliability.

[0058] According to wireless communication theory, the theoretical upper limit of the time slot utilization rate of the ALOHA protocol is approximately... = 36.8%. When the channel bit error rate (BER) increases further, the probability of successful decoding of EPC data packets decreases exponentially, leading to a significant reduction in identification throughput and a significant increase in retransmission delay. Existing research and experiments have verified that when the bit error rate is only 2% to 5%, the average reading delay of the RFID system can increase by 10 to 600 times, seriously affecting real-time performance and stability.

[0059] In summary, insufficient reliability is a key bottleneck currently faced by UHF RFID systems, especially in low signal-to-noise ratio (SNR) and high-density tag environments, where traditional EPC communication mechanisms cannot effectively resist channel noise.

[0060] In communication systems, forward error correction (FEC) is a coding technique that introduces redundant information at the transmitting end to achieve automatic error correction at the receiving end. Unlike CRC, which can only detect errors, FEC can recover some or all of the erroneous bits without retransmission, thus significantly improving the reliability and efficiency of data transmission.

[0061] Typical forward error correction codes include:

[0062] 1. Convolutional codes and Viterbi decoders – suitable for continuous data streams, widely used in satellite communications and early cellular networks;

[0063] 2. Block code, such as Hamming code, BCH code, Reed-Solomon code—used for fixed-length data blocks;

[0064] 3. Turbo codes and LDPC codes (Low-Density Parity-Check Codes) – widely used in modern communication systems (such as 4G LTE and Wi-Fi 6);

[0065] 4. Polar Code – Proposed by Erdal Arıkan in 2009, it is the first coding scheme mathematically proven to achieve Shannon channel capacity and has been incorporated into the 5G NR standard.

[0066] FEC (Fault-Correcting) technology typically adds redundant bits to the original information, enabling the receiver to correct errors introduced by signal noise using this redundant information. Its error-correcting capability is directly proportional to the number of redundant bits (i.e., the reciprocal of the code rate). The main advantages of FEC include:

[0067] (1) Improve transmission reliability under low SNR channels;

[0068] (2) Reduce system retransmission overhead;

[0069] (3) Improve effective throughput;

[0070] (4) Supports stable real-time communication.

[0071] However, implementing these encoding algorithms typically requires additional logic gates and storage resources. For example, a standard 16-bit CRC requires only about 500 logic gates, while a minimally designed polar encoder requires 4,000–7,000 logic gates. For passive tags costing only $0.05–$0.10, this hardware overhead is unacceptable.

[0072] Different types of FEC codes vary significantly in hardware overhead, error correction performance, and coding complexity, and are suitable for different scenarios. Convolutional codes have low coding complexity, but require a Viterbi decoder for decoding, and their hardware implementation demands a large amount of storage and computational logic, posing power consumption and cost pressures for passive RFID tags. Hamming codes can only correct single-bit errors, offering limited error correction capabilities and failing to meet the multi-bit error correction requirements of complex industrial environments. BCH and Reed-Solomon codes have strong error correction capabilities, but their encoding and decoding processes involve complex polynomial operations, requiring numerous multipliers and adders, resulting in high hardware overhead and making them unsuitable for passive RFID tags. Turbo codes and LDPC codes have error correction performance close to the Shannon limit, but the iterative process of encoding and decoding requires a lot of computing resources and time, resulting in poor real-time performance. Moreover, their hardware implementation is extremely complex, making them unsuitable for the low power consumption and low resource requirements of passive RFID tags. Although polar codes theoretically have the best error correction performance, the hardware overhead of traditional polar encoders still exceeds the carrying capacity of passive tags. However, their encoding structure is optimizable. By reasonably designing the freeze bits and encoding process, lightweight modifications can be made to adapt them to the resource constraints of RFID systems.

[0073] As mentioned earlier, while existing UHF RFID systems have made significant progress in terms of identification distance, cost, and standardization, they still suffer from the following major technical shortcomings in complex electromagnetic environments:

[0074] 1. Lacking forward error correction capability, reliability heavily depends on channel quality.

[0075] The current EPCglobal Gen2 standard only provides a CRC error detection mechanism and cannot correct bit flips caused by channel noise. If a tag has a single-bit error, the entire EPC data packet will be deemed invalid, and a read request must be re-initiated. This full-packet retransmission mechanism causes the system throughput to decrease exponentially in low signal-to-noise ratio environments, severely limiting the read rate and stability.

[0076] 2. It is impossible to introduce an FEC mechanism without changing the agreement.

[0077] Traditional forward error correction algorithms (such as Hamming codes, BCH codes, Turbo codes, LDPC codes, Polar codes, etc.) all require adding data redundancy bits, thereby changing the data frame structure or transmission timing. However, the EPC Gen2 protocol defines strict data packet formats and field lengths. Any change in code length will lead to incompatibility with existing readers, chips, and middleware systems, making it difficult to achieve protocol-level modifications.

[0078] 3. Limited hardware resources prevent support for complex coding calculations.

[0079] The core chip of passive RFID tags has a limited number of logic gates (generally between 5×10² and 2×10³), enabling only basic CRC, random number generation, and baseband modulation functions. Forward error correction algorithms typically require a large number of multiplications, additions, or logical operations (e.g., polar coding requires approximately 4000 to 7000 logic gates), exceeding the capabilities of existing tag chips. Increased circuit complexity also leads to increased energy consumption, shortened communication distance, and higher manufacturing costs.

[0080] 4. The retransmission strategy is inefficient, significantly increasing communication latency.

[0081] When an EPC read fails, the existing system needs to re-initiate the read operation in a new anti-collision cycle, involving multiple Query and ACK command interactions. This "protocol-layer-based retransmission" mechanism incurs significant overhead in multi-label scenarios. Experimental results show that at a bit error rate of only 2%, system latency can increase by more than ten times, and at 5%, it can even reach 600 times.

[0082] 5. The research plan lacks practical engineering applicability.

[0083] Existing research on RFID forward error correction (FEC) in the literature is mostly limited to the simulation stage. For example, Smietanka et al. (IEEE ICIT 2013) proposed an error detection method based on BCH codes, and Albright et al. (IEEE RFID 2015) explored the possibility of introducing FEC into the Gen2 link. However, these schemes all require the implementation of encoding logic at the tag end, lack compatibility verification with existing tags, and have not yet formed a practically deployable system solution.

[0084] The existing research solutions lack engineering feasibility, mainly in three aspects: First, most solutions assume that the tag has certain encoding and computing capabilities, ignoring the hardware resource constraints of passive tags, making them unusable on commercial tags. Second, some solutions require modifications to the frame structure or communication timing of the EPC Gen2 protocol, making them incompatible with existing readers and backend systems, necessitating large-scale equipment replacement at extremely high costs. Third, existing solutions do not consider complex interference factors in real-world industrial scenarios, verifying error correction performance only in ideal simulation environments. When applied to real-world industrial scenarios, the error correction effect drops significantly, failing to meet practical application requirements. Furthermore, most existing solutions do not consider the compatibility between encoding redundancy and tag storage capacity, resulting in redundant information not being stored on the tags, further limiting the practical deployment feasibility of the solutions.

[0085] In summary, current RFID communication has fundamental defects in physical layer anti-interference capability, protocol compatibility, and low power consumption implementation mechanism, resulting in insufficient system reliability, decreased reading rate, and increased latency in noise, electromagnetic interference, or complex scenarios, which cannot meet the high reliability identification requirements of the industrial Internet of Things environment.

[0086] To address the aforementioned shortcomings, the primary objective of this invention is to improve the reliability of EPC data transmission without modifying existing hardware or communication protocols. This includes implementing forward error correction for channel errors, reducing the number of data packet retransmissions, thereby lowering read latency and increasing system throughput. Secondary objectives include, on the one hand, constructing a reliability enhancement mechanism that can be directly adapted to existing tags and readers while maintaining full compatibility with the EPCglobalGen2 standard; and on the other hand, improving the EPC data structure design to protect and redundantly encapsulate the original EPC information. Specifically, redundant information is introduced by the reader performing polarization coding only once when initially writing standard EPC information, ensuring that the tag can stably return decodeable identification data even in harsh channel environments. Through these designs, this invention aims to fill the gaps in physical layer error correction and signal robustness in traditional RFID systems, address the deficiencies of existing technologies in noise immunity, real-time performance, and system compatibility, and provide a more reliable technical foundation for industrial-grade RFID applications.

[0087] It is important to note that the core innovation of this invention lies in the proposal and implementation of the "tunneling coding" concept. Essentially, without altering the existing RFID system's hardware architecture and communication protocols, it enables error correction during transmission by redundantly encapsulating and lightweight coding the EPC data itself, while maintaining full compatibility with existing systems. Compared to existing technologies, this invention requires no additional coding or computational logic on the tag side; all coding and decoding operations are centralized at the reader end, controlling tag cost and power consumption while reducing the difficulty and cost of system upgrades. Furthermore, by rationally designing the matching relationship between coding redundancy and tag storage capacity, it fully utilizes the underutilized storage resources of existing tags, transforming storage redundancy into channel protection redundancy, achieving efficient resource utilization. In addition, the solution of this invention has undergone extensive testing and verification in real-world industrial scenarios, demonstrating that its error correction performance and system compatibility meet the application requirements of the Industrial Internet of Things (IIoT), possessing strong engineering feasibility and effectively addressing the pain point of insufficient reliability in traditional RFID systems in complex industrial environments.

[0088] The various embodiments of the present invention will be described in detail below.

[0089] Please see Figure 1 This embodiment provides an EPC tunneling coding method to improve the reliability of RFID tag identification, including the following steps:

[0090] S11: Perform lightweight forward error correction coding on the standard EPC information. By introducing redundant information into the standard EPC information, redundant error correction EPC data containing a redundant protection structure is constructed. The redundant information is used to provide error correction constraints for decoding and recovering the standard EPC information.

[0091] It should be noted that standard EPC information, or Electronic Product Code, is the core data used to identify items in an RFID system. It follows the EPCglobal Gen2 standard format and is the unique identifier for item identification.

[0092] Lightweight forward error correction (FEC) coding is a computationally inefficient and low-redundancy-overhead forward error correction (FEC) coding technique. Unlike traditional FEC coding, this method adds redundant information with fixed association rules to the original EPC information. Its purpose is to provide a basis for verifying and recovering errors in data transmission without changing the data packet format or field length. The redundant error-correcting EPC data is a composite data structure that integrates standard EPC information and redundant information. Error correction constraints refer to the mathematical association rules between redundant information and original EPC information. The decoding end can use these rules to verify data integrity and recover erroneous data.

[0093] The core principle of forward error correction coding is that the transmitter adds redundancy and the receiver performs autonomous error correction, without requiring feedback interaction between the transmitter and receiver. This step adopts a lightweight solution, which avoids the occupation of RFID tag storage and computing resources by complex coding, and meets the premise of not modifying the hardware. By introducing redundant information to construct redundant error correction EPC data, it essentially establishes an error correction protection layer for the original EPC information. When a small number of errors occur in subsequent transmissions, the decoding end can directly recover the data through the redundant information, rather than triggering retransmission.

[0094] S12: Write the redundant error correction EPC data into the RFID tag; the length of the redundant error correction EPC data is within the range of EPC field length specified in the EPCglobalGen2 standard.

[0095] It should be noted that the EPCglobal Gen2 standard is an RFID air interface protocol standard developed by the EPCglobal organization. It is the mainstream protocol for current UHF RFID systems and specifies the length range of EPC fields (such as 96 bits, 128 bits, etc.), data format, and communication rules.

[0096] The EPC field length range is defined by the EPCglobal Gen2 standard as the maximum and minimum length of EPC data. Data packets exceeding this range cannot be recognized and parsed by existing readers.

[0097] This step controls the total length of the redundant error correction EPC data to be within the EPC field length range specified in the EPCglobal Gen2 standard. If the data length exceeds the standard range, the existing RFID tag's EPC storage area cannot accommodate it, and the reader cannot recognize it. In this case, the hardware storage capacity or protocol parsing rules must be modified. However, through length adaptation, the redundant error correction EPC data can be directly written into the existing tag's EPC storage area without any adjustments to the tag hardware or reader protocol.

[0098] In actual writing, this invention supports two writing modes to adapt to different types of RFID tags and application scenarios: The first is a one-time writing mode, where the reader completes the polarization encoding of standard EPC information and the writing of redundant error-correcting EPC data in one go during the initial deployment of the tag. Subsequent tags only need to transmit data back according to the standard process, without needing to perform encoding operations again. This mode is suitable for scenarios where tags are used permanently and do not require frequent modifications to EPC information. The second is a rewritable mode, where when the tag's EPC information needs to be modified, the reader first deletes the original redundant error-correcting EPC data in the tag, then performs lightweight forward error correction encoding on the new standard EPC information to generate new redundant error-correcting EPC data and writes it to the tag. This mode is suitable for scenarios where tags need to frequently update their EPC information. Regardless of the writing mode used, the writing process follows the writing commands and timing requirements of the EPCglobal Gen2 standard, is fully compatible with the writing logic of existing readers, and requires no modification to the reader's firmware or hardware. Meanwhile, to ensure the reliability of the written data, after the writing is completed, the reader will immediately read the redundant error correction EPC data in the tag and compare it with the locally generated redundant error correction EPC data. If the comparison is consistent, the writing is confirmed to be successful; if the comparison is inconsistent, the writing operation will be retried until the writing is successful, which effectively avoids data errors caused by bit errors during the writing process.

[0099] S13: The reader and RFID tag perform an interaction process so that the reader receives redundant error correction EPC data and performs a decoding operation corresponding to the lightweight forward error correction code, and recovers the standard EPC information using the redundant information.

[0100] It should be noted that the interaction process follows the air interface communication process of the EPCglobal Gen2 standard, including tag wake-up, identity authentication, data reading, etc., which is the standard interaction mode of existing RFID systems.

[0101] Decoding is the inverse operation corresponding to the lightweight forward error correction coding at the transmitting end. It involves extracting redundant information from the received data and verifying and restoring the standard EPC information according to the error correction constraint rules.

[0102] This step's interaction process fully complies with the EPCglobal Gen2 standard, without any modifications to the existing communication protocol. After receiving the redundant error-correcting EPC data, the reader performs the corresponding decoding operation. The principle is to utilize the correlation constraints between redundant information and the original EPC information to deduce and correct errors generated during transmission, directly achieving forward error correction for channel errors. Compared to the traditional RFID system's mechanism of retransmission upon error, this step reduces the number of retransmissions after the initial data read failure through autonomous error correction, thereby directly reducing read latency and improving system throughput.

[0103] S14: Perform cyclic redundancy check on the standard EPC information. If the check passes, upload the standard EPC information to the upper layer application. If the check fails, re-trigger the interaction process.

[0104] It should be noted that Cyclic Redundancy Check (CRC) is a hash function verification method based on polynomial operations. By calculating the CRC check value of the data, it determines whether errors have occurred during the transmission and processing of the data. It has the characteristics of high error detection rate and low computational complexity.

[0105] Upper-layer applications refer to the terminal systems that receive and use EPC data. Re-triggering the interaction process means that when the CRC check fails, the reader / writer re-initiates the communication process with the RFID tag to reread the data.

[0106] This step calculates the CRC check value for the recovered standard EPC information and compares it with the preset check value. If the check passes, it means the data is completely correct and can be uploaded to the upper-layer application. If the check fails, it means the bit error exceeds the capability of the forward error correction, and only then will the interaction process be triggered again.

[0107] This embodiment proposes an EPC tunneling coding method to improve the reliability of RFID tag identification without modifying existing RFID hardware or the EPCglobal Gen2 communication protocol. This method features a two-layer data reliability guarantee mechanism of lightweight forward error correction coding and cyclic redundancy check. Through tunneling coding, error-correcting EPC data containing redundant information is adapted to the standard EPC field length range, achieving transparent transmission and autonomous error correction of EPC data. This method abandons the traditional RFID system's reliance on retransmission error correction. Through a collaborative process of pre-adding redundant information at the transmitting end, decoding and recovery at the receiving end, and secondary verification at the checking end, it achieves forward error correction of channel errors and reduces data reading latency by reducing the number of retransmissions. It also avoids increased costs and compatibility issues caused by modifying hardware or protocols. Ultimately, without changing the existing RFID system deployment architecture, it significantly improves the reliability of EPC tag identification and system throughput.

[0108] In one embodiment of the present invention, the lightweight forward error correction coding is polar coding, and the polar coding is only performed once when the RFID tag is first written. The polar coding process includes:

[0109] S21: Using a 96-bit standard EPC as the information source, construct an input bit vector of length 128 bits; the first 96 bits of the input bit vector are standard EPC information bits, and the last 32 bits are frozen bits that are fixed to zero. The frozen bits are redundant information.

[0110] That is, construct the input bit vector as The first 96 bits are EPC information bits, and the last 32 bits are freeze bits (fixed to 0).

[0111] S22: Construct the polarization generation matrix.

[0112] Let the generating matrix be... .

[0113] S23: Perform matrix multiplication on the input bit vector and the polarization generation matrix to obtain 128-bit redundant error correction EPC data; the 128-bit polarization EPC data is the redundant error correction EPC data.

[0114] That is, perform matrix multiplication. , obtain code This is denoted as Polar-EPC, and the 128-bit Polar-EPC is then stored in the tag's EPC area. It should be noted that the encoding is performed only once by the reader during the initial write operation; subsequent tags will not repeat this calculation.

[0115] This embodiment proposes introducing redundant encapsulation at the EPC data level, so that the original EPC information forms a redundant protection structure (Polar-EPC) after polar coding. Polar-EPC is completely consistent with the standard EPC frame format at the physical layer, but has forward error correction capability at the logical layer. This is equivalent to building a "data tunnel" within the original EPC field to resist channel noise and interference. This embodiment is the first to propose applying a "tunneling" structure to RFID EPC transmission, achieving data self-protection.

[0116] Furthermore, this embodiment proposes a lightweight implementation method of "offline encoding + standard reading" at the tag end. That is, all encoding work is completed by the reader during the writing phase, generating a Polar-EPC and writing it to the tag's storage area. During the reading phase, the tag does not perform real-time encoding; it only needs to transmit the stored content according to the EPC field. The entire communication process does not modify the EPC Gen2 protocol format, nor does it increase the number of tag logic gates, achieving a "zero hardware modification, zero protocol modification" error correction scheme. This is a key point regarding the engineering feasibility of this invention.

[0117] In a further embodiment of the present invention, the polarization generation matrix is:

[0118]

[0119] In the formula, It is an N×N dimensional generating matrix. , It is the basic kernel matrix, and , For Kronecker exponentiation, This represents the number of operations performed by the Kronecker exponentiation.

[0120] In one embodiment of the present invention, the decoding operation process includes:

[0121] S31: Demodulate the 128-bit polarized EPC data to obtain the log-likelihood ratio of each bit.

[0122] Demodulation refers to the process of converting a received radio frequency analog signal into a bit stream or probability value in the digital domain. The log-likelihood ratio (LLR) is a quantitative parameter that measures the probability of a bit value and is used to characterize the confidence that each bit is 0 or 1 after demodulation.

[0123] S32: According to the polar coding freeze bit construction rules, the position of the corresponding freeze bit in the demodulated data is forcibly set to zero.

[0124] S33: Based on the log-likelihood ratio, perform SC decoding recursive operation bit by bit to obtain the estimated information bit sequence.

[0125] Perform bitwise SC (Successive Elimination) decoding recursive operations:

[0126] or ;

[0127] In the formula, To estimate the log-likelihood ratio for the i-th information bit. and The two log-likelihood ratios obtained from the preceding decoding are: For the preceding estimated information bits of the completed judgment, f and This is the polarization function.

[0128] During the operation, the polarization functions f and g work together to make bit-by-bit decisions. Function f is used to merge adjacent bit pairs and outputs the merged LLR value to improve bit reliability. Function g is used to perform recursive calculations based on the values ​​of the decided bits, using the decision result of the previous bit as the calculation condition for the next bit. At the same time, the known value of the frozen bit is directly used as a fixed condition in the recursion without additional decision-making. Finally, a 128-bit estimated information bit sequence containing 96 information bits and 32 frozen bits is generated. .

[0129] S34: Remove the frozen bits from the estimated information bit sequence to recover the 96-bit standard EPC information.

[0130] Based on the polar coding freeze bit construction rules, the last 32 bits are determined as the freeze bit positions, and these redundant bits without information carrying function are removed, leaving only the 96 information bits that carry the item identification information, thereby restoring the original EPC information that conforms to the EPCglobal Gen2 standard.

[0131] The decoding scheme in this embodiment can effectively use frozen bits as anchor points to repair random errors, thereby significantly reducing the bit error rate.

[0132] To further improve decoding efficiency and real-time performance, this invention optimizes and improves the SC decoding algorithm. It employs a lookup table method and integer approximation to calculate the log-likelihood ratio (LLR), replacing traditional floating-point arithmetic and significantly reducing the computational complexity and hardware overhead of the decoding process. Specifically, the results of the polarization functions f and g are pre-stored in a lookup table. During decoding, there is no need to calculate the function values ​​in real time; the results can be quickly obtained by looking up the table based on the preceding LLR value. Simultaneously, the LLR value is approximated using an 8-bit integer, replacing the traditional 32-bit floating-point representation. This reduces storage resource consumption and computational latency, keeping the decoding time of the 128-bit Polar-EPC within 1 millisecond, fully meeting industrial real-time requirements. Furthermore, this invention introduces an early termination mechanism during decoding. When decoding reaches a certain stage, and the constraint of the frozen bits confirms that subsequent bits are error-free, the decoding operation can be terminated early, further improving decoding efficiency and reducing the computational overhead of the reader / writer.

[0133] In one embodiment of the present invention, the interaction process follows the EPCglobal Gen2 standard, and redundant error correction EPC data is carried in the communication frame to realize the interaction process. The structure of the communication frame includes:

[0134] The field includes a preamble, a protocol control field, a redundancy correction EPC data field, and a CRC field, wherein the content of the redundancy correction EPC data field is the redundancy correction EPC data.

[0135] All protocol commands in the interaction process remained unchanged.

[0136] Specifically, this embodiment maintains the EPCglobal Gen2 standard frame structure unchanged, namely: Preamble + PC (Protocol Control Field) / XPC (Extended Protocol Control) field + EPC field (Polar-EPC) + CRC field. The Polar-EPC length is 128 bits, consistent with the maximum EPC length of the original protocol, without disrupting the reader's packet length identification mechanism. Therefore, the system is fully compatible at the protocol layer, and all commands (Query, ACK, Read, Write, Req_RN) require no modification.

[0137] The entire interaction process is as follows:

[0138] (1) The reader issues a Query command;

[0139] (2) The label returns RN16;

[0140] (3) The reader sends an ACK;

[0141] (4) The tag sends the EPC field, where EPC is Polar-EPC;

[0142] (5) After receiving the data, the reader performs polarization decoding to restore the original EPC.

[0143] If the CRC verification passes, the reader submits the result to the upper-layer application (such as an asset management system). If the verification fails, a new request for reading is made, without requiring any modification to the tag.

[0144] This embodiment proposes an "EPC storage area redundancy extension utilization" mechanism. Leveraging the fact that most commercial RFID chips support 128 bits (or longer) in their EPC storage area, the original 96-bit EPC information is extended and encapsulated into 128-bit redundant polarized data without altering the chip architecture, enabling error correction information embedding. This utilization method fully exploits the unused storage space of existing chips, transforming what was originally "wasted storage redundancy" into "channel protection redundancy," representing a significant engineering innovation of this invention.

[0145] This embodiment also features protocol transparency and full compatibility. The packet structure, field positions, and command timing of Polar-EPC during reader-tag interaction are consistent with the EPC Gen2 standard. The original "preamble + PC / XPC + EPC + CRC" frame structure remains unchanged. Even after Polar-EPC replaces the EPC field content, it can still be recognized by existing systems. This design of "physical layer enhancement with protocol layer transparency" achieves a comprehensive advantage of compatibility, low cost, and direct deployment.

[0146] This embodiment also proposes an integrated detection-error correction data verification mechanism. At the reader / writer end, after recovering the EPC through polarization decoding, it is then compared with the original frame's CRC for consistency, forming a closed-loop logic of "decoding → verification → confirmation." This mechanism enables automatic error correction and reliable confirmation while maintaining the original CRC framework. This mechanism significantly reduces the number of rereads and lowers latency.

[0147] In one embodiment of the present invention, the decoding operation is implemented through a software module or a hardware module on the reader / writer side, specifically as follows:

[0148] The software module is a decoding module added to the reader firmware; the decoding module is used to complete the decoding operation by using a lookup table method and an integer approximation of the log-likelihood ratio.

[0149] For example, a Polar decoding module can be added to the existing reader firmware, using lookup tables and integer approximation LLR calculations to reduce CPU load. Tests show that 128-bit Polar decoding can be completed in sub-milliseconds on a 32-bit ARM processor, meeting real-time requirements.

[0150] The hardware module is a decoder built on an FPGA with a parallel pipeline structure. The decoder's decoding depth matches the length of the redundant error correction EPC data. The bit path uses the Min-Sum approximation algorithm to reduce the number of multipliers. It is connected to the original reader / writer system through an AXI bus to realize the streaming input and output of data during the decoding process, thereby completing the decoding operation.

[0151] For example, the SC decoder can be implemented on an FPGA using a parallel pipelined architecture. The decoding depth is 128, and the bit path employs a Min-Sum approximation to reduce the number of multipliers. It is connected to the original system via an AXI bus to achieve streaming data input and output.

[0152] The frozen bit table and generator matrix are loaded from the firmware when the system is powered on, supporting multiple bitrate configurations (e.g., 96 / 128, 96 / 144, etc.).

[0153] This embodiment introduces a polarization decoding module (an integrity verification module can also be added) into the reader / writer. This module, which can be implemented in software or firmware, is used to identify the Polar-EPC format and recover the original EPC. The module is compatible with existing protocol control units and CRC detection logic, and can be deployed through firmware upgrades or plug-and-play module integration without modifying the RF front-end or timing logic. This structure represents a key system-level innovation for realizing tunneled communication.

[0154] Both software and hardware modules can be flexibly selected according to the needs of actual application scenarios, offering strong flexibility and adaptability. The software module implementation requires no modification to the reader's hardware structure; decoding functionality can be added simply through firmware upgrades, resulting in extremely low cost. It is suitable for upgrading existing RFID systems, such as logistics warehousing and retail, where real-time requirements are relatively low. The hardware module implementation utilizes an FPGA parallel pipeline structure, resulting in faster decoding speeds, stronger real-time performance, and superior anti-interference capabilities. It is suitable for complex scenarios with extremely high real-time and reliability requirements, such as industrial manufacturing and steel smelting. Furthermore, the decoding module of this invention supports multiple code rate configurations, allowing flexible adjustment of the length of redundant information based on changes in the channel environment. When the channel environment is favorable (low error rate), a lower redundancy code rate (e.g., 96 / 112) can be used to reduce redundancy overhead; when the channel environment is unfavorable (high error rate), a higher redundancy code rate (e.g., 96 / 144) can be used to improve error correction capabilities, achieving a dynamic balance between error correction performance and system overhead. Meanwhile, the decoding module also has an adaptive recognition function, which can automatically distinguish whether the tag stores standard EPC data or redundant error correction EPC data. For tags storing standard EPC data, the decoding module does not perform decoding operations, but directly uploads the data to the upper layer application, further improving the system's compatibility.

[0155] In one embodiment of the present invention, redundant error correction EPC data is written into the EPC or User storage area of ​​the RFID tag.

[0156] In one embodiment of the present invention, the lightweight forward error correction coding is: low-density parity-check code, BCH code, short block convolutional code, or polar coding.

[0157] In addition to polar codes, other lightweight forward error correction codes, such as low-density parity-check codes (LDPC), BCH codes, or short-block convolutional codes, can also be used to encode EPC information offline and store it in the tag's EPC area. As long as the encoding can be decoded at the reader end and the tag's communication protocol structure is not changed, the tunneling protection effect of EPC data can still be achieved.

[0158] Please see Figure 2In the (a) Virtual EPC Tunnel section of the diagram, in the noisy channel between the reader and the RFID tag, the original EPC is processed into a PolarEPC containing a freeze bit (redundant error correction bit), and then encapsulated into a standard EPC data packet. This data packet acts like a "virtual tunnel," allowing the PolarEPC with error correction function to be transmitted compatiblely within the existing RFID channel and protocol framework. In the (b) Packet Structure section, the entire data packet follows the EPCglobalGen2 standard format, including a preamble, payload, and CRC. The PC / XPC field in the payload is the protocol control module, while PolarEPC, as the core data, integrates the freeze bit and the original EPC. It is compatible with the standard EPC field length and can achieve forward error correction through the freeze bit. The overall design does not modify the existing hardware / protocol and can improve the reliability of EPC identification.

[0159] like Figure 3 and 4 As shown, Figure 3 This is a comparison graph showing the packet reception rate (reflecting transmission throughput) of the Polar EPC solution and the traditional EPC-Only solution as a function of signal-to-noise ratio (SNR). The horizontal axis represents the SNR (in dB), and the vertical axis represents the packet reception rate (in %). As can be seen, under different SNR conditions, the packet reception rate of Polar EPC (pink bars) is higher than that of EPC-Only (blue bars), especially in low SNR scenarios (such as 4.7 dB), where the advantage is more significant. This indicates that Polar EPC can improve the effective data transmission volume in noisy environments, resulting in higher system throughput. Figure 4 This is a comparison chart of the cumulative distribution function (CDF) of data reception delay for the two schemes. The horizontal axis represents the reception delay time (in seconds), and the vertical axis represents the percentage of data packets with a delay not exceeding the corresponding time. The CDF curve of Polar EPC (blue curve) is significantly to the left, and it is marked that its delay is reduced by 54.6% compared to the traditional EPC-Only scheme (red curve). This indicates that the reception delay of most data packets is shorter under the Polar EPC scheme, effectively reducing the data reading delay.

[0160] Combining the above embodiments and Figure 2-4As can be seen, in a specific embodiment of the present invention, the overall principle is as follows: Existing Radio Frequency Identification (RFID) systems typically only use Cyclic Redundancy Check (CRC) at the data link layer to detect transmission errors. CRC is an algorithm that only has error detection capabilities but no error correction functions. It generates a check sequence by performing polynomial modulo operations on the data segment, enabling the receiver to identify the occurrence of bit errors. However, when a bit error occurs, CRC can only determine "data error" and cannot locate and repair the erroneous bit. Therefore, the system can only request the tag to resend the complete EPC packet. Since passive RFID tags have extremely low power budgets (typically only tens of microwatts), retransmission operations significantly increase communication overhead and energy consumption. Especially in low signal-to-noise ratio environments, frequent bit error retransmissions lead to a decrease in system throughput and a significant increase in read latency. In addition, the physical layer of the RFID communication link typically uses Amplitude Shift Keying (ASK) or Load Modulation, which is highly susceptible to electromagnetic interference, reflection, multipath fading, and coupling instability in industrial environments. Experimental studies have shown that when the bit error rate (BER) exceeds 0.02, the successful decoding rate of EPC packets drops sharply, and the system read latency may increase tenfold or even a hundredfold. Therefore, the lack of a bit-level error correction mechanism is one of the fundamental reasons for the current insufficient reliability of EPC communication.

[0161] Therefore, this invention employs a technique to enhance the reliability of EPC transmission using polar coding. Polar coding is a forward error correction code that theoretically approximates the Shannon Capacity. Its core idea is to transform a set of originally equivalent transmission channels into a portion of almost completely reliable "good channels" and a portion of almost completely unreliable "bad channels" through a "channel polarization" process. During the coding process, information bits are allocated to the "good channels," while the "bad channels" are filled with fixed known values ​​(called frozen bits). The receiving end uses the prior information of the frozen bits to gradually recover the interfered bits during decoding, achieving efficient correction of random errors. Based on this principle, this specific implementation performs polar coding operations during the EPC data writing stage:

[0162] Using the standard EPC (96-bit) as the information sequence input to the polar encoder, a 128-bit input vector is constructed, where the first 96 bits are the EPC information bits and the last 32 bits are freeze bits (usually set to 0). After polarization transformation matrix... (in After the operation, the output codeword is the Polar-EPC data. This Polar-EPC embeds a redundant structure within the bit sequence, allowing it to be recovered at the decoding end even during channel transmission, in the event of interference or bit flipping. The Polar-EPC is then written into the tag's EPC storage area, replacing the original EPC storage.

[0163] It is worth noting that the above design does not modify the tag's communication protocol or hardware structure. For the tag, the read / write process fully complies with the EPCglobal Class-1 Generation-2 (EPC Gen2) standard: in a read operation, the tag reads the content from the EPC storage area and modulates it into a reflected signal to return it to the reader. The only difference is that the returned data is pre-polarized encoded Polar-EPC, not the original EPC. Since Polar-EPC remains a standard length (e.g., 128 bits), its frame format (including the PC / XPC field and CRC field) remains completely consistent, thus ensuring full compatibility with existing systems.

[0164] At the reader / writer end, this invention adds a Polar Decoder Module. This module uses Successive Cancellation (SC) to decode the received Polar-EPC. The decoding process is based on the Log-Likelihood Ratio (LLR) of the received signal, combined with the fixed value constraint of the frozen bits, to update and decide the conditional probability of each bit, thereby gradually reconstructing the original EPC information. The decoded EPC is received by the system and uploaded to the host computer application after CRC verification.

[0165] This architecture essentially creates a "logical tunnel" within the original EPC field, allowing the EPC data to be "wrapped" and protected by redundant bits during air transmission. These redundant bits provide error correction constraints, enabling the reader to recover the correct EPC even if it receives partially noise-contaminated codewords, thanks to the polarization decoding algorithm. In other words, the redundant structure of Polar-EPC logically establishes a "shielding layer" for the EPC signal, effectively isolating it from the effects of random interference.

[0166] Through this tunneling mechanism, the communication link, which originally relied on "detection-retransmission," gains "self-recovery" capability. Under low signal-to-noise ratio conditions (e.g., SNR below 6 dB), traditional EPC communication often suffers a sharp drop in reading efficiency due to error retransmission, while the system using the solution of this invention can still maintain a reading success rate of over 90%. Since the tag does not participate in encoding operations, the hardware cost and energy consumption of the system remain almost unchanged; and the error correction operation is concentrated in the software or firmware of the reader, thus this solution combines high reliability, low cost, strong compatibility, and engineering feasibility.

[0167] In summary, this invention achieves an EPC tunneling transmission mechanism based on redundant bits by introducing polarization coding during the EPC writing stage and implementing polarization decoding at the reader end. This mechanism enables the EPC to acquire characteristics similar to a "noise-resistant protection channel" at the physical channel layer, thus maintaining high recognition rate and low latency performance even in complex environments such as electromagnetic interference, distance attenuation, liquid absorption, or metal reflection. This provides a novel approach to achieving industrial-grade reliability for RFID systems.

[0168] In summary, this invention, by proposing the concept of "EPC tunneling," innovatively stores the polar code result as EPC data content in the tag's storage area. This eliminates the need for the tag to perform any calculations during the data transmission phase, allowing the reader to recover the original EPC through polar code decoding. This design maintains full compatibility between the protocol and hardware while providing the system with low cost, strong error correction, and high reliability. In complex scenarios such as noise, electromagnetic interference, or metal obstruction, this invention can significantly improve tag reading success rate, reduce communication latency, and enhance the availability and stability of RFID systems in industrial IoT environments.

[0169] Furthermore, in some applications, the encoding and decoding functions can be integrated into the reader / writer, with the reader / writer completing the "EPC polarization encapsulation" and "decoding recovery" steps on the host computer side, while the tag itself still operates in read-only mode. This type of solution is suitable for systems with small tag capacity or limited writing processes, and it can still achieve the goal of improving channel anti-interference capabilities.

[0170] The above embodiments of the present invention take the extension of 96-bit EPC to 128-bit Polar-EPC as an example, but different redundancy ratios (such as 112-bit, 144-bit, etc.) can also be set according to application requirements, or a multi-segment block coding method can be adopted to balance redundancy overhead and error correction performance.

[0171] In summary, although several alternative solutions may exist in terms of encoding algorithm type, redundancy ratio, or implementation location, these variations all belong to the same technical concept: improving transmission reliability by introducing redundancy at the EPC data layer without changing the protocol structure and hardware. Therefore, these alternative solutions should all be considered equivalent technical solutions or reasonable variations of this invention.

[0172] Based on the same inventive concept, this application also provides an EPC tunneling coding system for improving the reliability of RFID tag identification, which implements the aforementioned EPC tunneling coding method for improving the reliability of RFID tag identification. The solution provided by this system is similar to the implementation scheme described in the above method. Therefore, the specific limitations in the embodiments of the EPC tunneling coding system for improving the reliability of RFID tag identification provided below can be found in the limitations of the EPC tunneling coding method for improving the reliability of RFID tag identification described above, and will not be repeated here.

[0173] Please see Figure 5 This invention also provides an EPC tunneling coding system to improve the reliability of RFID tag identification, comprising:

[0174] The encoding unit is used to perform lightweight forward error correction coding on the standard EPC information. By introducing redundant information into the standard EPC information, redundant error-corrected EPC data containing a redundant protection structure is constructed. The redundant information is used to provide error correction constraints for decoding and recovering the standard EPC information.

[0175] The writing unit is used to write redundant error correction EPC data into the RFID tag; the length of the redundant error correction EPC data is within the range of EPC field length specified in the EPCglobal Gen2 standard.

[0176] The decoding unit is used to perform an interaction process between the reader and the RFID tag, so that the reader receives redundant error correction EPC data and performs a decoding operation corresponding to the lightweight forward error correction code, and recovers the standard EPC information using the redundant information.

[0177] The verification unit is used to perform cyclic redundancy verification on the standard EPC information. If the verification passes, the standard EPC information is uploaded to the upper-layer application; if the verification fails, the interaction process is retried.

[0178] Furthermore, the lightweight forward error correction coding is polar coding, and polar coding is only performed once when the RFID tag is first written. The polar coding process includes:

[0179] Using a 96-bit standard EPC as the information source, a 128-bit input bit vector is constructed. The first 96 bits of the input bit vector are standard EPC information bits, and the last 32 bits are frozen bits that are fixed to zero. The frozen bits are redundant information.

[0180] Construct the polarization generation matrix;

[0181] The input bit vector is multiplied by the polarization generation matrix to obtain 128-bit redundant error correction EPC data; the 128-bit polarization EPC data is the redundant error correction EPC data.

[0182] Furthermore, the polarization generation matrix is:

[0183]

[0184] In the formula, It is an N×N dimensional generating matrix. It is the basic kernel matrix, and , For Kronecker exponentiation, This represents the number of operations performed by the Kronecker exponentiation.

[0185] Furthermore, the decoding process includes:

[0186] Demodulate the 128-bit polarized EPC data to obtain the log-likelihood ratio of each bit.

[0187] According to the polar coding freeze bit construction rules, the position of the corresponding freeze bit in the demodulated data is forcibly set to zero;

[0188] Based on the log-likelihood ratio, perform SC decoding recursive operation bit by bit to obtain the estimated information bit sequence;

[0189] By removing the frozen bits from the estimated information bit sequence, the 96-bit standard EPC information is recovered.

[0190] Furthermore, the interaction process follows the EPCglobal Gen2 standard. Redundant error-correcting EPC data is carried in communication frames to implement the interaction process. The structure of the communication frame includes:

[0191] The field includes a preamble, a protocol control field, a redundancy correction EPC data field, and a CRC field, wherein the content of the redundancy correction EPC data field is the redundancy correction EPC data.

[0192] All protocol commands in the interaction process remained unchanged.

[0193] Furthermore, the decoding operation is implemented through software or hardware modules on the reader / writer side, specifically as follows:

[0194] The software module is a decoding module added to the reader firmware; the decoding module is used to complete the decoding operation by using a lookup table method and an integer approximation of the log-likelihood ratio.

[0195] The hardware module is a decoder built on an FPGA with a parallel pipeline structure. The decoder's decoding depth matches the length of the redundant error correction EPC data. The bit path uses the Min-Sum approximation algorithm to reduce the number of multipliers. It is connected to the original reader / writer system through an AXI bus to realize the streaming input and output of data during the decoding process, thereby completing the decoding operation.

[0196] Furthermore, redundant error correction EPC data is written into the EPC or User storage area of ​​the RFID tag.

[0197] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the system can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0198] Reference Figure 6 The present invention also provides a computer device, including: a memory and a processor, and a computer program stored in the memory. When the computer program is executed on the processor, it implements the EPC tunneling coding method for improving the reliability of RFID tag identification as described in any of the above methods.

[0199] The computer device may be a desktop computer, laptop, handheld computer, or cloud server, etc. This computer device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that... Figure 6 The examples of computer devices are merely examples and do not constitute a limitation on computer devices. They may include more or fewer components than shown in the illustration, or combinations of certain components, or different components. For example, they may also include input / output devices, network access devices, etc.

[0200] The processor referred to can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0201] In some embodiments, the memory may be an internal storage unit of the computer device, such as a hard drive or RAM. In other embodiments, the memory may be an external storage device of the computer device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory may include both internal and external storage units of the computer device. The memory is used to store the operating system, applications, boot loader, data, and other programs, such as the program code of the computer program. The memory can also be used to temporarily store data that has been output or will be output.

[0202] This invention also provides a computer-readable storage medium storing a computer program thereon. When the computer program is run by a processor, it implements the EPC tunneling coding method for improving the reliability of RFID tag identification as described in any of the above methods.

[0203] In this embodiment, if the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0204] This invention provides a computer program product, including a computer program that, when executed by a processor, implements the EPC tunneling coding method for improving the reliability of RFID tag identification as described in any of the above methods.

[0205] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0206] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0207] In the embodiments disclosed in this application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0208] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An EPC tunneling encoding method for improving the identification reliability of an RFID tag, characterized in that, Includes the following steps: Lightweight forward error correction coding is performed on the standard EPC information. By introducing redundant information into the standard EPC information, redundant error correction EPC data containing a redundancy protection structure is constructed. The redundant information is used to provide error correction constraints for decoding and recovering the standard EPC information. The redundant error correction EPC data is written into the RFID tag; the length of the redundant error correction EPC data is within the range of EPC field length specified in the EPCglobalGen2 standard. The reader interacts with the RFID tag to receive the redundant error correction EPC data and perform a decoding operation corresponding to the lightweight forward error correction code, thereby recovering the standard EPC information using the redundant information. Cyclic redundancy check is performed on the standard EPC information. If the check passes, the standard EPC information is uploaded to the upper-layer application. If the check fails, the interaction process is retried.

2. The EPC tunneling coding method for improving the reliability of RFID tag identification according to claim 1, characterized in that, The lightweight forward error correction coding is polar coding, and the polar coding is only performed once when the RFID tag is first written. The polar coding process includes: Using a 96-bit standard EPC as the information source, an input bit vector of length 128 bits is constructed; the first 96 bits of the input bit vector are standard EPC information bits, and the last 32 bits are frozen bits that are fixed to zero, and the frozen bits are the redundant information. Construct the polarization generation matrix; The input bit vector is multiplied by the polarization generation matrix to obtain 128-bit redundant error correction EPC data; the 128-bit polarization EPC data is the redundant error correction EPC data.

3. The EPC tunneling coding method for improving the reliability of RFID tag identification according to claim 2, characterized in that, The polarization generation matrix is: In the formula, It is an N×N dimensional generating matrix. It is the basic kernel matrix, and , For Kronecker exponentiation, This represents the number of operations performed by the Kronecker exponentiation.

4. The EPC tunneling coding method for improving the reliability of RFID tag identification according to claim 2, characterized in that, The decoding operation process includes: The 128-bit polarized EPC data is demodulated to obtain the log-likelihood ratio of each bit. According to the polar coding freeze bit construction rules, the position of the corresponding freeze bit in the demodulated data is forcibly set to zero; Based on the log-likelihood ratio, perform SC decoding recursive operation bit by bit to obtain the estimated information bit sequence; Remove the frozen bits from the estimated information bit sequence to recover the 96-bit standard EPC information.

5. The EPC tunneling coding method for improving the reliability of RFID tag identification according to claim 1, characterized in that, The interaction process follows the EPCglobal Gen2 standard. The redundant error correction EPC data is carried in a communication frame to implement the interaction process. The structure of the communication frame includes: The field includes a preamble, a protocol control field, a redundancy correction EPC data field, and a CRC field, wherein the content of the redundancy correction EPC data field is the redundancy correction EPC data. All protocol commands in the interaction process remain unchanged.

6. The EPC tunneling coding method for improving the reliability of RFID tag identification according to claim 1, characterized in that, The decoding operation is implemented through a software or hardware module on the reader / writer side, specifically as follows: The software module is a decoding module added to the reader firmware; the decoding module is used to complete the decoding operation by using a lookup table method and an integer approximation of the log-likelihood ratio. The hardware module is a decoder built on an FPGA with a parallel pipeline structure. The decoder's decoding depth matches the length of the redundant error correction EPC data. The bit path uses the Min-Sum approximation algorithm to reduce the number of multipliers. It is connected to the original reader / writer system via an AXI bus to realize the streaming input and output of data during the decoding process, thereby completing the decoding operation.

7. The EPC tunneling coding method for improving the reliability of RFID tag identification according to claim 1, characterized in that, The redundant error correction EPC data is written into the EPC or User storage area of ​​the RFID tag.

8. An EPC tunneling coding system for improving the reliability of RFID tag identification, characterized in that, include: The encoding unit is used to perform lightweight forward error correction coding on the standard EPC information. By introducing redundant information into the standard EPC information, redundant error correction EPC data containing a redundancy protection structure is constructed. The redundant information is used to provide error correction constraints for decoding and recovering the standard EPC information. A writing unit is used to write the redundant error correction EPC data into an RFID tag; the length of the redundant error correction EPC data is within the range of EPC field length specified in the EPCglobal Gen2 standard. The decoding unit is used to perform an interaction process with the RFID tag through the reader, so that the reader receives the redundant error correction EPC data and performs a decoding operation corresponding to the lightweight forward error correction code, and recovers the standard EPC information using the redundant information. The verification unit is used to perform cyclic redundancy verification on the standard EPC information. If the verification passes, the standard EPC information is uploaded to the upper-layer application. If the verification fails, the interaction process is retried.

9. A computer device, characterized in that, The device includes a processor and a memory: The memory is used to store computer programs and send the instructions of the computer programs to the processor; The processor executes, according to the instructions of the computer program, an EPC tunneling coding method for improving the reliability of RFID tag identification as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements an EPC tunneling coding method for improving the reliability of RFID tag identification as described in any one of claims 1-7.

Images