Integrated thermal management and parallel interconnect humanoid robot data storage module and fabrication process

Abstract

The application provides an integrated thermal management and parallel interconnection humanoid robot data storage module and a preparation process, and relates to the technical field of humanoid robot special electronic module integration. The integrated thermal management and parallel interconnection humanoid robot data storage module and the preparation process comprise the following steps: based on the comprehensive requirements of high thermal conductivity, structural stability and parallel interconnection compatibility of the humanoid robot data storage module, a metal matrix composite material is selected and combined with a ceramic material to form a substrate; a high-thermal-conductivity composite substrate is prepared by using a laminated sintering process; and a heat diffusion layer structure is preset in the substrate to improve the overall heat conduction efficiency. By constructing the high-thermal-conductivity composite substrate and presetting the heat diffusion structure in the substrate, the overall heat conduction efficiency of the substrate is significantly improved, which lays a foundation for subsequent heat dissipation channels; a metallized microchannel is formed in the substrate by using a laser microprocessing and electrochemical deposition combined process, a high-efficiency longitudinal heat dissipation path is established, and the heat generated by high-power-density chips is effectively led out.

Description

Technical Field

[0001] This invention relates to the field of electronic module integration technology for humanoid robots, specifically to a humanoid robot data storage module integrating thermal management and parallel interconnection, and its manufacturing process. Background Technology

[0002] The field of integrated electronic module technology for humanoid robots primarily focuses on solving core issues such as high-density packaging, efficient heat dissipation, resistance to mechanical stress interference, and high-speed data interaction of electronic functional units within the complex internal structure of humanoid robots. This field involves the adaptability design of electronic modules to the robot's joints and torso structure within a limited space, emphasizing that thermal management solutions must address localized high-power-density heat generation while ensuring signal integrity of high-speed interconnects in dynamic bending and vibration environments. Specifically, the integrated thermal management and parallel interconnect humanoid robot data storage module and its manufacturing process refer to an electronic module and its manufacturing method specifically developed for humanoid robots that integrates high-bandwidth data storage functionality with active heat dissipation mechanisms and high-speed signal transmission channels in a three-dimensional manner.

[0003] Existing technologies often employ a separate design approach to address the internal heat dissipation and high-speed signal transmission requirements of electronic modules. The heat dissipation structure and signal wiring layer are laid out independently, occupying additional space and increasing the overall thickness and weight of the module, making it difficult to meet the compact space requirements of humanoid robot joints. The lack of coordinated planning between thermal management paths and signal transmission channels leads to mutual interference between heat accumulation areas and high-speed interconnects, causing signal integrity degradation or localized overheating. The layout of memory chips does not adequately consider power consumption differences; the concentrated distribution of high-power chips exacerbates localized temperature rise problems, affecting system stability. The packaging structure often uses rigid materials, which are unable to effectively absorb the mechanical stress generated by joint bending, vibration, and thermal expansion and contraction during movement, easily leading to solder joint cracking or circuit breakage. The physical connection between the module and the robot skeleton only achieves electrical fixation, failing to utilize the thermal conductivity of the metal skeleton to construct auxiliary heat dissipation paths, thus wasting the system's heat dissipation potential. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a humanoid robot data storage module integrating thermal management and parallel interconnection, as well as its manufacturing process. This solves the problem that existing technologies often employ a separate design approach when dealing with the internal heat dissipation and high-speed signal transmission requirements of electronic modules. The heat dissipation structure and signal wiring layer are independently laid out, occupying extra space, increasing the overall thickness and weight of the module, and making it difficult to meet the compact space requirements of humanoid robot joints.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a humanoid robot data storage module integrating thermal management and parallel interconnection, and its manufacturing process, comprising the following steps:

[0006] S1: Based on the comprehensive requirements of humanoid robot data storage module for high thermal conductivity, structural stability and parallel interconnect compatibility, a metal matrix composite material and a ceramic material are selected to form a substrate. A high thermal conductivity composite substrate is prepared by lamination sintering process, and a heat diffusion layer structure is preset inside the substrate to improve the overall heat conduction efficiency.

[0007]

[0008] in, Indicates the overall thermal conductivity. The thermal conductivity of the material. This represents the cross-sectional area of ​​the heat conduction channel. For temperature difference, This is the length of the heat conduction path;

[0009] S2: Based on the high thermal conductivity composite substrate layer generated by S1, a vertically penetrating microchannel structure is formed inside the substrate using laser micromachining technology. Subsequently, a high thermal conductivity metal layer is deposited on the inner wall of the microchannel using electrochemical deposition technology, thereby constructing a vertical microchannel heat dissipation network for rapid heat removal from the chip.

[0010] S3: Based on the vertical microchannel heat dissipation substrate structure generated by S2, a low dielectric constant insulating dielectric layer is introduced on its surface, and a multi-channel parallel interconnect redistribution layer is constructed through photolithography and metal deposition processes, so that the parallel interconnects and the heat dissipation channels below are spatially coordinated to reduce signal delay and crosstalk.

[0011] S4: Based on the parallel interconnect redistribution heat dissipation substrate generated by S3, various types of data storage chips are heterogeneously mounted according to power consumption levels using flip-chip bonding technology, and the signal terminals of each memory chip are connected to the parallel interconnect redistribution layer in a one-to-one correspondence, thereby forming a high-bandwidth memory chip array structure.

[0012] S5: Parallel interconnect unit of heterogeneous memory chip generated based on S4. A phase change thermal conductive material layer is introduced between the memory chip and the subsequent packaging layer. Through low temperature coating and curing process, it can absorb and release heat when the operating temperature changes, and at the same time buffer the impact of thermal stress on the chip and interconnect structure.

[0013]

[0014] in, This refers to the amount of heat transferred during the phase change heat conduction process. For the quality of phase change materials, The latent heat of phase change materials, For temperature difference;

[0015] S6: Based on the phase change thermally conductive buffer storage structure generated in S5, a vertical interconnect channel is formed through the storage chip, the phase change thermally conductive layer and the parallel interconnect layer using a vertical through-hole processing technology. The vertical interconnect channel is precisely aligned in space with the vertical microchannel heat dissipation network formed in step 2 to achieve synchronous transmission of signal and heat.

[0016] S7: Based on the thermal signal generated by S6, a vertical interconnect structure is coordinated and a flexible polymer encapsulation material is introduced around it. A stress relief layer is formed through a molding encapsulation process to adapt to the bending, impact and thermal expansion and contraction generated by the humanoid robot during movement, thereby improving the mechanical reliability of the storage module.

[0017] S8: Based on the flexible packaged storage module semi-finished product generated by S7, it is assembled and integrated with the humanoid robot structural components, so that the module shell and the robot skeleton form an auxiliary heat dissipation path, and complete electrical testing and thermal performance testing, and finally form an integrated data storage module that can be used for humanoid robots.

[0018] Preferably, step S1 includes the following steps:

[0019] S101: Based on the requirements of humanoid robot data storage module for high thermal conductivity and structural stability, metal-based materials and ceramic materials are selected as raw materials, and the two materials are designed and uniformly mixed in proportion using a material composite ratio process to obtain a composite raw material system with both high thermal conductivity and mechanical strength, thereby generating a composite substrate raw material system.

[0020] S102: Based on the composite substrate raw material system, a high temperature and high pressure molding process is adopted for lamination sintering, and an internal heat diffusion structure is formed simultaneously during the sintering process to generate a high thermal conductivity composite substrate layer.

[0021] Preferably, step S2 includes the following steps:

[0022] S201: Based on a high thermal conductivity composite substrate layer, multiple longitudinally penetrating microchannel structures are formed in the substrate along the thickness direction using laser micromachining technology to generate a longitudinal microchannel substrate matrix;

[0023] S202: Based on the aforementioned longitudinal microchannel substrate, a high thermal conductivity metal material is deposited on the inner wall of the microchannel using an electrochemical deposition process to generate a longitudinal microchannel heat dissipation substrate structure.

[0024] Preferably, step S3 includes the following steps:

[0025] S301: Based on a longitudinal microchannel heat dissipation substrate structure, a low dielectric constant insulating material is coated on its surface and a dielectric layer is formed by curing, thus generating a low dielectric insulating substrate structure.

[0026] S302: Based on the low-dielectric insulating substrate structure, a multi-channel parallel interconnect redistribution layer is constructed using photolithography and metal deposition processes to generate a parallel interconnect redistribution heat dissipation base.

[0027] Preferably, step S4 includes the following steps:

[0028] S401: Based on the parallel interconnect rewiring heat dissipation substrate, the memory chip heterogeneous layout substrate is generated by partitioning according to the power consumption level and functional type of the memory chip.

[0029] S402: Based on the heterogeneous layout substrate of the memory chips, each memory chip is fixed in its corresponding position by flip-chip bonding process to generate a heterogeneous memory chip parallel interconnection unit.

[0030] Preferably, step S5 includes the following steps:

[0031] S501: Based on the parallel interconnect unit of heterogeneous memory chips, a phase change thermal conductive material is coated on the surface of the memory chip to generate a phase change thermal conductive covering structure.

[0032] S502: Based on the phase change thermal conductive covering structure, a stable phase change thermal conductive buffer layer is formed through a curing process to generate a phase change thermal conductive buffer storage structure.

[0033] Preferably, step S6 includes the following steps:

[0034] S601: Based on the phase change thermally conductive buffer storage structure, a vertical interconnect via is formed through the storage chip, the phase change thermally conductive layer and the parallel interconnect layer by a vertical via fabrication process, thus generating a vertical interconnect via structure.

[0035] S602: Based on the vertical interconnect via structure, adjust its spatial position so that the vertical interconnect via is precisely aligned with the longitudinal microchannel heat dissipation network in space, thereby generating a thermal signal coordinated vertical interconnect structure.

[0036] Preferably, step S7 includes the following steps:

[0037] S701: Based on the thermal signal coordinated vertical interconnection structure, a flexible polymer encapsulation material is introduced on its exterior to generate a flexible encapsulation cover structure;

[0038] S702: Based on the aforementioned flexible packaging cover structure, a protective layer with stress relief function is formed using a molding packaging process to generate a semi-finished flexible packaging storage module.

[0039] Preferably, step S8 includes the following steps:

[0040] S801: Based on the semi-finished flexible packaged storage module, it is assembled with the structural components of a humanoid robot to generate a structurally integrated storage module assembly;

[0041] S802: Based on the integrated storage module component of the structure, complete the electrical performance test and thermal performance test, and generate a humanoid robot data storage module product with integrated thermal management and parallel interconnection.

[0042] Preferably, the humanoid robot data storage module integrating thermal management and parallel interconnection is characterized by including a manufacturing process for the humanoid robot data storage module integrating thermal management and parallel interconnection.

[0043] This invention provides a humanoid robot data storage module integrating thermal management and parallel interconnection, as well as its fabrication process. It offers the following advantages:

[0044] This invention significantly improves the overall thermal conductivity of the substrate by constructing a high thermal conductivity composite substrate and pre-setting a thermal diffusion structure within it, laying the foundation for subsequent heat dissipation channels. A combination of laser micromachining and electrochemical deposition is used to form metallized microchannels within the substrate, establishing an efficient vertical heat dissipation path to effectively remove heat generated by high-power-density chips. A low-dielectric layer and a parallel interconnect redistribution layer are constructed on the surface of the heat dissipation structure to achieve spatially coordinated layout of signal traces and heat dissipation channels, reducing high-speed signal transmission delay and crosstalk. Heterogeneous partitioning and flip-chip mounting are performed according to the power consumption level of the memory chip to optimize heat distribution and improve data access bandwidth. A phase change thermal conductive material is introduced. The material layer acts as a thermal buffer interface, dynamically absorbing and releasing heat to alleviate thermal stress damage to the chip and interconnect structure. Vertical via technology is used to achieve precise spatial alignment between the signal channel and the heat dissipation network, promoting the synchronous and efficient transmission of thermal energy and electrical signals. Flexible polymer material is encapsulated around the module to form a stress relief layer, enhancing the structural reliability of the module under mechanical bending, impact, and thermal expansion conditions. The module shell is assembled and integrated with the robot skeleton to form an auxiliary heat dissipation path. The system structure is fully utilized to optimize thermal management, ultimately resulting in an integrated storage module with high stability, high bandwidth, and strong environmental adaptability, meeting the real-time data processing needs of humanoid robots. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the main steps of the present invention;

[0046] Figure 2 This is a detailed schematic diagram of S1 of the present invention;

[0047] Figure 3 This is a detailed schematic diagram of S2 of the present invention;

[0048] Figure 4 This is a detailed schematic diagram of S3 of the present invention;

[0049] Figure 5 This is a detailed schematic diagram of S4 of the present invention;

[0050] Figure 6This is a detailed schematic diagram of S5 of the present invention;

[0051] Figure 7 This is a detailed schematic diagram of S6 of the present invention;

[0052] Figure 8 This is a detailed schematic diagram of S7 of the present invention;

[0053] Figure 9 This is a detailed schematic diagram of S8 of the present invention. Detailed Implementation

[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] Example:

[0056] like Figure 1-9 As shown, this embodiment of the invention provides a humanoid robot data storage module integrating thermal management and parallel interconnection, and its manufacturing process, including the following steps:

[0057] S1: Based on the comprehensive requirements of humanoid robot data storage module for high thermal conductivity, structural stability and parallel interconnect compatibility, a metal matrix composite material and a ceramic material are selected to form a substrate. A high thermal conductivity composite substrate is prepared by lamination sintering process, and a heat diffusion layer structure is preset inside the substrate to improve the overall heat conduction efficiency.

[0058]

[0059] in, Indicates the overall thermal conductivity. The thermal conductivity of the material. This represents the cross-sectional area of ​​the heat conduction channel. For temperature difference, This is the length of the heat conduction path;

[0060] S2: Based on the high thermal conductivity composite substrate layer generated by S1, a vertically penetrating microchannel structure is formed inside the substrate using laser micromachining technology. Subsequently, a high thermal conductivity metal layer is deposited on the inner wall of the microchannel using electrochemical deposition technology, thereby constructing a vertical microchannel heat dissipation network for rapid heat removal from the chip.

[0061] S3: Based on the vertical microchannel heat dissipation substrate structure generated by S2, a low dielectric constant insulating dielectric layer is introduced on its surface, and a multi-channel parallel interconnect redistribution layer is constructed through photolithography and metal deposition processes, so that the parallel interconnects and the heat dissipation channels below are spatially coordinated to reduce signal delay and crosstalk.

[0062] S4: Based on the parallel interconnect redistribution heat dissipation substrate generated by S3, various types of data storage chips are heterogeneously mounted according to power consumption levels using flip-chip bonding technology, and the signal terminals of each memory chip are connected to the parallel interconnect redistribution layer in a one-to-one correspondence, thereby forming a high-bandwidth memory chip array structure.

[0063] S5: Parallel interconnect unit of heterogeneous memory chip generated based on S4. A phase change thermal conductive material layer is introduced between the memory chip and the subsequent packaging layer. Through low temperature coating and curing process, it can absorb and release heat when the operating temperature changes, and at the same time buffer the impact of thermal stress on the chip and interconnect structure.

[0064]

[0065] in, This refers to the amount of heat transferred during the phase change heat conduction process. For the quality of phase change materials, The latent heat of phase change materials, For temperature difference;

[0066] S6: Based on the phase change thermally conductive buffer storage structure generated in S5, a vertical interconnect channel is formed through the storage chip, the phase change thermally conductive layer and the parallel interconnect layer using a vertical through-hole processing technology. The vertical interconnect channel is precisely aligned in space with the vertical microchannel heat dissipation network formed in step 2 to achieve synchronous transmission of signal and heat.

[0067] S7: Based on the thermal signal generated by S6, a vertical interconnect structure is coordinated and a flexible polymer encapsulation material is introduced around it. A stress relief layer is formed through a molding encapsulation process to adapt to the bending, impact and thermal expansion and contraction generated by the humanoid robot during movement, thereby improving the mechanical reliability of the storage module.

[0068] S8: Based on the flexible packaged storage module semi-finished product generated by S7, it is assembled and integrated with the humanoid robot structural components, so that the module shell and the robot skeleton form an auxiliary heat dissipation path, and complete electrical testing and thermal performance testing, and finally form an integrated data storage module that can be used for humanoid robots.

[0069] S1 includes the following steps:

[0070] S101: Based on the requirements of humanoid robot data storage module for high thermal conductivity and structural stability, metal-based materials and ceramic materials are selected as raw materials, and the two materials are designed and uniformly mixed in proportion using a material composite ratio process to obtain a composite raw material system with both high thermal conductivity and mechanical strength, thereby generating a composite substrate raw material system.

[0071] Based on the requirements of humanoid robot data storage modules for high thermal conductivity and structural stability, metal-based materials and ceramic materials were selected as raw materials. The metal-based material was an aluminum-silicon alloy, and the ceramic material was aluminum nitride powder. The proportion of the two materials was designed and uniformly mixed through a material composite ratio process. The proportion of aluminum-silicon alloy was controlled in the range of 60% to 70%, and the proportion of aluminum nitride powder was in the range of 30% to 40%. A planetary mixer was used to mix the materials at a speed of 200 rpm for 30 minutes to obtain a composite raw material system with both high thermal conductivity and mechanical strength, thus generating a composite substrate raw material system.

[0072] S102: Based on the composite substrate raw material system, a high temperature and high pressure molding process is adopted for lamination sintering, and an internal heat diffusion structure is formed simultaneously during the sintering process to generate a high thermal conductivity composite substrate layer.

[0073] Based on the composite substrate material system, a high-temperature and high-pressure molding process is adopted using lamination sintering. The raw material is filled into the mold, and the temperature is first raised to 200 degrees Celsius at 5 degrees Celsius / minute and held for 1 hour to remove the organic binder. Then, the temperature is raised to 600 degrees Celsius at 10 degrees Celsius / minute, an axial pressure of 20 MPa is applied and held for 2 hours. During the sintering process, an internal thermal diffusion structure is formed simultaneously. The thermal diffusion structure consists of a radially distributed array of microchannels with a channel density of 80 to 100 channels per square centimeter and a channel width of 50 to 100 micrometers, generating a high thermal conductivity composite substrate layer.

[0074] S2 includes the following steps:

[0075] S201: Based on a high thermal conductivity composite substrate layer, multiple longitudinally penetrating microchannel structures are formed in the substrate along the thickness direction using laser micromachining technology to generate a longitudinal microchannel substrate matrix;

[0076] Based on a high thermal conductivity composite substrate, the substrate has a thermal conductivity ranging from 180 to 220 watts per meter per Kelvin. Laser micromachining is employed, using a 355 nm ultraviolet laser with a power range of 10 to 15 watts, a pulse frequency range of 20 to 50 kHz, and a focused spot diameter range of 30 to 50 micrometers. The substrate is processed along its thickness, with a thickness ranging from 1.0 to 1.5 millimeters, forming multiple longitudinally penetrating microchannel structures. The microchannel diameter ranges from 50 to 100 micrometers, the channel spacing ranges from 80 to 150 micrometers, and the channel depth matches the substrate thickness. During processing, the roughness of the channel sidewalls is monitored in real time, with the roughness value controlled within the range of 0.5 to 1.0 micrometers, thus generating a longitudinal microchannel substrate.

[0077] S202: Based on a vertical microchannel substrate, a high thermal conductivity metal material is deposited on the inner wall of the microchannel using an electrochemical deposition process to generate a vertical microchannel heat dissipation substrate structure.

[0078] Based on a vertical microchannel substrate, the surface cleanliness of the microchannel inner wall must meet the standards of being free of oil and oxide layers. An electrochemical deposition process is employed, with pretreatment of the substrate before deposition. The pretreatment includes alkaline ultrasonic cleaning and acid activation treatment. The pH value of the cleaning solution is controlled within the range of 9 to 11, and the activation solution is a dilute sulfuric acid solution with a concentration controlled within the range of 5% to 10%. The deposition solution uses a copper sulfate system, with a copper ion concentration range of 50 to 100 g / L and a sulfuric acid concentration range of 50 to 150 g / L. Additives include brighteners and leveling agents, with the brightener concentration controlled within the range of 0.5 to 2.0 mL / L and the leveling agent concentration controlled within the range of 1 to 5 mL / L. The current density during deposition is set within the range of 1 to 5 amperes per square decimeter, the deposition time is controlled within the range of 10 to 30 minutes, and the deposition layer thickness is controlled within the range of 5 to 20 micrometers. After deposition, the substrate is annealed under an inert atmosphere with an annealing temperature range of 150 to 250 degrees Celsius to generate a vertical microchannel heat dissipation substrate structure.

[0079] S3 includes the following steps:

[0080] S301: Based on a longitudinal microchannel heat dissipation substrate structure, a low dielectric constant insulating material is coated on its surface and a dielectric layer is formed by curing, thus generating a low dielectric insulating substrate structure.

[0081] Based on a vertical microchannel heat dissipation substrate structure, the thickness of the metal layer on the inner wall of the microchannel is between 5 and 20 micrometers, and the surface roughness is between 0.1 and 0.5 micrometers. A low dielectric constant insulating material is coated on its surface. The material is polyimide resin with a dielectric constant controlled between 3.4 and 3.8. A spin coating process is used, with the spin coating speed set between 1000 and 3000 rpm and the coating thickness controlled between 20 and 30 micrometers. A stepped curing process is used, first preheating at 80 degrees Celsius for 10 minutes, then raising the temperature to 120 degrees Celsius and holding for 30 minutes, and finally curing at 180 degrees Celsius for 60 minutes to form a dielectric layer. The uniformity deviation of the dielectric layer thickness is controlled within ±5%, and the surface is free of bubbles and cracks, thus generating a low dielectric insulating substrate structure.

[0082] S302: Based on a low-dielectric insulating substrate structure, a multi-channel parallel interconnect redistribution layer is constructed using photolithography and metal deposition processes to generate a parallel interconnect redistribution heat dissipation base.

[0083] Based on a low-dielectric insulating substrate structure, the surface flatness of the dielectric layer is required to achieve a height difference of less than 1 micrometer per centimeter. A photolithography process is employed, first coating photoresist with a thickness controlled between 1 and 3 micrometers, setting the pre-baking temperature between 90 and 100 degrees Celsius, and the baking time between 1 and 2 minutes. Exposure is performed using ultraviolet light with a wavelength range of 365 to 405 nanometers and an exposure energy range of 100 to 200 millijoules per square centimeter. Parallel interconnect patterns are then formed using a mask, with a linewidth range of 5 to 10 micrometers and a line spacing range of 5 to 15 micrometers. Development is performed using an alkaline solution with a concentration range of 0.5% to 1.0% and a development time range of 30 to 60 seconds. Next, a metal deposition process is used, with copper as the deposited metal. A seed layer is formed through sputtering with a thickness controlled between 0.1 and 0.5 micrometers. A thicker copper layer is then electroplated, with a thickness range of 1 to 2 micrometers. Finally, excess photoresist and the seed layer are removed to generate a parallel interconnect redistribution heat dissipation substrate.

[0084] S4 includes the following steps:

[0085] S401: Based on the parallel interconnect rewiring heat dissipation substrate, the memory chip heterogeneous layout substrate is generated by partitioning according to the power consumption level and functional type of the memory chip.

[0086] Based on a parallel interconnect redistribution heat dissipation substrate, the parallel interconnect line width on the substrate surface is in the range of 5 to 10 micrometers, and the line spacing is in the range of 5 to 15 micrometers. According to the power consumption classification standard of memory chips, high-power chips are defined as having a single chip power consumption greater than 2 watts, medium-power chips are 1 to 2 watts, and low-power chips are less than 1 watt. The functional types include dynamic random access memory, three-dimensional stacked NAND gate flash memory, and static random access memory. The partitioning plan adopts a grid layout strategy, dividing the substrate surface into multiple functional blocks. High-power chips are concentrated in the area close to the vertical microchannel heat dissipation network, while medium and low-power chips are dispersed in the edge area. The dynamic random access memory is aligned with the high-speed signal ports of the parallel interconnect redistribution layer, the three-dimensional stacked NAND gate flash memory is arranged in the dense data bus area, and the static random access memory is close to the processor interface. The block spacing is controlled in the range of 200 to 500 micrometers. The chip coordinate position is confirmed by an optical positioning system, and the coordinate positioning accuracy deviation is less than 10 micrometers, thus generating a heterogeneous layout substrate for memory chips.

[0087] S402: Based on a heterogeneous layout substrate for memory chips, a flip-chip bonding process is used to fix each memory chip in its corresponding position to generate a parallel interconnect unit for heterogeneous memory chips.

[0088] Based on a heterogeneous layout substrate for memory chips, the substrate surface must meet a dust-free and static-free standard. A flip-chip soldering process is employed. First, solder is printed onto the substrate pads. The solder is a tin-silver-copper alloy, with a tin content controlled between 95% and 97%, a silver content between 2% and 3%, and a copper content between 0.5% and 1.0%. The solder ball diameter is controlled between 50 and 100 micrometers. The memory chips are then precisely placed in their corresponding partition positions using a surface mount device, with a placement accuracy controlled within ±5 micrometers. After the chip solder balls are aligned with the substrate pads, the reflow soldering stage begins. The reflow temperature... The curve is divided into a preheating zone, a heat preservation zone, a reflow zone, and a cooling zone. The temperature range of the preheating zone is set at 150 to 180 degrees Celsius, and the time range is 60 to 90 seconds. The temperature range of the heat preservation zone is 180 to 220 degrees Celsius, and the time range is 30 to 60 seconds. The peak temperature range of the reflow zone is set at 240 to 250 degrees Celsius, and the time range is 10 to 20 seconds. The cooling rate is controlled at 3 to 5 degrees Celsius per second. After soldering, the void rate of the solder balls is detected by X-ray. If the void rate is less than 5%, the signal connectivity is verified by electrical testing to generate parallel interconnect units for heterogeneous memory chips.

[0089] S5 includes the following steps:

[0090] S501: Based on the parallel interconnect unit of heterogeneous memory chips, a phase change thermal conductive material is coated on the surface of the memory chip to generate a phase change thermal conductive covering structure.

[0091] Based on a parallel interconnect unit for heterogeneous memory chips, the height difference of the memory chips on the surface of this unit is controlled within ±20 micrometers. A phase change thermal conductive material is coated on the surface of the memory chips. The material is a paraffin-based composite phase change material with a phase change temperature range of 45 to 55 degrees Celsius and a thermal conductivity range of 1.5 to 2.5 watts per meter per Kelvin. The process is carried out using either dispensing or screen printing. The inner diameter of the dispensing needle is controlled within 0.2 to 0.5 millimeters, the opening size of the printing screen is set within 100 to 200 micrometers, and the coating thickness is controlled within 30 to 50 micrometers. During the coating process, the coating amount is dynamically adjusted according to the height difference of the chips. For every 10-micrometer increase in height difference, the coating amount increases by 5% to 8%. After coating, the material coverage area is greater than 95% of the chip surface area, and the edge overflow is less than 5%, thus generating a phase change thermal conductive coverage structure.

[0092] S502: Based on the phase change thermal conductive covering structure, a stable phase change thermal conductive buffer layer is formed through a curing process to generate a phase change thermal conductive buffer storage structure.

[0093] Based on the phase change thermally conductive coating structure, the coating thickness uniformity deviation is required to be less than ±10%. Through a curing process, a stepped temperature rise procedure is adopted. First, the material is preheated at 40 to 50 degrees Celsius for 10 to 15 minutes to remove the solvent. Then, the temperature is raised to 60 to 70 degrees Celsius and held for 20 to 30 minutes to achieve initial softening and flow of the material. Finally, the material is cured at 80 to 90 degrees Celsius for 40 to 60 minutes to form a stable cross-linked structure. After curing, the surface flatness of the phase change material layer is required to meet the standard of less than 5 micrometers per centimeter in height difference. There are no bubbles or delamination inside. The bonding strength with the chip and substrate interface is greater than 5 MPa per square centimeter, thus generating a phase change thermally conductive buffer storage structure.

[0094] S6 includes the following steps:

[0095] S601: Based on the phase change thermally conductive buffer storage structure, a vertical interconnect via is formed through the storage chip, the phase change thermally conductive layer and the parallel interconnect layer by a vertical via fabrication process, thus generating a vertical interconnect via structure.

[0096] Based on a phase change thermally conductive buffer memory structure, the phase change material layer thickness is between 30 and 50 micrometers, the memory chip thickness is between 100 and 150 micrometers, and the parallel interconnect layer thickness is between 1 and 2 micrometers. A vertical through-hole (VH) fabrication process is employed, using an ultraviolet laser with a wavelength range of 355 to 405 nanometers, a laser power range of 15 to 25 watts, a pulse frequency range of 20 to 50 kHz, and a focused spot diameter range of 30 to 50 micrometers. The drilling sequence is from top to bottom, penetrating the memory chip and the phase change material layer. The system employs a variable thermal conductivity layer and a parallel interconnect layer. Laser parameters are adjusted for different material layers: the chip layer uses a higher power range of 20 to 25 watts, the phase change layer uses a medium power range of 15 to 20 watts, and the interconnect layer uses a lower power range of 10 to 15 watts. The hole wall quality is monitored in real time during drilling, with the hole wall roughness controlled within the range of 0.5 to 1.0 micrometers, the hole diameter set within the range of 50 to 80 micrometers, the hole spacing controlled within the range of 100 to 150 micrometers, and the through-hole verticality deviation less than 1 degree, thus generating a vertical interconnect through-hole structure.

[0097] S602: Based on the vertical interconnect via structure, its spatial position is adjusted to make the vertical interconnect via precisely aligned with the vertical microchannel heat dissipation network in space, generating a thermal signal coordinated vertical interconnect structure.

[0098] Based on the vertical interconnect via structure, the deviation between the via position coordinates and the design value is required to be less than 10 micrometers. The spatial position is adjusted, and the actual coordinates of the current via are obtained through an optical positioning system. These coordinates are compared with the preset coordinates of the longitudinal microchannel heat dissipation network formed in step 2. When the coordinate deviation is greater than 10 micrometers, position calibration is triggered. A piezoelectric ceramic micro-displacement platform is used, with a displacement accuracy of 0.1 micrometers. The offset is compensated along the X / Y direction, with a compensation time of 5 to 10 seconds for every 10 micrometers of offset. After calibration, the spatial distance between the center of the via and the center of the microchannel is controlled within 5 micrometers, achieving spatial alignment in three dimensions. The alignment accuracy requirement is ±3 micrometers for the X / Y direction deviation and ±5 micrometers for the Z direction deviation, generating a thermal signal-coordinated vertical interconnect structure.

[0099] S7 includes the following steps:

[0100] S701: Based on the thermal signal coordinated vertical interconnection structure, a flexible polymer encapsulation material is introduced on its exterior to generate a flexible encapsulation cover structure;

[0101] Based on a thermally-coordinated vertical interconnect structure, the diameter of the vertical interconnect vias on the surface of this structure is in the range of 50 to 80 micrometers, and the spacing between the vias is in the range of 100 to 150 micrometers. A flexible polymer encapsulation material is introduced on the outside of this structure. The material is an organosilicon resin with an elastic modulus controlled in the range of 1 to 10 MPa, an elongation at break greater than 100%, and a coefficient of thermal expansion set in the range of 50 to 100 ppm per degree Celsius. Injection molding or transfer molding processes are used, with the injection temperature set in the range of 80 to 120 degrees Celsius, the injection pressure controlled in the range of 5 to 15 MPa, and the material filling speed set in the range of 10 to 50 mm per second. During the filling process, the material flow front is monitored in real time to avoid the formation of air bubbles or cavities in the encapsulation area. The material coverage thickness is controlled in the range of 0.5 to 1.0 mm. After encapsulation, the vertical interconnect structure and the chip surface are completely covered, with no material accumulation or missing material at the edges, forming a flexible encapsulation coverage structure.

[0102] S702: Based on a flexible packaging cover structure, a protective layer with stress relief function is formed by molding packaging process to generate a flexible packaging storage module semi-finished product.

[0103] Based on a flexible encapsulation cover structure, the thickness uniformity deviation of the encapsulation layer is required to be less than ±10%. A molding encapsulation process is adopted, in which the cover structure is placed in a mold cavity. The mold temperature is set between 100 and 150 degrees Celsius, the mold closing pressure is controlled between 10 and 20 MPa, and the holding pressure time is set between 3 and 8 minutes. The material softens and flows when heated in the mold cavity, completely filling the cavity gaps. After the holding pressure is completed, the material is cooled to room temperature at a rate of 1 to 3 degrees Celsius per second. After demolding, the surface of the encapsulation layer is free from warping and deformation, and there is no delamination or cracks inside. The bonding strength between the encapsulation layer and the substrate interface is greater than 3 MPa per square centimeter. The Shore hardness of the encapsulation layer is controlled between Type A 30 and 50 degrees, which can withstand repeated deformation with a bending radius of less than 5 mm, thus generating a semi-finished flexible encapsulation storage module.

[0104] S8 includes the following steps:

[0105] S801: Based on the semi-finished flexible packaged storage module, it is assembled with the structural components of a humanoid robot to generate a structurally integrated storage module assembly;

[0106] Based on a flexible encapsulated storage module semi-finished product, the surface encapsulation layer of this semi-finished product has a Shore hardness of 30 to 50 degrees (Type A) and a bending tolerance radius of less than 5 mm. It is assembled with a humanoid robot structural component. The structural component is made of aluminum alloy or titanium alloy, with a thickness ranging from 1.0 to 2.0 mm. The assembly uses a combination of mechanical fastening and thermally conductive interface materials. First, thermally conductive silicone grease with a thermal conductivity greater than 3 watts per Kelvin per meter is applied to the mounting surface of the structural component, with a coating thickness ranging from 20 to 50 micrometers. The module semi-finished product is then secured to the structural component using locating pins. Align the holes, with the locating pin diameter ranging from 2.0 to 3.0 mm and the clearance tolerance controlled at H7 / g6 grade. Then, tighten the titanium alloy bolts in stages, with the bolt diameter ranging from 3 to 5 mm and the preload ranging from 5 to 10 N·m. Apply the torque in three increments, each time increasing by 30% to 50%, with a 30-second interval between each increment. Monitor the assembly stress using a strain gauge. Stop tightening when the stress value exceeds 30% of the material's yield strength. After assembly, the gap between the module shell and the structural component contact surface is less than 30 micrometers, generating a structurally integrated storage module assembly.

[0107] S802: Based on the structurally integrated storage module component, complete the electrical performance testing and thermal performance testing, and generate a humanoid robot data storage module product with integrated thermal management and parallel interconnection.

[0108] Based on the structurally integrated storage module component, the component's assembly stress distribution uniformity deviation is required to be less than ±15%. Electrical performance testing is completed, including insulation resistance, withstand voltage testing, and signal integrity testing. The insulation resistance test applies a 500V DC voltage, requiring a resistance value greater than 100 megohms. The withstand voltage test applies a 1000V AC voltage, with a leakage current less than 1 mA. The signal integrity test uses eye diagram analysis, with a data rate greater than 5 gigabits per second, an eye diagram opening greater than 70%, and a bit error rate less than 10^-12. Thermal performance testing uses constant power loading, with a power consumption range of 1 to 5 watts. Temperature distribution is monitored using an infrared thermal imager, with a temperature rise rate less than 2 degrees Celsius per minute, a steady-state temperature not exceeding 85 degrees Celsius, a temperature difference between chips less than 5 degrees Celsius, and a thermal resistance of less than 1.5 Kelvin per watt. After testing, a humanoid robot data storage module product integrating thermal management and parallel interconnection is generated.

[0109] A humanoid robot data storage module integrating thermal management and parallel interconnection, including the manufacturing process of the humanoid robot data storage module integrating thermal management and parallel interconnection.

[0110] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A fabrication process for a humanoid robot data storage module integrating thermal management and parallel interconnection, characterized in that, Includes the following steps: S1: Based on the comprehensive requirements of humanoid robot data storage module for high thermal conductivity, structural stability and parallel interconnect compatibility, a metal matrix composite material and a ceramic material are selected to form a substrate. A high thermal conductivity composite substrate is prepared by lamination sintering process, and a heat diffusion layer structure is preset inside the substrate to improve the overall heat conduction efficiency. ； in, Indicates the overall thermal conductivity. The thermal conductivity of the material. This represents the cross-sectional area of ​​the heat conduction channel. For temperature difference, This is the length of the heat conduction path; S2: Based on the high thermal conductivity composite substrate layer generated by S1, a vertically penetrating microchannel structure is formed inside the substrate using laser micromachining technology. Subsequently, a high thermal conductivity metal layer is deposited on the inner wall of the microchannel using electrochemical deposition technology, thereby constructing a vertical microchannel heat dissipation network for rapid heat removal from the chip. S3: Based on the vertical microchannel heat dissipation substrate structure generated by S2, a low dielectric constant insulating dielectric layer is introduced on its surface, and a multi-channel parallel interconnect redistribution layer is constructed through photolithography and metal deposition processes, so that the parallel interconnects and the heat dissipation channels below are spatially coordinated to reduce signal delay and crosstalk. S4: Based on the parallel interconnect redistribution heat dissipation substrate generated by S3, various types of data storage chips are heterogeneously mounted according to power consumption levels using flip-chip bonding technology, and the signal terminals of each memory chip are connected to the parallel interconnect redistribution layer in a one-to-one correspondence, thereby forming a high-bandwidth memory chip array structure. S5: Parallel interconnect unit of heterogeneous memory chip generated based on S4. A phase change thermal conductive material layer is introduced between the memory chip and the subsequent packaging layer. Through low temperature coating and curing process, it can absorb and release heat when the operating temperature changes, and at the same time buffer the impact of thermal stress on the chip and interconnect structure. ； in, This refers to the amount of heat transferred during the phase change heat conduction process. For the quality of phase change materials, The latent heat of phase change materials, For temperature difference; S6: Based on the phase change thermally conductive buffer storage structure generated in S5, a vertical interconnect channel is formed through the storage chip, the phase change thermally conductive layer and the parallel interconnect layer using a vertical through-hole processing technology. The vertical interconnect channel is precisely aligned in space with the vertical microchannel heat dissipation network formed in step 2 to achieve synchronous transmission of signal and heat. S7: Based on the thermal signal generated by S6, a vertical interconnect structure is coordinated and a flexible polymer encapsulation material is introduced around it. A stress relief layer is formed through a molding encapsulation process to adapt to the bending, impact and thermal expansion and contraction generated by the humanoid robot during movement, thereby improving the mechanical reliability of the storage module. S8: Based on the flexible packaged storage module semi-finished product generated by S7, it is assembled and integrated with the humanoid robot structural components, so that the module shell and the robot skeleton form an auxiliary heat dissipation path, and complete electrical testing and thermal performance testing, and finally form an integrated data storage module that can be used for humanoid robots.

2. The fabrication process of the humanoid robot data storage module with integrated thermal management and parallel interconnection according to claim 1, characterized in that: S1 includes the following steps: S101: Based on the requirements of humanoid robot data storage module for high thermal conductivity and structural stability, metal-based materials and ceramic materials are selected as raw materials, and the two materials are designed and uniformly mixed in proportion using a material composite ratio process to obtain a composite raw material system with both high thermal conductivity and mechanical strength, thereby generating a composite substrate raw material system. S102: Based on the composite substrate raw material system, a high temperature and high pressure molding process is adopted for lamination sintering, and an internal heat diffusion structure is formed simultaneously during the sintering process to generate a high thermal conductivity composite substrate layer.

3. The fabrication process of the humanoid robot data storage module with integrated thermal management and parallel interconnection according to claim 1, characterized in that: S2 includes the following steps: S201: Based on a high thermal conductivity composite substrate layer, multiple longitudinally penetrating microchannel structures are formed in the substrate along the thickness direction using laser micromachining technology to generate a longitudinal microchannel substrate matrix; S202: Based on the aforementioned longitudinal microchannel substrate, a high thermal conductivity metal material is deposited on the inner wall of the microchannel using an electrochemical deposition process to generate a longitudinal microchannel heat dissipation substrate structure.

4. The fabrication process of the humanoid robot data storage module with integrated thermal management and parallel interconnection according to claim 1, characterized in that: S3 includes the following steps: S301: Based on a longitudinal microchannel heat dissipation substrate structure, a low dielectric constant insulating material is coated on its surface and a dielectric layer is formed by curing, thus generating a low dielectric insulating substrate structure. S302: Based on the low-dielectric insulating substrate structure, a multi-channel parallel interconnect redistribution layer is constructed using photolithography and metal deposition processes to generate a parallel interconnect redistribution heat dissipation base.

5. The fabrication process of the humanoid robot data storage module with integrated thermal management and parallel interconnection according to claim 1, characterized in that: S4 includes the following steps: S401: Based on the parallel interconnect rewiring heat dissipation substrate, the memory chip heterogeneous layout substrate is generated by partitioning according to the power consumption level and functional type of the memory chip. S402: Based on the heterogeneous layout substrate of the memory chips, each memory chip is fixed in its corresponding position by flip-chip bonding process to generate a heterogeneous memory chip parallel interconnection unit.

6. The fabrication process of the humanoid robot data storage module with integrated thermal management and parallel interconnection according to claim 1, characterized in that: S5 includes the following steps: S501: Based on the parallel interconnect unit of heterogeneous memory chips, a phase change thermal conductive material is coated on the surface of the memory chip to generate a phase change thermal conductive covering structure. S502: Based on the phase change thermal conductive covering structure, a stable phase change thermal conductive buffer layer is formed through a curing process to generate a phase change thermal conductive buffer storage structure.

7. The fabrication process of the humanoid robot data storage module with integrated thermal management and parallel interconnection according to claim 1, characterized in that: S6 includes the following steps: S601: Based on the phase change thermally conductive buffer storage structure, a vertical interconnect via is formed through the storage chip, the phase change thermally conductive layer and the parallel interconnect layer by a vertical via fabrication process, thus generating a vertical interconnect via structure. S602: Based on the vertical interconnect via structure, adjust its spatial position so that the vertical interconnect via is precisely aligned with the longitudinal microchannel heat dissipation network in space, thereby generating a thermal signal coordinated vertical interconnect structure.

8. The fabrication process of the humanoid robot data storage module with integrated thermal management and parallel interconnection according to claim 1, characterized in that: S7 includes the following steps: S701: Based on the thermal signal coordinated vertical interconnection structure, a flexible polymer encapsulation material is introduced on its exterior to generate a flexible encapsulation cover structure; S702: Based on the aforementioned flexible packaging cover structure, a protective layer with stress relief function is formed using a molding packaging process to generate a semi-finished flexible packaging storage module.

9. The fabrication process of the humanoid robot data storage module with integrated thermal management and parallel interconnection according to claim 1, characterized in that: S8 includes the following steps: S801: Based on the semi-finished flexible packaged storage module, it is assembled with the structural components of a humanoid robot to generate a structurally integrated storage module assembly; S802: Based on the integrated storage module component of the structure, complete the electrical performance test and thermal performance test, and generate a humanoid robot data storage module product with integrated thermal management and parallel interconnection.

10. A humanoid robot data storage module integrating thermal management and parallel interconnection, characterized in that: The manufacturing process for a humanoid robot data storage module with integrated thermal management and parallel interconnection as described in any one of claims 1-9.

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