Test circuit

Abstract

A circuit (100) for testing a DUT (104) (device under test) includes an inductor (112) coupled to a first switch (140), and the first switch (140) is coupled to a second switch (148). The circuit (100) includes a test module (108) coupled to the first switch (140) and the second switch (148). The test module (108) includes a DUT (104). The circuit (100) also includes a TVS (146) (transient voltage suppressor) coupled to the second switch (148).

Description

Technical Field

[0001] This specification relates to a circuit for determining the characteristics of a DUT (device under test). Background Technology

[0002] Electronic fuses, commonly known as electronic fuses, are resettable overcurrent protection devices used in electronic circuits. They utilize semiconductor technology to enhance control and ensure safety. Unlike conventional fuses, which permanently disconnect a circuit by melting under excessive current, electronic fuses are designed for non-destructive interruption and are resettable for multiple uses. The operation of an electronic fuse relies on components such as FETs (field-effect transistors) to monitor current flow. When the current level exceeds a predetermined limit, the electronic fuse quickly activates to disconnect the circuit, preventing damage to electronic components, overheating, or potential fire hazards.

[0003] Electronic fuses feature a resettable function, allowing for automatic or manual reactivation after tripping. Therefore, electronic fuses provide accurate current sensing for rapid response to overcurrent conditions. Additional protection features can be integrated into electronic fuses, such as overvoltage protection, undervoltage lockout, thermal shutdown, and fault indication output. The compact design of electronic fuses achieves a small footprint on printed circuit boards, facilitating integration into IC (integrated circuit) packages. Summary of the Invention

[0004] The first example relates to a circuit for determining the characteristics of a device under test (DUT), the circuit including an inductor coupled to a first switch. The first switch is coupled to a second switch. The circuit includes a test module coupled to the first switch and the second switch. The test module contains the DUT. The circuit also includes a TVS (transient voltage suppressor) coupled to the second switch.

[0005] The second example relates to a circuit for determining the characteristics of a DUT (Distributed Underlying Device). The circuit includes an inductor configured to store energy and a first switch coupled to the inductor and operable to provide a charging path for the inductor. The circuit includes a second switch coupled to the first switch. The first and second switches cooperate to control the discharge of the inductor through a first discharge path, and the second switch is operable to provide a second discharge path for the inductor in response to a timed triggering of a DUT avalanche interval. The circuit includes a TVS (Transient Voltage Suppressor) on the second discharge path. The TVS is coupled to the second switch, wherein the energy from the inductor is diverted to the TVS in response to the timed triggering of the DUT avalanche interval. The circuit includes a test module on the first discharge path, coupled to the first and second switches. The test module connects the DUT to the current output of the inductor during the DUT avalanche interval to test the current rating of the DUT.

[0006] A third example relates to a method for determining the characteristics of a digital under-conductor (DUT), wherein the DUT closes a first switch of a circuit to precharge an inductor of the circuit. The method includes opening the first switch to discharge the inductor through the DUT, thereby applying a transient fault condition within an avalanche interval of the DUT. The method further includes measuring the DUT's response to the transient fault condition and closing a second switch in response to a timed avalanche interval of the DUT to divert current from the inductor to a TVS. Attached Figure Description

[0007] Figure 1 This section describes an example of a test circuit used to measure the response to transient fault conditions provided to the DUT (Device Under Test).

[0008] Figure 2 This illustrates another example of a test circuit used to measure the response to transient fault conditions supplied to the DUT.

[0009] Figure 3 Explanation of plotting as a function of time Figure 2 A diagram illustrating the component responses of the test circuit.

[0010] Figure 4 The instructions can be used for implementation. Figure 2 An example of an NFET (n-channel field-effect transistor) in a DUT and an equivalent large-signal model of an NFET.

[0011] Figure 5A and 5B The explanation will Figure 4 The drain current ID of the NFET is plotted as a function of the drain-to-source voltage.

[0012] Figure 6A A sample graph illustrating the measured response characteristics of the NFET 400 during the DUT avalanche interval.

[0013] Figure 6B The explanation will Figure 4 The voltage of the NFET is plotted as a function of the current.

[0014] Figure 7A , 7B And 7C Explanation Display Figure 2 A diagram illustrating the measured response of the DUT to a first example of transient fault conditions during the avalanche interval of the DUT.

[0015] Figure 8A , 8B And 8C Explanation Showcase Figure 2 A diagram illustrating the measured response of the DUT to a second example of transient fault conditions during the avalanche interval of the DUT.

[0016] Figure 9A , 9B And 9C Explanation Showcase Figure 2 A diagram illustrating the measured response of the DUT to a third example of transient fault conditions during the avalanche interval of the DUT.

[0017] Figure 10A and 10B Explanation and display Figure 2 A diagram illustrating the measured response of the DUT to a fourth example of transient fault conditions during the avalanche interval of the DUT.

[0018] Figure 11A , 11B And 11C Explanation Showcase Figure 2 A graphical representation of the measured response of the DUT to a first example of a repetitive transient fault condition during avalanche intervals.

[0019] Figure 12A , 12B And 12C Explanation Showcase Figure 2 A diagram illustrating the measured response of the DUT to a second example of a repetitive transient fault condition during avalanche intervals.

[0020] Figure 13A , 13B and 13C explanation display Figure 2 A diagram illustrating the measured response of the DUT to a third example of a repetitive transient fault condition during avalanche intervals.

[0021] Figure 14 A block diagram illustrating the circuit of an electronic fuse coupled between a power source and a load is provided.

[0022] Figure 15 This section provides an example of a method used to determine the characteristics of a DUT. Detailed Implementation

[0023] This specification relates to a test circuit for determining the characteristics (e.g., operational characteristics) of a device under test (DUT), such as an electronic fuse. More specifically, in some examples, the test circuit measures the response to transient fault conditions applied to the DUT. The test circuit is used to determine the transient voltage ratings and / or current ratings of the DUT, which allows the user of the DUT to ensure that the DUT can handle voltage / current spikes during fault conditions without suffering damage.

[0024] The evaluation process begins with the pre-charging of an inductor within the test circuit. This inductor is then discharged through the DUT to simulate transient fault conditions that the DUT might encounter during normal operation, such as short circuits or overloads. The DUT's response to these simulated transient fault conditions is measured to evaluate performance and reliability.

[0025] To achieve precise control over the testing process, the circuit includes a first switch and a second switch, which are controlled to initiate the pre-charging of the inductor and allow for a precisely controlled time interval for discharging the inductor, referred to as the DUT avalanche interval. The DUT avalanche interval is designed to expose the DUT to the discharge current for a predetermined duration, thereby allowing monitoring of the voltage and current across the DUT during this DUT avalanche interval.

[0026] In response to the timed triggering of the DUT avalanche interval, a second switch closes to divert energy (more specifically, current) released from the inductor to the TVS (Transient Voltage Suppressor). Following the DUT avalanche interval, the TVS clamps the voltage across the DUT. The DUT's response to transient fault conditions is measured and recorded for subsequent analysis to determine the DUT's transient voltage and current ratings, which characterize the DUT's (e.g., an electronic fuse) ability to withstand transient voltage spikes. Therefore, in the example where the DUT is an electronic fuse, the electronic fuse's transient voltage and current ratings characterize its ability to protect downstream loads during overload and / or short-circuit conditions.

[0027] Figure 1 This describes an example of a test circuit 100 used to measure the response of a DUT 104 to transient fault conditions, such as an electronic fuse. A transient fault condition refers to an overvoltage and / or overcurrent condition supplied to the DUT 104 within a controlled time interval, referred to as the DUT avalanche interval.

[0028] Test circuit 100 includes test module 108 (or evaluation module) which includes DUT 104. Test module 108 is coupled to inductor 112. Additionally, diode 114 is coupled between inductor 112 and test module 108. Besides DUT 104, in various examples, test module 108 also includes components facilitating biasing, DUT connection, control pins, etc. More specifically, inductor 112 has a first node 116 coupled to switching node 118 of test circuit 100 and a second node 120 coupled to the positive output terminal of power supply 124, and test module 108 is coupled to switching node 118 via diode 114.

[0029] The first switch 140 is also coupled to switch node 118 and ground node 136, such that the first switch 140 is coupled in parallel with the test module 108. The anode of diode 144 is coupled to switch node 118, and the cathode of diode 144 is coupled to the second switch 148. The second switch 148 is coupled to TVS 146, such as a unidirectional TVS. The cathode of TVS 146 is coupled to the second switch 148, and the anode of TVS 146 is coupled to ground node 136.

[0030] The first switch 140 and the second switch 148 are implemented as normally open switches controlled by the controller 160. More specifically, the controller outputs signals, namely a first control signal to the first switch 140 and a second control signal to the second switch 148. In some examples, the second switch 148 is implemented using a transistor such as an NFET (N-channel field-effect transistor). In such examples, an assertion of the first control signal causes the first switch 140 to close. The closing of the first switch 140 shorts the switch node 118 to the ground node 136. A revocation assertion of the first control signal causes 140 to open, thereby decoupling the switch node 118 from the ground node 136. Additionally, an assertion of the second control signal couples the cathode of diode 144 to the cathode of TVS 146. Conversely, a revocation assertion of the second control signal causes the second switch 148 to open. The opening of the second switch 148 decouples diode 144 from TVS 146.

[0031] The controller 160 is implemented using a microcontroller or another device that provides control signals. In some examples, the controller 160 is a stand-alone device. In other examples, the controller 160 interfaces with an external system, such as a computer.

[0032] As used herein, an assertion of a signal, such as an assertion of a first control signal and a second control signal, refers to a signal state that causes the receiving device to change from an off state (e.g., a default state) to an on state (e.g., an active state). Therefore, in the example where the first switch 140 and the second switch 148 are implemented using an NFET, an assertion of the first control signal and / or the second control signal indicates a logic high (e.g., 5 V) signal output to the gate of the first switch 140 and / or the second switch 148, and a deactivation assertion of the first control signal and / or the second control signal indicates a logic low (e.g., 0 V) ​​signal output to the gate of the first switch 140 and / or the second switch 148.

[0033] Power supply 124 is a DC power supply, which responds to a power control signal ( Figure 1 The power supply 124 is labeled PCS and outputs a voltage at the second node 120 of inductor 112. In some examples, a power control signal is provided from an external system such as a computer, causing the power supply 124 to be controlled by software. In alternative examples, a power control signal is provided from a controller 160. In some examples, an assertion of the power control signal causes the power supply 124 to output an output voltage to the second node 120 of inductor 112. In some examples, the output voltage is approximately 5-20 V (e.g., 7 V). Conversely, a de-assertion of the power control signal causes the power supply 124 to stop outputting the voltage.

[0034] Test circuit 100 includes probes 164 for measuring voltage and / or current across DUT 104. In some examples, the output of probe 164 is provided to controller 160 or ADC (analog-to-digital converter). In some examples, the output (e.g., a digital value) is provided to an external system, such as a computer for storage and analysis.

[0035] During operation, the test circuit 100 has four states: (i) off state, (ii) inductor charging state, (iii) DUT avalanche state, and (iv) TVS clamping state. In the off state, the control signal output by the controller 160 is de-asserted, resulting in no current flowing through the test circuit 100. In the inductor charging state, the first switch 140 is closed and the second switch 148 is open, causing the inductor to couple to the charging path including the first switch 140. Therefore, to initiate the inductor charging state, the power control signal output to the power supply 124 and the first control signal output to the first switch 140 are asserted, and the second control signal output to the second switch 148 is de-asserted. Thus, in the charging state, the inductor 112 is charged to ramp up the stored current.

[0036] In response to reaching the desired peak level, controller 160 retracts the assertion on first switch 140, thereby opening first switch 140, and continues to retract the assertion on the second control signal, thereby keeping second switch 148 open, thus transitioning test circuit 100 to DUT avalanche state. In DUT avalanche state, the current stored in inductor 112 is rapidly discharged through a first discharge path comprising test module 108 and DUT 104, more specifically, for a controllable amount of time, referred to as the DUT avalanche interval. In other words, the inductor current discharges through DUT 104 during the DUT avalanche interval. Additionally, since both first switch 140 and second switch 148 are open, this time interval is alternatively referred to as the deadtime interval between first switch 140 and second switch 148. In this way, first switch 140 and second switch 148 cooperate to control the discharge of the inductor through the first discharge path and through DUT 104.

[0037] During the DUT avalanche interval, the voltage and / or current across DUT 104 are measured and recorded. In some examples, the voltage across DUT 104 is from about 12 V to about 100 V (e.g., from about 23-27 V in some examples), and the current across DUT 104 is in the range of from about 50 amperes (A) to about 300 A. Furthermore, the DUT avalanche interval is about 1 microsecond (μs) or less, for example, in the range of from about 100 nanoseconds (ns) to about 1 μs. The duration of the DUT avalanche interval can be adjusted based on a first timing control signal provided to the first switch 140 and a second timing control signal provided to the second switch 148. The response of DUT 104 during the DUT avalanche interval can be used to determine the reliability characteristics of DUT 104. Therefore, during the DUT avalanche interval, transient fault conditions (e.g., overvoltage and / or overcurrent) are applied to DUT 104.

[0038] In response to the timed triggering of the DUT avalanche interval, controller 160 asserts a second control signal, thereby closing second switch 148. This diverts inductor current (more generally, energy) from test module 108 to a second discharge path comprising diode 144 and TVS 146, making second switch 148 operable to provide a second discharge path for inductor 112. The closing of second switch 148 causes test circuit 100 to transition to a TVS clamped state. In the TVS clamped state, inductor current discharges across diode 144 and TVS 146, causing TVS 146 to clamp the voltage across DUT 104 at a level defined by the operating characteristics of TVS 146. More specifically, TVS 146 conducts in response to a voltage exceeding the forward voltage of diode 144 and exceeding the breakdown voltage of TVS 146, thereby clamping the voltage. Therefore, the breakdown voltage of TVS 146 defines the clamping voltage of TVS 146. During the TVS clamping state, the current stored in inductor 112 discharges to near 0 A.

[0039] In some cases, the test circuit 100 returns to the off state in response to a timed trigger TVS clamping state. In other examples, multiple DUT avalanche intervals are applied to DUT 104 to test the reliability of DUT 104. In such cases, controller 160 can re-assert and de-assert assertion control signals to power supply 124, first switch 140, and second switch 148 to transition the test circuit 100 to the inductor charging state, DUT avalanche state, and TVS clamping state. Therefore, the effects of multiple transient fault conditions (multiple instances of DUT avalanche intervals) can be measured and recorded. Furthermore, the architecture of the test circuit 100, particularly the first switch 140 and second switch 148, allows for precise control of the magnitude of the fault conditions and the duration of the DUT avalanche intervals to determine the transient voltage and current ratings of DUT 104. In this way, DUT 104 (e.g., an electronic fuse) can be confidently deployed in other circuits that depend on the specific operating characteristics present in the fault conditions applied during the DUT avalanche interval. Therefore, in the example where DUT 104 is an electronic fuse, the transient voltage and current ratings of the electronic fuse characterize the ability of the electronic fuse to protect downstream loads during overload and / or short-circuit conditions.

[0040] Figure 2 The instructions can be used for implementation. Figure 1 Example of test circuit 200 for test circuit 100. Test circuit 200 can be used to measure the response to transient fault conditions provided to DUT 204, such as an electronic fuse. Transient fault conditions refer to overvoltage and / or overcurrent conditions provided to DUT 204 within a controlled DUT avalanche interval (time interval).

[0041] Test circuit 200 includes test module 208, which includes DUT 204. DUT 204 is represented as an NFET (e.g., a power NFET) having a gate coupled to a source and a ground node 206. Test circuit 200 includes an inductor 212 coupled to test module 208 via diode 210. More specifically, inductor 212 has a first node 216 coupled to a switching node 218 of test circuit 200 and a second node 220 coupled to a positive output terminal of power supply 224, and test module 208 is coupled to switching node 218 via diode 210. Test circuit 200 includes diode 210 coupled in series with test module 208. More specifically, diode 210 has an anode coupled to switching node 218 and a cathode coupled to the drain of DUT 204 and discharge resistor 232 Rdch. Test module 208 also includes other components required for biasing, DUT connections, controller pins, etc. In some examples, the discharge resistor 232 has a resistance of approximately 1 kiloohm (kΩ) to approximately 10 megaohms (MΩ). The discharge resistor 232 is coupled in parallel with the DUT 204, such that the discharge resistor 232 is also coupled to the ground node 206.

[0042] The drain of the first NFET 240 is also coupled to the switching node 218, and the source of the first NFET 240 is coupled to the ground node 206, so that the first NFET 240 is coupled in parallel with the test module 208. The first NFET 240 can be used to implement... Figure 1 The first switch 140. The anode of diode 244 is coupled to switch node 218, and the cathode of diode 244 is coupled to the drain of second NFET 248. Second NFET 248 can be used to implement... Figure 1 The second switch 148. The second NFET 248 is also coupled to the TVS 246. In the test circuit 200, the TVS 246 is unidirectional, and the cathode of the TVS 246 is coupled to the source of the second NFET 248 and the anode of the TVS 246 is coupled to the ground node 206.

[0043] The first NFET 240 and the second NFET 248 are implemented as enhancement-mode NFETs that are default off and operate in the cutoff region. However, in other examples, other types of transistors, including p-channel FETs, may be used. The gate of the first NFET 240 and the gate of the second NFET 248 are coupled to the output of the controller 260. More specifically, the controller 260 outputs signals, namely a first control signal to the gate of the first NFET 240 and a second control signal to the gate of the second NFET 248. In such examples, an assertion of the first control signal, such as a logic high (e.g., a 5V signal), causes the first NFET 240 to turn on and transition to the ohmic region, which is equivalent to closing the switch. Turning on the first NFET 240 shorts the switching node 218 to the ground node 206. De-asserting the first control signal so that a logic low (e.g., 0V) signal is provided to the gate of the first NFET 240 causes 240 to turn off and transition to the cutoff region, thereby decoupling the switching node 218 from the ground node 206. Turning off the first NFET 240 is equivalent to opening the switch. Conversely, asserting the second control signal to apply a logic high signal to the gate of the second NFET (e.g., logic high) will turn on the second NFET 248, equivalent to closing the switch. Turning on the second NFET couples the cathode of diode 244 to the cathode of TVS 246. Conversely, de-asserting the second control signal to provide a logic low signal to the gate of the second NFET 248 will turn off the second NFET 248, thus switching it to the cutoff region, equivalent to opening the switch. Turning off the second NFET 248 decouples diode 244 and TVS 246.

[0044] The controller 260 is implemented using a microcontroller or another device that provides control signals. In some examples, the controller 260 is a stand-alone device. In other examples, the controller 260 interfaces with an external system, such as a computer.

[0045] Power Supply 224 is a DC power supply, which responds to Figure 2 A power control signal, labeled PCS, outputs a voltage at the second node 220 of inductor 212. In some examples, the power control signal is provided from an external system, such as an external computer, causing power supply 224 to be software-controlled. In other examples, the power control signal is output from controller 260. In some examples, an assertion of the power control signal causes power supply 224 to output an output voltage to the second node 220 of inductor 212. In some examples, the output voltage is approximately 5-20 V (e.g., 7 V). Conversely, a de-assertion of the power control signal causes power supply 224 to stop applying the output voltage.

[0046] Test circuit 200 includes probes 264 for measuring voltage and / or current across DUT 204. In some examples, the output of probe 264 is provided to controller 260 or ADC (analog-to-digital converter) for recording. In some examples, the digital values ​​are provided to an external computer for recording and analysis.

[0047] During operation, the test circuit 200 has four states: (i) off state, (ii) inductor charging state, (iii) DUT avalanche state, and (iv) TVS clamping state. In the off state, the control signal output by the controller 260 is de-asserted, causing no current to flow through the test circuit 200. In the inductor charging state, the first NFET 240 is turned on and the second NFET 248 is turned off. Therefore, to initiate the inductor charging state, the power control signal output to the power supply 224 and the first control signal output to the first NFET 240 are asserted, thereby turning on the first NFET 240. In addition, to initiate the inductor charging state, the second control signal output to the second NFET 248 is de-asserted, causing the second NFET 248 to be turned off. Therefore, in the charging state, inductor 212 is coupled to the charging path including the first NFET 240, such that inductor 212 is charged to ramp up the stored current (or more generally, energy) to the peak level.

[0048] In response to reaching a peak level, controller 260 retracts the assertion of a first control signal provided to first NFET 240, thereby turning off first NFET 240, and continues to retract the assertion of a second control signal, thereby keeping second NFET 248 off, thus transitioning test circuit 200 to DUT avalanche state. In DUT avalanche state, the current stored in inductor 212 discharges rapidly through a first discharge path, wherein test module 208, on the first discharge path, causes the inductor current to discharge through DUT 204 for a controllable amount of time, referred to as the DUT avalanche interval. In other words, first NFET 240 and second NFET 248 cooperate to control the discharge of the inductor through the first discharge path to DUT 204. Furthermore, since both first NFET 240 and second NFET 248 are off, this time interval is alternatively referred to as the no-load time interval between first NFET 240 and second NFET 248. Additionally, the duration of the DUT avalanche interval is controlled by the timing of the first and second control signals. More specifically, the controller adjusts the timing of the first control signal and / or the second control signal to change the duration of the DUT avalanche interval.

[0049] In response to the timed triggering of the DUT avalanche interval, controller 260 asserts a second control signal, thereby turning off the second NFET 248. This diverts current (more generally, energy) from the first discharge path to a second discharge path comprising diode 244 and TVS 246, making the second NFET 248 operable to provide a second discharge path for inductor 212. In this way, inductor current is diverted from DUT 204 to TVS 246. More generally, turning on the second NFET 248 causes test circuit 200 to transition to a TVS clamped state. In the TVS clamped state, TVS 246 clamps the voltage across DUT 204 at a level defined by the operating characteristics of TVS 246. More specifically, in response to a voltage exceeding the forward voltage of diode 244 and exceeding the breakdown voltage of TVS 246, diode 244 and TVS 246 turn on, thereby clamping the voltage. Therefore, the breakdown voltage of TVS 246 limits the clamping voltage of TVS 246. In the TVS clamped state, discharge resistor 232 controls the modulation of the voltage drop time across DUT 204. During the TVS clamped state, the current stored in inductor 212 discharges to near 0 A.

[0050] Figure 3 The description indicates that the data is plotted as a function of time (e.g., in μs). Figure 2 The test circuit 200 is illustrated in diagram 300, with each diagram plotted at the same time interval. The first diagram 320 will... Figure 2 The drain-source voltage of DUT 204 is plotted as a function of time. The second figure, 340, shows... Figure 2 The inductor current of inductor 212 is plotted as a function of time. The third figure shows a 360° plot. Figure 2 The drain current of DUT 204.

[0051] In Figure 300, from time t0 to time t1, the test circuit is turned off, resulting in approximately zero inductor current (as illustrated in the second figure 340) and zero drain current, as indicated in the third figure 360. Additionally, the drain-to-source voltage VDS of the DUT 204 is equal to the source voltage Vs. At time t1, the test circuit 200 transitions to the inductor charging state. From time t1 to time t2, the test circuit 200 operates in the inductor charging state. In the inductor charging state, the DUT... Figure 2The first NFET 240 is short-circuited, causing both the drain current and drain-source voltage of DUT 204 to be approximately zero, as illustrated in the first figure 320 and the third figure 360. Additionally, as illustrated in the second figure 340, the inductor current of inductor 212 slopes from 0 A to the peak current Ipk. The magnitude of Ipk can be controlled by the duration of the charging state (the time interval between time t1 and t2). In various examples, the peak current Ipk ranges from approximately 50 A to approximately 300 A.

[0052] At time t2, test circuit 200 transitions to the DUT avalanche state. From time t2 to t3, denoted as DUT avalanche interval 364, test circuit 200 operates in the DUT avalanche state. DUT avalanche interval 364 is approximately 1 μs or less (e.g., approximately 100 ns to approximately 1 μs in some examples). During DUT avalanche interval 364, as illustrated in the first figure 320, the drain-to-source voltage reaches the breakdown voltage Vbr.

[0053] As illustrated in Figures 340 and 360, during the DUT avalanche interval 364, current from inductor 212 rapidly discharges across DUT 204. This rapid discharge imposes transient fault conditions on DUT 204. Therefore, during the DUT avalanche interval 364, the voltage and / or current across DUT 204 are measured and recorded. In some examples, the voltage across DUT 204 is from about 22 V to about 100 V (e.g., about 23-27 V in some examples), and the current across DUT 204 is in the range of about 50 amperes (A) to about 300 A. The response of DUT 204 during the DUT avalanche interval can be used to determine the reliability characteristics of DUT 204. Therefore, during the DUT avalanche interval, transient fault conditions (e.g., overvoltage and / or overcurrent) are applied to DUT 204.

[0054] Figure 4 The instructions can be used for implementation. Figure 2 An example of an NFET 400 in DUT 204 and its equivalent large-signal model 420 are provided. As illustrated, the NFET 400 has a body diode 404, wherein the anode of the body diode 404 is connected to the source of the NFET 400, and the cathode is connected to the drain of the NFET 400. As illustrated in the equivalent large-signal model 420, the body diode 404 is represented by a DC voltage source 424 having a voltage Vbr as the breakdown voltage and a dynamic resistance 428 Rdyn. The dynamic resistance 428 represents a resistance characterizing the behavior of the body diode 404 in the reverse conduction region of the body diode 404.

[0055] Figure 5A and5B Plotted as Figure 4 The drain-to-source voltage VDS of the NFET 400 is a function of the drain current ID of the NFET 400. More specifically, Figure 5A This is a first graph 500 plotting the drain current ID as a function of the drain-to-source voltage VDS for different gate-to-source voltages VGS of the NFET 400. As illustrated, as the drain-to-source voltage VDS increases, the NFET 400 transitions from the ohmic (linear) region to the saturation region and then to the breakdown region. More specifically, the NFET 400 transitions to the breakdown region in response to the drain-to-source voltage VDS reaching the drain-to-source breakdown voltage BVDSS. The drain-to-source breakdown voltage BVDSS is a parameter specifying the maximum drain-to-source voltage that the NFET 400 can withstand without entering avalanche breakdown. In other words, the drain-to-source breakdown voltage BVDSS is the voltage at which the drain-to-source junction begins to conduct in reverse due to the avalanche effect, which causes an uncontrolled increase in current.

[0056] Figure 5B A second graph 550 is shown, which plots the drain current ID as a function of the drain-source voltage of the NFET 400 for a single gate-to-source voltage VGS. Additionally, for clarity, the second graph 550 is scaled to enhance the visual representation of the breakdown region of the NFET 400. Furthermore, the value Rdyn of the dynamic resistance 428 can be calculated by measuring (or simulating) the drain current ID for different drain-to-source voltages VDS, as shown in Equation 1:

[0057] Equation 1:

[0058] in:

[0059] VDS1 is the first drain-to-source voltage measured for the NFET;

[0060] VDS2 is the second drain-to-source voltage measured for the NFET;

[0061] ID2 is the drain current of the NFET for VDS2; and

[0062] ID1 is the drain current of the NFET for VDS1.

[0063] The dynamic resistance 428 Rdyn and the current I_DUT across the NFET 400 (e.g., by...) Figure 2 The current measured by probe 264 can be used in Equation 2 to calculate the voltage V_DUT of NFET 400 during the avalanche interval.

[0064] Equation 2:

[0065] in:

[0066] Rdyn is the dynamic resistance of the NFET;

[0067] Vbr is the breakdown voltage of the NFET; and

[0068] I_DUT is the current measured across the NFET.

[0069] Figure 6A Figure 600 illustrates a sample of the measured response characteristics of the NFET 400 during the DUT avalanche interval. Figure 600 includes parameters for the current I_DUT across the NFET 400 and the voltage V_DUT across the NFET 400. The parameters for I_DUT include the maximum current Max (A) and minimum current Min (A) in amperes, the rise time tr (ns) in nanoseconds, the fall time tf (ns) in nanoseconds, and the on-time ton (ns) of the NFET 400 in nanoseconds. The parameters for I_DUT also include the duration of the DUT avalanche interval in nanoseconds, the I_DUT duration. The parameters for V_DUT of the NFET 400 include the minimum voltage Min (V), the maximum voltage Max (V), and the average voltage Avg (V). Figure 6B The illustration shows that the voltage across the NFET 400, in volts (V), is plotted as a function of the current across the NFET 400, in amperes (A).

[0070] Return to reference Figure 3 At time t3, test circuit 200 transitions to TVS clamp state, where the second NFET 248 is turned on. From time t3 to t4, test circuit 200 performs TVS clamp state. As illustrated in the second figure 340, the inductor current of inductor 212 decays at a rate less than the discharge rate during the avalanche region of the DUT. Furthermore, as illustrated in the first figure 320, the drain-to-source voltage of DUT 204 drops to the breakdown voltage Vbr_TVS of TVS 246. When inductor 212 has fully discharged, at time t4, as indicated in the second figure 340, the drain-to-source voltage of DUT 204 returns to Vs, causing test circuit 200 to transition to the off state.

[0071] Figure 7A , 7B And 7C Explanation Display Figure 2 A diagram illustrating the measured response of DUT 204 to a first example of transient fault conditions during avalanche interval 704. Figure 7A , 7BThe diagram 7C plots the power dissipation PD_OUT of DUT 204, the voltage V_DUT across DUT 204, the current I_DUT across DUT 204, and the current I_IND released by inductor 212. More specifically, Figure 7A The first illustration 700 depicts the avalanche interval 704 of the DUT. Figure 7B A second illustration 720 is shown, representing a portion of the first illustration 700, which has an enlarged region containing the DUT avalanche interval 704. Figure 7C A third illustration 740 is shown, including a DUT avalanche interval 744, where a 20 V DC offset has been applied to the voltage V_DUT across DUT 204. In the illustrated example, it is assumed that a transient fault condition of a single pulse of 100 A avalanche current is applied to DUT 204 during DUT avalanche intervals 704 and 744. In the illustrated example, there is no deviation in the operating parameters of DUT 204 before or after the 100 A avalanche current transient fault condition is applied to DUT 204.

[0072] Figure 8A , 8B And 8C Explanation Showcase Figure 2 A diagram illustrating the measured response of DUT 204 to a second example of transient fault conditions during the avalanche interval of the DUT. Figure 8A , 8B The 8C plot shows the power dissipation PD_OUT of DUT 204, the voltage V_DUT across DUT 204, the current I_DUT across DUT 204, and the current I_IND released by inductor 212. More specifically, Figure 8A The first illustration 800 depicts the avalanche interval 804 of the DUT. Figure 8B A second illustration 820 is shown, representing a portion of the first illustration 800, which has an enlarged region containing the DUT avalanche interval 804. Figure 8C A third illustration 840 is shown, including a DUT avalanche interval 844, where a 20 V DC offset has been applied to the voltage V_DUT across DUT 204. In the illustrated example, it is assumed that a transient fault condition of a single pulse of 200 A avalanche current is applied to DUT 204 during DUT avalanche intervals 804 and 844. In the illustrated example, there is no deviation in the operating parameters of DUT 204 before or after the 200 A avalanche current transient fault condition is applied to DUT 204.

[0073] Figure 9A , 9B And 9C Explanation Showcase Figure 2A diagram illustrating the measured response of DUT 204 to a third example of transient fault conditions during the avalanche interval of the DUT. Figure 9A , 9B The diagram 9C plots the power dissipation PD_OUT of DUT 204, the voltage V_DUT across DUT 204, the current I_DUT across DUT 204, and the current I_IND released by inductor 212. More specifically, Figure 9A The first illustration 900 depicts the avalanche interval 904 of the DUT. Figure 9B A second illustration 920 is shown, representing a portion of the first illustration 900, which has an enlarged region containing the DUT avalanche interval 904. Figure 9C A third illustration 940 is shown, including a DUT avalanche interval 944, where a 20 V DC offset has been applied to the voltage V_DUT across DUT 204. In the illustrated example, it is assumed that a transient fault condition of a single pulse of 288 A avalanche current is applied to DUT 204 during DUT avalanche intervals 904 and 944. In the illustrated example, there is no deviation in the operating parameters of DUT 204 before or after the transient fault condition of 288 A avalanche current is applied to DUT 204.

[0074] Figure 10A and 10B Explanation and display Figure 2 A diagram illustrating the measured response of DUT 204 to a fourth example of transient fault conditions during DUT operation. Figure 10A and 10B The power dissipation PD_OUT of DUT 204, the voltage V_DUT across DUT 204, the current I_DUT across DUT 204, and the current I_IND released by inductor 212 are plotted. More specifically, Figure 10A The first illustration 1000 depicts the avalanche interval of the DUT. Figure 10B A second illustration 1020 is shown, incorporating a DUT avalanche interval, where a 20 V DC offset has been applied to the voltage V_DUT across DUT 204. In the illustrated example, it is assumed that a transient fault condition of a single pulse of 300 A avalanche current is applied to DUT 204 during the DUT avalanche interval. In the illustrated example, DUT 204 is short-circuited, indicating that DUT 204 has failed, causing the single pulse of 300 A avalanche current to exceed the rating of DUT 204.

[0075] Return to reference Figure 2 ,exist Figure 9A , 9BIn the example illustrated in 9C, DUT 65—and thus, in this case, DUT 204—can be used (e.g., as an electronic fuse) for systems that may experience transient fault conditions with current spikes of 288 A or less.

[0076] Furthermore, in some cases, multiple DUT avalanche intervals are applied to DUT 204 to test the reliability of DUT 204. In such cases, controller 260 can re-assert and de-assert assertion control signals to power supply 224, first NFET 240, and second NFET 248 to transition test circuit 200 to inductor charging state, DUT avalanche state, and TVS clamping state. Therefore, the effects of multiple transient fault conditions (multiple instances of DUT avalanche intervals) can be measured and recorded.

[0077] Figure 11A , 11B And 11C Explanation Showcase Figure 2 A graphical representation of the measured response of DUT 204 to a first example of repetitive transient fault conditions during multiple DUT avalanche intervals. More specifically, Figure 11A , 11B The 11C plots the power dissipation PD_OUT of DUT 204, the voltage V_DUT across DUT 204, the current I_DUT across DUT 204, and the current I_IND released by inductor 212. Figure 11A A first illustration 1100 depicts a first DUT avalanche interval 1104 and a second DUT avalanche interval 1108. Figure 11B A second illustration 1120 is shown, representing a portion of the first illustration 1100, having an enlarged region containing the first DUT avalanche interval 1104. Figure 11C The third figure 1140 illustrates a further magnified region of the first DUT avalanche interval 1104. In the illustrated example, it is assumed that a transient fault condition of a repetitive pulse of a 50 A avalanche current at a frequency of 1 Hz for 1 μs is applied to the DUT 204 during the first DUT avalanche interval 1104. In the illustrated example, after 2000 repetitive pulses of a 50 A avalanche current at a frequency of 1 Hz for 1 μs, the operating parameters of the DUT 204 remain unchanged.

[0078] Figure 12A , 12B And 12C Explanation Showcase Figure 2 A graphical representation of the measured response of DUT 204 to a second example of repetitive transient fault conditions during multiple DUT avalanche intervals. More specifically, Figure 12A , 12BThe 12C plots the power dissipation PD_OUT of DUT 204, the voltage V_DUT across DUT 204, the current I_DUT across DUT 204, and the current I_IND released by inductor 212. Figure 12A A first illustration 1200 is depicted. The first illustration 1200 includes a first DUT avalanche interval 1204 and a second DUT avalanche interval 1208. Figure 12B A second illustration 1220 is shown, representing a portion of the first illustration 1200, having an enlarged region containing the first DUT avalanche interval 1204. Figure 12C The third illustration 1240 is shown, which includes a further magnified region of the first DUT avalanche interval 1204. In the illustrated example, it is assumed that a transient fault condition of a repetitive pulse of a 75 A avalanche current at a frequency of 1 Hz for 1 μs is applied to DUT 204 during the first DUT avalanche interval 1204. In the illustrated example, after 2000 repetitive pulses of a 75 A avalanche current at a frequency of 1 Hz for 1 μs, the operating parameters of DUT 204 are unbiased.

[0079] Figure 13A , 13B and 13C explanation display Figure 2 A graphical representation of the measured response of DUT 204 to a third example of repetitive transient fault conditions during multiple DUT avalanche intervals. More specifically, Figure 13A , 13B The 13C plots the power dissipation PD_OUT of DUT 204, the voltage V_DUT across DUT 204, the current I_DUT across DUT 204, and the current I_IND released by inductor 212. Figure 13A A first illustration 1300 depicts a first DUT avalanche interval 1304 and a second DUT avalanche interval 1308. Figure 13B A second illustration 1320 is shown, representing a portion of the first illustration 1300, which has an enlarged region containing the first DUT avalanche interval 1304. Figure 13C The third figure 1340 is illustrated, which includes a further magnified region of the first DUT avalanche interval 1304. In the illustrated example, it is assumed that a transient fault condition of a repetitive pulse of a 100 A avalanche current at a frequency of 1 Hz applied to DUT 204 for 1 μs during the first DUT avalanche interval 1304 causes a fault in DUT 204. In the illustrated example, DUT 204 short-circuits in response to 40 instances of the repetitive pulse of the 100 A avalanche current for 1 μs, thereby indicating a fault in DUT 204.

[0080] Return to reference Figure 2 ,like Figure 12A , 12B As shown in the example of 12C, DUT 204 has a current rating of 75 A for repetitive pulses lasting about 1 μs or less and a frequency of 1 Hz or less. Therefore, in this case, DUT 204 can be used (e.g., as an electronic fuse) in systems that may experience transient fault conditions of 75 A for repetitive pulses lasting about 1 μs or less at a frequency of 1 Hz or less.

[0081] As shown, the architecture of the test circuit 200, particularly the first NFET 240 and the second NFET 248, enables precise control over the magnitude of the fault condition and the duration of the DUT avalanche interval. Therefore, the precise transient voltage and / or current ratings of the DUT 204 can be determined. In this way, the DUT 204 (e.g., an electronic fuse) can be confidently deployed in other circuits that depend on the specific operating characteristics present in the fault condition applied during the DUT avalanche interval. Thus, in the example where the DUT 204 is an electronic fuse, the transient voltage and current ratings of the electronic fuse characterize its ability to protect downstream loads during overload and / or short-circuit conditions.

[0082] Figure 14 A block diagram of a circuit 1400 is shown illustrating an electronic fuse 1404 coupled between a power supply 1408 and a load 1412. In this manner, the load 1412 is downstream of the electronic fuse 1404. The electronic fuse 1404 can be used to implement... Figure 1 DUT 104 and / or Figure 2 The DUT 204. Inductor 1416 is coupled between power supply 1408 and electronic fuse 1404. Load 1412 is implemented as a resistive and / or reactive load. In the illustrated example, it is assumed that electronic fuse 1404 may be exposed to conditions similar to those described above. Figure 1 and 2 The transient fault conditions explained.

[0083] In operation, power supply 1408 provides DC voltage to load 1412 via electronic fuse 1404. Therefore, electronic fuse 1404 is normally closed. Additionally, electronic fuse 1404 serves as a resettable overcurrent protection device for circuit 1400. When the current level exceeds a predefined limit, the electronic fuse quickly activates to disconnect the current path between power supply 1408 and load 1412, thereby preventing damage to load 1412 during overload and / or short-circuit conditions. Furthermore, electronic fuse 1404 is resettable after tripping.

[0084] Figure 15This flowchart illustrates an example method 1500 for determining the characteristics of a DUT. In some examples, the DUT is implemented using an electronic fuse. In some examples, method 1500 utilizes... Figure 1 The test circuit 100 is implemented. In block 1510, the first switch of the test circuit (e.g., Figure 1 The first switch 140) is closed to test the inductor of the circuit (e.g., Figure 1 The inductor 112 is pre-charged. In some examples, the first switch is implemented using a FET. In block 1515, the first switch is turned off to allow the inductor to discharge through the DUT to apply a transient fault condition within the DUT avalanche interval. In block 1520, the response of the DUT to the transient fault condition is measured.

[0085] In box 1525, the second switch is closed in response to the timed DUT avalanche interval (e.g., ...). Figure 1 A second switch 148 is used to divert the inductor current from the DUT to the TVS. The TVS clamps the voltage across the electronic fuse in response to the closing of the second switch. In some examples, the second switch is also implemented using a FET. The circuit is configured such that the controller (e.g., Figure 1 The controller 160 outputs control signals to the first and second switches to control the duration of the DUT avalanche interval.

[0086] In this specification, unless otherwise stated, "about" before a parameter means within + / - 10% of said parameter. Furthermore, in this specification, the terms "coupled," "coupled," or "couples" mean indirect or direct connection. Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. A circuit for determining the characteristics of a DUT (device under test), the circuit comprising: An inductor, which is coupled to the first switch; The first switch is coupled to the second switch; A test module coupled to the first switch and the second switch, the test module comprising a DUT; and TVS (Transient Voltage Suppressor) is coupled to the second switch.

2. The circuit according to claim 1, wherein the DUT is an electronic fuse.

3. The circuit of claim 2, wherein the test module further includes a discharge resistor coupled in parallel with the electronic fuse.

4. The circuit of claim 3, wherein the circuit further comprises a diode coupled to the first switch, the second switch, the electronic fuse, and the discharge resistor.

5. The circuit of claim 4, further comprising a power supply configured to apply voltage to the inductor.

6. The circuit of claim 5, wherein the TVS is configured to clamp the voltage to a predetermined level in response to closing the second switch.

7. The circuit of claim 6, further comprising a controller configured to adjust timing control signals output to the first switch and the second switch to change the DUT avalanche interval, the DUT avalanche interval comprising the time interval between the opening of the first switch and the closing of the second switch.

8. The circuit of claim 1, wherein the first switch and the second switch are FETs (field-effect transistors).

9. A circuit for determining the characteristics of a DUT (device under test), the circuit comprising: An inductor, configured to store energy; A first switch is coupled to the inductor and is operable to provide a charging path for the inductor; A second switch coupled to the first switch, wherein the first switch and the second switch cooperate to control the discharge of the inductor through a first discharge path, and the second switch is operable to provide a second discharge path for the inductor in response to a timed DUT avalanche interval. A TVS (Transient Voltage Suppressor) is located on the second discharge path, the TVS being coupled to the second switch, wherein the energy from the inductor is diverted to the TVS in response to the timed triggering of the avalanche interval of the DUT; as well as A test module, located on the first discharge path, coupled to the first switch and the second switch, wherein the test module connects the DUT to the current output by the inductor during the avalanche interval of the DUT for testing the current rating of the DUT.

10. The circuit of claim 9, wherein the DUT is an electronic fuse.

11. The circuit of claim 10, wherein the inductor, the first switch, the second switch, and the TVS are configured to apply transient fault conditions to the DUT during the DUT avalanche interval, the DUT avalanche interval comprising the time interval between the opening of the first switch and the closing of the second switch.

12. The circuit of claim 11, wherein the DUT avalanche interval is adjustable based on a timing control signal.

13. The circuit of claim 12, further comprising a controller configured to adjust the timing control signal to change the DUT avalanche interval.

14. The circuit of claim 10, wherein the TVS is configured to clamp the voltage to a predetermined level in response to the timer triggering of the DUT avalanche interval.

15. The circuit of claim 10, wherein the current rating of the electronic fuse characterizes the ability of the electronic fuse to protect downstream loads during overload and / or short-circuit conditions.

16. The circuit of claim 9, wherein the first switch and the second switch are FETs (field-effect transistors).

17. A method for determining the characteristics of a DUT (device under test), the method comprising: The first switch of the closed circuit is used to precharge the inductor of the circuit; Disconnect the first switch to allow the inductor to discharge through the DUT, thereby applying transient fault conditions within the DUT avalanche interval; Measure the response of the DUT to the transient fault condition; as well as In response to the timed triggering of the avalanche interval of the DUT, the second switch is closed to divert the inductor current to the TVS (transient voltage suppressor).

18. The method of claim 17, wherein the DUT is an electronic fuse.

19. The method of claim 18, wherein the TVS clamps the voltage across the electronic fuse in response to the closing of the second switch.

20. The method of claim 17, wherein the first switch and the second switch are FETs (field-effect transistors).

21. The method of claim 17, wherein the controller outputs control signals to the first switch and the second switch to control the duration of the DUT avalanche interval.

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