A distributed quantum circuit teleportation optimization method based on gate exchange pruning

Abstract

The present application relates to the technical field of distributed quantum computing, and more particularly to a distributed quantum circuit teleportation optimization method based on gate exchange pruning. The problem of long solving time or excessive expansion branches caused by the lack of fine pruning and state merging mechanism is solved. The technical scheme is as follows: step S1: quantum circuit analysis and data structure establishment; step S2: weighted interaction graph construction and candidate partition set generation; step S3: global gate identification and single-pass teleportation construction; step S4: pruning search to solve the minimum single-pass teleportation times and plan output. The beneficial effects of the present application are as follows: compared with the prior art, the present application has more sufficient and verifiable beneficial effects: the global communication overhead can be directly quantified to decrease; the single batch throughput is improved and the redundant teleportation is reduced; and the solution cost is significantly reduced.

Description

Technical Field

[0001] This invention relates to the field of distributed quantum computing technology, and in particular to a distributed quantum circuit state transfer optimization method based on gate switching pruning. Background Technology

[0002] Quantum computing, leveraging quantum mechanical properties such as superposition and entanglement, exhibits potential computational advantages in problems involving large number factorization, database searching, quantum chemistry, and combinatorial optimization. (Reference paper: Cardama FJ, Vázquez-Pérez J., Pena TF, et al. Quantum Compilation Process: A Survey. In: Euro-Par2024: Parallel Processing Workshops, LNCS 15385, pp.100–112 (First Online 11June 2025). DOI:10.1007 / 978-3-031-90200-0_9.) Due to the limitations of current hardware capabilities at the Noisy Intermediate-Scale Quantum (NISQ) stage, quantum programs must be compiled before execution. This involves mapping high-level quantum circuitry to the gate sets and coupling topologies of specific devices, and minimizing the number of two-qubit gates and circuit depth to mitigate decoherence and error accumulation.

[0003] Referring to the papers (Caleffi M., et al. Distributed quantum computing: a survey. Computer Networks, 2024. DOI:10.1016 / j.comnet.2024.110672.) and (Barral D., Cardama FJ, Díaz-Camacho G., et al. Review of Distributed Quantum Computing: From single QPU to High Performance Quantum Computing. ComputerScience Review, 57 (2025) 100747. DOI:10.1016 / j.cosrev.2025.100747.), as application scale increases, the number of qubits, connectivity, and usable fidelity of a single quantum processor gradually become bottlenecks. Distributed quantum computing, by interconnecting multiple quantum processors (QPUs), distributes quantum tasks beyond the capabilities of a single chip to multiple nodes for collaborative completion, and is widely considered an important expansion path for large-scale quantum systems. The referenced paper (Carrera Vazquez A., Tornow C., Ristè D., et al. Combining quantumprocessors with real-time classical communication. Nature 636, 75–79 (2024).) has demonstrated real-time classical communication collaboration and dynamic circuit capabilities across two QPUs on real hardware, verifying the engineering feasibility of "multi-QPU joint execution"; the referenced paper (Aghaee Rad A., et al. Scaling and networking a modular photonic quantum computer. Nature 638, 912–919 (2025).) shows that modular architectures oriented towards fault tolerance and scalability are also being rapidly advanced on platforms such as photonics.

[0004] In a distributed quantum computing framework, quantum circuits are typically split and executed locally on different QPUs. When a circuit contains cross-partition two-bit interactions (also known as global gates), long-range coupling is achieved using pre-shared entanglement and classical communication. The referenced paper (Bennett CH, Brassard G., Crépeau C., Jozsa R., Peres A., Wootters WK Teleporting an unknown quantum state via dual classical and EPR channels. Physical Review Letters, 1993.) states that quantum teleportation, as a fundamental operation of quantum networks, can realize quantum state transfer under the condition of consuming entanglement resources and cooperating with classical communication. The referenced paper (Gottesman D., Chuang IL Demonstrating the viability of universal quantum computation using teleportation and single-qubit operations. Nature 402, 390–393 (1999.)) further demonstrates that universal quantum computing based on teleportation can realize universal gate sets and nonlocal operations through Bell measurement, entanglement resources, and single-qubit correction. The realization of nonlocal gates inevitably introduces additional entanglement and communication overhead, thus significantly affecting the overall system delay and error accumulation.

[0005] Therefore, distributed quantum compilation not only needs to generate partitions with smaller cut edges, but also needs to jointly consider the generation of entangled pairs, remote operation scheduling, and necessary local transformations under given network and device constraints, thereby reducing the overall execution time and resource consumption. The following paper (Promponas P., Mudvari A., Della Chiesa L., et al. Compiler for Distributed Quantum Computing: a Reinforcement Learning Approach. arXiv:2404.17077 (2024). DOI:10.48550 / arXiv.2404.17077.) has already begun to propose compilation frameworks that are closer to the execution layer in order to achieve this goal: for example, by modeling the environment through reinforcement learning and adaptively arranging EPR pairs and remote gate scheduling, and by proposing efficient compilation for architectures such as linear interconnects / linear layouts to reduce nonlocal interactions and SWAP overhead. See the following paper (Liu K., Zhou Y., Luo H., et al. ECDQC: Efficient Compilation for Distributed Quantum Computing with Linear Layout. arXiv:2410.23857 (2024).). These studies demonstrate that "transfer count" and "entanglement overhead" are often key indicators that determine the efficiency and reliability of distributed execution.

[0006] On the other hand, many common quantum algorithms and variational circuits contain numerous diagonal or Pauli rotation-type two-qubit gates (such as controlled phase and RZZ: two-qubit interaction rotation gates), which exhibit strong commutativity and fusion under certain conditions. Recent compilation work has also utilized inter-layer rotation push / pull and RZZ merging techniques to compress two-qubit gate structures and reduce implementation overhead. This suggests that if the structural feature of "diagonal gate commutativity" can be more fully exploited in distributed scenarios, it may be possible to merge multiple cross-partition interactions into fewer communication batches, thereby further reducing the number of state transfers and classical interaction rounds.

[0007] In distributed quantum circuits, scheduling and compilation, with minimum number of state transfers as the core metric, typically require simultaneously determining the execution order of remote two-qubit gates, batching methods, generation and occupancy of entangled pairs, and classical communication synchronization. This is a strongly constrained combinatorial optimization problem, and the search space can easily explode as the number of global gates increases. Therefore, existing technologies generally introduce pruning to control solution time. Common practices include: performing structured simplification before solving, such as normalizing or merging gate sequences using gate dependencies and the commutativity of diagonal / Pauli rotation gates to reduce remote interactions that must be explicitly scheduled; performing feasibility pruning during the search process, directly discarding candidate batches that would lead to insufficient entanglement resources, excessive link concurrency, or excessive resident capacity; constructing a lower bound estimate of "at least how many rounds of communication are needed for the remaining remote gates," and immediately stopping the expansion of the branch when the number of used rounds plus the lower bound cannot be better than the current best solution; and combining repeated state merging and heuristic screening to retain only a small number of candidates with a better chance of reducing the number of state transfers for further searching.

[0008] In summary, the existing technology has the following shortcomings:

[0009] (1) The interchangeability and mergeability are not fully utilized, especially for diagonal / Pauli rotation type two-bit gates, which often adopt a more conservative decision rule, making it difficult to rearrange and aggregate cross-partition interactions over a larger range, thus underestimating the number of state transfers that can be reduced;

[0010] (2) After introducing constraints such as quantum state residency and limited additional storage bits, the state space of existing batch construction and remote gate scheduling increases significantly. The pruning and state merging mechanisms are often not refined enough, which can easily lead to problems such as excessive solution time or too many extended branches. Summary of the Invention

[0011] The purpose of this invention is to provide a distributed quantum circuit state transfer optimization method based on gate switching pruning. This invention features a clear hierarchy, can be modeled in a unified manner with hardware constraints, and can improve global gate merging, reduce the number of state transfers, and significantly shorten solution time while ensuring circuit equivalence, thereby enhancing the engineering usability and research value of distributed quantum computing.

[0012] To achieve the aforementioned objectives, the present invention employs the following technical solution: a distributed quantum circuit state transfer optimization method based on gate-switching pruning, comprising the following steps:

[0013] Step S1: Quantum circuit analysis and data structure establishment; determine the type, endpoint logical qubits, and timing position of each quantum gate. This provides reliable input for subsequent global gate identification and gate swap mobility determination, reducing misjudgments and redundant calculations.

[0014] Step S11: Obtain the quantum circuit to be executed and resolve it into a sequence of quantum gates arranged in chronological order. Record the gate type, the set of functional logic qubits for each quantum gate, and its index position in the quantum gate sequence. ;

[0015] in: Represents a quantum gate, Representing quantum gates Position number in the sequence;

[0016] Step S12: For each two-qubit gate Record its endpoint logical qubits and ;

[0017] Step S2: Weighted interaction graph construction and candidate partition set generation; This pre-screens for more reasonable partitioning schemes, as partitions directly determine the scale of cross-partition interactions, thus affecting transfer overhead. By generating a weighted interaction graph and candidate partitions, the subsequent search space is reduced and partition quality is improved at a lower cost, making optimization more efficient and stable.

[0018] Step S21: Construct a weighted interaction graph of logical qubits based on the quantum gate sequence: using logical qubits as nodes and logical qubit pairs with at least one two-qubit gate interaction as edges; logical qubits and The edge weights are calculated according to formula (1):

[0019] (1);

[0020] in: Representing logical qubits and Interaction weights; Indicates the endpoint is A set of two-qubit gates; Represents a two-qubit gate The weight is taken when the gate type is not distinguished. ;

[0021] Step S22: Construct a Laplace matrix for the weighted interaction graph and perform spectral embedding to obtain the eigenvector representation of each logical qubit;

[0022] Step S23: Perform clustering in the spectral space to obtain multiple candidate partitioning schemes. ;

[0023] in: Indicates the partitioning scheme;

[0024] Step S24: Perform capacity equalization processing on the candidate partitioning schemes to ensure that the number of logical qubits in each partition meets the preset capacity constraints;

[0025] Step S25: Deduplicate and filter the equalized candidate partitions and evaluate the candidate partitioning schemes using a cost function. The cost function is calculated according to formula (2):

[0026] (2);

[0027] in, Partition scheme The value of the substitute; In the partition scheme The set of logical qubit pairs spanning the lower partition;

[0028] Calculate cut weights Calculate according to formula (3):

[0029] (3);

[0030] in: Represents the set of edges in a weighted interaction graph; Representing logical qubits The partition number; Representing logical qubits and They were assigned to different partitions;

[0031] Step S3: Global Gate Identification and One-Way Transmission Construction: This step involves identifying opportunities for merged execution of cross-partition two-bit gates that actually generate communication overhead. By using anchor gates, endpoint enumeration, and exchangeable gate switching rules, more global gates are aggregated into the same one-way transmission batch, thereby reducing the number of batches and cross-node switching, improving transmission utilization, and reducing actual overhead.

[0032] Step S31: For candidate partitioning schemes Traverse the two-qubit gates in the quantum gate sequence; when the following conditions are met... When this happens, the two-qubit gate is determined to be a global gate, forming a global gate set.

[0033] Step S32: Calculate the global number of gates Calculate according to formula (4):

[0034] (4);

[0035] in: The set of two-qubit gates in a quantum gate sequence; : Indicator function, returns 1 if the condition is true, otherwise returns 0; Indicates the partition number;

[0036] Step S33: Construct a mergeable one-way transfer state: use the first global gate in the quantum gate sequence as the anchor gate;

[0037] Enumerate the endpoint logical qubits of the anchor gate as one-way moving logical qubits and determine that they are moved to the target partition for execution; within a preset window interval, filter candidate global gates that are consistent with the target partition, wherein the other endpoint logical qubits of the candidate global gates, excluding the one-way moving logical qubits, are located in the same target partition;

[0038] Step S34: Based on the gate exchange rule, determine whether the candidate global gate can be moved to the anchor gate through exchange, and merge the candidate global gates that meet the mobility and target partition into the same one-way transfer state;

[0039] The gate commutative rules include:

[0040] Diagonal gate strong commutativity rule: When two quantum gates to be determined are both diagonal gates, the two quantum gates are determined to be commutative, so as to allow the candidate global gate to move across the diagonal gate and participate in the same one-way transfer state merging;

[0041] Selected gate ignore rule: When determining whether a candidate global gate is movable, the set of quantum gates that have been selected into the same one-way transfer state are ignored in the mobility detection, and the set of selected gates is regarded as a whole moving together.

[0042] Step S4: Pruning search to find the minimum number of single-pass state transfers and the planned output; ensuring solution quality while controlling computational load. By using greedy upper and lower bound pruning, branches that cannot be improved are promptly removed and the range of the optimal solution is dynamically tightened, resulting in a faster and better single-pass state transfer batch and execution plan.

[0043] Step S41: For each candidate partitioning scheme Based on a greedy strategy, a feasible one-way transfer sequence is constructed to obtain the upper bound corresponding to the candidate partition. ;

[0044] Step S42: During the branch and bound search process, define the set of remaining global gates for the current search node. The number of its gates Calculate according to formula (5):

[0045] (5);

[0046] in: This represents the set of global gates that have not yet been covered under the current search node; Indicates the number of elements;

[0047] Step S43: For each logical qubit Calculate the number of endpoint participations of each endpoint in the remaining global gate set. Calculate according to formula (6):

[0048] (6);

[0049] in: Indicates counting; if global gate The endpoints are Then for and Each is incremented by 1; q is the endpoint of the global gate g;

[0050] Step S44: All logical qubits Arranged in descending order, the sequence satisfies formula (7):

[0051] (7);

[0052] in: Indicates the first The number of times large endpoints participate. The number of logical qubits;

[0053] Step S45: Construct a simple lower bound :make As an optimistic upper bound for "the number of global gates that can be processed in a single batch", the minimum number of batches required for the remaining global gates is calculated according to formula (8):

[0054] (8);

[0055] in: Indicates rounding up; To avoid Divide by zero;

[0056] Step S46: Construct a lower bound based on the number of remaining global gates :make The maximum number of global gates that can be merged in a single, one-way transfer is calculated according to formula (9):

[0057] (9);

[0058] in: ; This is the maximum number of elements that can be merged, either preset or obtained from rules.

[0059] Step S47: Construct the endpoint cover lower bound Let d i= degi Then calculate according to formula (10):

[0060] (10);

[0061] in: The smallest positive integer that satisfies the covering condition; The number of times each endpoint participates after sorting; This represents the remaining number of global gates.

[0062] Step S48 Pruning condition: During the search process, the number of one-way state transfers formed by the current node is recorded as follows: Get the lower bound of the current node ;when Prune the search branch as needed;

[0063] Step S419: Output the minimum number of one-way state transfers after the search ends. And calculate the number of round trips according to formula (11). :

[0064] (11);

[0065] in: This represents the minimum number of single-pass state transfers. The number of round trips is given; and S3 and S4 are executed on each candidate partition in the candidate partition set to obtain and output the partition scheme, the number of global gates, and the total number of round trips.

[0066] In practical use, this invention takes the quantum circuit to be executed as input, sets the number of partitions and the upper limit of the capacity of each partition, and optionally sets a resident model switch and the number of additional storage bits for the target partition. The system first generates and filters candidate partitions, then constructs a one-way transfer for each candidate partition and solves for the minimum depth, finally outputting the optimal partition and its transfer execution plan. The transfer execution plan can be directly converted into a distributed control flow: the one-way transfer operation is completed at the beginning of each one-way transfer, the merged global gates are executed sequentially within the batch in the target partition, and a backhaul is performed when necessary, thereby completing the distributed execution of the entire quantum circuit.

[0067] Meanwhile, the present invention proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed, it implements the steps of the method described in the present invention.

[0068] Furthermore, the present invention proposes a computer-readable storage medium having a computer program stored thereon, the computer program being configured to implement the steps of the method described in the present invention when invoked by a processor.

[0069] Finally, the present invention provides a computer program product comprising a computer program / instructions that, when executed by a processor, implement the steps of the method described in the present invention.

[0070] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0071] (1) Global communication overhead can be directly quantified and reduced: This invention addresses the communication overhead caused by the two-qubit gate across partitions. Under the premise of maintaining the functional equivalence of the line, it coordinates the partition generation and state transfer scheduling to optimize the overall efficiency. This can reduce the number of single-trip state transfer batches and the number of round-trip state transfers at the global level, thereby reducing the number of cross-node communication interactions and distributed execution waiting overhead, and directly improving the overall execution efficiency. This effect can be verified by comparing the number of batches and the number of state transfers before and after optimization.

[0072] (2) Improved single-batch throughput and reduced redundant transfer: The present invention identifies global gates under a given partition, enumerates the logical qubits of the moving endpoints starting from the anchor gate, and combines the gate commutativity determination with gate exchange movement to aggregate global gates that are consistent with the target partition and can be legally rearranged into the same single-pass transfer batch as much as possible, so that the scattered cross-partition operations are centrally processed, thereby reducing the need for repeated switching of logical qubits between partitions from a mechanism perspective, reducing repeated transfer and increasing the number of cross-partition operations that a single batch can carry, thereby reducing the overall transfer overhead.

[0073] (3) Closer to the optimal solution and significantly reduced solution cost: In response to the problems of unstable quality of local greedy solutions and the explosion of computational cost of exhaustive search, this invention introduces a pruning search strategy that combines upper and lower bounds in the scheduling solution. The upper bound is formed by constructing feasible solutions through greed, and the lower bound is constructed by the number of remaining global gates and the number of times the endpoints participate. Pruning is carried out in a timely manner based on the condition that the sum of the number of batches used and the lower bound cannot be better than the current upper bound. At the same time, the upper bound is continuously tightened when a better feasible solution is found, so that the search space is continuously reduced. Thus, while ensuring that the scheduling result is closer to the optimal solution, the computation time and resource consumption are significantly reduced, and the optimization process is more efficient and stable. Attached Figure Description

[0074] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0075] Figure 1 This is a schematic diagram of the quantum circuit before optimization in this invention.

[0076] Figure 2 This is a schematic diagram of the optimized quantum circuit of the present invention. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Of course, the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0078] Example 1

[0079] The present invention provides a technical solution for optimizing the state transfer of distributed quantum circuits based on gate-switching pruning, comprising the following steps:

[0080] Step S1: Quantum circuit analysis and data structure establishment; determine the type, endpoint logical qubits, and timing position of each quantum gate. This provides reliable input for subsequent global gate identification and gate swap mobility determination, reducing misjudgments and redundant calculations.

[0081] Step S11: Obtain the quantum circuit to be executed and resolve it into a sequence of quantum gates arranged in chronological order. Record the gate type, the set of functional logic qubits for each quantum gate, and its index position in the quantum gate sequence. ;

[0082] in: Represents a quantum gate, Representing quantum gates Position number in the sequence;

[0083] Step S12: For each two-qubit gate Record its endpoint logical qubits and ;

[0084] Step S2: Weighted interaction graph construction and candidate partition set generation; This pre-screens for more reasonable partitioning schemes, as partitions directly determine the scale of cross-partition interactions, thus affecting transfer overhead. By generating a weighted interaction graph and candidate partitions, the subsequent search space is reduced and partition quality is improved at a lower cost, making optimization more efficient and stable.

[0085] Step S21: Construct a weighted interaction graph of logical qubits based on the quantum gate sequence: using logical qubits as nodes and logical qubit pairs with at least one two-qubit gate interaction as edges; logical qubits and The edge weights are calculated according to formula (1):

[0086] (1);

[0087] in: Representing logical qubits and Interaction weights; Indicates the endpoint is A set of two-qubit gates; Represents a two-qubit gate The weight is taken when the gate type is not distinguished. ;

[0088] Step S22: Construct a Laplace matrix for the weighted interaction graph and perform spectral embedding to obtain the eigenvector representation of each logical qubit;

[0089] Step S23: Perform clustering in the spectral space to obtain multiple candidate partitioning schemes. ;

[0090] in: Indicates the partitioning scheme;

[0091] Step S24: Perform capacity equalization processing on the candidate partitioning schemes to ensure that the number of logical qubits in each partition meets the preset capacity constraints;

[0092] Step S25: Deduplicate and filter the equalized candidate partitions and evaluate the candidate partitioning schemes using a cost function. The cost function is calculated according to formula (2):

[0093] (2);

[0094] in, Partition scheme The value of the substitute; In the partition scheme The set of logical qubit pairs spanning the lower partition;

[0095] Calculate cut weights Calculate according to formula (3):

[0096] (3);

[0097] in: Represents the set of edges in a weighted interaction graph; Representing logical qubits The partition number; Representing logical qubits and They were assigned to different partitions;

[0098] Step S3: Global Gate Identification and One-Way Transmission Construction: This step involves identifying opportunities for merged execution of cross-partition two-bit gates that actually generate communication overhead. By using anchor gates, endpoint enumeration, and exchangeable gate switching rules, more global gates are aggregated into the same one-way transmission batch, thereby reducing the number of batches and cross-node switching, improving transmission utilization, and reducing actual overhead.

[0099] Step S31: For candidate partitioning schemes Traverse the two-qubit gates in the quantum gate sequence; when the following conditions are met... When this happens, the two-qubit gate is determined to be a global gate, forming a global gate set.

[0100] Step S32: Calculate the global number of gates Calculate according to formula (4):

[0101] (4);

[0102] in: The set of two-qubit gates in a quantum gate sequence; : Indicator function, returns 1 if the condition is true, otherwise returns 0; Indicates the partition number;

[0103] Step S33: Construct a mergeable one-way transfer state: use the first global gate in the quantum gate sequence as the anchor gate;

[0104] Enumerate the endpoint logical qubits of the anchor gate as one-way moving logical qubits and determine that they are moved to the target partition for execution; within a preset window interval, filter candidate global gates that are consistent with the target partition, wherein the other endpoint logical qubits of the candidate global gates, excluding the one-way moving logical qubits, are located in the same target partition;

[0105] Step S34: Based on the gate exchange rule, determine whether the candidate global gate can be moved to the anchor gate through exchange, and merge the candidate global gates that meet the mobility and target partition into the same one-way transfer state;

[0106] The gate commutative rules include:

[0107] Diagonal gate strong commutativity rule: When two quantum gates to be determined are both diagonal gates, the two quantum gates are determined to be commutative, so as to allow the candidate global gate to move across the diagonal gate and participate in the same one-way transfer state merging;

[0108] Selected gate ignore rule: When determining whether a candidate global gate is movable, the set of quantum gates that have been selected into the same one-way transfer state are ignored in the mobility detection, and the set of selected gates is regarded as a whole moving together.

[0109] Step S4: Pruning search to find the minimum number of single-pass state transfers and the planned output; ensuring solution quality while controlling computational load. By using greedy upper and lower bound pruning, branches that cannot be improved are promptly removed and the range of the optimal solution is dynamically tightened, resulting in a faster and better single-pass state transfer batch and execution plan.

[0110] Step S41: For each candidate partitioning scheme Based on a greedy strategy, a feasible one-way transfer sequence is constructed to obtain the upper bound corresponding to the candidate partition. ;

[0111] Step S42: During the branch and bound search process, define the set of remaining global gates for the current search node. The number of its gates Calculate according to formula (5):

[0112] (5);

[0113] in: This represents the set of global gates that have not yet been covered under the current search node; Indicates the number of elements;

[0114] Step S43: For each logical qubit Calculate the number of endpoint participations of each endpoint in the remaining global gate set. Calculate according to formula (6):

[0115] (6);

[0116] in: Indicates counting; if global gate The endpoints are Then for and Each is incremented by 1; q is the endpoint of the global gate g;

[0117] Step S44: All logical qubits Arranged in descending order, the sequence satisfies formula (7):

[0118] (7);

[0119] in: Indicates the first The number of times large endpoints participate. The number of logical qubits;

[0120] Step S45: Construct a simple lower bound :make As an optimistic upper bound for "the number of global gates that can be processed in a single batch", the minimum number of batches required for the remaining global gates is calculated according to formula (8):

[0121] (8);

[0122] in: Indicates rounding up; To avoid Divide by zero;

[0123] Step S46: Construct a lower bound based on the number of remaining global gates :make The maximum number of global gates that can be merged in a single, one-way transfer is calculated according to formula (9):

[0124] (9);

[0125] in: ; This is the maximum number of elements that can be merged, either preset or obtained from rules.

[0126] Step S47: Construct the endpoint cover lower bound Let d i= deg i Then calculate according to formula (10):

[0127] (10);

[0128] in: The smallest positive integer that satisfies the covering condition; The number of times each endpoint participates after sorting; This represents the remaining number of global gates.

[0129] Step S48 Pruning condition: During the search process, the number of one-way state transfers formed by the current node is recorded as follows: Get the lower bound of the current node ;when Prune the search branch as needed;

[0130] Step S419: Output the minimum number of one-way state transfers after the search ends. And calculate the number of round trips according to formula (11). :

[0131] (11);

[0132] in: This represents the minimum number of single-pass state transfers. The number of round trips is given; and S3 and S4 are executed on each candidate partition in the candidate partition set to obtain and output the partition scheme, the number of global gates, and the total number of round trips.

[0133] In practical use, this invention takes the quantum circuit to be executed as input, sets the number of partitions and the upper limit of the capacity of each partition, and optionally sets a resident model switch and the number of additional storage bits for the target partition. The system first generates and filters candidate partitions, then constructs a one-way transfer for each candidate partition and solves for the minimum depth, finally outputting the optimal partition and its transfer execution plan. The transfer execution plan can be directly converted into a distributed control flow: the one-way transfer operation is completed at the beginning of each one-way transfer, the merged global gates are executed sequentially within the batch in the target partition, and a backhaul is performed when necessary, thereby completing the distributed execution of the entire quantum circuit.

[0134] Example 2

[0135] Based on Example 1,

[0136] Step S1: Quantum Circuit Analysis and Data Structure Establishment

[0137] Step S11: Obtain Figure 1 The quantum circuit to be executed shown is resolved into a sequence of quantum gates arranged in chronological order, and the gate type, the set of active logic qubits, and their index positions for each quantum gate are recorded. For example, the sequence begins with... , Subsequently, several two-qubit gates appeared in sequence. and local diagonal door .

[0138] Step S12: Gate each two-qubit in the sequence Record its endpoint logical qubits For example: Regarding Record ,right Record ,right Record ,right Record .

[0139] Step S2: Weighted Interaction Graph Construction and Candidate Partition Set Generation

[0140] Step S21: Construct a weighted interaction graph of logical qubits based on the quantum gate sequence, with nodes as follows: The edges are bit pairs with two-qubit interactions. In this embodiment, the interaction edges include... Its border rights The weighted sum of the occurrence counts of the corresponding two-qubit gates is obtained according to formula (1). (In this embodiment, the gate type is not distinguished.) ).

[0141] Step S22: Construct a Laplace matrix for the interaction graph and perform spectral embedding to obtain the eigenvector representation of each logical qubit.

[0142] Step S23: Perform clustering in the spectral space to generate a set of multiple candidate partitioning schemes. .

[0143] Step S24: Perform capacity equalization processing on the candidate partitions to ensure that the number of logical qubits in each partition meets the QPU capacity constraint (2 bits per partition in this embodiment).

[0144] Step S25: Remove duplicates from the equalized candidate partitions and calculate according to formula (2). An evaluation is performed to obtain a set of candidate partitions. This embodiment selects those partitions that satisfy the capacity constraint and are consistent with... Figure 1 Continue execution if a consistent candidate partition is found: , .

[0145] Step S3: Global gate recognition and one-way state transfer construction

[0146] Step S31: In the selected candidate partition The next traversal of the two-qubit gate, if satisfying This is then determined to be a global gate, forming a set of global gates. Figure 1 The partition shown. The endpoints are located in different partitions and are all identified as global gates.

[0147] Step S32: Count the number of global gates according to formula (4) This embodiment yields .

[0148] Step S33: Use the first global gate in the quantum gate sequence as the anchor gate. Figure 1 The middle anchor point door is acceptable. Enumerating the anchor gate endpoint logic qubits as one-way moving logic qubits, this embodiment selects the moving endpoint as... The target partition is Within a preset window range, filter for "all endpoints except the mobile endpoint are located in..." The candidate global gate is then Satisfy its other endpoint Therefore, it was selected as a candidate for merger gate.

[0149] Step S34: Based on the gate exchangeability rule, determine whether the candidate global gate can be moved to the anchor gate through exchange and participate in the same one-way state transfer merging. In this embodiment, the line includes... and the aforementioned When the door is a diagonal door, the "strong commutability rule for diagonal doors" must be satisfied, allowing... Equivalent rearrangement is performed across diagonal gates and diagonal two-qubit gates within the window; simultaneously, the "selected gate ignore rule" is used to treat the set of gates already incorporated into the same one-way transfer as a whole for joint movement. This constructs... Figure 2 Medium batch One-way travel Execution combined in this one-way trip After completion, the remaining global gate set is then processed again, with the first one appearing as the anchor gate (in this embodiment, this can be taken as...). or Select mobile endpoint as And the target partition is Similarly, batches are constructed. One-way travel , merge execution After the above merging and equivalent rearrangement, we obtain Figure 2 The optimized route is shown.

[0150] Step S4: Pruning search to find the minimum number of one-way state transfers and the planned output.

[0151] Step S41: For the selected candidate partition P, a greedy strategy is used to prioritize the single-pass transfer sequence with the "maximum number of mergeable gates" to construct a feasible sequence. In this embodiment, the greedy strategy can obtain a feasible solution with two single-pass transfers, i.e. Figure 2 Given (B1, B2), we obtain the upper bound UB = 2.

[0152] Step S42: In the branch and bound search, define the set of remaining global gates at the root node as Grem={G02,G03,G13,G12}, with the number of gates R=|Grem|=4

[0153] Step S43: Calculate the number of endpoint participations: deg(q0)=2; deg(q1)=2; deg(q2)=2; deg(q3)=2

[0154] Step S44: Sort deg(q) in descending order to get deg1=deg2=deg3=deg4=2.

[0155] Step S45: Construct a simple lower bound LBsimple. In this embodiment, since a single-trip movement fixes one endpoint, and the number of global gates associated with that endpoint is at most 2, we can take M=2, thus obtaining... Step S46: Construct LB1. In this embodiment, the maximum number of global gates that can be merged in a single one-way transfer is set to Mmax=2.

[0156] Step S47: Construct the endpoint cover lower bound .make Then it satisfies The smallest It is 2 (because) Therefore . Step S48: Take When the number of one-way transfers formed by the search node is... At that time, if Then prune that branch; in this embodiment, the root node There is already and If they are equal, it can be directly determined that the two batches of solutions obtained by the greedy algorithm have reached the optimal level, thus terminating further development. Step S49: Output the minimum number of single-pass state transfers And calculate the number of round trips according to formula (11). The final output plan corresponds to... Figure 2 :batch move merge execution ,batch move merge execution Under the premise of ensuring the functional equivalence of the lines, compared to Figure 1 The method of triggering remote interaction for each global gate by the lieutenant general ( Figure 1 If the gate commutative rule is not adopted, the number of state transfers is obviously 8, which is reduced by 50%, significantly reducing the total number of state transfers.

[0157] Example 3: This example proposes an electronic system, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method steps of the present invention.

[0158] Example 4: This example proposes a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it implements the steps of the method described in this invention, which will not be repeated here.

[0159] Example 5: This example proposes a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, they implement the steps of the method described in this invention, which will not be repeated here.

[0160] It should be noted that the processing flow of embodiments 2-5 corresponds to the specific steps of the method provided in embodiment 1 of the present invention, and has the corresponding functional modules and beneficial effects of the method. Technical details not described in detail in this embodiment can be found in the method provided in embodiment 1 of the present invention.

[0161] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0162] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A distributed quantum circuit state transfer optimization method based on gate-switching pruning, characterized in that, Includes the following steps: Step S1: Quantum circuit analysis and data structure establishment; Step S2: Construction of weighted interaction graph and generation of candidate partition set; Step S3: Global gate identification and one-way state transfer construction; Step S4: Pruning search to find the minimum number of one-way state transfers and the planned output.

2. The distributed quantum circuit state transfer optimization method based on gate-switching pruning according to claim 1, characterized in that, Step S1 includes the following steps: Step S11: Obtain the quantum circuit to be executed and resolve it into a sequence of quantum gates arranged in chronological order. Record the gate type, the set of functional logic qubits for each quantum gate, and its index position in the quantum gate sequence. ; in: Represents a quantum gate, Representing quantum gates Position number in the sequence; Step S12: For each two-qubit gate Record its endpoint logical qubits and .

3. The distributed quantum circuit state transfer optimization method based on gate-switching pruning according to claim 1, characterized in that, Step S2 includes the following steps: Step S21: Construct a weighted interaction graph of logical qubits based on the quantum gate sequence: using logical qubits as nodes and logical qubit pairs with at least one two-qubit gate interaction as edges; logical qubits and The edge weights are calculated according to formula (1): （1）； in: Representing logical qubits and Interaction weights; Indicates the endpoint is A set of two-qubit gates; Represents a two-qubit gate The weight is taken when the gate type is not distinguished. ; Step S22: Construct a Laplace matrix for the weighted interaction graph and perform spectral embedding to obtain the eigenvector representation of each logical qubit; Step S23: Perform clustering in the spectral space to obtain multiple candidate partitioning schemes. ; in: Indicates the partitioning scheme; Step S24: Perform capacity equalization processing on the candidate partitioning schemes to ensure that the number of logical qubits in each partition meets the preset capacity constraints; Step S25: Deduplicate and filter the equalized candidate partitions and evaluate the candidate partitioning schemes using a cost function. The cost function is calculated according to formula (2): （2）； in, Partition scheme The value of the substitute; In the partition scheme The set of logical qubit pairs spanning the lower partition; Calculate cut weights Calculate according to formula (3): （3）； in: Represents the set of edges in a weighted interaction graph; Representing logical qubits The partition number; Representing logical qubits and They were assigned to different partitions.

4. The distributed quantum circuit state transfer optimization method based on gate-switching pruning according to claim 1, characterized in that, Step S3 includes the following steps: Step S31: For candidate partitioning schemes Traverse the two-qubit gates in the quantum gate sequence; when the following conditions are met... At this time, the two-qubit gate is determined to be a global gate, forming a set of global gates; Step S32: Calculate the global number of gates Calculate according to formula (4): （4）； in, The set of two-qubit gates in a quantum gate sequence; : Indicator function, returns 1 if the condition is true, otherwise returns 0; Indicates the partition number; Step S33: Construct a mergeable one-way transfer state: use the first global gate in the quantum gate sequence as the anchor gate; Enumerate the endpoint logical qubits of the anchor gate as one-way moving logical qubits and determine that they are moved to the target partition for execution; within a preset window interval, filter candidate global gates that are consistent with the target partition, wherein the other endpoint logical qubits of the candidate global gates, excluding the one-way moving logical qubits, are located in the same target partition; Step S34: Based on the gate exchange rule, determine whether the candidate global gate can be moved to the anchor gate through exchange, and merge the candidate global gates that meet the mobility and target partition into the same one-way transfer state.

5. The distributed quantum circuit state transfer optimization method based on gate-switching pruning according to claim 4, characterized in that, The gate commutative rules include: Diagonal gate strong commutativity rule: When two quantum gates to be determined are both diagonal gates, the two quantum gates are determined to be commutative, so as to allow the candidate global gate to move across the diagonal gate and participate in the same one-way transfer state merging; Selected gate ignore rule: When determining whether a candidate global gate is movable, the set of quantum gates that have been selected into the same one-way transfer state are ignored in the mobility detection, and the set of selected gates is regarded as a whole moving together.

6. The distributed quantum circuit state transfer optimization method based on gate-switching pruning according to claim 1, characterized in that, Step S4 includes the following steps: Step S41: For each candidate partitioning scheme Based on a greedy strategy, a feasible one-way transfer sequence is constructed to obtain the upper bound corresponding to the candidate partition. ; Step S42: During the branch and bound search process, define the set of remaining global gates for the current search node. The number of its gates Calculate according to formula (5): （5）； in: This represents the set of global gates that have not yet been covered under the current search node; Indicates the number of elements; Step S43: For each logical qubit Calculate the number of endpoint participations of each endpoint in the remaining global gate set. Calculate according to formula (6): （6）； in: Indicates counting; if global gate The endpoints are Then for and Each is incremented by 1; q is the endpoint of the global gate g; Step S44: All logical qubits Arranged in descending order, the sequence satisfies formula (7): （7）； in: Indicates the first The number of times large endpoints participate. The number of logical qubits; Step S45: Construct a simple lower bound :make As an optimistic upper bound for "the number of global gates that can be processed in a single batch", the minimum number of batches required for the remaining global gates is calculated according to formula (8): （8）； in: Indicates rounding up; To avoid Divide by zero; Step S46: Construct a lower bound based on the number of remaining global gates :make The maximum number of global gates that can be merged in a single, one-way transfer is calculated according to formula (9): （9）； in: ; This is the maximum number of elements that can be merged, either preset or obtained from rules. Step S47: Construct the endpoint cover lower bound Let d i= deg i Then calculate according to formula (10): （10）； in: The smallest positive integer that satisfies the covering condition; The number of times each endpoint participates after sorting; This represents the remaining number of global gates. Step S48: Pruning condition: During the search process, the number of one-way state transfers formed by the current node is recorded as follows: Get the lower bound of the current node ;when Prune the search branch as needed; Step S49: Output the minimum number of one-way state transfers after the search ends. And calculate the number of round trips according to formula (11). : （11）； in: This represents the minimum number of single-pass state transfers. The number of round trips is given; and steps S3 and S4 are executed for each candidate partition in the candidate partition set to obtain and output the partition scheme, the number of global gates, and the total number of round trips.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the computer program is executed, it implements the steps of the method as described in any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program is configured to implement the steps of the method according to any one of claims 1 to 6 when invoked by a processor.

9. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1 to 6.

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