A volatile memory device having grouped memory cells

Abstract

A volatile memory device comprising: a first chip comprising a sub word line drive (SWD) circuit that applies a word line enable voltage to activate one or more selected memory cells; and a second chip bonded to the first chip such that a surface of the first chip and a surface of the second chip are in contact with each other, the second chip comprising a first memory cell, a second memory cell, a first conductive line connecting the first memory cell to the SWD circuit, and a second conductive line connecting the second memory cell to the SWD circuit, wherein the first memory cell receives the first word line enable voltage, and wherein the second memory cell receives the second word line enable voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0192497, filed on December 20, 2024, with the Korean Intellectual Property Office, and all benefits thereof, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a volatile memory device having a group of memory cells. Background Technology

[0004] Recently, with the increasing multifunctionality and high performance of information and communication equipment, there is a demand for large-capacity and highly integrated memory devices. Various structures have been explored for forming memory cells, such as vertically stacking memory cells outside of planar structures, to achieve large capacity and high integration. Specifically, in three-dimensional structures where memory cells are stacked vertically relative to a substrate, the design of conductive lines connecting multiple memory cells to logic becomes more complex as the number of memory cells increases. For example, in the design of memory devices, the differences in RC components need to be considered based on the variations in the lengths of conductive lines of various lengths. Therefore, even if the same voltage can be applied to a memory cell, the amplitude of the voltage received by the transistor in the lower memory cell may be lower than the amplitude of the voltage received by the transistor in the upper memory cell. Summary of the Invention

[0005] The purpose of this disclosure is to provide a volatile memory device that improves power consumption and improves the reliability of stored data by compensating for the characteristic differences between memory cells caused by the differences in the RC components of conductive lines of various lengths.

[0006] The purposes of this disclosure are not limited to those mentioned above, and those skilled in the art will clearly understand from the following description of this disclosure any additional purposes not mentioned herein.

[0007] According to an aspect of this disclosure, a volatile memory device includes: a first chip including a sub-word line driving (SWD) circuit that applies a word line enable voltage to activate one or more selected memory cells; and a second chip coupled to the first chip such that the surfaces of the first chip and the second chip are in contact with each other, the second chip including: (i) a first memory cell, (ii) a second memory cell, (iii) a first conductive line connecting the first memory cell to the SWD circuit, and (iv) a second conductive line connecting the second memory cell to the SWD circuit, wherein the first memory cell receives the first word line enable voltage from the SWD circuit through the first conductive line, wherein the second memory cell receives a second word line enable voltage from the SWD circuit through the second conductive line, the second word line enable voltage having a voltage level higher than the first word line enable voltage, and the length of the second conductive line being longer than the length of the first conductive line.

[0008] According to an aspect of this disclosure, a volatile memory device includes: a first chip including a sub-word line drive (SWD) circuit that applies a word line enable voltage to activate one or more selected memory cells; and a second chip bonded to the first chip such that the surfaces of the first chip and the second chip are in contact with each other, the second chip including a substrate and a plurality of memory cells stacked in a first direction perpendicular to the substrate, wherein a first memory cell among the plurality of memory cells receives a first word line enable voltage from the SWD circuit, and wherein a second memory cell has a stacking level different from that of the first memory cell among the plurality of memory cells, wherein a second memory cell receives a second word line enable voltage from the SWD circuit, and wherein the second word line enable voltage has a voltage level different from that of the first word line enable voltage.

[0009] According to one aspect of this disclosure, a volatile memory device includes: a first chip including (i) a refresh controller that refreshes one or more selected memory cells according to a preset period, and (ii) a sub-word line drive (SWD) circuit that applies a word line enable voltage under the control of the refresh controller for refreshing one or more selected memory cells; and a second chip coupled to the first chip such that the surfaces of the first chip and the second chip are in contact with each other, the second chip including: (i) a first memory cell, (ii) a second memory cell, (iii) a first conductive line connecting the first memory cell to the SWD circuit, and (iv) a second conductive line connecting the second memory cell to the SWD circuit, wherein the refresh controller refreshes the first memory cell at a first period by controlling the SWD circuit, wherein the refresh controller refreshes the second memory cell at a second period shorter than the first period by controlling the SWD circuit, and wherein the length of the second conductive line is longer than the length of the first conductive line.

[0010] Details of other embodiments are included in the detailed description and the accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a memory system according to one or more embodiments.

[0012] Figure 2 This illustrates one or more embodiments. Figure 1 A block diagram of a memory device.

[0013] Figure 3 This is a diagram illustrating a memory device with a three-dimensional structure according to one or more embodiments.

[0014] Figure 4 This is a plan view showing a first chip according to one or more embodiments.

[0015] Figure 5 This is a circuit diagram illustrating a second chip according to one or more embodiments.

[0016] Figure 6 This is a plan view showing a second chip according to one or more embodiments.

[0017] Figure 7 This is a perspective view showing a second chip according to one or more embodiments.

[0018] Figure 8 This is a circuit diagram illustrating a grouping method based on the height difference between memory cells according to one or more embodiments.

[0019] Figure 9 This is a circuit diagram illustrating a grouping method based on the height difference between memory cells according to one or more embodiments.

[0020] Figure 10 This is a diagram illustrating a method of providing different word line enable voltages to each group of memory cells according to one or more embodiments.

[0021] Figure 11 This is a diagram illustrating a method for performing a refresh operation by changing the period of each group of memory cells according to one or more embodiments.

[0022] Figure 12 This is a plan view showing a second chip according to one or more embodiments.

[0023] Figure 13 This is a perspective view showing a second chip according to one or more embodiments.

[0024] Figure 14This is a plan view illustrating a grouping method based on the overlapping relationship between regions according to one or more embodiments. Detailed Implementation

[0025] In the following description, embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0026] It should be understood that although the terms first, second, third, fourth, etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0027] It should be understood that when a component or layer is referred to as being "above," "on top," "above," "below," "under," "connected to," or "coupled to" another component or layer, it can be directly above, above, below, under, or connected to the other component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as being "directly above," "directly above," "directly on," "directly on," "directly below," "directly under," "directly connected to," or "directly coupled to," there are no intermediate components or layers.

[0028] A layer can be described as having an upper surface and a lower surface. As will be understood by those skilled in the art, the surface of a layer can also be described as a first surface and a second surface, wherein the first surface can be one of the upper surface and the lower surface of the layer, and the second surface can be the other of the upper surface and the lower surface of the layer.

[0029] As used herein, the term “connected” or “connecting” is intended to cover both direct connections between two elements and indirect connections in which one or more intermediate elements, devices, or structures may be inserted. Unless otherwise specified, a description of one element being “connected” to another element includes cases where the elements are in direct physical or electrical contact as well as cases where the elements are operatively coupled through one or more intermediate components.

[0030] Figure 1 This is a block diagram illustrating a memory system according to one or more embodiments.

[0031] refer to Figure 1The memory system 1 may include an external host 20 and a memory storage device 10. The memory storage device 10 may include a memory device 200 and a memory controller 1000.

[0032] The memory controller 1000 can control the overall operation of the memory device 200. For example, the memory controller 100 can control the data exchange between the external host 20 and the memory device 200. For example, the memory controller 100 can control the memory device 200 to write or read data according to the request of the external host 20.

[0033] The memory controller 100 and the memory device 200 can communicate with each other via a memory interface MEM I / F. In one or more examples, the memory controller 100 and the external host 20 can communicate with each other via a host interface. That is, the memory controller 100 can relay signals between the memory device 200 and the external host 20. The memory controller 100 can control the operation of the memory device 200 by applying a command CMD for controlling the memory device 200. In this case, the memory device 200 may include dynamic memory cells. For example, the memory device 200 may include dynamic random access memory (DRAM), double data rate 4 (DDR4), synchronous DRAM (SDRAM), low power DDR4 (LPDDR4) SDRAM, or LPDDR5 SDRAM, but embodiments according to the spirit of this disclosure are not limited thereto. The memory device 200 may include a non-volatile memory device. However, in this embodiment, the memory device 200 will be described as a volatile memory device.

[0034] The memory controller 100 can send clock signals CLK, command CMD, address ADDR signals, etc., to the memory device 200. The memory controller 100 can provide data DQ to the memory device 200 and receive data DQ from the memory device 200. The memory device 200 may include a memory cell array 280 for storing data DQ, control logic circuitry 210, and a data input / output buffer 295.

[0035] Figure 2 This illustrates one or more embodiments. Figure 1 A block diagram of a memory device.

[0036] refer to Figure 2The memory device 200 may include, for example, control logic circuitry 210, address register 220, bank control logic circuitry 230, row address multiplexer 240, refresh controller 245, column address latch 250, bank row decoder 260, column decoder 270, memory cell array 280, sense amplifier 285, input / output gating circuit 290, and data input / output buffer 295.

[0037] The memory cell array 280 may include multiple memory bank arrays 280a to 280h. Although Figure 2 The memory cell array 280 shown includes eight memory bank arrays 280a to 280h, but this disclosure is not limited thereto.

[0038] Each of the multiple memory bank arrays 280a to 280h may include multiple word lines WL, multiple bit lines BL, and multiple memory cells MC formed at the points where the word lines WL and bit lines BL intersect each other.

[0039] Control logic circuit 210 can control the operation of memory device 200. For example, control logic circuit 210 can generate control signals to cause memory device 200 to perform write or read operations. Control logic circuit 210 may include command decoder 211 for decoding commands CMD received from memory controller 100 and mode register 212 for setting the operating mode of memory device 200.

[0040] The row address multiplexer 240 may include multiple memory bank row decoders 260a to 260h, each connected to a plurality of memory bank arrays 280a to 280h. The column decoder 270 may include multiple column decoders 270a to 270h, each connected to a plurality of memory bank arrays 280a to 280h. The sense amplifier 285 may include multiple sense amplifiers 285a to 285h, each connected to a plurality of memory bank arrays 280a to 280h.

[0041] Address register 220 can be accessed from the memory controller ( Figure 1 Address register 220 receives address ADDR, which includes bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR. Address register 220 can provide the received bank address BANK_ADDR to bank control logic circuit 230, provide the received row address ROW_ADDR to row address multiplexer 240, and provide the received column address COL_ADDR to column address latch 250.

[0042] The memory bank control logic circuit 230 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, the memory bank row decoder corresponding to the memory bank address BANK_ADDR among the plurality of memory bank row decoders 260a to 260h can be activated, and the column decoder corresponding to the memory bank address BANK_ADDR among the plurality of column decoders 270a to 270h can be activated.

[0043] The refresh controller 245 can perform a refresh operation in response to a refresh command received from the control logic circuit 210. For example, the refresh controller 245 can perform a refresh operation on a memory cell selected according to a set refresh period TREF. In one or more examples, the refresh controller 245 can output a refresh address REF_ADDR for refresh.

[0044] The row address multiplexer 240 can receive the row address ROW_ADDR from the address register 220 and the refresh address REF_ADDR from the refresh controller 245. The row address multiplexer 240 can selectively output either the row address ROW_ADDR or the refresh address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 can be applied to each of the multiple memory bank row decoders 260a to 260h.

[0045] Among the multiple bank row decoders 260a to 260h, the bank row decoder activated by the bank control logic circuit 230 can decode the row address RA output from the row address multiplexer 240 to activate the word line corresponding to the row address. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address.

[0046] Column address latch 250 can receive column address COL_ADDR from address register 220 and can temporarily store the received column address COL_ADDR. Column address latch 250 can gradually increment the received column address COL_ADDR in burst mode. Column address latch 250 can apply the temporarily stored column address COL_ADDR or the gradually incremented column address COL_ADDR to each of the multiple column decoders 270a to 270h.

[0047] The column decoders 270a to 270h activated by the memory bank control logic circuit 230 can activate the sense amplifiers corresponding to the memory bank address BANK_ADDR and the column address COL_ADDR through the corresponding input / output gate circuit 290.

[0048] The input / output gating circuit 290 may include input data masking logic, a read data latch for storing data output from multiple memory bank arrays 280a to 280h, a write driver for writing data into the multiple memory bank arrays 280a to 280h, and circuitry for gating input / output data.

[0049] Data DQ to be read from one of the multiple memory bank arrays 280a to 280h can be sensed by a sense amplifier (e.g., one of 285a to 285h) corresponding to one of the memory bank arrays and stored in a read data latch. The data DQ stored in the read data latch can be provided to the memory controller 100 through a data input / output buffer 295.

[0050] Data DQ to be written to one of the multiple memory bank arrays 280a to 280h can be provided to the input / output gate circuit 290, and the input / output gate circuit 290 can write data to a memory bank array via a write driver.

[0051] The memory cell MC can be, for example, a DRAM memory cell. Each memory cell MC can be connected to a word line WL and a bit line BL. The memory cell MC can store charge through a cell capacitor. Because leakage current occurs in the memory cell MC due to its structure, the data stored in the cell capacitor may be corrupted.

[0052] Therefore, the memory device 200 can perform a refresh operation to recharge the data in the memory cell MC to prevent the data stored in the memory cell MC from being changed due to leakage current.

[0053] Memory device 200 may have a three-dimensional structure. For example, memory device 200 may have a chip-to-chip (C2C) structure. A C2C structure may refer to manufacturing a chip including a cell region, manufacturing a chip including a peripheral circuit region, and then stacking the two chips to connect them to each other. For example, the cell region may include a memory cell array 280. The peripheral circuit region may include control logic circuitry 210, address register 220, memory bank control logic circuitry 230, row address multiplexer 240, column address latch 250, memory bank row decoder 260, column decoder 270, sense amplifier 285, input / output gating circuitry 290, data input / output buffer 295, etc., but the invention is not limited thereto. Each of the cell region and the peripheral circuit region may further include different components, or some of the components may be omitted.

[0054] Figure 3 This is a diagram showing the three-dimensional structure of a memory device.

[0055] refer to Figure 3 The memory device 200 can be manufactured by bonding pads formed on the bottommost metal layer of the first chip 300 to bonding pads formed on the topmost metal layer of the second chip 400 to make contact with each other. For example, when the bonding pads are formed of copper (Cu), the bonding method can be a Cu-Cu bonding method, and the bonding pads can also be formed of aluminum or tungsten. In Cu-Cu bonding, the two copper surfaces can be directly bonded without solder or other bonding agents. Cu-Cu bonding can be performed using thermocompression bonding or surface activation bonding. The first chip 300 may include cell regions, and the second chip 400 may include peripheral circuit regions. However, according to embodiments of the present disclosure, the first chip 300 may include peripheral circuit regions, and the second chip 400 may include cell regions, but the present disclosure is not limited thereto. Hereinafter, for ease of description, the description will be based on the first chip 300 including peripheral circuit regions and the second chip 400 including cell regions. As will be understood by those skilled in the art, the embodiments are not limited to Cu-Cu bonding. For example, a metal-to-metal hybrid bonding process can be used to bond the first chip 300 and the second chip 400. This metal-to-metal hybrid bonding process may include forming a bond between the two metals by fusing embedded metal pads in the bonding interface. This bonding technique advantageously enables heterogeneous integration to connect two components with different functions and sizes.

[0056] Figure 4 This is a plan view showing a first chip according to one or more embodiments.

[0057] refer to Figure 4 The bit-line sense amplifier (BLSA) circuit 310 and the sub word-line driver (SWD) circuit 320 can be arranged in a portion of the first chip 300.

[0058] BLSA circuit 310 can correspond to Figure 2 The sensing amplifier 285 described herein. The BLSA circuit 310 can sense data stored in the memory cell array, amplify the voltage corresponding to the sensed data, and output the amplified data to the external device in response to a request from an external device.

[0059] SWD circuitry 320 may include a plurality of sub-word line drivers (SWDs) capable of driving a plurality of sub-word lines. SWD circuitry 320 may activate a sub-word line selected in response to a word line drive signal and a word line enable signal. In this disclosure, the term 'sub-word line' may be used interchangeably with the term 'word line'.

[0060] SWD circuit 320 can apply a word line enable voltage VPP, higher than the supply voltage VDD, to a selected word line based on a word line drive signal (e.g., PXID) and a word line enable signal (e.g., NWEI). SWD circuit 320 can apply word line enable voltage VPP to a selected word line to activate the corresponding word line (or the memory cell connected to the corresponding word line).

[0061] Figure 5 This is a circuit diagram illustrating a second chip according to one or more embodiments.

[0062] refer to Figure 5 The second chip may include multiple memory cells MC. Each memory cell may include a unit transistor TR and a data storage element CAP. Although Figure 5 Eight memory cells are shown, but this is for ease of description, and the number of memory cells is not limited to eight. As will be understood by those skilled in the art, the number of memory cells may be more or less than eight. Cell transistors TR and data storage elements CAP may be connected in series. Bit lines may be conductive patterns (e.g., metallic conductive lines) extending in the vertical direction Z. Bit lines may be spaced apart from each other along a first horizontal direction Y and a second horizontal direction X. The first horizontal direction Y and the second horizontal direction X may intersect each other. The first horizontal direction Y, the second horizontal direction X, and the vertical direction Z may intersect each other. Hereinafter, the lower part, upper part, lower surface, and upper surface are defined based on the vertical direction Z.

[0063] Bit lines may include a first local bit line LBL1, a second local bit line LBL2, and a global bit line GBL. Although in Figure 5 The diagram shows two local bit lines and one global bit line, but this is for ease of description, and the number of bit lines is not limited to those shown. Local bit lines LBL1 and LBL2 may be spaced apart from each other along the second horizontal direction X.

[0064] Some bit lines can be connected to each other via global bit lines (GBL). For example, local bit lines LBL1 and LBL2, which are spaced apart from each other along the second horizontal direction X, can be connected to each other via global bit lines (GBL).

[0065] The horizontal conductive line HCL can be a conductive pattern (e.g., a metallic conductive line) extending from each memory cell MC in a first horizontal direction Y. The horizontal conductive line HCL can be a portion of a word line connecting logic circuitry (e.g., SWD circuit 320) to each memory cell MC. Word line pads WP connecting the vertical conductive line extending from the upper surface of the second chip along the vertical direction Z to the horizontal conductive line HCL can be formed at the ends of each horizontal conductive line HCL. To connect the vertical conductive line extending from the upper surface of the second chip 400 along the vertical direction Z to the memory cells vertically stacked on the substrate, the horizontal conductive line HCL can have a stepped structure. However, the structure suggested above is an example of a three-dimensional memory cell structure, and each memory cell and conductive line can be formed in different structures.

[0066] A horizontal conductive line HCL can be connected to the gate of the cell transistor TR in each memory cell MC. The first source / drain of the cell transistor TR can be connected to the data storage element CAP, and the second source / drain of the cell transistor TR can be connected to the bit line. The data storage element CAP can be a capacitor or a variable resistor. In the following description, for ease of description, it is assumed that the data storage element CAP is a capacitor.

[0067] Figure 6 This is a plan view showing a second chip according to one or more embodiments.

[0068] refer to Figure 6 The memory cell region CELL 410 and the conductive line region CLA 420 can be arranged in a portion of the second chip 400. When the surfaces of the first chip 300 and the second chip 400 are engaged with each other in a contact manner, the memory cell region 410 can... Figure 4 The conductive line region 420 at least partially overlaps with the BLSA circuit 310 on the first chip 300 in the vertical direction Z. In one or more examples, when the surfaces of the first chip 300 and the second chip 400 are bonded to each other, the conductive line region 420 may at least partially overlap with the SWD circuit 320 on the first chip 300 in the vertical direction Z. Figure 4 The first chip 300 and Figure 6The areas shown in the same shaded pattern in the second chip 400 indicate their overlapping relationship. When the second chip 400 is viewed in the vertical direction Z, a plurality of memory cells and bit lines vertically stacked on the substrate in the second chip 400 can be arranged in the memory cell region 410, and when the second chip 400 is viewed in the vertical direction Z, word line pads WP formed at the ends of the horizontal conductive lines extending from each memory cell in the first horizontal direction Y can be arranged in the conductive line region 420. That is, a plurality of memory cells and bit lines vertically stacked on the substrate in the second chip 400 can overlap with the memory cell region 410 in the vertical direction Z, and word line pads WP formed at the ends of the horizontal conductive lines extending from each memory cell in the first horizontal direction Y can overlap with the conductive line region 420 in the vertical direction Z.

[0069] Figure 7 This is a perspective view showing a second chip according to one or more embodiments.

[0070] refer to Figure 7 Multiple bonding pads BP can be arranged on the upper part of the second chip 400. For ease of description, it is assumed that the first chip 300 and the second chip 400 are connected to each other by bonding pads, but this disclosure is not limited thereto. When the first chip 300 and the second chip 400 are bonded to each other in a manner that they are in contact with each other, the bonding pads BP of the second chip 400 can contact the bonding pads of the first chip 300 to connect the second chip 400 to the first chip 300. Although the bonding pads BP are shown as being arranged on the conductive line region 420 of the second chip 400, this is merely exemplary, and the bonding pads BP can be arranged anywhere on the upper part of the second chip 400. Vertical conductive lines VCL can extend from the bonding pads BP of the second chip 400 in the vertical direction Z, and thus can be connected to the word line pads WP. Figure 7 In the diagram, the vertical conductive line VCL is shown extending in the vertical direction Z; however, this configuration is for ease of description and for design reasons, each vertical conductive line VCL may include a portion extending in the first horizontal direction Y or the second horizontal direction X.

[0071] Multiple memory cells MC of the second chip 400 can be connected to bonding pads BP via corresponding horizontal conductive lines HCL and corresponding vertical conductive lines VCL. The length of the corresponding conductive line connecting a memory cell MC to its corresponding bonding pad BP can be defined as the sum of the lengths of the corresponding horizontal conductive line HCL and the corresponding vertical conductive line VCL. In this case, the length of the horizontal conductive line HCL corresponding to a memory cell MC can be defined as the length of the line extending from the cell transistor to the word line pad WP. In one or more examples, the length of the vertical conductive line VCL corresponding to a memory cell MC can be defined as the length of the line extending from the word line pad WP to the bonding pad BP.

[0072] As memory cells become highly integrated, the length of the conductive lines connecting the memory cells to the logic tends to increase, and the thickness of the conductive lines tends to decrease. With the increase in the length and thickness of the conductive lines, the size of the RC component generated on the conductive lines also increases. For example, when the same word line enable voltage is applied to two memory cells with conductive lines of different lengths, the magnitude of the voltage received by the gates of the two memory cells may differ due to the RC component.

[0073] Figure 8 This is a circuit diagram illustrating a grouping method based on the height difference between memory cells according to one or more embodiments.

[0074] refer to Figure 8 Multiple memory cells MC1 to MC8 can be stacked on the substrate 430 of the second chip 400 in the vertical direction Z. Therefore, the stacking levels of the multiple memory cells MC1 to MC8 can be different. For example, the first memory cell MC1 and the second memory cell MC2 can have the same stacking level or a different stacking level than the other memory cells. Furthermore, the third memory cell MC3 and the fourth memory cell MC4 can have the same stacking level or a different stacking level than the other memory cells. The height of each memory cell in the vertical direction Z can vary depending on the stacking level. For example, the distance D1 between the first memory unit MC1 and the second memory unit MC2 and the upper part 440 of the second chip 400 can be the shortest of all distances; the distance D2 between the third memory unit MC3 and the fourth memory unit MC4 and the upper part 440 of the second chip 400 can be the second shortest of all distances; the distance D3 between the fifth memory unit MC5 and the sixth memory unit MC6 and the upper part 440 of the second chip 400 can be the third shortest of all distances; and the distance D4 between the seventh memory unit MC7 and the eighth memory unit MC8 and the upper part 440 of the second chip 400 can be the longest of all distances.

[0075] The distance D5 between the first memory cell MC1 and the second memory cell MC2 and the substrate 430 of the second chip 400 can be the longest of all distances; the distance D6 between the third memory cell MC3 and the fourth memory cell MC4 and the substrate 430 of the second chip 400 can be the second longest of all distances; the distance D7 between the fifth memory cell MC5 and the sixth memory cell MC6 and the substrate 430 of the second chip 400 can be the third longest of all distances; and the distance D8 between the seventh memory cell MC7 and the eighth memory cell MC8 and the substrate 430 of the second chip 400 can be the shortest of all distances.

[0076] According to some embodiments, multiple memory cells MC1 to MC8 can be grouped depending on the stacking level. For example, a first memory cell MC1 and a second memory cell MC2 having a shortest distance D1 to the upper portion 440 of the second chip 400, and a third memory cell MC3 and a fourth memory cell MC4 having a second shortest distance D2 to the upper portion 440 of the second chip 400, can be grouped into a first group GR1. Furthermore, a seventh memory cell MC7 and an eighth memory cell MC8 having a longest distance D4 to the upper portion 440 of the second chip 400, and a fifth memory cell MC5 and a sixth memory cell MC6 having a second longest distance D3 to the upper portion 440 of the second chip 400, can be grouped into a second group GR2.

[0077] Since the memory cell can be further away from the top of the bonding pads in the second chip 400, the length of the vertical conductive line corresponding to the corresponding memory cell can be longer. In one or more examples, since the horizontal conductive line has a stepped structure, the length of the horizontal conductive line corresponding to the corresponding memory cell can be longer as the distance from the top of the bonding pads in the second chip 400 increases. Therefore, the length of the conductive line corresponding to the corresponding memory cell can be longer as the memory cell is further away from the top of the bonding pads in the second chip 400. That is, the length of the conductive line belonging to the memory cell in the second group GR2 can be longer than the length of the conductive line belonging to the memory cell in the first group GR1.

[0078] Figure 9 This is a circuit diagram illustrating a grouping method based on the height difference between memory cells according to one or more embodiments.

[0079] refer to Figure 9 ,and Figure 8Unlike other memory cells, MC1 through MC8 can be grouped into three or more groups depending on the stacking hierarchy. For example, a first memory cell MC1 and a second memory cell MC2, having a shortest distance D1 to the upper portion 440 of the second chip 400, can be grouped into a first group GR1. In one or more examples, a third memory cell MC3 and a fourth memory cell MC4, having a second shortest distance D2 to the upper portion 440 of the second chip 400, can be grouped into a second group GR2. In one or more examples, a fifth memory cell MC5 and a sixth memory cell MC6, having a second longest distance D3 to the upper portion 440 of the second chip 400, can be grouped into a third group GR3. In one or more examples, a seventh memory cell MC7 and an eighth memory cell MC8, having a longest distance D4 to the upper portion 440 of the second chip 400, can be grouped into a fourth group GR4.

[0080] Figure 10 This is a diagram illustrating a method of providing different word line enable voltages to each group of memory cells according to one or more embodiments.

[0081] refer to Figure 10 SWD circuits (e.g., Figure 4 The SWD circuit 320 can apply different group-specific voltages to memory cells belonging to different groups. For example, the SWD circuit can apply a word line enable voltage VPP with different amplitudes specific to the group to a selected word line based on the word line drive signal and the word line enable signal.

[0082] Suppose, for example, that multiple memory cells MC1 to MC8 are grouped into four groups GR1 to GR4 depending on the stacking levels. Therefore, memory cells belonging to the group that is relatively far from the upper part of the second chip, where the bonding pads are arranged, can have a relatively large RC component of the conductive lines compared to memory cells belonging to the group that is relatively close to the upper part of the second chip.

[0083] According to some embodiments, the SWD circuit can apply a first word line enable voltage VPP1 to memory cells belonging to a first group GR1, a second word line enable voltage VPP2 to memory cells belonging to a second group GR2, a third word line enable voltage VPP3 to memory cells belonging to a third group GR3, and a fourth word line enable voltage VPP4 to memory cells belonging to a fourth group GR4. In this case, when the fourth word line enable voltage VPP4 has a voltage level equal to the voltage level of VPP, for example, the third word line enable voltage VPP3 may have a voltage level of approximately VPP-50mV, the second word line enable voltage VPP2 may have a voltage level of approximately VPP-100mV, and the first word line enable voltage VPP1 may have a voltage level of approximately VPP-150mV. The voltage levels of each of the above word line enable voltages VPP1 to VPP4 are exemplary, but not limited thereto.

[0084] Even if the SWD circuit applies the same word line enable voltage to each word line, the magnitude of the voltage transferred to the gate of each memory cell can vary depending on the stack level. For example, when the level of the word line enable voltage applied to activate memory cells belonging to the fourth group GR4 is VPP, memory cells belonging to the first group GR1 can be activated even if the word line enable voltage has a lower voltage level than VPP. Therefore, according to some embodiments, word line enable voltages with different voltage levels can be applied to each group, enabling the provision of memory devices with improved power consumption.

[0085] Figure 11 This is a diagram illustrating a method for performing a refresh operation by changing the period of each group of memory cells according to one or more embodiments.

[0086] refer to Figure 11 Refresh the controller (e.g., Figure 2 The refresh controller 245 can perform refresh operations on memory cells belonging to different groups by changing the cycle of each memory cell group. In this case, the refresh controller can perform refresh operations on memory cells belonging to different groups by controlling the SWD circuit, and a cycle can mean the time required to refresh a specific memory cell again after refreshing a specific memory cell.

[0087] Suppose, for example, that multiple memory cells MC1 to MC8 are grouped into four groups GR1 to GR4 depending on the stacking levels. Therefore, memory cells belonging to the group that is relatively far from the upper part of the second chip, where the bonding pads are arranged, can have a relatively large RC component of the conductive lines compared to memory cells belonging to the group that is relatively close to the upper part of the second chip.

[0088] According to some embodiments, the refresh controller can refresh memory cells belonging to the first group GR1 in a first cycle tREF1, refresh memory cells belonging to the second group GR2 in a second cycle tREF2, refresh memory cells belonging to the third group GR3 in a third cycle tREF3, and refresh memory cells belonging to the fourth group GR4 in a fourth cycle tREF4. In this case, the second cycle tREF2 can be half of the first cycle tREF1, the third cycle tREF3 can be half of the second cycle tREF2, and the fourth cycle tREF4 can be half of the third cycle tREF3. Each of the above cycles is merely an example, and the embodiments are not limited to these configurations.

[0089] Due to the difference in RC components caused by the difference in the length of the conductive lines, data storage elements (e.g., capacitors, etc.) belonging to the group of memory cells relatively far from the upper part of the second chip, compared to data storage elements belonging to the group of memory cells relatively close to the upper part of the second chip, may be more susceptible to current leakage. Therefore, according to some embodiments, the refresh cycle of memory cells belonging to the group of memory cells relatively far from the upper part of the second chip can be set to be shorter than the refresh cycle of memory cells belonging to the group relatively close to the upper part of the second chip, thereby providing a memory device with improved reliability of stored data.

[0090] Figure 12 This is a plan view showing a second chip according to one or more embodiments.

[0091] In Figure 12 Chinese omission of pairs Figure 6 A detailed description of the redundant parts described herein. (See reference) Figure 12 The memory cell region 410 and the conductive line region may be arranged in a portion of the second chip 400. The conductive line region may be divided into a first conductive line region 450 and a second conductive line region 460. When the surfaces of the first chip 300 and the second chip 400 are bonded together in a contact manner, the memory cell region 410 may at least partially overlap with the BLSA circuit 310 on the first chip 300 in the vertical direction Z. In one or more examples, when the surfaces of the first chip 300 and the second chip 400 are bonded together in a contact manner, the conductive line region may at least partially overlap with the SWD circuit 320 on the first chip 300 in the vertical direction Z.

[0092] In this case, the area of ​​the conductive line region that overlaps with the SWD circuit 320 in the vertical direction Z can be defined as the first conductive line region 450, and the area of ​​the conductive line region that does not overlap with the SWD circuit 320 in the vertical direction Z can be defined as the second conductive line region 460.

[0093] When the second chip 400 is viewed in the vertical direction Z, a plurality of memory cells and bit lines on the substrate stacked vertically in the second chip 400 can be arranged in the memory cell region 410, and when the second chip 400 is viewed in the vertical direction Z, word line pads WP formed at the ends of horizontal conductive lines extending from each memory cell in the first horizontal direction Y can be arranged in the first conductive line region 450 and the second conductive line region 460.

[0094] Figure 13 This is a perspective view showing a second chip according to one or more embodiments.

[0095] In Figure 13 Chinese omission of pairs Figure 7 A detailed description of the redundant parts described herein. (See reference) Figure 13 Multiple bonding pads BP can be arranged on the upper part of the second chip 400. When the first chip 300 and the second chip 400 are bonded to each other in a contacting manner, the bonding pads BP of the second chip 400 can connect the second chip 400 to the first chip 300 in a contacting manner with the bonding pads of the first chip 300. Although the bonding pads BP are shown as being arranged on the first conductive line region 450 of the second chip 400, this is an example, and the bonding pads BP can be arranged anywhere on the upper part of the second chip 400. Vertical conductive lines VCL can extend from the bonding pads BP of the second chip 400 in the vertical direction Z and thus connect to the word line pads WP. Although the vertical conductive lines VCL are shown as extending precisely in the vertical direction Z, this is for ease of description, and for design reasons, each vertical conductive line VCL can partially include the portion extending in the first horizontal direction Y or the second horizontal direction X. Multiple memory cells MC of the second chip 400 can be connected to the bonding pads BP respectively via corresponding horizontal conductive lines HCL and corresponding vertical conductive lines VCL.

[0096] With the increasing capacity and high integration of memory devices, there is a need to reduce the area occupied by various logic circuits arranged in the first chip 300. Therefore, the area occupied by the SWD circuits in the first chip 300 may also be limited. As a result, some word line pads can be arranged without overlapping with the SWD circuits in the vertical direction Z. For example, when the second chip 400 is viewed in the vertical direction Z, the first word line pad set WPS1 can be arranged in the first conductive line region 450, and the first word line pad set WPS1 can overlap with the SWD circuits in the vertical direction Z. When the second chip 400 is viewed in the vertical direction Z, the second word line pad set WPS2 can be arranged in the second conductive line region 460, and the second word line pad set WPS2 can be arranged without overlapping with the SWD circuits in the vertical direction Z.

[0097] Since the word line pads included in the second word line pad set WPS2 do not overlap with the SWD circuit in the vertical direction Z, the vertical conductive lines connected to the corresponding word line pads need to extend relatively long in either the first horizontal direction Y or the second horizontal direction X. On the other hand, since the word line pads included in the first word line pad set WPS1 overlap with the SWD circuit in the vertical direction Z, the vertical conductive lines connected to the corresponding word line pads can extend relatively short in either the first horizontal direction Y or the second horizontal direction X, or can extend only in the vertical direction Z. Therefore, the length of the conductive lines connected to the word line pads included in the second word line pad set WPS2 can be relatively longer than the length of the conductive lines connected to the word line pads included in the first word line pad set WPS1.

[0098] Figure 14 This is a plan view illustrating a grouping method based on the overlapping relationship between regions according to one or more embodiments.

[0099] In Figure 14 Chinese omission of pairs Figure 6 and Figure 12 A detailed description of the redundant parts described herein. (See reference) Figure 14 The word line pads arranged in the first conductive line region 450 and the memory cells connected to the corresponding word line pads can be grouped into a first group GR1. The word line pads arranged in the second conductive line region 460 and the memory cells connected to the corresponding word line pads can be grouped into a second group GR2.

[0100] As described above, the first conductive line region 450 may be a region that overlaps with the SWD circuit in the vertical direction Z, and the second conductive line region 460 may be a region that does not overlap with the SWD circuit in the vertical direction Z. Therefore, including... Figure 13The word line pads in the first word line pad set WPS1 can overlap with the first conductive line region 450 in the vertical direction Z. On the other hand, including Figure 13 The word line pads in the second word line pad set WPS2 can overlap with the second conductive line region 460° in the vertical direction Z. For the above reasons, the length of the conductive lines of the memory cells belonging to the second group GR2 can be longer than the length of the conductive lines of the memory cells belonging to the first group GR1.

[0101] Reference Figure 14 and Figure 10 They will be described together. According to some embodiments, the SWD circuit can apply a first word line enable voltage VPP1 to memory cells belonging to the first group GR1 and a second word line enable voltage VPP2 to memory cells belonging to the second group GR2. The voltage level of the first word line enable voltage VPP1 can be lower than the voltage level of the second word line enable voltage VPP2.

[0102] Even if the SWD circuit applies the same word line enable voltage to each word line, the magnitude of the voltage transferred to the gate of each memory cell can differ due to variations in the length of the conductive line structure. For example, suppose the word line enable voltage applied to activate memory cells belonging to the second group GR2 is VPP. In this case, memory cells belonging to the first group GR1 can be sufficiently activated even if the word line enable voltage has a voltage level lower than VPP. Therefore, according to some embodiments, word line enable voltages with different voltage levels can be applied to each group, enabling the provision of memory devices with improved power consumption.

[0103] Reference Figure 14 and Figure 11 They will be described together. According to some embodiments, the refresh controller can refresh memory cells belonging to the first group GR1 in a first cycle tREF1 and refresh memory cells belonging to the second group GR2 in a second cycle tREF2. In this case, the second cycle tREF2 can be half of the first cycle tREF1. Each cycle described above is an example and is not a limitation.

[0104] Due to the difference in the RC component based on the difference in the length of the conductive lines, the data storage elements (e.g., capacitors) of memory cells belonging to the second group GR2 may be more susceptible to current leakage than the data storage elements of memory cells belonging to the first group GR1. Therefore, the refresh cycle of the memory cell connected to the word line pad that overlaps with the second conductive line region 460 in the vertical direction Z can be set to be shorter than the refresh cycle of the memory cell connected to the word line pad that overlaps with the first conductive line region 450 in the vertical direction Z, thereby providing a memory device with improved reliability of stored data.

[0105] Although some embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to these embodiments and can be implemented in various different forms. Those skilled in the art to which this disclosure pertains will understand that the present disclosure can be implemented in other specific forms without altering the technical concept or essential features of the disclosure. Therefore, it should be understood that the embodiments described above are illustrative in all respects rather than limiting.

Claims

1. A volatile memory device, comprising: The first chip includes a sub-word line driver SWD circuit, which applies a word line enable voltage to activate one or more selected memory cells. and A second chip is bonded to the first chip such that the surfaces of the first chip and the second chip are in contact with each other, the second chip comprising: First memory unit; Second memory unit; A first conductive line connects the first memory cell to the SWD circuit; and The second conductive line connects the second memory cell to the SWD circuit. The first memory cell receives the first word line enable voltage from the SWD circuit via the first conductive line. The second memory cell receives a second word line enable voltage from the SWD circuit via the second conductive line. This second word line enable voltage has a voltage level higher than the first word line enable voltage. The length of the second conductive wire is longer than the length of the first conductive wire.

2. The volatile memory device according to claim 1, wherein, The distance from the surface of the second chip to the first memory cell in a first direction perpendicular to the second chip is shorter than the distance from the surface of the second chip to the second memory cell in the first direction.

3. The volatile memory device according to claim 2, wherein, The second chip also includes: The first memory cell group includes a plurality of memory cells containing the first memory cells; and The second memory cell group includes a plurality of memory cells containing the second memory cells, and Wherein, each distance from the surface of the second chip to each of the plurality of memory cells in the first memory cell group in the first direction is shorter than each distance from the surface of the second chip to each of the plurality of memory cells in the second memory cell group in the first direction.

4. The volatile memory device according to claim 1, wherein, The second chip also includes a substrate. The first memory cell and the second memory cell are stacked on the substrate in a first direction perpendicular to the substrate, and the height of the first memory cell on the substrate in the first direction is higher than the height of the second memory cell on the substrate in the first direction.

5. The volatile memory device according to claim 1, wherein, The second chip also includes: The first conductive line region overlaps with the SWD circuit in a first direction perpendicular to the second chip; and The second conductive line region does not overlap with the SWD circuit in the first direction. The first conductive line includes: A first horizontal conductive line extends from the first unit transistor in a second direction intersecting the first direction; and The first letter pad is located at the end of the first horizontal conductive line. The second conductive wire includes: A second horizontal conductive line extends from the second unit transistor in the second direction; and The second letter pad is located at the end of the second horizontal conductive line. Wherein, the first word line pad overlaps with the first conductive line region in the first direction, and The second word line pad overlaps with the second conductive line region in the first direction.

6. The volatile memory device according to claim 5, wherein, The second chip also includes: The first memory cell group includes one or more memory cells containing the first memory cell; The second memory cell group includes one or more memory cells containing the second memory cell; A first conductive line group, including the first conductive line and connecting one or more memory cells of the first memory cell group to the SWD circuit; and The second conductive line group includes the second conductive line and connects one or more memory cells of the second memory cell group to the SWD circuit. Wherein, each conductive line in the first conductive line group includes a word line pad, the word line pad being located at the end of a horizontal conductive line extending in the second direction from one or more memory cells in the first memory cell group and overlapping with the first conductive line region in the first direction, and Each conductive line in the second conductive line group includes a word line pad at the end of a horizontal conductive line that extends in the second direction from one or more memory cells in the second memory cell group and overlaps with the second conductive line region in the first direction.

7. The volatile memory device according to claim 1, wherein, The second chip also includes: The first memory cell group includes a plurality of memory cells containing the first memory cell; The second memory cell group includes a plurality of memory cells containing the second memory cell; The first conductive line group includes multiple conductive lines containing the first conductive line, and connects the multiple memory cells of the first memory cell group to the SWD circuit; and The second conductive line group includes multiple conductive lines containing the second conductive line, and connects the multiple memory cells of the second memory cell group to the SWD circuit. The plurality of memory cells in the first memory cell group receive the first word line enable voltage. Wherein, the plurality of memory cells in the second memory cell group receive the second word line enable voltage, and Wherein, the length of each of the plurality of conductive wires in the first conductive wire group is shorter than the length of each of the plurality of conductive wires in the second conductive wire group.

8. The volatile memory device according to claim 1, wherein, The second chip further includes: a third memory unit and a third conductive line connecting the third memory unit to the SWD circuit. The third memory cell receives a third word line enable voltage from the SWD circuit via the third conductive line. This third word line enable voltage has a voltage level higher than the second word line enable voltage. The length of the third conductive wire is longer than the length of the second conductive wire.

9. A volatile memory device, comprising: The first chip includes a sub-word line driver SWD circuit, which applies a word line enable voltage to activate one or more selected memory cells. and A second chip is bonded to the first chip such that the surfaces of the first chip and the second chip are in contact with each other, the second chip comprising: Substrate; and Multiple memory cells are stacked in a first direction perpendicular to the substrate. The first memory cell among the plurality of memory cells receives the first word line enable voltage from the SWD circuit, and The second memory cell has a different stacking level than the first memory cell among the plurality of memory cells. The second memory cell receives the second word line enable voltage from the SWD circuit, and The second word line enable voltage has a voltage level different from that of the first word line enable voltage.

10. The volatile memory device according to claim 9, wherein, The height of the first memory cell on the substrate in the first direction is greater than the height of the second memory cell on the substrate in the first direction, and The voltage level of the second word line enable voltage is higher than the voltage level of the first word line enable voltage.

11. The volatile memory device according to claim 9, wherein, The distance from the surface of the second chip to the first memory cell in the first direction is shorter than the distance from the surface of the second chip to the second memory cell in the first direction, and The voltage level of the second word line enable voltage is higher than the voltage level of the first word line enable voltage.

12. The volatile memory device according to claim 9, wherein, A first memory cell group, comprising one or more memory cells having the same stacking level as the first memory cell, receives the first word line enable voltage from the SWD circuit, and The second memory cell group, which includes one or more memory cells having the same stacking level as the second memory cell, receives the second word line enable voltage from the SWD circuit.

13. The volatile memory device according to claim 9, wherein, The third memory cell, which has a different stacking level than the first and second memory cells, receives a third word line enable voltage from the SWD circuit. The third word line enable voltage has a voltage level that is different from the voltage levels of the first word line enable voltage and the second word line enable voltage.

14. The volatile memory device according to claim 13, wherein, A first memory cell group, comprising one or more memory cells having the same stacking level as the first memory cell, receives the first word line enable voltage from the SWD circuit. Among the plurality of memory cells, a group of second memory cells, including one or more memory cells having the same stacking level as the second memory cell, receives the second word line enable voltage from the SWD circuit, and The third memory cell group, which includes one or more memory cells having the same stacking level as the third memory cell, receives the third word line enable voltage from the SWD circuit.

15. A volatile memory device, including: The first chip includes: The refresh controller refreshes one or more selected memory cells according to a preset period; and The sub-word line drive SWD circuit, under the control of the refresh controller, applies a word line enable voltage to refresh one or more selected memory cells; and A second chip is bonded to the first chip such that the surfaces of the first chip and the second chip are in contact with each other, the second chip comprising: First memory unit; Second memory unit; A first conductive line connects the first memory cell to the SWD circuit; and The second conductive line connects the second memory cell to the SWD circuit. The refresh controller controls the SWD circuit to refresh the first memory cell in a first cycle. The refresh controller controls the SWD circuit to refresh the second memory cell in a second cycle that is shorter than the first cycle. The length of the second conductive wire is longer than the length of the first conductive wire.

16. The volatile memory device according to claim 15, wherein, The distance from the surface of the second chip to the first memory cell in a first direction perpendicular to the second chip is shorter than the distance from the surface of the second chip to the second memory cell in the first direction.

17. The volatile memory device according to claim 16, wherein, The second chip also includes: The first memory cell group includes a plurality of memory cells containing the first memory cells; and The second memory cell group includes a plurality of memory cells containing the second memory cells, and Wherein, each distance from the surface of the second chip to each of the plurality of memory cells in the first memory cell group in the first direction is shorter than each distance from the surface of the second chip to each of the plurality of memory cells in the second memory cell group in the first direction.

18. The volatile memory device according to claim 15, wherein, The second chip also includes a substrate. The first memory cell and the second memory cell are stacked on the substrate in a first direction perpendicular to the substrate, and Wherein, the height of the first memory cell on the substrate in the first direction is higher than the height of the second memory cell on the substrate in the first direction.

19. The volatile memory device according to claim 15, wherein, The second chip also includes: The first conductive line region overlaps with the SWD circuit in a first direction passing through the second chip; and The second conductive line region does not overlap with the SWD circuit in the first direction. The first conductive line includes: A first horizontal conductive line extends from the first unit transistor in a second direction intersecting the first direction; and The first letter pad is located at the end of the first horizontal conductive line. The second conductive wire includes: A second horizontal conductive line extends from the second unit transistor in the second direction; and The second letter pad is located at the end of the second horizontal conductive line. Wherein, the first word line pad overlaps with the first conductive line region in the first direction, and The second word line pad overlaps with the second conductive line region in the first direction.

20. The volatile memory device according to claim 19, wherein, The second chip also includes: The first memory cell group includes one or more memory cells containing the first memory cell; The second memory cell group includes one or more memory cells containing the second memory cell; A first conductive line group, including the first conductive line and connecting one or more memory cells of the first memory cell group to the SWD circuit, and The second conductive line group includes the second conductive line and connects one or more memory cells of the second memory cell group to the SWD circuit. Wherein, each conductive line in the first conductive line group includes a word line pad, the word line pad being located at the end of a horizontal conductive line extending in the second direction from one or more memory cells in the first memory cell group and overlapping with the first conductive line region in the first direction, and Each conductive line in the second conductive line group includes a word line pad at the end of a horizontal conductive line that extends in the second direction from one or more memory cells in the second memory cell group and overlaps with the second conductive line region in the first direction.

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