Duty cycle tunable frequency multiplier, phase locked loop circuit, and electronic device

Abstract

The application discloses a duty cycle tunable frequency multiplier, a phase-locked loop circuit and electronic equipment, wherein the frequency multiplier comprises an input port, a first adjusting unit, a second adjusting unit, a third adjusting unit, a first control unit, a second control unit, a third control unit and a frequency multiplication unit. The frequency multiplier performs delay processing on a reference frequency through the adjusting units, selects a target delay signal through the control units, and then multiplies the reference frequency signal to generate a frequency multiplication signal, so that the duty cycle of the output clock signal is flexibly adjusted while the frequency multiplication is realized.

Description

Technical Field

[0001] This application relates to the field of frequency multiplier technology, specifically to a frequency multiplier with tunable duty cycle, a phase-locked loop circuit, and electronic equipment. Background Technology

[0002] In the fields of wireless / wired communication, clock integrated circuits, and high-speed ADCs, the frequency and duty cycle of the clock signal are key factors affecting system performance. As the core module for frequency synthesis and clock recovery, the phase-locked loop's loop bandwidth, closed-loop locking speed, and phase noise performance largely depend on the selection of the reference clock signal.

[0003] In phase-locked loop (PLL) systems, increasing the reference frequency can effectively reduce the PLL's phase noise. When the input reference frequency is limited by requirements such as crystal oscillator performance or power consumption and cannot be increased, using a reference frequency multiplier to achieve frequency multiplication becomes an important technical means to improve the overall noise performance of the system. A higher reference frequency allows the PLL to use a smaller division ratio, achieving a larger loop bandwidth in the system. This improves the closed-loop response speed of the PLL while also helping to reduce output spurious levels and achieve fast locking.

[0004] Traditional frequency multipliers typically use XOR gates or edge-triggered circuits to achieve frequency multiplication. However, these multipliers often have some design flaws: they output narrow pulses with a duty cycle deviating from 50%, rather than ideal symmetrical square waves, making them unsuitable for many applications requiring high stability, high precision, wide bandwidth, or standard clock signals. Furthermore, the performance of these multipliers is affected by temperature, manufacturing process, and voltage fluctuations, resulting in unstable output frequency and output pulse width offsets (duty cycle offsets). Summary of the Invention

[0005] This application provides a frequency multiplier with adjustable duty cycle, a phase-locked loop circuit, and an electronic device, which can flexibly adjust the duty cycle of the output clock signal while achieving frequency multiplication.

[0006] In a first aspect, embodiments of this application provide a frequency multiplier with a tunable duty cycle, comprising: An input port, which is used to receive a reference frequency signal; A first adjustment unit, connected to the input port, is used to perform a first delay processing on the reference frequency signal to generate a first delayed signal; The second adjustment unit is connected to the first adjustment unit and is used to perform a second delay processing on the first delayed signal to generate a second delayed signal; A first control unit is connected to the input port and the first adjustment unit respectively, and is used to select one signal output from the reference frequency signal and the first delay signal as a first selection signal; The second control unit is connected to the first control unit and the second adjustment unit respectively, and is used to select one signal from the first selection signal and the second delay signal to output as the second selection signal; The third adjustment unit is connected to the second control unit and is used to perform a third delay processing on the second selection signal to generate a third delay signal; A third control unit, connected to the third adjustment unit, is used to select a target sub-signal from the third delay signal; A frequency multiplication unit, which is connected to the input unit and the third control unit respectively, is used to perform frequency multiplication processing based on the target sub-signal and the reference frequency signal to generate a frequency multiplication signal.

[0007] In the duty cycle tunable frequency multiplier provided in the embodiments of this application, the first adjustment unit includes a plurality of cascaded first delay units for performing step-by-step delay processing on the reference frequency signal, and generating first candidate delay signals with different delay amounts at the output of each first delay unit, wherein the first delay signal is a combination of one or more signals among the first candidate delay signals.

[0008] In the duty cycle tunable frequency multiplier provided in this application embodiment, the second adjustment unit includes multiple cascaded second delay units for performing step-by-step delay processing on the first delay signal, and generating second candidate delay signals with different delay amounts at the output of each second delay unit, wherein the second delay signal is a combination of one or more of the second candidate delay signals.

[0009] In the frequency multiplier with tunable duty cycle provided in this application embodiment, both the first delay unit and the second delay unit are standard delay units, and the number of the standard delay units is configurable; by configuring the number of the first delay units, the first coarse delay range of the first delay signal relative to the reference frequency signal is adjusted; by configuring the number of the second delay units, the second coarse delay range of the second delay signal relative to the first delay signal is adjusted.

[0010] In the duty cycle tunable frequency multiplier provided in the embodiments of this application, the first control unit is a first multiplexer, whose first input terminal receives the reference frequency signal, whose second input terminal receives the first delay signal, and whose output terminal selects one of the channels as the first selected signal according to the first control signal. The second control unit is a second multiplexer. Its first input terminal receives the first selection signal, its second input terminal receives the second delay signal, and its output terminal selects one of the channels as the second selection signal according to the second control signal.

[0011] In the duty cycle tunable frequency multiplier provided in this application embodiment, the third adjustment unit includes multiple cascaded high-resolution fine-tuning delay units, which are used to perform step-by-step high-resolution fine-tuning delay processing on the second selected signal, and generate third candidate delay signals with different high-resolution fine-tuning delay amounts at the output of each high-resolution fine-tuning delay unit, wherein the third delay signal includes the multiple third candidate delay signals. The delay step of the high-resolution fine-tuning delay unit is smaller than that of the standard delay unit, and the number of the high-resolution fine-tuning delay units is configurable. By configuring the number of the high-resolution fine-tuning delay units, the high-resolution fine-tuning delay range of the third delay signal relative to the second selected signal is adjusted.

[0012] In the duty cycle tunable frequency multiplier provided in the embodiments of this application, the third control unit is a gating array, which includes multiple input terminals and one output terminal; The plurality of input terminals are respectively connected to the output terminals of the plurality of cascaded high-resolution fine-tuning delay units, and are used to receive the plurality of third candidate delay signals; The output terminal selects one of the plurality of third candidate delay signals as the target sub-signal and outputs it to the frequency multiplication unit according to the third control signal.

[0013] In the frequency multiplier with tunable duty cycle provided in the embodiments of this application, the frequency multiplication unit is an XOR gate, whose first input terminal receives the reference frequency signal and its second input terminal receives the target sub-signal. The XOR logic operation is performed on the two input signals to generate the frequency multiplication signal.

[0014] Secondly, embodiments of this application provide a phase-locked loop circuit, including the aforementioned duty cycle-tunable frequency multiplier, wherein the input terminal of the frequency multiplier is connected to a crystal oscillator, and the output terminal of the frequency multiplier is connected to the phase-frequency detector of the phase-locked loop.

[0015] Thirdly, embodiments of this application provide an electronic device including the aforementioned phase-locked loop circuit.

[0016] In summary, the duty cycle tunable frequency multiplier provided in this application includes an input port, a first adjustment unit, a second adjustment unit, a first control unit, a second control unit, a third adjustment unit, a third control unit, and a frequency multiplication unit; wherein, the input port is used to receive a reference frequency signal; the first adjustment unit is connected to the input port and is used to perform a first delay processing on the reference frequency signal to generate a first delayed signal; the second adjustment unit is connected to the first adjustment unit and is used to perform a second delay processing on the first delayed signal to generate a second delayed signal; the first control unit is connected to the input port and the first adjustment unit respectively, and is used to receive a reference frequency signal from the reference frequency signal and the first adjustment unit. A signal is selected from the delayed signals and output as a first selected signal; the second control unit is connected to the first control unit and the second adjustment unit respectively, and is used to select a signal from the first selected signal and the second delayed signal to output as a second selected signal; the third adjustment unit is connected to the second control unit and is used to perform a third delay processing on the second selected signal to generate a third delayed signal; the third control unit is connected to the third adjustment unit and is used to select a target sub-signal from the third delayed signal; the frequency multiplication unit is connected to the input unit and the third control unit respectively, and is used to perform frequency multiplication processing according to the target sub-signal and the reference frequency signal to generate a frequency multiplied signal. This embodiment of the application can flexibly adjust the duty cycle of the output clock signal while achieving frequency multiplication. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the frequency multiplier provided in the embodiments of this application.

[0019] Figure 2 This is a schematic diagram of the structure of the third control unit provided in the embodiments of this application. Detailed Implementation

[0020] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0021] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0022] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0023] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0024] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] Traditional frequency multipliers typically use XOR gates or edge-triggered circuits to achieve frequency multiplication. However, these multipliers often have some design flaws: they output narrow pulses with a duty cycle deviating from 50%, rather than ideal symmetrical square waves, making them unsuitable for many applications requiring high stability, high precision, wide bandwidth, or standard clock signals. Furthermore, the performance of these multipliers is affected by temperature, manufacturing process, and voltage fluctuations, resulting in unstable output frequency and output pulse width offsets (duty cycle offsets).

[0026] Based on this, embodiments of this application provide a frequency multiplier with tunable duty cycle, a phase-locked loop circuit, and an electronic device. The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0027] Please see Figure 1 , Figure 1 This is a schematic diagram of the frequency multiplier with tunable duty cycle provided in an embodiment of this application. This frequency multiplier with tunable duty cycle can be applied in a phase-locked loop (PLL) circuit to multiply the reference frequency signal generated by a low-frequency crystal oscillator, outputting a high-frequency multiplied signal with a flexibly adjustable duty cycle, thereby improving the phase noise, spurious performance, and locking speed of the PLL.

[0028] like Figure 1 As shown, the duty cycle adjustable frequency multiplier may include an input port 1, a first adjustment unit 2, a second adjustment unit 3, a first control unit 4, a second control unit 5, a third adjustment unit 6, a third control unit 7, and a frequency multiplication unit 8.

[0029] Input port 1 is used to receive a reference frequency signal. This reference frequency signal is typically generated by a low-frequency crystal oscillator, exhibiting a low frequency and high frequency stability. After receiving the reference frequency signal, input port 1 transmits it to the first adjustment unit 2 and the first control unit 4, respectively.

[0030] The first adjustment unit 2 is connected to the input port 1 and is used to perform a first delay processing on the reference frequency signal to generate a first delay signal.

[0031] In this embodiment, the first adjustment unit 2 includes multiple cascaded first delay units 21. These first delay units 21 are standard delay units, each generating a fixed delay amount for the input signal. The reference frequency signal passes sequentially through each of the first delay units 21, generating first candidate delay signals with different delay amounts at the output of each first delay unit 21. The first delay signal can be one or a combination of these first candidate delay signals, depending on the design requirements. For example, the output of the last stage of the first delay unit 21 can be used as the first delay signal, or all first candidate delay signals can be output in parallel to subsequent circuits. By configuring the number of first delay units 21, the first coarse adjustment delay range of the first delay signal relative to the reference frequency signal can be adjusted. The more first delay units 21 there are, the greater the maximum achievable delay amount and the wider the adjustment range.

[0032] The second adjustment unit 3 is connected to the first adjustment unit 2 and is used to perform a second delay processing on the first delay signal to generate a second delay signal. The second adjustment unit 3 includes multiple cascaded second delay units 31, which are also standard delay units with the same structure as the first delay unit 21.

[0033] In the specific implementation process, the first delay signal (which may be a node signal output by the first adjustment unit 2) is input to the second adjustment unit 3, and passes through each of the second delay units 31 in sequence. At the output of each second delay unit 31, a second candidate delay signal with a different delay amount is generated. The second delay signal can be one or a combination of these second candidate delay signals. By configuring the number of second delay units 31, the second coarse adjustment delay range of the second delay signal relative to the first delay signal can be adjusted.

[0034] In the embodiments of this application, the first coarse adjustment delay range and the second coarse adjustment delay range together constitute the coarse adjustment delay capability of the reference frequency signal, which can cover deviations under various process, voltage, and temperature (PVT) conditions.

[0035] The first control unit 4 is connected to both the input port 1 and the first adjustment unit 2. The first control unit 4 is used to select one signal from the reference frequency signal and the first delay signal to output as the first selection signal.

[0036] Specifically, the first control unit 4 can be a first multiplexer (MUX). This first multiplexer has a first input, a second input, and an output. The first input receives a reference frequency signal, and the second input receives a first delay signal. The first multiplexer selects one of the two input signals based on a first control signal (e.g., a gating instruction generated by an external controller or internal logic), and outputs it as a first selected signal. In this way, the first control unit 4 can select between the undelayed original reference frequency signal and the signal after a first coarse-tuned delay, providing a flexible starting point for subsequent delay adjustments.

[0037] The second control unit 5 is connected to both the first control unit 4 and the second adjustment unit 3. The second control unit 5 is used to select one signal from the first selection signal and the second delay signal to output as the second selection signal.

[0038] Similarly, the second control unit 5 can be a second multiplexer, with its first input receiving a first selection signal, its second input receiving a second delay signal, and its output selecting one of the channels as the second selection signal according to the second control signal.

[0039] In this embodiment, different delay paths can be selected through the cooperation of the first control unit 4 and the second control unit 5: for example, the original reference frequency signal can be selected directly, bypassing the first adjustment unit 2, and then delayed through the second adjustment unit 3; or the delay can be performed first through the first adjustment unit 2, and then the choice can be made whether to delay through the second adjustment unit 3; or the delay can be performed only through the first adjustment unit 2 without passing through the second adjustment unit 3 (by selecting the first selected signal through the second control unit 5). This structure greatly expands the flexibility of delay adjustment and enables a wide range of coarse delay selection.

[0040] The third adjustment unit 6 is connected to the second control unit 5 and is used to perform a third delay processing on the second selected signal to generate a third delayed signal. The third adjustment unit 6 includes multiple cascaded high-resolution fine-tuning delay units 61.

[0041] In this embodiment, the delay steps of these high-resolution fine-tuning delay units 61 are smaller than those of the first delay unit 21 and the second delay unit 31, thus enabling higher-resolution fine-tuning of the delay adjustment. The second selection signal is input to the third adjustment unit 6, passing sequentially through each of the high-resolution fine-tuning delay units 61, generating third candidate delay signals with different high-resolution fine-tuning delay amounts at the output of each high-resolution fine-tuning delay unit 61. The third delay signal includes these multiple third candidate delay signals. By configuring the number of high-resolution fine-tuning delay units 61, the high-resolution fine-tuning delay range of the third delay signal relative to the second selection signal can be adjusted. The more stages of the high-resolution fine-tuning delay units 61, the higher the achievable delay resolution and the higher the accuracy of the duty cycle adjustment.

[0042] The third control unit 7 is connected to the third adjustment unit 6 and is used to select the target sub-signal from the third delay signal.

[0043] In some embodiments, such as Figure 2 As shown, the third control unit 7 can be a selector array, which includes multiple input terminals and one output terminal. The multiple input terminals are connected one-to-one with the output terminals of multiple cascaded high-resolution fine-tuning delay units 61, for receiving multiple third candidate delay signals. The selector array selects one of the multiple third candidate delay signals as the target sub-signal according to the third control signal and outputs it to the frequency multiplication unit 8. Since the output of the high-resolution fine-tuning delay unit 61 provides a continuously varying delay amount, the third control unit 7 can select the output of any stage, thereby precisely controlling the delay amount of the target sub-signal relative to the second selected signal. Combined with the previous coarse-tuning stage, the overall delay time Td of the final target sub-signal relative to the original reference frequency signal can be continuously adjusted within a wide range and has high resolution.

[0044] The frequency multiplication unit 8 is connected to both the input port 1 and the third control unit 7. The frequency multiplication unit 8 is used to perform frequency multiplication processing based on the target sub-signal and the reference frequency signal to generate a multiplied frequency signal.

[0045] In this embodiment, the frequency multiplication unit 8 can be an XOR gate. This XOR gate has a first input terminal and a second input terminal. The first input terminal receives the original reference frequency signal, and the second input terminal receives the target sub-signal obtained after multiple stages of delay and selection. The XOR gate performs an XOR logic operation on the two input signals and outputs a frequency-multiplied signal that is twice the frequency of the reference frequency signal.

[0046] Understandably, the duty cycle of the frequency-multiplied signal output by the XOR gate depends on the delay time Td of the target sub-signal relative to the reference frequency signal. When Td is equal to one-quarter of the period T of the reference frequency signal, the duty cycle of the frequency-multiplied signal is 50%. By flexibly adjusting the number of delay units at each stage and the gating state of each control unit, Td can be precisely adjusted to the required value, thereby obtaining the desired duty cycle.

[0047] Additionally, it should be noted that in this embodiment, the first delay unit 21 and the second delay unit 31 are both standard delay units, and their number is configurable; the delay step of the high-resolution fine-tuning delay unit 61 is smaller than that of the standard delay units, and its number is also configurable. The first control unit 4, the second control unit 5, and the third control unit 7 are selected according to the first control signal, the second control signal, and the third control signal, respectively. These control signals can be provided by external circuits (such as the digital control module in the phase-locked loop) or dynamically adjusted according to the system's operating state.

[0048] In practical applications, this duty cycle-tunable frequency multiplier can be used in phase-locked loop (PLL) circuits to multiply the reference frequency generated by a low-frequency crystal oscillator. For example, if the crystal oscillator provides a reference signal with a frequency of Fref, this multiplier outputs a multiplied signal with a frequency of 2Fref, which serves as the reference input for the PLL. Because the multiplied reference frequency is higher, the PLL can use a smaller division ratio, thereby reducing the amplification factor of phase noise and improving the phase noise and spurious performance of the output signal. Simultaneously, by precisely adjusting the duty cycle of the multiplied signal to 50%, the problem of odd-even period asymmetry caused by the duty cycle deviating from the ideal value can be avoided, further suppressing spurious signals. Furthermore, this multiplier employs a multi-stage coarse-tuning and fine-tuning structure, enabling stable delay adjustment under various PVT conditions, ensuring rapid system locking and stable operation.

[0049] In summary, the frequency multiplier with tunable air ratio provided in this application includes an input port 1, a first adjustment unit 2, a second adjustment unit 3, a first control unit 4, a second control unit 5, a third adjustment unit 6, a third control unit 7, and a frequency multiplication unit 8; wherein, the input port 1 is used to receive a reference frequency signal; the first adjustment unit 2 is connected to the input port 1 and is used to perform a first delay processing on the reference frequency signal to generate a first delayed signal; the second adjustment unit 3 is connected to the first adjustment unit 2 and is used to perform a second delay processing on the first delayed signal to generate a second delayed signal; the first control unit 4 is connected to the input port 1 and the first adjustment unit 2 respectively, and is used to receive a reference frequency signal from the input port 1. A signal is selected from the frequency signal and the first delay signal and output as the first selected signal; the second control unit 5 is connected to the first control unit 4 and the second adjustment unit 3 respectively, and is used to select a signal from the first selected signal and the second delay signal and output it as the second selected signal; the third adjustment unit 6 is connected to the second control unit 5 and is used to perform a third delay processing on the second selected signal to generate a third delay signal; the third control unit 7 is connected to the third adjustment unit 6 and is used to select a target sub-signal from the third delay signal; the frequency multiplication unit 8 is connected to the input unit and the third control unit 7 respectively, and is used to perform frequency multiplication processing on the target sub-signal and the reference frequency signal to generate a frequency multiplied signal. The frequency multiplier with tunable duty cycle provided in this application embodiment achieves a wide range of coarse delay adjustment of the reference frequency signal through the coordinated operation of the first adjustment unit 2, the second adjustment unit 3, the first control unit 4, and the second control unit 5. This effectively covers delay deviations under different process, voltage, and temperature conditions. Simultaneously, the high-resolution fine-tuning delay adjustment achieved by the third adjustment unit 6 and the third control unit 7 enables precise control of the delay time of the target sub-signal at high resolution. This allows for flexible adjustment of the duty cycle of the multiplied signal to the ideal value (e.g., 50%), thereby effectively reducing the output spurious level of the phase-locked loop and improving the accuracy and stability of the system. Furthermore, the frequency multiplier uses an XOR gate to implement the frequency multiplication function, resulting in a simple circuit structure, small area, and low power consumption, achieving an optimal balance between cost and performance. Its multi-level gating structure also provides rich signal path selection, significantly enhancing design flexibility and system robustness.

[0050] This application also provides a phase-locked loop (PLL) circuit, which includes a frequency multiplier with an adjustable duty cycle as described in any of the above embodiments. The input of the frequency multiplier is connected to a crystal oscillator to receive a reference frequency signal generated by the crystal oscillator. The output of the frequency multiplier is connected to a frequency and phase detector of the PLL to provide the frequency multiplier signal to the frequency and phase detector.

[0051] Crystal oscillators are typically low-frequency crystal oscillators, offering advantages such as low cost, low power consumption, and high frequency stability. The reference frequency signal generated by the crystal oscillator is input to a frequency multiplier, which multiplies the frequency to generate a frequency-doubled signal that is twice the reference frequency. This multiplied signal serves as the input reference signal for the phase-locked loop (PLL) and is then fed into a frequency and phase detector.

[0052] In a phase-locked loop (PLL) circuit, the frequency-phase detector compares the phase and frequency of the multiplied signal and the feedback frequency-divided signal, outputting an error signal to control the subsequent charge pump, loop filter, and voltage-controlled oscillator (VCO), ultimately generating a stable high-frequency output signal. Because the frequency multiplier outputs a signal with a frequency higher than the original crystal oscillator frequency, the PLL can use a smaller division ratio, resulting in a larger loop bandwidth. The frequency-phase detector and charge pump also exhibit superior in-band phase noise capability at the multiplied reference frequency, effectively improving the PLL's phase noise performance.

[0053] Meanwhile, the frequency multiplier has the ability to flexibly adjust the duty cycle. By adjusting the number of delay units in the first adjustment unit 2, the second adjustment unit 3, and the third adjustment unit 6, as well as the gating state of the first control unit 4, the second control unit 5, and the third control unit 7, the duty cycle of the multiplied signal can be precisely achieved to 50% or other preset ideal values. When the multiplied signal has a 50% duty cycle, spurious components caused by signal pulse width asymmetry can be avoided, further reducing the reference spurious level in the phase-locked loop output spectrum. Reference spurious components mainly originate from leakage in the phase detector, and their intensity is proportional to the division ratio N. After the division ratio decreases, the amplitude of the harmonic components of the reference frequency in the output spectrum decreases accordingly, and the spurious performance of the phase-locked loop is significantly improved.

[0054] Furthermore, since the reference frequency is increased after frequency multiplication, the loop bandwidth of the phase-locked loop (PLL) can be increased accordingly, which is beneficial for achieving faster locking speed and meeting the needs of applications such as rapid frequency hopping. The multi-stage coarse and fine adjustment structure of the frequency multiplier can operate stably under various process, voltage, and temperature conditions, ensuring that the PLL can lock quickly and remain stable in different environments.

[0055] The phase-locked loop circuit provided in this application, by introducing a frequency multiplier with tunable duty cycle, achieves improved noise performance and spurious levels from a high-frequency reference signal while maintaining the low-cost advantage of low-frequency crystal oscillators, thus realizing a low-cost, low-power, and high-performance phase-locked loop design scheme.

[0056] This application also provides an electronic device that includes the phase-locked loop circuit described in the above embodiments. The electronic device can be any device requiring clock generation or frequency synthesis functions, such as wireless communication devices (e.g., mobile phones, base stations, WiFi routers), IoT devices, satellite navigation receivers, radar systems, test and measurement instruments, etc.

[0057] In this electronic device, a phase-locked loop (PLL) circuit is used to generate various high-frequency clock or carrier signals required for device operation. The PLL circuit's built-in duty-cycle-tunable frequency multiplier allows the PLL to use a low-frequency crystal oscillator as a reference source, reducing the device's dependence on high-frequency crystal oscillators and thus decreasing material costs and power consumption. Simultaneously, the frequency multiplier precisely adjusts the duty cycle of the reference frequency, ensuring that the PLL output signal has excellent phase noise and spurious performance, improving the overall signal quality and operational stability of the electronic device.

[0058] For example, in wireless communication devices, a phase-locked loop (PLL) circuit provides a high-frequency carrier signal to the local oscillator. The purity of the carrier signal directly affects the bit error rate and anti-interference capability of the communication. Through the PLL circuit provided in the embodiments of this application, wireless communication devices can obtain carrier signals with lower noise and lower spurious emissions, thereby improving communication quality and system capacity.

[0059] Low power consumption is a critical requirement in IoT devices. By using a low-frequency crystal oscillator combined with the frequency multiplier described in this application, the overall power consumption of the system can be effectively reduced and battery life extended while ensuring clock accuracy.

[0060] In radar or test and measurement instruments, fast frequency hopping and low phase noise are important specifications. The phase-locked loop circuit provided in this application can achieve fast locking and low-noise output, meeting the requirements of high-performance applications.

[0061] In summary, the electronic device provided in this application embodiment achieves a good balance between cost, power consumption, and performance by integrating a phase-locked loop circuit that includes a frequency multiplier with an adjustable duty cycle, and has broad application prospects.

[0062] The above provides a detailed description of the duty cycle tunable frequency multiplier, phase-locked loop circuit, and electronic equipment provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of this application. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A frequency multiplier with tunable duty cycle, characterized in that, include: An input port, which is used to receive a reference frequency signal; A first adjustment unit, connected to the input port, is used to perform a first delay processing on the reference frequency signal to generate a first delayed signal; The second adjustment unit is connected to the first adjustment unit and is used to perform a second delay processing on the first delayed signal to generate a second delayed signal; A first control unit is connected to the input port and the first adjustment unit respectively, and is used to select one signal output from the reference frequency signal and the first delay signal as a first selection signal; The second control unit is connected to the first control unit and the second adjustment unit respectively, and is used to select one signal from the first selection signal and the second delay signal to output as the second selection signal; The third adjustment unit is connected to the second control unit and is used to perform a third delay processing on the second selection signal to generate a third delay signal; A third control unit, connected to the third adjustment unit, is used to select a target sub-signal from the third delay signal; A frequency multiplication unit, which is connected to the input unit and the third control unit respectively, is used to perform frequency multiplication processing based on the target sub-signal and the reference frequency signal to generate a frequency multiplication signal.

2. The frequency multiplier with tunable duty cycle as described in claim 1, characterized in that, The first adjustment unit includes multiple cascaded first delay units for performing step-by-step delay processing on the reference frequency signal. Each first delay unit generates a first candidate delay signal with a different delay amount at its output. The first delay signal is a combination of one or more of the first candidate delay signals.

3. The frequency multiplier with tunable duty cycle as described in claim 2, characterized in that, The second adjustment unit includes multiple cascaded second delay units for performing step-by-step delay processing on the first delay signal. Each second delay unit generates a second candidate delay signal with a different delay amount at its output. The second delay signal is a combination of one or more of the second candidate delay signals.

4. The frequency multiplier with tunable duty cycle as described in claim 3, characterized in that, Both the first delay unit and the second delay unit are standard delay units, and the number of the standard delay units is configurable. By configuring the number of the first delay units, the first coarse adjustment delay range of the first delay signal relative to the reference frequency signal is adjusted. By configuring the number of the second delay units, the second coarse adjustment delay range of the second delay signal relative to the first delay signal is adjusted.

5. The frequency multiplier with tunable duty cycle as described in claim 1, characterized in that, The first control unit is a first multiplexer, whose first input terminal receives the reference frequency signal, whose second input terminal receives the first delay signal, and whose output terminal selects one of the channels according to the first control signal as the first selected signal output. The second control unit is a second multiplexer. Its first input terminal receives the first selection signal, its second input terminal receives the second delay signal, and its output terminal selects one of the channels as the second selection signal according to the second control signal.

6. The frequency multiplier with tunable duty cycle as described in claim 4, characterized in that, The third adjustment unit includes multiple cascaded high-resolution fine-tuning delay units, which are used to perform step-by-step high-resolution fine-tuning delay processing on the second selected signal. Each high-resolution fine-tuning delay unit generates a third candidate delay signal with a different high-resolution fine-tuning delay amount at its output. The third delay signal includes the multiple third candidate delay signals. The delay step of the high-resolution fine-tuning delay unit is smaller than that of the standard delay unit, and the number of the high-resolution fine-tuning delay units is configurable. By configuring the number of the high-resolution fine-tuning delay units, the high-resolution fine-tuning delay range of the third delay signal relative to the second selected signal is adjusted.

7. The frequency multiplier with tunable duty cycle as described in claim 6, characterized in that, The third control unit is a gating array, which includes multiple input terminals and one output terminal; The plurality of input terminals are respectively connected to the output terminals of the plurality of cascaded high-resolution fine-tuning delay units, and are used to receive the plurality of third candidate delay signals; The output terminal selects one of the plurality of third candidate delay signals as the target sub-signal and outputs it to the frequency multiplication unit according to the third control signal.

8. The frequency multiplier with tunable duty cycle as described in claim 1, characterized in that, The frequency multiplication unit is an XOR gate. Its first input terminal receives the reference frequency signal, and its second input terminal receives the target sub-signal. It performs an XOR logic operation on the two input signals to generate a frequency multiplication signal.

9. A phase-locked loop circuit, characterized in that, Includes a duty cycle tunable frequency multiplier as described in any one of claims 1 to 8, wherein the input of the frequency multiplier is connected to a crystal oscillator and the output of the frequency multiplier is connected to a phase detector of a phase-locked loop.

10. An electronic device, characterized in that, Includes the phase-locked loop circuit as described in claim 9.

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