PCIe high-speed parallel-serial conversion port station multi-split configuration structure

Abstract

The application relates to the technical field of high-speed digital baseband transmission, and discloses a PCIe high-speed parallel-serial conversion port station multi-split configuration structure, which changes the structure of a fixed-width port that cannot be split, enables a high-speed port to be dynamically split into multiple independent channels to adapt to external devices of different widths, solves the problem of idle channels, and improves the utilization efficiency of physical channels and bus bandwidths; the application introduces a physical coding sublayer combination architecture and a dynamic selector, so that the same hardware structure can support the overall access of high-bandwidth devices and can also be reconstructed into multiple independent links to access multiple low-bandwidth devices; different application topologies can be adapted without modifying a physical layout, and the flexibility of chip configuration is improved.

Description

Technical Field

[0001] This application relates to the field of high-speed digital baseband transmission technology, and in particular to a multi-split configuration structure for PCIe high-speed parallel-to-serial conversion port stations. Background Technology

[0002] Peripheral Component Interconnect (PCI) is a high-speed, serial, full-duplex computer expansion bus standard that uses a high-speed differential bus to achieve communication between two or more devices in a point-to-point connection manner. Since becoming an industry standard, this interface technology has undergone multiple iterations, significantly improving its single-channel transmission rate. With its high bandwidth, low latency, backward compatibility, and flexibility, this interconnect standard has become an important reference interface standard for the design of various hardware components. As data processing volumes increase, the computational load in data centers is also rising. Traditional general-purpose central processing units (CPUs) typically require external computing acceleration resources such as graphics processors (GPUs), digital signal processors (DSPs), and field-programmable gate arrays (FPGAs) or high-speed storage resources to handle matrix operations and high-concurrency data streams, thereby synergistically improving the overall system's computing performance and data throughput. In the aforementioned system-level application topology, the root complex, acting as the system's brain, usually needs to interface with various downstream endpoint devices or switches through high-speed parallel-to-serial conversion ports, forming a tree-like topology connection structure on the motherboard or backplane. Since different endpoint devices have varying bandwidth requirements based on their service attributes, they are designed with different bus access widths.

[0003] In existing controller-physical layer co-design architectures, there are architectural problems that lead to limited port resources. Typically, during integrated circuit tape-out, the physical coding sublayer and media access control layer logic of the physical layer are hardwired with a fixed maximum width configuration. This means that a fixed-width high-speed parallel-to-serial conversion port exists only as a single logical unit during its runtime, and can only connect to one device of the same width or, down the hierarchy, a device with a lower width. This backward-compatible but not hierarchical hardwired mechanism limits the application scenarios of high-speed ports. When a broadband access port connects to a low-width device, because the internal physical coding sublayer lacks independent control and splitting management capabilities for the underlying physical channels, the remaining physical channels of the port cannot be allocated to other devices, resulting in idle bandwidth. In system-on-a-chip (SoC) systems with high tape-out costs, bandwidth idleness caused by fixed port configurations reduces system resource utilization efficiency. Therefore, the industry needs an architectural solution that can decouple and reorganize the underlying physical channels. By dynamically splitting a broadband port into multiple independently operating narrowband ports, it can simultaneously connect to multiple external devices with different widths, thereby improving physical channel bandwidth utilization and meeting the expansion needs of heterogeneous systems. In light of the above background, this invention proposes a novel multi-split configuration structure solution. Summary of the Invention

[0004] This application proposes a multi-split configuration structure for PCIe high-speed parallel-to-serial conversion port stations to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, this application adopts the following technical solution: a PCIe high-speed parallel-to-serial conversion port station multi-split configuration structure, including: a high-speed parallel-to-serial conversion port group, a first channel selector, a physical coding sublayer combination, and a second channel selector; The lower end of the high-speed parallel-to-serial conversion port group is configured to connect to the physical interface of an external expansion device, and its upper end is connected to the first end of the first channel selector. It is used to convert high-speed serial data transmitted by downstream devices into low-speed parallel data streams in the receiving direction, and to convert low-speed parallel data streams transmitted by upstream systems into high-speed serial data and output them in the form of differential signals in the transmitting direction. The second end of the first channel selector is connected to the first end of the physical coding sublayer combination, and is used to establish a precise data interaction connection between the high-speed parallel-to-serial conversion port group and a specific sub-physical coding sublayer in the physical coding sublayer combination by dynamically reconstructing the underlying data path according to the preset port splitting configuration instruction. The second end of the physical coding sublayer combination is connected to the first end of the second channel selector. The physical coding sublayer combination contains multiple sub-physical coding sublayers with different numbers and different data widths, which are used to encode the parallel data stream transmitted by the first channel selector and then transmit it to the second channel selector, or to decode the parallel data stream transmitted by the second channel selector and then transmit it to the first channel selector. The second end of the second channel selector is configured to connect to multiple sets of kernel data interfaces of different widths, and is used to allocate and establish interactive mapping paths for parallel data streams between each sub-physical coding sublayer of the physical coding sublayer combination and the kernel data interface according to the port splitting configuration instruction.

[0006] Furthermore, the high-speed parallel-to-serial conversion port group integrates a link adaptive equalization module. The link adaptive equalization module is configured to detect the channel quality and signal integrity characteristics of the external link in real time, and adaptively and dynamically adjust the circuit configuration parameters of the internal receiver or transmitter according to the channel attenuation parameter, and select the optimal signal compensation configuration parameters according to the equalization calculation result to maintain link stability.

[0007] Furthermore, each sub-physical coding sublayer within the physical coding sublayer combination supports multi-protocol version compatible encoding and decoding logic and has the ability to dynamically switch encoding mechanisms according to the link negotiation rate. When the external link negotiation is a low-rate protocol standard, the sub-physical coding sublayer uses eight-bit to ten-bit encoding and decoding logic to process parallel data streams. When the external link negotiation is a high-rate protocol standard, the sub-physical coding sublayer uses one hundred and twenty-eight-bit to one hundred and thirty-bit encoding and decoding logic to process parallel data streams.

[0008] Furthermore, the port station includes a physical structure with a maximum physical bandwidth of eight channels, and the high-speed parallel-to-serial conversion port group is specifically composed of a first four-channel high-speed parallel-to-serial conversion port and a second four-channel high-speed parallel-to-serial conversion port. The physical coding sublayer combination includes at least: one eight-channel width sub-physical coding sublayer, two four-channel width sub-physical coding sublayers, and four two-channel width sub-physical coding sublayers. The kernel data interface includes at least: an eight-channel kernel data interface, a four-channel kernel data interface, a first two-channel kernel data interface, and a second two-channel kernel data interface.

[0009] Furthermore, when the multi-split configuration structure is configured in eight-channel full-bandwidth mode: The first channel selector connects the first four-channel high-speed parallel-to-serial conversion port to the lower four data ports of the eight-channel width sub-physical coding sub-layer, and connects the second four-channel high-speed parallel-to-serial conversion port to the higher four data ports of the eight-channel width sub-physical coding sub-layer. The eight-channel width sub-physical coding sublayer is used to receive the low four and high four parallel data streams and merge them into a complete eight-channel parallel data stream. The second channel selector is configured to map the entire eight-channel parallel data stream and pass it directly to the eight-channel kernel data interface.

[0010] Furthermore, when the multi-split configuration structure is configured as a dual four-channel balanced split mode: The first channel selector connects the first four-channel high-speed parallel-to-serial conversion port to the data port of the first four-channel width sub-physical coding sub-layer in the physical coding sub-layer combination, and connects the second four-channel high-speed parallel-to-serial conversion port to the data port of the second four-channel width sub-physical coding sub-layer. The second channel selector connects the lower four bits of the parallel data stream output by the first four-channel width sub-physical coding sub-layer to the lower four bits of the eight-channel kernel data interface, and connects the higher four bits of the parallel data stream output by the second four-channel width sub-physical coding sub-layer to the independent four-channel kernel data interface, thereby forming two parallel data transmission paths.

[0011] Furthermore, when the multi-split configuration structure is configured as four groups of two-channel fragmentation modes: The first channel selector independently connects the low two and high two paths of the first four-channel high-speed parallel-to-serial conversion port to the first two-channel width sub-physical coding sub-layer and the second two-channel width sub-physical coding sub-layer, respectively; and independently connects the low two and high two paths of the second four-channel high-speed parallel-to-serial conversion port to the third two-channel width sub-physical coding sub-layer and the fourth two-channel width sub-physical coding sub-layer, respectively. The second channel selector independently connects the parallel data streams output by the first, second, third, and fourth channel width sub-physical coding sub-layers to the lower two bits of the eight-channel kernel data interface, the lower two bits of the first two-channel kernel data interface, the lower two bits of the four-channel kernel data interface, and the second two-channel kernel data interface, respectively.

[0012] Furthermore, when the multi-split configuration structure is configured as a set of four-channel plus two sets of two-channel asymmetric split modes: The first channel selector connects the first four-channel high-speed parallel-to-serial conversion port as a whole to the first four-channel width sub-physical coding sub-layer; and connects the low two paths and the high two paths of the second four-channel high-speed parallel-to-serial conversion port to the first two-channel width sub-physical coding sub-layer and the second two-channel width sub-physical coding sub-layer, respectively. The second channel selector connects the parallel data stream output by the first four-channel width sub-physical coding sublayer to the lower four bits of the eight-channel kernel data interface; and connects the parallel data streams output by the first and second two-channel width sub-physical coding sublayers to the first two-channel kernel data interface and the second two-channel kernel data interface, respectively.

[0013] Furthermore, when the multi-split configuration structure is configured in cross-port split aggregation mode: The first channel selector connects the two lower paths of the first four-channel high-speed parallel-to-serial conversion port to the first two-channel width sub-physical coding sub-layer; it aggregates the two higher paths of the first four-channel high-speed parallel-to-serial conversion port and the two lower paths of the second four-channel high-speed parallel-to-serial conversion port together across the boundary and connects them to the first four-channel width sub-physical coding sub-layer; and it connects the two higher paths of the second four-channel high-speed parallel-to-serial conversion port to the second two-channel width sub-physical coding sub-layer. The second channel selector connects the parallel data stream output by the first two-channel width sub-physical coding sub-layer to the first two-channel kernel data interface; connects the parallel data stream output by the first four-channel width sub-physical coding sub-layer to the four-channel kernel data interface; and connects the parallel data stream output by the second two-channel width sub-physical coding sub-layer to the second two-channel kernel data interface.

[0014] The beneficial effects of this invention are as follows: This invention changes the fixed-width, non-splitable structure of ports, enabling high-speed ports to be dynamically divided into multiple independent channels to adapt to external devices of different widths. This solves the channel idleness problem and improves the utilization efficiency of physical channels and bus bandwidth. The invention introduces a physical coding sublayer combination architecture and a dynamic selector, allowing the same hardware structure to support the overall access of high-bandwidth devices or be reconfigured into multiple independent links to access multiple low-bandwidth devices. It adapts to different application topologies without modifying the physical layout, enhancing chip configuration flexibility. In the cross-port splitting mode, this invention reassembles channel data across physical boundaries through digital domain reorganization, giving motherboard engineers greater freedom in printed circuit board routing, reducing backplane routing complexity and parasitic interference, and optimizing hardware routing topology design. Furthermore, the splitting mechanism of this invention does not depend on specific manufacturing process nodes, making it suitable for CPU built-in port design, as well as interface design for digital signal processing arrays, programmable logic platforms, and switching chips, exhibiting broad system versatility. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort: Figure 1 This is a schematic diagram of the overall architecture and data flow hierarchy of the present invention; Figure 2 This invention provides a schematic diagram illustrating the connection relationship and breakdown principle of the core modules within the configuration structure station containing the first and second four-channel high-speed parallel-to-serial conversion ports. Figure 3 This is a detailed structural diagram of the various physical coding sublayer units with different numbers and bit widths contained within the physical coding sublayer assembly of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example

[0017] like Figure 1 , Figure 2 and Figure 3 As shown, this invention discloses a multi-split configuration structure for PCIe high-speed parallel-to-serial conversion port stations. This architecture introduces a station-level layered processing mechanism between the traditional physical and logical layers. From the perspective of data reception and uplink transmission, the system contains four data relay layers from bottom to top.

[0018] First, there's the high-speed parallel-to-serial conversion port group, which serves as the physical interaction layer. Its function is to convert the parallel data stream transmitted from the upstream logic layer into high-speed serial data for output; simultaneously, it converts high-speed serial data from downstream external devices into a parallel data stream for transmission. Second, there's the first channel selector, which acts as the underlying multiplexing array. Its function is to read port splitting configuration instructions, dynamically plan data paths, and establish dynamic connections between the physical coding sublayer assembly and the underlying high-speed parallel-to-serial conversion port group, completing precise data reassembly. Third, there's the physical coding sublayer assembly, the core data processing unit of this invention. It breaks away from the rigid limitations of a single coding module, internally pre-configuring multiple independent sub-physical coding sublayers of varying numbers and data widths, responsible for performing parallel operations on protocol logic such as scrambling, synchronization, and alignment. Finally, there's the second channel selector, responsible for mapping and allocating the data stream between the logic kernel data interface layer and the physical coding sublayer assembly at the top level according to the splitting configuration instructions.

[0019] To address the adaptive equalization feature of the link, and considering the signal attenuation and inter-symbol interference present in high-frequency signal routing on printed circuit boards or in cable transmission, the high-speed parallel-to-serial conversion port group integrates an adaptive equalization module. During actual operation, this module can detect channel quality in real time and dynamically adjust the circuit configuration parameters of the internal receiver or transmitter to compensate for channel loss, ensuring that each decomposed miniature physical link can meet the bit error rate specifications of the communication protocol under different operating environments.

[0020] To address the adaptive nature of the protocol, each sub-physical coding sublayer within the physical coding sublayer assembly possesses the ability to dynamically switch coding mechanisms based on the protocol version determined by the link training negotiation state machine. Specifically, when the external link negotiates a low-rate, early protocol due to device compatibility issues, the sub-physical coding sublayer automatically adopts 8-bit to 10-bit encoding / decoding logic; conversely, when negotiating a high-rate protocol, the sub-physical coding sublayer automatically switches to a more efficient 128-bit to 130-bit encoding / decoding logic, thereby effectively reducing the coding overhead of data transmission.

[0021] To further illustrate the specific physical implementation architecture and routing details of this invention, and in conjunction with the hardware instantiation configuration, the high-speed parallel-to-serial conversion port group in this embodiment is defined to contain two four-channel ports, namely the first four-channel high-speed parallel-to-serial conversion port and the second four-channel high-speed parallel-to-serial conversion port. The maximum theoretical width that this port station can support is eight channels. To adapt to various subsequent splitting and combination, the physical coding sublayer combination internal instantiation includes a computing resource pool: one eight-channel wide sub-physical coding sublayer, at least two four-channel wide sub-physical coding sublayers, and at least four two-channel wide sub-physical coding sublayers. Simultaneously, the system kernel provides corresponding eight-channel, four-channel, and first and second two-channel kernel data interfaces. Based on the above underlying hardware configuration, the system can derive various customized working modes.

[0022] When the system operates in eight-channel full-bandwidth mode, it is primarily used to connect high-bandwidth external devices. In this mode, the first channel selector connects the first and second four high-speed parallel-to-serial conversion ports to the lower four and higher four data ports of the eight-channel-wide sub-physical coding sublayer, respectively. This eight-channel-wide sub-physical coding sublayer receives the two data streams and performs clock skew compensation and joint decoding, merging them into a complete eight-channel parallel data stream. Finally, the second channel selector maps this entire data stream and directly transmits it to the eight-channel kernel data interface.

[0023] When the system executes the dual four-channel balanced splitting mode, the first channel selector acts as a traffic isolation unit, independently importing the data from the first and second four-channel high-speed parallel-to-serial conversion ports into the first and second four-channel width sub-physical coding sub-layers for parallel processing. Subsequently, the second channel selector connects the lower four bits of the parallel data stream output from the first four-channel width sub-physical coding sub-layer to the lower four bits of the eight-channel kernel data interface, and connects the higher four bits of the parallel data stream output from the second four-channel width sub-physical coding sub-layer to an independent four-channel kernel data interface, thereby splitting the decoded data to two independent transaction layer processing queues of the system.

[0024] When the system executes four sets of two-channel fragmentation modes, the two physical ports are logically divided into four independent channels to handle high-density external device access scenarios. The first channel selector independently routes the data from the low two and high two paths of the first four-channel high-speed parallel-to-serial conversion port, and the low two and high two paths of the second four-channel high-speed parallel-to-serial conversion port, into the first, second, third, and fourth two-channel width sub-physical encoding sub-layers for concurrent encoding and decoding tasks. After data processing, discrete mapping is performed, and the second channel selector independently connects the data from these four sub-physical encoding sub-layers to the low two bits of the eight-channel kernel data interface, the low two bits of the first two-channel kernel data interface, the low two bits of the four-channel kernel data interface, and the second two-channel kernel data interface.

[0025] When the system executes one set of four-channel plus two sets of two-channel asymmetric splitting modes, the first channel selector connects the entire first four-channel high-speed parallel-to-serial conversion port to the first four-channel width sub-physical coding sublayer; and connects the lower two and higher two paths of the second four-channel high-speed parallel-to-serial conversion port to the first and second two-channel width sub-physical coding sublayers respectively. After data encoding and decoding, the second channel selector connects the data stream output from the first four-channel width sub-physical coding sublayer to the lower four bits of the eight-channel kernel data interface; and connects the data streams output from the first and second two-channel width sub-physical coding sublayers to the independent first and second two-channel kernel data interfaces respectively. Correspondingly, the system also supports its mirror configuration logic (i.e., two sets of two-channel plus four-channel modes), and its splitting routing control process is symmetrically consistent with this.

[0026] When the system executes the cross-port split-aggregation mode, this configuration structure demonstrates the fault-tolerant routing capability of the digital domain. In this mode, the high two paths of the first four-channel high-speed parallel-to-serial conversion port and the low two paths of the second four-channel high-speed parallel-to-serial conversion port are jointly allocated to the same external device, forming a cross-boundary splicing of physical wiring. The first channel selector performs intelligent data scheduling in the digital domain, routing the two independent data paths that are not cross-boundary to the first and second two-channel width sub-physical coding sub-layers respectively; simultaneously, it captures and splices the data from the high two paths of the first four-channel high-speed parallel-to-serial conversion port and the low two paths of the second four-channel high-speed parallel-to-serial conversion port after cross-boundary aggregation, and routes them uniformly to a cross-domain four-channel width sub-physical coding sub-layer. This sub-physical coding sub-layer uses an internal elastic buffer to adaptively correct the timing offset caused by crossing physical channels. Finally, the second channel selector connects the data from the first and second two-channel width sub-physical coding sub-layers to the first and second two-channel core data interfaces respectively; and connects the data from the cross-domain four-channel width sub-physical coding sub-layer to an independent four-channel core data interface. This mode eliminates the impact of inconsistent hardware wiring sequence on data transmission at the logic layer, improving the flexibility of system-level topology design.

[0027] The parameters and calculations involved in the specific embodiments and mode variations described above can be adapted through data simulation and hardware prototype verification, and fine-tuned according to actual conditions. The various functional modules can be integrated into a single logic. The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-split configuration structure for a PCIe high-speed parallel-to-serial conversion port station, characterized in that, include: High-speed parallel-to-serial conversion port group, first channel selector, physical coding sublayer combination and second channel selector; The lower end of the high-speed parallel-to-serial conversion port group is configured to connect to the physical interface of an external expansion device, and its upper end is connected to the first end of the first channel selector. It is used to convert high-speed serial data transmitted by downstream devices into low-speed parallel data streams in the receiving direction, and to convert low-speed parallel data streams transmitted by upstream systems into high-speed serial data and output them in the form of differential signals in the transmitting direction. The second end of the first channel selector is connected to the first end of the physical coding sublayer combination, and is used to establish a precise data interaction connection between the high-speed parallel-to-serial conversion port group and a specific sub-physical coding sublayer in the physical coding sublayer combination by dynamically reconstructing the underlying data path according to the preset port splitting configuration instruction. The second end of the physical coding sublayer combination is connected to the first end of the second channel selector. The physical coding sublayer combination contains multiple sub-physical coding sublayers with different numbers and different data widths, which are used to encode the parallel data stream transmitted by the first channel selector and then transmit it to the second channel selector, or to decode the parallel data stream transmitted by the second channel selector and then transmit it to the first channel selector. The second end of the second channel selector is configured to connect to multiple sets of kernel data interfaces of different widths, and is used to allocate and establish interactive mapping paths for parallel data streams between each sub-physical coding sublayer of the physical coding sublayer combination and the kernel data interface according to the port splitting configuration instruction.

2. The PCIe high-speed parallel-to-serial conversion port station multi-split configuration structure according to claim 1, characterized in that, The high-speed parallel-to-serial conversion port group integrates a link adaptive equalization module. The link adaptive equalization module is configured to detect the channel quality and signal integrity characteristics of the external link in real time, and adaptively and dynamically adjust the circuit configuration parameters of the internal receiver or transmitter according to the channel attenuation parameter, and select the optimal signal compensation configuration parameters according to the equalization calculation result to maintain link stability.

3. The PCIe high-speed parallel-to-serial conversion port station multi-split configuration structure according to claim 2, characterized in that, Each sub-physical coding sublayer within the physical coding sublayer combination supports multi-protocol version compatible encoding and decoding logic and has the ability to dynamically switch encoding mechanisms according to the link negotiation rate. When the external link negotiation is a low-rate protocol standard, the sub-physical coding sublayer uses eight-bit to ten-bit encoding and decoding logic to process parallel data streams. When the external link negotiation is a high-rate protocol standard, the sub-physical coding sublayer uses one hundred and twenty-eight-bit to one hundred and thirty-bit encoding and decoding logic to process parallel data streams.

4. The PCIe high-speed parallel-to-serial conversion port station multi-split configuration structure according to claim 3, characterized in that, The port station includes a physical structure with a maximum physical bandwidth of eight channels, and the high-speed parallel-to-serial conversion port group is specifically composed of a first four-channel high-speed parallel-to-serial conversion port and a second four-channel high-speed parallel-to-serial conversion port. The physical coding sublayer combination includes at least: one eight-channel width sub-physical coding sublayer, two four-channel width sub-physical coding sublayers, and four two-channel width sub-physical coding sublayers. The kernel data interface includes at least: an eight-channel kernel data interface, a four-channel kernel data interface, a first two-channel kernel data interface, and a second two-channel kernel data interface.

5. The PCIe high-speed parallel-to-serial conversion port station multi-split configuration structure according to claim 4, characterized in that, When the multi-split configuration structure is configured in eight-channel full-bandwidth mode: The first channel selector connects the first four-channel high-speed parallel-to-serial conversion port to the lower four data ports of the eight-channel width sub-physical coding sub-layer, and connects the second four-channel high-speed parallel-to-serial conversion port to the higher four data ports of the eight-channel width sub-physical coding sub-layer. The eight-channel width sub-physical coding sublayer is used to receive the low four and high four parallel data streams and merge them into a complete eight-channel parallel data stream. The second channel selector is configured to map the entire eight-channel parallel data stream and pass it directly to the eight-channel kernel data interface.

6. The PCIe high-speed parallel-to-serial conversion port station multi-split configuration structure according to claim 5, characterized in that, When the multi-split configuration structure is configured as a dual four-channel balanced split mode: The first channel selector connects the first four-channel high-speed parallel-to-serial conversion port to the data port of the first four-channel width sub-physical coding sub-layer in the physical coding sub-layer combination, and connects the second four-channel high-speed parallel-to-serial conversion port to the data port of the second four-channel width sub-physical coding sub-layer. The second channel selector connects the lower four bits of the parallel data stream output by the first four-channel width sub-physical coding sub-layer to the lower four bits of the eight-channel kernel data interface, and connects the higher four bits of the parallel data stream output by the second four-channel width sub-physical coding sub-layer to the independent four-channel kernel data interface, thereby forming two parallel data transmission paths.

7. The PCIe high-speed parallel-to-serial conversion port station multi-split configuration structure according to claim 6, characterized in that, When the multi-split configuration structure is configured as a four-group two-channel fragmentation mode: The first channel selector independently connects the low two and high two paths of the first four-channel high-speed parallel-to-serial conversion port to the first two-channel width sub-physical coding sub-layer and the second two-channel width sub-physical coding sub-layer, respectively; and independently connects the low two and high two paths of the second four-channel high-speed parallel-to-serial conversion port to the third two-channel width sub-physical coding sub-layer and the fourth two-channel width sub-physical coding sub-layer, respectively. The second channel selector independently connects the parallel data streams output by the first, second, third, and fourth channel width sub-physical coding sub-layers to the lower two bits of the eight-channel kernel data interface, the lower two bits of the first two-channel kernel data interface, the lower two bits of the four-channel kernel data interface, and the second two-channel kernel data interface, respectively.

8. The PCIe high-speed parallel-to-serial conversion port station multi-split configuration structure according to claim 7, characterized in that, When the multi-split configuration structure is configured as a set of four-channel plus two sets of two-channel asymmetric split modes: The first channel selector connects the first four-channel high-speed parallel-to-serial conversion port as a whole to the first four-channel width sub-physical coding sub-layer; and connects the low two paths and the high two paths of the second four-channel high-speed parallel-to-serial conversion port to the first two-channel width sub-physical coding sub-layer and the second two-channel width sub-physical coding sub-layer, respectively. The second channel selector connects the parallel data stream output by the first four-channel width sub-physical coding sublayer to the lower four bits of the eight-channel kernel data interface; and connects the parallel data streams output by the first and second two-channel width sub-physical coding sublayers to the first two-channel kernel data interface and the second two-channel kernel data interface, respectively.

9. A multi-split configuration structure for a PCIe high-speed parallel-to-serial conversion port station according to claim 8, characterized in that, When the multi-split configuration structure is configured in cross-port split aggregation mode: The first channel selector connects the two lower paths of the first four-channel high-speed parallel-to-serial conversion port to the first two-channel width sub-physical coding sub-layer; it aggregates the two higher paths of the first four-channel high-speed parallel-to-serial conversion port and the two lower paths of the second four-channel high-speed parallel-to-serial conversion port together across the boundary and connects them to the first four-channel width sub-physical coding sub-layer; and it connects the two higher paths of the second four-channel high-speed parallel-to-serial conversion port to the second two-channel width sub-physical coding sub-layer. The second channel selector connects the parallel data stream output by the first two-channel width sub-physical coding sub-layer to the first two-channel kernel data interface; connects the parallel data stream output by the first four-channel width sub-physical coding sub-layer to the four-channel kernel data interface; and connects the parallel data stream output by the second two-channel width sub-physical coding sub-layer to the second two-channel kernel data interface.

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