Integrated electronic system for optical coherence tomography

Abstract

The disclosed technology relates to an integrated electronics system for OCT. In some examples, the integrated electronics system includes an integrated circuit configured to generate image data based on OCT interference signals for display. The integrated circuit includes an analog circuit, a core processing subsystem, and a backend processing subsystem. The analog circuit receives and digitizes the OCT interference signals to generate digitized interference signals. The core processing subsystem generates image data based on the digitized interference signals. The backend processing subsystem receives and processes the image data for display to a user.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefits of the following applications: U.S. Provisional Application No. 63 / 534554, filed August 24, 2023, entitled "System on Chip for OCT systems," and U.S. Patent Application No. 18 / 814367, filed August 23, 2024, entitled "Integrated Electronic System for Optical Coherence Tomography." The entire disclosure of each of these applications is incorporated herein by reference in its entirety for all purposes.

[0003] Any and all applications that identify foreign or domestic priority claims in the application data sheet filed with this application are incorporated herein by reference for all purposes and all contents contained herein in accordance with 37 CFR 1.57. Technical Field

[0004] This disclosure relates to systems and techniques for optical coherence tomography (OCT). More specifically, this disclosure relates to electronic systems for implementing OCT-related applications. Background Technology

[0005] The methods described in this section are merely possible methods and are not necessarily methods that have been conceived or implemented in advance. Therefore, unless otherwise stated, any method described should not be considered prior art simply because it is included in this section.

[0006] Optical coherence tomography (OCT) is a medical and biological imaging technique. OCT uses low-coherence interferometry to perform optical ranging within biological samples. OCT provides a unique tool for visualizing micron-level tissue features and structures with depth resolution. Summary of the Invention

[0007] The systems, methods, and apparatuses described herein each have multiple aspects, none of which can completely determine their ideal characteristics. Without limiting the scope of this disclosure, several non-limiting features will now be briefly described.

[0008] Optical coherence tomography (OCT) is an imaging technology widely used in medical, metrology, and industrial applications. Current OCT systems typically employ multiple discrete boards (e.g., printed circuit boards (PCBs)) and / or cards (e.g., data acquisition cards (DAQs)) deployed alongside associated optical or electrical components to achieve various functions. For example, an OCT system might use one board to capture optical signals and convert them into electrical signals, another board to control peripheral components (e.g., galvanometer scanners, protection circuits, etc.), and yet another board to control the laser module. Additionally, OCT systems can use discrete cards to linearize, process, and / or reconstruct image data based on digitized interferometric signals. OCT systems can also utilize computer workstations, laptops, and / or discrete graphics cards to display or render images to the user based on the image data. However, this unintegrated and segmented implementation may be insufficient to meet the growing demands of OCT systems, at least in terms of latency, resolution, signal bandwidth and / or data rate, and cost. For example, latency can arise from the physical interconnections between different boards, the resulting handshake protocols, and / or other necessary communications. Signal bandwidth may be limited by signal traces, discrete chip packaging, and wires connecting discrete boards and / or cards in the OCT system. As another example, signal quality may be degraded due to noise injection as signals are transmitted through physical connections between boards.

[0009] This disclosure implements an integrated electronic system (e.g., a system-on-chip (SoC)) that advantageously overcomes the various technical challenges described above, as well as others. In some embodiments, this integrated electronic system integrates at least some electronic subsystems within a single integrated circuit (IC) for implementing OCT-related applications. For example, compared to using multiple boards and / or cards to display OCT images, this integrated electronic system is capable of processing analog signals converted from optical signals (e.g., OCT interference signals), generating linear interference signals, reconstructing OCT images based on the linear interference signals, and displaying the OCT images within the IC. Advantageously, the integrated electronic system, at least due to its integrated nature, can achieve shorter latency while providing a cost-effective and reliable solution for implementing certain OCT applications. Furthermore, since the integrated electronic system requires or uses fewer cards or boards, the integration complexity and size of the OCT system can be reduced. Moreover, compared to other OCT systems employing fewer integrated electronic subsystems, performance related to the OCT system (e.g., resolution, a-line rate, ranging depth, throughput, etc.) can be improved.

[0010] In some aspects, the technology described herein relates to an integrated electronic system for optical coherence tomography (OCT), the integrated electronic system comprising: an integrated circuit (IC) configured to generate image data based on OCT interference signals for display, the IC comprising: analog circuitry configured to receive and digitize the OCT interference signals to generate digitized interference signals; a core processing subsystem configured to generate image data based on the digitized interference signals; and a back-end processing subsystem configured to receive the image data and display it to a user.

[0011] In some respects, the techniques described herein relate to an integrated electronic system in which a core processing subsystem includes a neural network (NN) model, a linearization circuit, or a reconstruction algorithm configured to process digitized interferometric signals to generate reconstructed interferometric signals.

[0012] In some respects, the techniques described in this paper relate to an integrated electronic system in which the dataset used for training the NN model includes a k-clock signal, a reconstructed OCT interference signal, and variations of the k-clock signal.

[0013] In some respects, the technology described herein relates to an integrated electronic system in which a core processing subsystem includes a reconstruction pipeline configured to reconstruct interferometric signals to generate image data.

[0014] In some respects, the technology described herein relates to an integrated electronic system in which a back-end processing subsystem includes a first path and a second path configured to receive image data and display it to a user, and wherein the first path has lower latency compared to the second path.

[0015] In some respects, the technology described herein relates to an integrated electronic system in which: analog circuitry includes multiple analog-to-digital converters (ADCs) configured to digitize OCT interference signals to generate digitized interference signals; and a core processing subsystem configured to generate control signals to reconfigure the multiple ADCs according to the application associated with the integrated electronic system.

[0016] In some respects, the technology described herein relates to an integrated electronic system, which also includes a printed circuit board (PCB) on which an IC and multiple peripheral components are deployed.

[0017] In some respects, the technology described herein relates to an integrated electronic system in which a core processing subsystem is configured to generate multiple control signals to control multiple peripheral components.

[0018] In some respects, the technology described herein relates to an integrated electronic system in which analog circuitry includes multiple digital-to-analog converters (DACs) configured to convert multiple control signals into multiple analog signals to control multiple peripheral components.

[0019] In some respects, the technology described herein relates to an integrated electronic system in which multiple peripheral components include temperature sensors, fans, laser components, cameras, optical sensors, or microelectromechanical systems (MEMS) components.

[0020] In some respects, the technology described herein relates to an integrated electronic system that also includes a graphics processing unit (GPU), wherein a back-end processing subsystem enables image data to be transferred to the GPU for display to the user.

[0021] In some respects, the technology described herein relates to a printed circuit assembly comprising: an optical detector configured to receive one or more optical signals and generate an OCT interference signal based on at least one or more optical signals; an integrated circuit (IC) configured to generate image data based on the OCT interference signal; and an image data interface configured to receive image data from the IC and transmit the image data to an external device for display to a user.

[0022] In some respects, the technology described herein relates to a printed circuit assembly in which the image data interface is a Thunderbolt port, a DisplayPort connector, an OCuLink connector, a Universal Serial Bus (USB) port, a High Definition Multimedia Interface (HDMI) port, an Ethernet connector, or a Peripheral Component Interconnect Express (PCIe) connector.

[0023] In some respects, the technology described herein relates to a printed circuit assembly, wherein the IC includes: an analog front-end (AFE) configured to receive and digitize an OCT interference signal to generate a digitized interference signal; a core processing subsystem configured to generate image data based on the digitized interference signal; and a back-end processing subsystem configured to receive image data from the core processing subsystem and transmit the image data to an image data interface.

[0024] In some respects, the technology described herein relates to a printed circuit assembly that also includes multiple peripheral components, wherein a core processing subsystem is configured to control the multiple peripheral components.

[0025] In some respects, the technology described herein relates to a printed circuit assembly in which the external device is a laptop, computer workstation, discrete graphics card, or mobile device.

[0026] In some respects, the techniques described herein relate to a printed circuit assembly in which one or more optical signals include an interferometric OCT signal or an interferometric k-clock signal.

[0027] In some respects, the technology described herein relates to an integrated circuit (IC) comprising: an analog circuit configured to receive and digitize an OCT interference signal to generate a digitized interference signal; a core processing subsystem configured to generate image data based on the digitized interference signal; and a back-end processing subsystem configured to receive the image data and display it to a user.

[0028] In some respects, the technology described herein relates to an integrated circuit in which a core processing subsystem includes a neural network (NN) model configured to reconstruct digitized interferometric signals to generate reconstructed interferometric signals.

[0029] In some respects, the technology described herein relates to an integrated circuit in which a back-end processing subsystem includes a first path and a second path configured to receive image data and transmit it to an image data interface, and wherein the first path has lower latency compared to the second path.

[0030] This disclosure also discloses and contemplates various combinations of the features, embodiments, implementation methods and aspects described above and below.

[0031] Additional embodiments of this disclosure are described below with reference to the appended claims, which may serve as an additional summary of this disclosure. Attached Figure Description

[0032] The following figures and related descriptions are used to describe embodiments of the present disclosure, but do not limit the scope of the claims. The aspects and many advantages of this disclosure will become more readily understood and appreciated by referring to the following detailed description in conjunction with the accompanying drawings, wherein:

[0033] Figure 1 This is a block diagram illustrating an exemplary OCT system including OCT electronic devices according to various embodiments of the present disclosure;

[0034] Figure 2 This illustrates an exemplary integrated electronic system according to various embodiments of the present disclosure, which can be used to implement... Figure 1 Some or all of the functions of OCT electronic devices;

[0035] Figure 3 It is based on various embodiments of this disclosure. Figure 2 An exemplary block diagram of an analog circuit in an integrated electronic system;

[0036] Figure 4A It is based on various embodiments of this disclosure. Figure 2 An exemplary block diagram of the core processing subsystem of a centrally integrated electronic system;

[0037] Figure 4B It is based on various embodiments of this disclosure. Figure 4A An exemplary block diagram of a refactoring pipeline for the core processing subsystem;

[0038] Figure 4C It is based on various embodiments of this disclosure. Figure 2 Another exemplary block diagram of the core processing subsystem of the integrated electronic system;

[0039] Figure 5 It is based on various embodiments of this disclosure. Figure 2 Block diagram of the back-end processing subsystem of the integrated electronic system;

[0040] Figure 6 Various embodiments according to this disclosure are shown. Figure 2 An exemplary integration scheme for at least some parts of an integrated electronic system;

[0041] Figure 7 This invention illustrates various embodiments of the invention, and... Figure 2 Exemplary waveforms associated with integrated electronic systems;

[0042] Figure 8 Various laser nonlinear waveforms according to various embodiments of the present disclosure are shown;

[0043] Figure 9 Exemplary contour plots according to various embodiments of this disclosure are shown, illustrating the effects of certain OCT applications. Figure 1 The performance requirements of the OCT system in the text; and

[0044] Figure 10 This invention illustrates various embodiments of the invention, and... Figure 2 Exemplary waveforms associated with integrated electronic systems. Detailed Implementation

[0045] Although certain preferred embodiments, examples, and examples are disclosed below, the scope of protection of this inventive subject extends to these specifically disclosed embodiments, covering other alternative embodiments and / or uses, modifications thereof, and their equivalents. Therefore, the scope of the appended claims is not limited to any particular embodiment described below. For example, in any method or process disclosed herein, the actions or operations of the method or process may be performed in any suitable order and are not necessarily limited to any particular disclosed order. Although multiple operations may be described sequentially as multiple discrete operations for ease of understanding of certain embodiments, the order of description should not be construed as implying a sequential dependency between these operations. Furthermore, the structures, systems, and / or devices described herein may be embodied as integrated components or separate components. Certain aspects and advantages of these embodiments are described for the purpose of comparing the various embodiments. It is not necessary to achieve all such aspects or advantages through any particular embodiment. Therefore, for example, multiple embodiments may be implemented in a manner that achieves or optimizes one or a set of advantages taught herein, without necessarily simultaneously achieving other aspects or other advantages that may be similarly taught or suggested herein.

[0046] Overview

[0047] As mentioned above, optical coherence tomography (OCT) is an imaging technology widely used in medical, metrology, and industrial applications. OCT systems typically employ multiple discrete boards (e.g., printed circuit boards (PCBs)) and / or cards (e.g., data acquisition cards (DAQs)) deployed together with associated optical or electrical components to achieve various functions. For example, an OCT system might use one board to capture optical signals and convert them into electrical signals, another board to control peripheral components (e.g., galvanometer scanners, protection circuits, etc.), and yet another board to control the laser module. Additionally, OCT systems can use discrete cards to linearize, process, and / or reconstruct image data based on digitized interferometric signals. OCT systems can also use computer workstations, laptops, and / or discrete graphics cards to display or render images to the user based on the image data. However, this unintegrated and segmented implementation may fail to meet the growing demands associated with OCT systems in at least several ways.

[0048] First, the unintegrated nature of OCT systems can increase latency (e.g., the time it takes for an OCT system to generate images based on optical signals) or at least become a bottleneck for latency reduction, which may be crucial for certain applications (e.g., real-time intraoperative, metrology, and examination). For example, latency can be caused by physical interconnects, signal traces, or wires connecting discrete boards and / or cards of the OCT system. Communication between boards and / or cards (e.g., handshakes or synchronization based on certain communication protocols, conversions or decoding between various data formats supported by the various subsystems used for data processing, etc.) can also lead to additional latency.

[0049] Secondly, achieving superior performance, such as generating images with higher resolution, higher line rates, wider detection range, and better signal quality and / or bandwidth, can be crucial. However, the unintegrated nature of OCT systems can be detrimental to improved signal quality. For example, optical signals captured and converted into electrical signals by on-board optical detectors may be transmitted via inter-board transmission lines to an analog-to-digital converter (ADC) on another board for digitization. Noise can be introduced during transmission through physical inter-board connections, degrading the quality of the electrical signal (e.g., integrity, signal-to-noise ratio). Furthermore, data conversion and decoding (e.g., serial-to-parallel conversion) processed between discrete boards or cards can introduce noise into the transmitted signal, leading to a deterioration in signal quality and performance metrics.

[0050] Furthermore, to achieve higher throughput, it may be desirable to implement an OCT system that supports higher signal bandwidth or sampling rates. While signal bandwidth can be increased by providing multiple channels for communication, implementing multiple channels between discrete boards and / or cards may require more hardware (e.g., wires, cables, connectors, interface modules, etc.), which can make the OCT system more complex or difficult to maintain. Using multiple boards, interface modules, wires, or connectors may further increase the size and cost of manufacturing or assembling the OCT system.

[0051] Alternatively, higher throughput can be achieved by increasing the sampling rate. For example, an OCT system can use an ADC operating at a higher sampling clock to generate a digitized signal with a higher sampling rate, and then transmit this digitized signal to a digital signal processor (DSP) on another board for further processing. However, at high frequencies or high sampling rates, signal interference between wires or cables between boards can be severe or exacerbated when transmitting signals through discrete boards, leading to performance degradation.

[0052] As described above, this disclosure implements an integrated electronic system (e.g., a system-on-a-chip (SoC)) that advantageously overcomes the various technical challenges mentioned above, as well as others. In some embodiments, this integrated electronic system integrates at least some electronic subsystems within a single integrated circuit (IC) for implementing OCT-related applications. For example, compared to using multiple boards and / or cards to display OCT images, this integrated electronic system is capable of processing analog signals converted from optical signals (e.g., OCT interference signals), generating linear interference signals, reconstructing OCT images based on the linear interference signals, and displaying the OCT images within the IC. Advantageously, the integrated electronic system, at least due to its integrated nature, can achieve shorter latency while providing a cost-effective and reliable solution for implementing certain OCT applications. Furthermore, since the integrated electronic system requires or uses fewer cards or boards, the integration complexity and size of the OCT system can be reduced. Moreover, compared to other OCT systems employing fewer integrated electronic subsystems, performance related to the OCT system (e.g., resolution, line rate, depth range, throughput, etc.) can be improved.

[0053] More specifically, integrated electronic systems can achieve shorter latency by integrating multiple functions into an IC (e.g., an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Array of Logics (FPGA), a combination of ASIC and FPGA, etc.) and eliminating the need for some of the wires, cables, or other connections required to connect multiple boards and / or cards. Therefore, the latency associated with inter-board connections can at least be avoided or reduced because integrated electronic systems use shorter signal paths to transmit signals. To further reduce latency, integrated electronic systems can use high-speed interfaces (e.g., the Peripheral Component Interconnect High Speed ​​Standard (PCIe)) to transmit the reconstructed OCT image to host and / or post-processing circuitry for processing and then display. Additionally and / or alternatively, integrated electronic systems can integrate the IC and the optical detector on a single board (e.g., a PCB). Therefore, the latency associated with the signal path between the optical detector and the IC analog circuitry can also be reduced due to the shortened transmission path.

[0054] To achieve higher throughput, integrated electronic systems can utilize multiple channels to receive and / or transmit optical and analog signals. In some implementations, the analog circuitry of the IC can use eight channels (e.g., each channel has an ADC) to digitize analog signals in parallel and transmit the digitized signals in parallel for linearization and / or image reconstruction. Compared to other OCT systems where analog and digital circuitry are deployed on separate boards, implementing multiple channels within the IC of an integrated electronic system does not increase the complexity of system integration, nor does it cause signal quality degradation due to signal transmission via inter-board wiring.

[0055] Additionally, eliminating certain connections between boards and / or performing data format conversions (e.g., serial-to-parallel conversion) helps maintain signal quality because less noise is introduced during communication. Furthermore and / or optionally, integrating the optical detector and IC onto the same board can enhance noise immunity associated with the signal paths between the analog circuitry of the optical detector and IC. Therefore, superior system performance (e.g., higher resolution, better signal-to-noise ratio (SNR)) can be achieved.

[0056] Example features related to system integration

[0057] As described above, by integrating at least a variety of electronic subsystems for OCT applications into an IC to form a System-on-a-Chip (SoC), excellent performance can be achieved through integrated electronic systems. In some implementations, the integrated electronic system may include analog circuitry (e.g., analog front-end, ADC, and DAC), a core processing subsystem, and a back-end processing subsystem. The core processing subsystem, the back-end processing subsystem, and at least a portion of the analog circuitry can all be implemented in the IC. Additionally and / or optionally, the integrated electronic system may also include an optical detector for receiving optical signals (e.g., OCT interference signals) and converting them into electrical signals (e.g., the electrical form of the OCT interference signal). Both the optical detector and the IC can be deployed on a board (e.g., a PCB). To achieve a higher level of system integration, some peripheral devices (e.g., laser modules, cameras, thermal detectors, microelectromechanical systems (MEMS), etc.) may also be deployed on the board.

[0058] Example features related to analog circuits

[0059] Integrated electronic systems can process electrical signals received from optical detectors to generate digital signals. In some embodiments, the integrated electronic system may include multiple channels (e.g., two, four, eight, twelve, etc.) for receiving electrical signals (e.g., OCT interference signals) converted by the optical detectors. Each of the multiple channels may include an ADC that digitizes the electrical signals (e.g., k-clock signals, OCT interference signals). As mentioned above, the ADC and the optical detector can be deployed on the same board, thereby achieving better noise immunity and reducing costs. Advantageously, multiple channels enable the integrated electronic system to provide greater signal bandwidth for improved performance (e.g., higher throughput).

[0060] The integrated electronic system may also include multiple channels for transmitting control signals generated by the core processing subsystem and / or back-end processing subsystem to control peripheral devices on the board. Each of the multiple channels for transmitting control signals may include a digital-to-analog converter (DAC), which converts digital signals into analog signals for controlling peripheral devices.

[0061] Example features related to the core processing subsystem

[0062] Integrated electronic systems can process electrical signals received from an analog front end to generate image data. In some implementations, the integrated electronic system (e.g., a signal processing engine) can linearize and / or reconstruct the image data based on a k-clock signal and an OCT interferometer signal. The integrated electronic system can utilize a neural network (NN) model to reconstruct the OCT interferometer signal. The NN model can be trained using a dataset that includes a k-clock model, the corresponding linearized OCT interferometer signal, and variations of the k-clock signal to achieve better performance in linearization. Based on the linearized interferometer signal, the integrated electronic system (e.g., a reconstruction pipeline) can also reconstruct the image data through operations including background noise removal, dispersion compensation, FFT, logarithmic scaling, display scaling, etc.

[0063] Integrated electronic systems (such as acquisition engines) can transmit image data to back-end processing systems for displaying or rendering OCT images. In some implementations, the integrated electronic system may include two paths for displaying OCT images. To reduce latency in certain applications, the integrated electronic system may utilize a high-speed path to transmit image data for display. The high-speed path may utilize a PCIe interface for data transmission. For applications with lower latency requirements, the integrated electronic system may utilize a normal-speed path (e.g., via a memory controller) to transmit image data for display.

[0064] Furthermore, integrated electronic systems can establish direct and low-latency communication channels between analog circuits, on-board peripherals, and / or the core processing subsystem. For example, an acquisition engine can generate control signals to enable high-speed control of analog circuits and / or peripherals. Because the acquisition engine can operate at higher speeds and higher clock frequencies and / or without firmware intervention (e.g., compared to the back-end processing system), control of analog circuits and / or peripherals can be performed in a more real-time manner, responding to or adjusting the integrated electronic system in a timely manner, thereby achieving better performance. Additionally and / or optionally, the acquisition engine can control analog circuits and / or peripherals based on settings or parameters received from the back-end processing subsystem.

[0065] In some examples, integrated electronic systems (such as acquisition engines) can reconfigure analog circuitry depending on the application. For instance, in applications where the integrated electronic system does not require linearization of the OCT interference signal, it can disable certain channels in the analog circuitry. In other applications, the integrated electronic system can enable more channels in the analog circuitry and / or increase the sampling rate associated with the analog circuitry.

[0066] Example features related to the backend processing subsystem

[0067] Integrated electronic systems (e.g., back-end processing subsystems) can transmit and / or process image data generated by the core processing subsystem for displaying OCT images. In some implementations, compared to displaying OCT images using a computer workstation, the integrated electronic system can display OCT images by transmitting image data to a display unit via a display port interface. By integrating the display port interface and the SoC on the same board, latency can be significantly reduced (e.g., from a few milliseconds to tens of milliseconds).

[0068] Additionally and / or optionally, depending on the application, the integrated electronic system may employ a graphics processing unit (GPU) to render image data generated by the core processing subsystem. For example, when used for applications that may require intensive image processing, such as feature recognition, cancer detection, and tissue separation, the integrated electronic system may transfer image data to the GPU for rendering. In some implementations, the GPU may be on a separate board, different from the board on which the SoC is deployed.

[0069] Example features related to peripheral device control

[0070] As described above, integrated electronic systems can integrate peripheral devices, ICs including ADCs and DACs, core processing subsystems, and back-end processing subsystems onto a single board. Peripheral devices can be controlled by the IC to perform certain control and protection functions. For example, the IC can control a camera that captures optical signals via a MEMS module deployed on the board. As another example, the IC can coordinate with temperature sensors and fans to provide thermal protection (e.g., cooling) to prevent overheating from performing intensive computations and synchronization operations. As yet another example, the IC can transmit control signals to peripheral devices to perform various functions, such as calibrating a laser module or camera. By integrating peripheral devices and ICs onto the same board and utilizing high-speed logic (e.g., the core processing subsystem) to generate control signals for controlling the peripheral devices, calibration and / or adjustments associated with the integrated electronic system can be performed in real time.

[0071] Additional example information related to various implementation methods

[0072] To facilitate understanding of the systems and methods discussed herein, several terms are described below and throughout this document. These terms, as well as other terms used herein, should be interpreted to include the descriptions provided, the ordinary and conventional meanings of the terms, and / or any other implied meanings of the corresponding terms, where such interpretation should be consistent with the context in which the terms are used. Therefore, the descriptions below and throughout this document do not limit the meaning of these terms, but are provided only as illustrative examples.

[0073] As used in this disclosure, the term "model" can include any type and any level of complexity of computer models, such as any type of sequential, functional, or concurrent model. A model can also include various types of computational models, such as artificial neural networks ("NN"), language models (e.g., large language models ("LLMs")), artificial intelligence ("AI") models, machine learning ("ML") models, multimodal models (e.g., models or combinations of models that can accept multiple modal inputs, such as images and text), etc.

[0074] The term "OCT signal" can refer to the optical signal used in an OCT system. An OCT signal can originate from a light source and be directed toward the sample being imaged. An OCT signal can include OCT interference signals and other optical signals used in an OCT system. An OCT interference signal can be the result of a combination of light backscattered from the sample and light reflected from a reference mirror.

[0075] Example OCT system

[0076] Figure 1 An exemplary optical coherence tomography (OCT) system 100 is illustrated. The example OCT system 100 includes OCT optics 140, OCT electronics 120, and user equipment 160. OCT optics 140 includes a light source 140A, an interferometer 140B, photodetectors 140E and 140G, a k-clock interferometer 140F, a scanner 140H, a safety interlock 140I, a sample arm 140C, and a reference arm 140D. Within OCT optics 140, light from the light source 140A (e.g., a broadband light source with short-time coherence, a tunable wavelength laser source, etc.) can be emitted and guided to illuminate a sample (e.g., tissue in the human eye, not in the eye). Figure 1 (As shown in the figure). The light scattered from the sample can be collected and combined with the reference light to form an OCT interference signal. The OCT interference signal can be detected by an optical detector and converted into an electrical form of the OCT interference signal (e.g., current and / or voltage) for processing by OCT electronics 120 to generate an OCT image, which can be transmitted to user equipment 160 and displayed on user equipment 160.

[0077] In some examples, light source 140A can be a broadband light source with short-time coherence, such as a tunable wavelength laser. The beam emitted by the light source is guided into interferometer 140B. In scanning source OCT (SS-OCT), a tunable laser is used to scan a series of wavelengths, providing the spectral information required for imaging. Interferometer 140B can split the light from light source 140A into two paths, corresponding to the sample arm path and the reference arm, respectively. Interferometer 140B can use a beam splitter to divide or separate the light. In sample arm 140C, light is guided toward biological tissue or the sample being imaged. The light penetrates the tissue or sample and is scattered back from different depths within the sample. The scattered light carries information about the internal structure of the tissue or sample. In reference arm 140D, light is guided toward a reference mirror. The reference mirror reflects the light back to the beam splitter. The reference arm provides a known reference path length, which is used to generate an interference pattern when combined with light from the sample arm.

[0078] In some examples, photodetectors 140E and 140G are used to detect the interference signal generated when light from the sample arm and reference arm recombines at the beam splitter. The interference pattern contains information about the depth and structure of the sample. Photodetectors 140E and 140G convert the optical interference signal into an electrical signal that can be processed by OCT electronics 120. A k-clock interferometer 140F is used in the scanning source OCT system to generate a k-clock signal. This signal provides instantaneous wavenumber information about the scanning laser source, which is used to linearize the interference signal in the wavenumber domain. The k-clock signal helps correct nonlinearities in the laser scanning. A scanner 140H (e.g., a galvanometer scanner) is used to guide the beam through the sample in a controlled manner. By scanning the beam in two dimensions, the OCT system 100 can create a cross-sectional or volumetric image of the sample. The scanner ensures that different regions of the sample are illuminated and imaged sequentially. A safety interlock 140I is a protective mechanism that ensures the OCT system 100 operates within safe limits. It may include functions such as power monitoring and automatic shutdown to prevent excessive exposure to the light source, which could potentially cause harm to the sample or the user.

[0079] like Figure 1As shown, a typical OCT electronics device 120 includes multiple discrete components (e.g., amplifiers 120A and 120B, digitizer 120D, controller 120C, and GPU 120K), which must be interconnected via wires, cables, connectors, and / or the like. Some of these components (e.g., digitizer 120D and controller 120C) include even more refined discrete components (e.g., FPGA 120S, processor 120I, memory 120J, FPGA 120L, processor 120Y, and memory 120P). For example, digitizer 120D and / or controller 120C use discrete chips connected on a printed circuit board. In some examples, amplifiers 120A and 120B are used to convert captured OCT interference signals (e.g., captured using photodetector 140E) from current to voltage, and then amplify the OCT interference signals. Within the digitizer 120D, components 120E and 120F are used for signal conditioning and conversion of the signal into a differential signal, while components 120G and 120H can convert analog signals into digital signals. The digital signals are then passed to the FPGA 120S for data manipulation, processing, linearization, processing, and / or reconstruction of image data.

[0080] Image data can be transmitted to user equipment 160 (e.g., a computer or mobile device) and GPU 120K. Digitizer 120D utilizes processor 120I and memory 120J to perform certain tasks. Within controller 120C, FPGA 120L is used for data manipulation and processing, and for communication with user equipment 160. Data generated by FPGA 120L is then transmitted to digital-to-analog converter 120M and signal conditioning module 120N to control peripheral components (e.g., scanner 140H and safety interlock 140I). Figure 1 In the discrete electronic system shown, communication between some critical components is typically achieved via one or more cables 120Q and 120R, which leads to limitations in electronic characteristics such as bandwidth and noise. Similarly, the separate packaging of discrete components on the board can cause performance limitations regarding bandwidth and noise. As mentioned above, to improve performance, reliability, or reduce cost, it may be necessary to integrate some or all of the components of the controller 120C and digitizer 120D of the OCT electronics 120.

[0081] Exemplary integrated electronic systems and block diagrams

[0082] Figure 2Exemplary integrated electronic systems 200 according to various embodiments of this disclosure are depicted. In many embodiments, the integrated electronic system 200 can be used to replace OCT electronics 120 and / or implement some or all of the functions of OCT electronics 120 in OCT system 100. Compared to OCT electronics 120, according to some embodiments, the integrated electronic system 200 can be implemented on a single board (e.g., PCB, motherboard, master board, etc.). Figure 2 As shown, the integrated electronic system 200 includes an integrated circuit 210, peripheral devices 230, an analog front-end 240, an image data interface 250, input / output (I / O) circuitry 270, a read-only memory (ROM) 260 including a basic input / output system (BIOS) 262, and a graphics processing unit (GPU) 280.

[0083] Integrated circuit 210 includes an ADC / DAC 212 (which may include one or more analog-to-digital converters (ADCs) and / or one or more digital-to-analog converters (DACs)), a core processing subsystem 214, and a back-end processing subsystem 216. Integrated circuit 210 may optionally include memory 218 and memory 220. Memory 218 may be dedicated to and accessed by the core processing subsystem 214. Memory 220 may be dedicated to and accessed by the back-end processing subsystem 216. Core processing subsystem 214 and back-end processing subsystem 216 may include one or more processors and programmable logic (PL) for performing various signal processing and arithmetic operations. Figure 2 The connections and data flows shown are merely examples of some of the processing procedures performed by the integrated electronic system 200, and are not intended to include all possible functional modules and related components. Furthermore, some or all of the components shown in the block diagram (e.g., I / O circuitry 270, ROM 260, image data interface 250, GPU 280) may be optional for the integrated electronic system 200, or may be integrated into the integrated circuit 210. Figure 2 As shown, the ADC / DAC 212, analog front-end 240, and / or peripheral device 230 can be controlled by the core processing subsystem 214 and / or the back-end processing subsystem 216. For example, the core processing subsystem 214 can control the peripheral device 230 via the ADC / DAC 212. A more detailed description of the use of integrated circuit 210 to control components of the integrated electronic system 200 (such as peripheral device 230) will refer to [reference needed]. Figure 3 and Figure 4A Describe it.

[0084] In some examples, peripheral device 230 may include an optical detector, laser module, camera, thermal detector, microelectromechanical system (MEMS), fan, etc. Peripheral device 230 may implement or perform some functions associated with OCT optics 140. For example, the laser module may use a light source to emit light to illuminate a sample, and the optical detector may detect OCT interference signals and convert them into analog signals. The operation associated with peripheral device 230 will be further described below. In some examples, peripheral device 230 may be controlled by integrated circuit 210 to generate position data. The position data may be read and processed by the integrated circuit to determine the accurate position associated with peripheral device 230. Peripheral device 230 may optionally be controlled by integrated circuit 210 to generate data, which may be processed by integrated circuit 210 to measure optical power and / or determine the state associated with peripheral device 230. In some examples, peripheral device 230 may include a scanning imaging subsystem comprising a light source or scanning device (e.g., a scanning laser ophthalmoscope or an optical scanning aberrometer). Integrated circuit 210 can control or process data generated by the scanning image subsystem (e.g., control the light source and / or read the signal of the scanning beam).

[0085] In some examples, I / O circuitry 270 may be any interface circuit capable of receiving and / or transmitting data generated by integrated circuitry 210. I / O circuitry 270 may include multiple general-purpose input / output (GPIO) pins for receiving, transmitting, and / or storing data from integrated circuitry 210. In some examples, I / O circuitry 270 may be implemented within integrated circuitry 210 as part of a system-on-a-chip (SoC). I / O circuitry 270 may optionally include interface circuitry to enable communication with and / or control of integrated circuitry 210. For example, I / O circuitry 270 may include inter-integrated circuitry (I2C), improved inter-integrated circuitry (I3C), serial peripheral interface (SPI), controller area network (CAN bus), universal asynchronous receiver / transmitter (UART), etc.

[0086] In some examples, memory 218 and / or memory 220 can be embodied as any type of volatile or non-volatile memory or data storage device, such as dynamic random access memory (DRAM), static random access memory (SRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), or low latency DRAM (RLDRAM). Memory 218 and / or memory 220 can store various data and program code during the operation of integrated electronic system 200, including operating systems (e.g., real-time operating systems (RTOS)), application programs, libraries, drivers, etc. As described above, memory 218 can be communicatively coupled to core processing subsystem 214, and memory 220 can be communicatively coupled to back-end processing subsystem 216.

[0087] In some examples, BIOS 262 refers to a combination of hardware or instructions used to initialize, control, or operate computing devices before the integrated electronic system 200 executes an operating system (such as a real-time operating system (RTOS)). The instructions included within BIOS 262 can be software, firmware, microcode, or other programs that define or control the functionality or operation of BIOS 262. In one example, BIOS 262 can be implemented using instructions, such as the platform firmware of the integrated electronic system 200, which is processor-executable. BIOS 262 can operate or execute before the execution of the RTOS of the integrated electronic system 200. BIOS 262 can initialize, control, or operate components such as hardware parts of the computing device, and can load or boot the RTOS of the integrated electronic system 200. In some examples, BIOS 262 can provide or establish an interface between the hardware devices or platform firmware of the integrated electronic system 200 and the RTOS of the integrated electronic system 200, through which the RTOS of the integrated electronic system 200 can control or operate the hardware devices or platform firmware of the integrated electronic system 200. In some examples, BIOS 262 may implement the Unified Extensible Firmware Interface (UEFI) specification or other specifications or standards used for initializing, controlling, or operating the integrated electronic system 200. BIOS 262 may be stored in memory, such as ROM 260, flash memory (in... Figure 2 (not shown in the image) or other non-volatile memory.

[0088] In some examples, the image data interface 250 can be embodied as any interface circuit, port, and / or slot supporting communication protocols / interfaces for receiving and / or transmitting image data generated by integrated circuit 210, thereby displaying OCT images to user equipment 160 (e.g., a display, mobile device, etc.). For example, the image data interface 250 may include or support various protocols, interfaces, and / or connections, such as display ports, High Definition Multimedia Interface (HDMI), Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​Standard (PCIe), Serial Advanced Technology Attachment (SATA) (SATA), Thunderbolt ports, Lightning connectors, etc.

[0089] In some examples, GPU 280 may be an integrated circuit device and may be used for applications such as image rendering. In some instances, GPU 280 may be incorporated into a board in which integrated circuit 210 is also deployed. Alternatively, GPU 280 may be deployed on a graphics card or on a subboard connected to a motherboard, while integrated circuit 210 is deployed on that motherboard. In some examples, GPU 280 may work directly with integrated circuit 210 and / or via image data interface 250 to perform tasks such as 3D video rendering. In some examples, Figure 2 Volatile memory (e.g., DDR memory) and / or non-volatile memory (e.g., solid-state drives), not shown, may be dedicated to GPU 280 for rendering. In some embodiments, integrated electronic system 200 (e.g., electronic board) may include GPU 280, and / or be paired with GPU (in... Figure 2 (not shown in the image) to accelerate processing or reasoning.

[0090] In some examples, integrated circuit 210 may be embodied as an integrated circuit device, an application-specific integrated circuit (ASIC), a field-programmable array of logic (FPGA), a combination of ASIC and FPGA, etc. Integrated circuit 210 may include one or more semiconductor chips and may be manufactured using any suitable semiconductor process or technology, such as complementary metal-oxide-semiconductor (CMOS) technology. In some examples, integrated circuit 210 may perform some or all of the functions associated with the plurality of discrete components 120A-120D of OCT electronic device 120.

[0091] Compared to OCT electronics 120, integrated circuit 210 achieves shorter latency and improved signal integrity by eliminating some of the wires, cables, or other connections required between the multiple discrete components 120A-120D. Because integrated circuit 210 uses shorter paths for transmitting and receiving signals, it avoids or at least reduces latency associated with connections between the multiple discrete components 120A-120D. Additionally, integrated circuit 210 reduces potential sources of signal degradation to achieve improved signal integrity, such as impedance mismatch, electromagnetic interference, and crosstalk. Integrated circuit 210 can also employ high-speed interfaces (e.g., the Peripheral Component Interconnect High Speed ​​Standard (PCIe)) to transmit reconstructed OCT images to a host for further processing, analysis, and display. By coordinating with the host and / or utilizing direct display interfaces (e.g., DisplayPort, HDMI, or similar interfaces) to transmit, process, and / or display images, integrated electronics system 200 can achieve reduced latency in image display. Combinations of two paths (e.g., a path associated with the host and a path associated with the direct display interface) can also be used to enable simultaneous real-time display and recording of data on the host. Additionally and / or optionally, integrated circuit 210 and at least some peripheral devices 230 (e.g., optical detectors) can be deployed on a single board, thereby reducing the associated delay of the signal path between the optical detector and integrated circuit 210 due to the shortened transmission path, direct on-chip reconstruction, and direct projection display. Integrated circuit 210 can utilize multiple channels to receive and / or transmit electrical signals. In some examples, integrated circuit 210 can use multiple (e.g., four, six, seven, eight, ten, twelve) channels to digitize analog signals (e.g., OCT interferometric signals received from the optical detector of the peripheral device) in parallel and transmit the digitized signals in parallel for linearization and / or image reconstruction.

[0092] Compared to OCT electronics 120, which may have analog and digital circuits deployed on different entities across multiple discrete components 120A-120D, implementing multiple channels within integrated circuit 210 neither increases system integration complexity nor causes signal quality degradation due to the need for signal transmission through wires between discrete components 120A-120D. Furthermore, due to the reduced noise introduced during communication, the elimination of certain connections and / or data format conversions (e.g., serial-to-parallel conversions) across multiple discrete components 120A-120D can help maintain signal quality. Additionally and / or optionally, by integrating some peripheral devices 230 (e.g., optical detectors) and integrated circuit 210 onto the same board, noise immunity associated with the signal path between the optical detector and integrated circuit 210 can be enhanced. Therefore, superior system performance (e.g., higher resolution, better signal-to-noise ratio (SNR)) can be achieved based on integrated circuit 210.

[0093] As described above, integrated circuit 210 may include ADC / DAC 212, core processing subsystem 214, and back-end processing subsystem 216. ADC / DAC 212 can process electrical signals received from analog front-end 240 and peripheral devices 230 (e.g., optical detectors) to generate digital signals. In some examples, analog front-end 240 may filter and condition the signal output from the optical detector for further signal processing by ADC / DAC 212. ADC / DAC 212 may include multiple channels (e.g., two, four, eight, twelve, etc.) for receiving electrical signals (e.g., OCT interference signals) converted by the optical detector. Each of the multiple channels may include an ADC that digitizes the electrical signal (e.g., a k-clock signal, an OCT interference signal). In some examples, the ADC and optical detector may be deployed on the same board, resulting in better noise immunity and reduced cost. Advantageously, multiple channels can allow ADC / DAC 212 to provide greater signal bandwidth for improved performance (e.g., higher throughput). The ADC / DAC 212 may also include multiple channels for transmitting control signals generated by the core processing subsystem 214 and / or the back-end processing subsystem 216 to control the peripheral device 230. Each of the multiple channels for transmitting control signals may include a digital-to-analog converter (DAC) that converts digital signals into analog signals for controlling the peripheral device 230 and / or the analog front-end 240.

[0094] The core processing subsystem 214 processes electrical signals from the ADC / DAC 212 to generate image data. In some examples, the core processing subsystem 214 (e.g., a signal processing engine) can linearize and / or reconstruct the image data based on a k-clock signal and an OCT interference signal. The core processing subsystem 214 can utilize a neural network (NN) model to linearize the OCT interference signal. The NN model can be trained using a dataset including a k-clock model, the corresponding linearized OCT interference signal, and variations of the k-clock signal to achieve better performance in linearization. Based on the linearized interference signal, the core processing subsystem 214 (e.g., a reconstruction pipeline) can also reconstruct the image data through operations including background noise removal, dispersion compensation, FFT, logarithmic scaling, display scaling, etc. The core processing subsystem 214 (e.g., an acquisition engine) can transmit image data to a back-end processing subsystem 216 for displaying or rendering the OCT image. In some examples, the core processing subsystem 214 and the back-end processing subsystem 216 can include two paths for displaying the OCT image. To reduce latency in certain applications, the core processing subsystem 214 and the back-end processing subsystem 216 can utilize a high-speed path to transmit image data for display. This high-speed path can utilize the PCIe interface for data transmission. For applications with lower latency requirements, the core processing subsystem 214 and the back-end processing subsystem 216 can utilize a normal-speed path (e.g., via the memory controller) to transmit image data for display.

[0095] Additionally, the core processing subsystem 214 can establish a direct, low-latency, and highly synchronized communication channel between the ADC / DAC 212, the analog front-end 240, and / or the peripheral devices 230. For example, the core processing subsystem 214 can generate control signals to achieve high-speed control of the ADC / DAC 212, the analog front-end 240, and / or the peripheral devices 230. Because the core processing subsystem 214 can operate at higher speeds and higher clock frequencies, and / or without firmware intervention (e.g., compared to the back-end processing subsystem 216), control of the ADC / DAC 212, the analog front-end 240, and / or the peripheral devices 230 can be performed in a more real-time manner, responding or adjusting the integrated electronics system 200 in a timely manner, thereby achieving better performance. Additionally and / or optionally, the core processing subsystem 214 can control the ADC / DAC 212, the analog front-end 240, and / or the peripheral devices 230 based on settings or parameters received from the back-end processing subsystem 216. In some instances, the core processing subsystem 214 (e.g., the acquisition engine) can be reconfigured for the ADC / DAC 212 depending on the application. For example, in applications where the integrated circuit 210 does not require linearization of the OCT interference signal, the core processing subsystem 214 can disable certain channels in the ADC / DAC 212. In other applications, the core processing subsystem 214 can enable more channels in the ADC / DAC 212 and / or increase the sampling rate associated with the ADC / DAC 212.

[0096] The back-end processing subsystem 216 can transmit and / or process image data generated by the core processing subsystem 214 for displaying OCT images. Compared to displaying OCT images using a computer workstation, the back-end processing subsystem 216 can directly transmit image data to the display unit (in the image data interface 250) via the image data interface 250. Figure 2 (Not shown in the image). In some examples, by integrating the image data interface 250 and the integrated circuit 210 on the same board, latency can be significantly reduced (e.g., from hundreds of milliseconds to tens of milliseconds). Additionally and / or optionally, depending on the application, the back-end processing subsystem 216 may employ the GPU 280 to render the image data generated by the core processing subsystem 214. For example, when used for applications that may require intensive image processing, such as feature recognition, cancer detection, and tissue separation, the back-end processing subsystem 216 may transfer image data (indirectly via the image data interface 250 or directly to the GPU 280) to the GPU 280 for rendering.

[0097] In some examples, the core processing subsystem 214 and / or the back-end processing subsystem 216 can control the peripheral device 230 to implement certain control and protection functions. For example, the core processing subsystem 214 and / or the back-end processing subsystem 216 can control the camera of the peripheral device 230 to capture optical signals through the MEMS module of the peripheral device 230. As another example, the core processing subsystem 214 and / or the back-end processing subsystem 216 can coordinate with the temperature sensor and fan of the peripheral device 230 to achieve thermal protection (e.g., cooling) for the integrated circuit 210 to prevent it from overheating due to performing intensive computation and synchronization operations. As yet another example, the core processing subsystem 214 and / or the back-end processing subsystem 216 can transmit control signals to the peripheral device 230 to implement various functions, such as calibration of the laser module or camera of the peripheral device 230. As yet another example, the peripheral device 230 may include an interface or circuitry for controlling a motor in the integrated electronic system 200. The core processing subsystem 214 and / or the back-end processing subsystem 216 can transmit control signals to the peripheral device 230 to control the motor in the integrated electronic system 200. By integrating the peripheral device 230 and the integrated circuit 210 on the same board and utilizing high-speed logic (such as the core processing subsystem 214) to generate control signals for controlling the peripheral device, calibrations and / or adjustments associated with the integrated electronic system 200 can be performed in real time to achieve better performance than the OCT electronics 120.

[0098] Additional example implementations and operations of the system

[0099] Figure 3 Exemplary block diagrams of an ADC / DAC 212 and an analog front-end 240 according to various embodiments of the present disclosure are shown. Figure 3 As shown, the ADC / DAC 212 includes analog-to-digital converters (ADCs) 302A to 302N and digital-to-analog converters (DACs) 304A to 304N. The analog front-end 240 includes filtering and signal conditioning modules 308 and 310. A phase-locked loop (PLL) 306 may be included in the ADC / DAC 212 or the analog front-end 240. N can be any positive integer, allowing the ADC / DAC 212 to accommodate any number of ADCs and DACs.

[0100] Each of ADCs 302A through 302N can correspond to a communication channel for parallel digitizing electrical signals (e.g., OCT interference signals, k-clock signals, scan trigger signals) received from analog front-end 240 to increase signal bandwidth. In some examples, each of ADCs 302A through 302N can be a 12-bit, 14-bit, or 16-bit ADC. Alternatively, each of ADCs 302A through 302N can generate digital outputs with different bit depths. Each of ADCs 302A through 302N can be implemented as a successive approximation (SAR) ADC, a Δ-Σ ADC, a dual-slope ADC, a pipelined ADC, a flash ADC, etc.

[0101] The filter and signal conditioning module 308 may include one or more analog anti-aliasing filters that filter the OCT interference signal before the ADCs 302A to 302N digitize it. In some examples, each of the ADCs 302A to 302N may be paired with each of the one or more analog anti-aliasing filters. The cutoff frequency of the analog anti-aliasing filter may be approximately equal to or lower than the bandwidth of the corresponding ADC 302A to 302N. The filter and signal conditioning module 308 may also condition the OCT interference signal so that the ADCs 302A to 302N can digitize the OCT interference signal efficiently or accurately. For example, the filter and signal conditioning module 308 may adjust the amplitude or oscillation of the OCT interference signal to maintain the signal-to-noise ratio (SNR).

[0102] The filtering and signal conditioning module 310 may include one or more analog anti-aliasing filters that filter the analog signals received from DACs 304A to 304N. The filtering and signal conditioning module 310 may also condition the OCT analog signals from DACs 304A to 304N for robust control of the peripheral device 230.

[0103] PLL 306 can generate a low-jitter, high-quality clock source to directly or indirectly clock ADCs 302A to 302N and DACs 304A to 304N, achieving improved jitter and synchronization performance. PLL 306 can be implemented as an analog phase-locked loop (APLL), linear phase-locked loop (LPLL), digital phase-locked loop (DPLL), all-digital phase-locked loop (ADPLL), software phase-locked loop (SPLL), or any combination thereof. In some examples, ADCs 302A to 302N can be clocked by PLL 306, enabling ADCs 302A to 302N to generate digitized samples of the electrical signals received from peripheral device 230 at a data rate of at least one gigasamples per second (GSPS) or five gigasamples per second (GSPS).

[0104] In some examples, the filter and signal conditioning module 308 can filter the electrical signal 350 received from the peripheral device 230 and the analog front end 240 to generate an electrical signal 352 for the ADCs 302A to 302N. Based on a control signal 362 (e.g., a clock signal) provided by the PLL 306, the ADCs 302A to 302N can digitize the electrical signal 352 to generate a digitized signal 354, which can be further processed by the core processing subsystem 214. For example, the electrical signal 350 may include an OCT interference signal detected and converted by an optical detector of the peripheral device 230, and the digitized signal 354 may include the digitized interference signal, which forms a digital representation of the OCT interference signal. As another example, the electrical signal 350 may include a k-clock signal provided by a laser module of the peripheral device 230 (e.g., using a Mach-Zehnder interferometer (MZI)), and the digitized signal 354 may include a digitized k-clock signal forming a digital representation of that k-clock signal.

[0105] In some examples, the core processing subsystem 214 and / or the back-end processing subsystem 216 can reconfigure ADCs 302A to 302N using control signal 356, depending on the application. For example, using control signal 356, the core processing subsystem 214 and / or the back-end processing subsystem 216 can disable a portion of ADCs 302A to 302N while enabling other portions. In some applications where the integrated electronics system 200 does not require linearization of the OCT interference signal, the core processing subsystem 214 and / or the back-end processing subsystem 216 can enable ADC 302A while disabling ADCs 302B to 302N using control signal 356. In some examples, the core processing subsystem 214 and / or the back-end processing subsystem 216 can utilize control signal 370 to control PLL 306, causing PLL 306 to generate control signal 362 to clock ADCs 302A to 302N at different clock frequencies. Therefore, depending on the application, the digitized signal 354 generated by ADCs 302A to 302N can correspond to a lower or higher sampling rate.

[0106] In some examples, ADCs 302A to 302N can be controlled (e.g., using control signal 356) to record the a-line trigger signal or the OCT tunable laser trigger signal. Advantageously, using ADCs 302A to 302N to probe the a-line trigger signal can significantly reduce the jitter associated with the a-line trigger signal, thereby allowing integrated circuit 210 to support certain applications (e.g., applications requiring low jitter). In some examples, at least two of ADCs 302A to 302N can share the same internal clock signal (e.g., be driven by the same clock signal).

[0107] In some examples, DACs 304A to 304N can be driven by a control signal 364 clock generated by PLL 306. DACs 304A to 304N can receive control signal 366 from core processing subsystem 214 and / or back-end processing subsystem 216 and convert control signal 366 into analog signal 368. Analog signal 368 can be further processed by filtering and signal conditioning module 310 for controlling peripheral device 230. For example, control signal 366 can be used to control the camera of peripheral device 230, thereby capturing optical signals through the MEMS module of peripheral device 230. As another example, control signal 366 can be used to activate a fan associated with integrated circuit 210 to achieve thermal protection (e.g., cooling) for integrated circuit 210. As yet another example, control signal 366 can be used to achieve various functions, such as calibration of laser module or camera, or control of a motor by integrated electronics system 200 via the aforementioned peripheral device 230, or direct control of the motor via core processing subsystem 214 or back-end processing subsystem 216.

[0108] Figure 4A An exemplary block diagram of a core processing subsystem 214 according to various embodiments of the present disclosure is shown. For example... Figure 4A As shown, the core processing subsystem 214 may include a neural network model 402, a reconstruction pipeline 404 including the neural network model 402, a linearization circuit 420 and a reconstruction circuit 490, an acquisition engine 406, and an arbitrary waveform generator 408. Additional example implementations of the reconstruction pipeline 404 will be discussed later. Figure 4B The explanation is as follows.

[0109] In some examples, the neural network model 402 may include multiple layers, where each layer may include one or more nodes. The neural network model 402 can be trained using a dataset including a k-clock signal, the original interference signal, and the corresponding linearized OCT interference signal, as well as variations in the k-clock signal, to achieve better reconstruction performance. For example, variations in the amplitude and frequency of the k-clock signal can be used to train the neural network model 402. More specifically, variations in the k-clock signal may include a percentage change in the frequency and / or amplitude of the k-clock signal relative to its nominal value (e.g., 1%, 3%, 5%, 10%, 15%, 20%, etc.). Such variations may originate from differences between various laser technologies, or simply from differences between laser modes or laser scans. The most critical variation on the k-clock signal can be represented as fluctuations in the instantaneous frequency of the signal. A dataset including pairs of original k-clock signals and corresponding linearized interference signals can be prepared for training the neural network model 402. In some examples, the neural network model 402 may include an input layer, hidden layers, and an output layer. The input layer may take the k-clock signal and the original interference signal as input, while the output layer may generate the reconstructed interference signal. In other examples, neural network model 402 can be replaced by other types of machine learning models, artificial intelligence models, support vector machines, Bayesian networks, regression models, etc.

[0110] In some examples, a loss function (e.g., mean squared error) can be used to train a neural network model 402 to quantify the difference between the predicted and the actual linearized and / or reconstructed signal. Optimization techniques (e.g., gradient descent) are used to iteratively adjust the network's internal parameters to improve accuracy.

[0111] In some examples, a training dataset generated based on certain mathematical functions can be used to train the neural network model 402. For instance, to generate a training set, the point spread function (PSF) can be calculated based on the performance associated with the components of the integrated electronic system 200 and variations in these performances (e.g., variations associated with optical bandwidth, optical loss, data acquisition rate, artifacts, operating mode, penetration depth of the imaged material or object, etc.). Based on the point spread function, a dataset with a transformation-restricted PSF can be generated and used as a training dataset to train the neural network model 402.

[0112] Additionally and / or optionally, a separate validation dataset can be used to validate the performance of the neural network model 402 to ensure that the neural network model 402 can generalize to unseen data. This step helps detect overfitting and ensures the robustness of the neural network model 402. Advantageously, by preparing and training the neural network model 402 as described above, the neural network model 402 can generalize well to new or unseen OCT interference signals and can make the integrated circuit 210 less sensitive to hardware changes. The neural network model 402 can also perform linearization processing more efficiently by reducing the requirement for multiple FFT calculations and high-order interpolation, and can capture complex relationships in the data, thereby achieving more accurate linearization.

[0113] It should be noted that in other examples, integrated circuit 210 may use other signal processing techniques or modules (e.g., linearization circuit 420 instead of neural network model 402) to generate the linearized and / or reconstructed interference signal 450. Depending on the user's choice, integrated circuit 210 may use linearization and / or reconstruction circuit 420 or neural network model 402 to generate the linearized and / or reconstructed interference signal 450. For example, linearization circuit 420 may use a k-clock signal for linearization. More specifically, the k-clock signal may be generated by laser electronics or a dedicated k-clock module to indicate the time at which the swept light source sweeps across a predetermined wavenumber increment each time within the scanning range. Linearization circuit 420 may identify features (e.g., zero crossings) in the k-clock data set to provide a reference point for linearization and may use higher-order interpolation and upsampling to achieve linearization. The OCT interference signal may be resampled by linearization circuit 420 based on a uniformly spaced k-space grid to ensure that the data is uniformly distributed in k-space. Linearization circuit 420 may employ various numerical methods to resample the digitized interference signal 354A. This may involve simultaneously capturing the k-clock signal 354B and the digitized interferometric signal 354A, creating a dataset for each signal, and then using an algorithm to resample the interferometric data to achieve a uniform k-space distribution.

[0114] In some examples, the reconstruction circuit 490 may be embodied as performing arithmetic logic (e.g., adders, multipliers, frequency dividers, multiplexers, registers, quantizers, other computational elements, etc.) in a data processing pipeline, performing operations including some or all of the steps in background noise removal, dispersion compensation, FFT, logarithmic scaling, and display scaling. The reconstruction circuit 490 may reconstruct image data based on a linearized interference signal 450 generated by the neural network model 402 or the linearization circuit 420. In some embodiments, the linearization circuit 420 may implement conventional linearization techniques to generate the linearized interference signal 450.

[0115] In some examples, the acquisition engine 406 can be embodied as digital logic that can be used to implement timing control and / or synchronization, real-time feedback, real-time data acquisition, or other real-time control associated with the integrated electronic system 200.

[0116] In some examples, the arbitrary waveform generator 408 may be digital logic that can be used to generate various waveforms to control at least the peripheral device 230. For example, the arbitrary waveform generator 408 may generate half-triangle waves, half-sawtooth waves, square waves, or other types of waveforms for controlling various components of the peripheral device 230.

[0117] During operation, the neural network model 402 can receive digitized interference signals 354A from ADCs 302A to 302N. The digitized interference signal 354A can be a digital representation of the OCT interference signal. The neural network model 402 can also receive a k-clock signal 354B from ADCs 302A to 302N. Based on the digitized interference signal 354A and the k-clock signal 354B, the neural network model 402 can generate a linearized interference signal 450, which can be received by the reconstruction circuit 490. Based on the linearized interference signal 450, the reconstruction circuit 490 can generate or reconstruct image data 460 through operations including background noise removal, dispersion compensation, FFT, logarithmic scaling, and display scaling.

[0118] The acquisition engine 406 can receive image data 460 and transmit the image data 460 to the back-end processing subsystem 216 for displaying the OCT image. For example... Figure 4A As shown, the core processing subsystem 214 can use either the normal speed path 430B or the high-speed path 430A to transmit image data 460 to the back-end processing subsystem 216 and / or the image data interface 250. The high-speed path 430A can use a PCIe interface for data transmission to reduce latency. For applications with low latency requirements, the acquisition engine 406 can use the normal speed path 430B to transmit image data 460 for display.

[0119] In some examples, the acquisition engine 406 can establish a direct and low-latency communication channel between the ADC / DAC 212 and the core processing subsystem 214 and / or between the peripheral device 230 and the core processing subsystem 214. For example, the acquisition engine 406 can generate control signals 470 to enable high-speed control of the ADC / DAC 212, analog front-end 240, and / or peripheral device 230. Because the acquisition engine 406 can operate at higher speeds, higher clock frequencies, and / or without firmware intervention (e.g., compared to the back-end processing subsystem 216), control of the ADC / DAC 212, analog front-end 240, and / or peripheral device 230 can be performed in a more real-time manner to respond to or adjust the integrated electronics system 200 in a timely manner, thereby achieving better performance. Additionally and / or optionally, the acquisition engine 406 can control the ADC / DAC 212, analog front-end 240, and / or peripheral device 230 based on settings or parameters received from the back-end processing subsystem 216.

[0120] In some examples, control signal 470 can be processed by arbitrary waveform generator 408 to generate control signal 366 for controlling peripheral device 230. For example, based on control signal 470, arbitrary waveform generator 408 can generate control signal 366, which corresponds to a half-triangular wave or a half-sawtooth wave, to drive part of peripheral device 230 (e.g., a beam scanner). In some examples, arbitrary waveform generator 408 can be bypassed, so that control signal 470 can be used directly to control peripheral device 230.

[0121] Additionally, depending on the application used by the integrated electronic system 200, the acquisition engine 406 can generate control signals 356 and / or 370 to reconfigure the ADC / DAC 212 and / or analog front-end 240. For example, in applications where the integrated electronic system 200 does not require linearization of the OCT interference signal, the acquisition engine 406 can use control signal 356 to disable some of the ADCs 302A to 302N in the ADC / DAC 212. In other applications, the acquisition engine 406 can enable more channels in the ADC / DAC 212 (e.g., enable all ADCs 302A to 302N) and / or increase the sampling rate of the ADCs 302A to 302N.

[0122] In some examples, such as Figure 4A As shown, the acquisition engine 406 can transmit image data 460, other data, or information to the I / O circuit 270. For example, the GPIO pins of the I / O circuit 270 can allow the acquisition engine 406 to transmit data or information to other parts of the integrated electronic system 200 to achieve real-time data access.

[0123] Figure 4BExemplary embodiments of the reconfiguration pipeline 404 according to various embodiments of the present disclosure are shown. For example... Figure 4B As shown, the reconstruction pipeline 404 (e.g., chirp compensation 406B) can generate a linearized interference signal 450. The linearized interference signal 450 can be generated based on the output of one of the ADCs 302A to 302N (e.g., digitized interference signal 354A and k-clock signal 354B). Here, the digitized interference signal 354 is shown as a 12-bit signal, while the output of the reconstruction pipeline 404 (e.g., image data 460) is 8 bits.

[0124] like Figure 4B As shown, the digitized interference signal 354A can undergo multiple consecutive processing stages, including background removal 402B, apodization 404B, chirp compensation 406B, dispersion compensation 408B, zero padding 410B, Fast Fourier Transform (FFT) 412B, pseudo-random bit sequence (PRBS) 414B, logarithmic scaling 416B, and scaling and downsampling 418B. In the reconstruction pipeline 404, the bit length of the data can be increased and / or decreased based on the desired accuracy, computational complexity, and available hardware resources. In some embodiments, chirp compensation 406B can be embodied in or derived from... Figure 4A The neural network model 402 and / or the linearized circuit 420 are implemented. Figure 4B In the exemplary embodiment of the reconstruction pipeline 404 shown, the bit length of the data is 16 bits during the apodization 404B, chirp compensation 406B, dispersion compensation 408B, zero padding 410B, Fast Fourier Transform (FFT) 412B, Pseudo-random Bit Sequence (PRBS) 414B, and logarithmic scaling 416B processes. During scaling and downsampling 418B, the bit length is truncated to 8 bits.

[0125] Figure 4C An exemplary block diagram of a core processing subsystem 214 according to various embodiments of the present disclosure is shown. For example... Figure 4C As shown, the core processing subsystem 214 may include an inference engine 422 (e.g., an inference device), an acquisition engine 406, and an arbitrary waveform generator 408. Unless otherwise stated, Figure 4C The components can be with Figure 4A The components with corresponding numbers are the same or substantially similar. In some embodiments, the inference engine 422 may be implemented or embodied as an integrated circuit (e.g., an application-specific integrated circuit (ASIC), a processor chip, etc.). The inference engine 422 may perform functions performed by the reconstruction pipeline 404 (e.g., including network model 402, linearization circuit 420, and / or reconstruction circuit 490) to generate image data 460 based on the digitized interference signal 354A and the k-clock signal 354B. Figure 4CAs shown, the inference engine 422 can process the image data transmitted on the high-speed path 430A and / or the normal speed path 430B (e.g., perform further image analysis on the image data 460) before the host or post-processing circuitry performs further processing on the image data 460.

[0126] Figure 5 An exemplary block diagram of a back-end processing subsystem 216 according to various embodiments of the present disclosure is shown. Figure 5 As shown, the back-end processing subsystem 216 includes a memory controller 502, a system processor 504, and a communication interface 506. As described above, the back-end processing subsystem 216 may include a normal speed path 430B and a high-speed path 430A for transmitting image data 460 to the image data interface 250. The normal speed path 430B includes the memory controller 502 and the system processor 504. The high-speed path 430A includes the communication interface 506 and the memory controller 508.

[0127] In some examples, system processor 504 may be embodied as any type of single-core, single-threaded, multi-core, or multi-threaded processor capable of performing the functions described herein. System processor 504 may be embodied as a microprocessor, central processing unit (CPU), digital signal processor (DSP), microcontroller, or other processor or processing / control circuitry. System processor 504 may communicate with image data interface 250, ROM 260, and / or memory 218 or memory 220 to perform various functions for managing integrated electronic system 200, including system boot (using BIOS 262 within ROM 260), system shutdown, file management, memory management, system calibration, system management (e.g., using an RTOS running on memory 218 or memory 220), and other functions. For example, system processor 504 may provide image data 460 to image data interface 250 for displaying OCT images to user equipment 160, and / or pass image data 460 to the host for display.

[0128] In some examples, the memory controller 502 may be embodied as circuitry or a component to enable the acquisition engine 406 and / or system processor 504 to access memory 218 and / or memory 220. The memory controller 502 may also monitor access to memory 218 and / or memory 220 and trigger a system management interrupt (SMI) when a specific access event and / or request is detected.

[0129] In some examples, the communication interface 506 may be embodied as circuitry, logic, or components to enable input / output operations associated with the acquisition engine 406 and / or the image data interface 250. For example, the communication interface 506 may be embodied as or include a platform controller hub, an input / output control hub, firmware devices, communication links such as bus links and printed circuit board traces, and other components that can assist in enabling input / output operations associated with the acquisition engine 406, the image data interface 250, and / or other components of the integrated electronics system 200 (e.g., the GPU 280). In some examples, the communication interface 506 may be embodied as a Peripheral Component Interconnect High-Speed ​​(PCIe) interface, a platform controller hub (PCH), or may implement the Scalable Host Controller Interface (xHCI) specification to at least facilitate communication between the acquisition engine 406 and the image data interface 250.

[0130] During operation, the back-end processing subsystem 216 can receive image data 460 from the core processing subsystem 214. Depending on the application, the back-end processing subsystem 216 can transmit the image data 460 to the image data interface 250 for display via either the normal speed path 430B or the high-speed path 430A. As described above, for applications with high latency requirements, the back-end processing subsystem 216 can transmit the image data 460 to the image data interface 250 via the high-speed path 430A (e.g., using the communication interface 506 and the memory controller 508). For applications with low latency requirements, the back-end processing subsystem 216 can transmit the image data 460 to the image data interface 250 via the normal speed path 430B (e.g., using the memory controller 502 and the system processor 504).

[0131] Figure 6 Example integration methods of at least some portions of an integrated electronic system 200 according to various embodiments of the present disclosure are shown. For example... Figure 6 As shown, the integrated electronic system 200 can be represented as a board (e.g., a PCB board) on which various components are mounted. For example, Figure 6 At least the following components are shown deployed on the board: integrated circuit 210, I / O circuitry 270, components 602 (e.g., slots, connectors, etc.), high-speed path 430A, and image data interface 250. Component 602 facilitates the transmission of OCT interferometric signals from a photodetector (in...). Figure 6(Not shown) Data is transmitted to ADCs 302A to 302N of integrated circuit 210. Image data interface 250 may include an SFP+ module, such as an enhanced version of a Small Pluggable (SFP) transceiver module. This SFP+ module provides a compact, hot-pluggable network interface for data communication and high-speed connectivity. Image data interface 250 may also support the 10GbE (10 Gigabit Ethernet) standard for high-speed data transmission. Image data interface 250 may also include a microSD (Secure Digital) card interface and / or module for data transmission with electronic devices such as smartphones, tablets, digital cameras, and other compact devices. I / O circuitry 270 may support the USB 3.2 standard, offering significant improvements in data transmission speed and functionality compared to previous standards. Integrated electronic system 200 may integrate a PCI Express (PCIe) interface in high-speed path 430A to enable low-latency communication between integrated circuit 210 and other components or expansion cards, thereby improving overall system performance and responsiveness.

[0132] Exemplary waveforms and system performance

[0133] Figure 7 Exemplary waveforms 700A, 700B, and 700C associated with an integrated electronic system 200 (e.g., ADC / DAC 212) according to various embodiments of the present disclosure are shown.

[0134] Waveform 700A shows the time-domain waveform of the digitized interference signal 354A. The digitized interference signal 354A can be generated by ADCs 302A to 302N by capturing and digitizing an electrical signal 350 (e.g., an OCT interference signal) from a peripheral device 230 (e.g., an optical detector). In waveform 700A, the digitized interference signal 354A can be generated by ADCs 302A to 302N at a data rate of one GSPS.

[0135] Waveform 700B shows the frequency domain waveform on a logarithmic scale associated with the digitized interferometric signal 354A. More specifically, waveform 700B can be generated by using or applying the point spread function (PSF) to the digitized interferometric signal 354A.

[0136] Waveform 700C shows a frequency domain waveform on a logarithmic scale associated with the signal generated or processed by the core processing subsystem 214. More specifically, waveform 700C can be generated by using or applying a point spread function (PSF) on the output of reconstruction pipeline 404 (e.g., image data 460). Compared to waveform 700B, waveform 700C exhibits improved spectral characteristics, such as an improved signal-to-noise ratio (SNR). The improved spectral characteristics can be attributed at least in part to the linearization processing performed by neural network model 402 on the digitized interferometric signal 354A, and the various compensation functions performed by reconstruction pipeline 404. Although not easily observed from waveform 700C, the measured SNR can exceed 80 dB, which meets the requirements of all ophthalmic OCT applications.

[0137] Figure 8 Exemplary waveform 800A and reference waveform 800B according to various embodiments of this disclosure are shown. Waveform 800A illustrates laser nonlinearity associated with integrated electronic system 200. Waveform 800B illustrates laser nonlinearity associated with commercial OCT data acquisition card.

[0138] More specifically, waveform 800A, which shows the time-domain waveform of the digitized interference signal 354A, can be generated using the phase information associated with waveform 700A. Waveform 800B can be generated using data captured by a commercial OCT data acquisition card. Waveforms 800A and 800B exhibit a high degree of similarity compared to each other. This demonstrates that the integrated electronic system 200 can achieve competitive performance using fewer discrete components, such as eliminating the need for a discrete OCT data acquisition card.

[0139] Figure 9 Exemplary contour maps 900A and 900B are shown, illustrating the requirements of certain OCT applications on the OCT system 100. More specifically, Figure 9 High sampling rates or clock frequencies are shown on OCT electronics 120 and / or integrated electronic systems 200 to achieve desired scan rates and axial resolution.

[0140] Contour plot 900A shows the clock frequency requirements for achieving the desired scan rate and axial resolution at an imaging depth of 3 mm. Contour plot 900B shows the clock frequency requirements for achieving the desired scan rate and axial resolution at an imaging depth of 7 mm. In contour plots 900A and 900B, the numbers on the contour lines (e.g., 2, 4, 6, 8, or 10) represent the clock frequency values ​​required to achieve the desired scan rate and axial resolution.

[0141] In some examples, the cross mark 910 in the contour plot 900B indicates the minimum performance required for intraoperative scan source (SS) OCT-related applications (such as 4D image capture). Compared to the OCT electronics 120, which uses multiple components 120A-120D to process electrical signals, the integrated electronics system 200, by integrating various components or circuits into the integrated circuit 210, is able to operate with the advantages of higher clock frequencies, higher signal bandwidth, and / or lower latency. Therefore, the integrated electronics system 200 provides a promising solution to overcome the bottleneck problems caused by the limitations of the OCT electronics 120 in certain applications.

[0142] Figure 10 Exemplary waveforms 1000 associated with arbitrary waveform generator 408 according to various embodiments of the present disclosure are shown. More specifically, waveform 1000 shows the waveform of a specific control signal 366 generated by arbitrary waveform generator 408. As described above, waveform 1000 can be used to control some peripheral devices 230.

[0143] in conclusion

[0144] The foregoing disclosure is not intended to limit this disclosure to the precise form or specific field of use disclosed. Therefore, various alternative embodiments and / or modifications may arise based on this disclosure, whether or not such embodiments and modifications are expressly described or implied herein. Consequently, those skilled in the art, upon understanding this disclosure, will recognize that modifications to form and detail may be made without departing from the scope of this disclosure. Therefore, this disclosure is limited only by the claims.

[0145] It should be understood that not all objectives or advantages can necessarily be achieved according to any particular example described herein. Therefore, for example, those skilled in the art will recognize that some examples may operate in a manner that achieves or optimizes one or more advantages taught herein, without necessarily achieving other objectives or advantages that may be taught or suggested herein.

[0146] All the processes described herein can be embodied in software code modules, and fully automated by executing these modules via a computing system containing a computer or processor. The code modules can be stored on any type of non-volatile computer-readable medium or other computer storage device. Some or all of the methods can be embodied in dedicated computer hardware.

[0147] Many other variations will be apparent from this disclosure. For example, depending on the specific example, certain actions, events, or functions of any algorithm described herein may be performed in a different order, or may be added, combined, or omitted entirely (e.g., not all described actions or events are necessary for the implementation of the algorithm). Furthermore, in some examples, actions or events may occur concurrently, for example, through multithreading, interrupt handling, multiple processors or processor cores, or on other parallel architectures, rather than sequentially. Additionally, different tasks or processes may be performed by different machines and / or computing systems that can work together.

[0148] The various illustrative logic blocks and modules described in conjunction with the examples disclosed herein can be implemented or executed by a machine, such as a processing unit or processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be a controller, a microcontroller, or a state machine, a combination thereof, etc. The processor may include circuitry to process computer-executable instructions. In some examples, the processor includes an FPGA or other programmable device that can perform logical operations without processing computer-executable instructions. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, a microprocessor combined with a DSP core, or any other such configuration. Although this document primarily describes digital technologies, the processor may also primarily include analog components. The computing environment may include any type of computer system, including, but not limited to, to name a few, microprocessor-based computer systems, mainframe computers, digital signal processors, portable computing devices, device controllers, or computing engines within devices, etc.

[0149] Elements of the methods, processes, routines, or algorithms described in conjunction with the embodiments disclosed herein can be directly embodied in hardware, software modules executed by a processor device, or a combination of both. Software modules can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of non-volatile computer-readable storage medium. An exemplary storage medium can be coupled to a processor device such that the processor device can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor device. The processor device and storage medium can reside in an ASIC. The ASIC can reside in a user terminal. Alternatively, the processor device and storage medium can reside as discrete components in the user terminal.

[0150] The processes described herein or illustrated in the accompanying drawings may be initiated in response to an event, such as a predetermined or dynamically determined schedule, when initiated on demand by a user or system administrator, or in response to other events. When such a process is initiated, a set of executable program instructions stored on one or more non-volatile computer-readable media (e.g., hard disk drives, flash memory, removable media, etc.) may be loaded into the memory (e.g., RAM) of a server or other computing device. The executable instructions may then be executed by the hardware-based computer processor of the computing device. In some embodiments, such processes, or portions thereof, may be implemented serially or in parallel on multiple computing devices and / or multiple processors.

[0151] Conditional language, such as “can,” “able,” “may,” or “may,” unless otherwise expressly stated or understood in the specific context of use, is generally intended to convey that certain implementations include certain features, elements, and / or steps, while other implementations do not. Unless otherwise expressly stated or understood in the specific context of use, such conditional language is generally not intended to imply that one or more implementations must arbitrarily require the presence of these features, elements, and / or steps, nor is it intended to imply that one or more implementations must include logic for determining (with or without user input or prompts) whether these features, elements, and / or steps are included or will be performed in any particular implementation.

[0152] When the terms “substantially” and “real-time” are used together, they form phrases that are easily understood by a person skilled in the art. For example, it is easy to understand that such language would include speeds with virtually no perceptible delay or waiting, or speeds with delays short enough that they do not cause user disruption, annoyance, or other inconvenience.

[0153] For example, conjunctions such as "at least one of X, Y, and Z" or "at least one of X, Y, or Z" should be understood, in the context of their use, generally to convey that an item, term, etc., can be any one of X, Y, or Z, or any combination thereof. For instance, the term "or" is used in its inclusive (rather than exclusive) sense; therefore, when used, for example, to connect a list of elements, the term "or" means one, some, or all of the elements in the list. Thus, such connective language generally does not imply that some implementation requires that each of them must have at least one X, at least one Y, and at least one Z.

[0154] The term “a” as used herein should be understood as inclusive rather than exclusive. For example, unless otherwise specified, the term “a” should not be understood as meaning “exactly one” or “only one”; rather, the indefinite article means “one or more” or “at least one”, regardless of whether the term is used in the claims or elsewhere in the specification, and regardless of whether quantifiers such as “at least one,” “one or more,” or “multiple” are used elsewhere in the claims or specification.

[0155] The term "comprising" as used herein should be understood as inclusive rather than exclusive. For example, the inclusion of one or more processors in a general-purpose computer should not be construed as excluding other computer components, and may include components such as memory, input / output devices, and / or network interfaces.

[0156] The detailed description above has elucidated, illustrated, and pointed out the novel features applicable to various embodiments. However, it should be understood that various omissions, substitutions, and modifications can be made to the form and details of the described apparatus or process without departing from the spirit of this disclosure. It should be understood that some embodiments of the invention described herein may be embodied in a form that does not necessarily possess all the features and advantages set forth herein, as some features may be used or practiced independently of others. The scope of certain inventions disclosed herein is defined by the appended claims rather than the foregoing description. All modifications consistent with the meaning and scope of the claims should be included within their protection scope.

Claims

1. An integrated electronic system for optical coherence tomography (OCT), said integrated electronic system comprising: An integrated circuit (IC) configured to generate image data for display based on OCT signals, the IC comprising: An analog circuit is configured to receive and digitize the OCT signal to generate a digitized signal; The core processing subsystem is configured to generate the image data based on the digitized signal; and A backend processing subsystem is configured to receive and process the image data for display to the user.

2. The integrated electronic system according to claim 1, wherein, The core processing subsystem includes a model or linearization circuit configured to linearize the digitized signal to generate a linearized interference signal.

3. The integrated electronic system according to claim 2, wherein, The model is a neural network model or machine learning model, which is trained using a dataset that includes a k-clock signal, a linearized OCT interference signal, and variations of the k-clock signal.

4. The integrated electronic system according to claim 2, wherein, The core processing subsystem includes a reconstruction pipeline configured to reconstruct the linearized interference signal using reconstruction circuitry or a neural network (NN) to generate the image data.

5. The integrated electronic system according to claim 1, wherein, The backend processing subsystem includes a first path and a second path, which are configured to receive the image data and display the image data to the user, wherein the latency of the first path is lower than that of the second path.

6. The integrated electronic system according to claim 1, wherein: The analog circuitry includes multiple analog-to-digital converters (ADCs) configured to digitize the OCT signal to generate a digitized signal; and The core processing subsystem is configured to generate control signals to reconfigure the plurality of ADCs based on the application associated with the integrated electronic system.

7. The integrated electronic system of claim 6 further includes a printed circuit board (PCB), wherein, The IC and multiple peripheral components are deployed on the PCB.

8. The integrated electronic system according to claim 7, wherein, The core processing subsystem is configured to generate multiple control signals to control the multiple peripheral components.

9. The integrated electronic system of claim 8, wherein the analog circuitry includes a plurality of digital-to-analog converters (DACs) configured to convert the plurality of control signals into a plurality of analog signals to control the plurality of peripheral components.

10. The integrated electronic system according to claim 8, wherein, At least two of the plurality of control signals are generated based on a single clock signal generated by the IC.

11. The integrated electronic system according to claim 7, wherein, The plurality of peripheral components include at least one optical sensor, at least one light source, a camera, at least one position sensor, at least one motor, or a beam scanning assembly.

12. The integrated electronic system according to claim 6, wherein, At least one of the plurality of ADCs is used to sample or record the a-line trigger signal.

13. The integrated electronic system of claim 1, further comprising a graphics processing unit (GPU), wherein, The back-end processing subsystem enables the image data to be transmitted to the GPU for processing and / or display to the user.

14. The integrated electronic system according to claim 13, wherein, The GPU is used as an inference device that is placed inside or outside the IC.

15. A printed circuit assembly, comprising: An optical detector, configured as follows: Receive one or more optical signals; as well as An optical coherence tomography (OCT) interference signal is generated based on at least one or more of the optical signals; Integrated circuit (IC) configured to generate image data based on the OCT interference signal; as well as The image data interface is configured as follows: Receive the image data from the IC; and The image data is transmitted to an external device for display to the user.

16. The printed circuit assembly of claim 15, wherein, The image data interface is a Thunderbolt port, DisplayPort connector, OCuLink connector, Universal Serial Bus (USB) port, High Definition Multimedia Interface (HDMI) port, Ethernet connector, or Peripheral Component Interconnect High Speed ​​(PCIe) connector.

17. The printed circuit assembly of claim 15, wherein, The IC includes: An analog circuit is configured to receive and digitize the OCT interference signal to generate a digitized interference signal; A core processing subsystem configured to generate the image data based on the digitized interferometric signal; and The backend processing subsystem is configured as follows: Receive the image data from the core processing subsystem; and The image data is transmitted to the image data interface.

18. The printed circuit assembly of claim 17, further comprising a plurality of peripheral components, wherein, The core processing subsystem is configured to control the plurality of peripheral components.

19. The printed circuit assembly of claim 15, wherein, The external device is a laptop, computer workstation, dedicated graphics card, or mobile device.

20. The printed circuit assembly of claim 15, wherein, The one or more optical signals include an interferometric OCT signal or an interferometric k-clock signal.

21. An integrated circuit (IC), comprising: Analog circuitry configured to receive and digitize optical coherence tomography (OCT) interference signals to generate digitized interference signals; The core processing subsystem is configured to generate image data based on the digitized interference signal; as well as A backend processing subsystem is configured to receive and display the image data to the user.

22. The integrated circuit according to claim 21, wherein, The core processing subsystem includes a model configured to process the digitized interference signal to generate the processed interference signal, wherein the model is a neural network model or a machine learning model.

23. The integrated circuit according to claim 21, wherein, The backend processing subsystem includes a first path and a second path, which are configured to receive the image data and transmit the image data to an image data interface, wherein the latency of the first path is lower than that of the second path.

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