An instruction transmitting method and device based on asymmetric function unit and dynamic detection

Abstract

This invention provides an instruction issuing method and apparatus based on asymmetric functional units and dynamic detection, relating to the field of processor technology. Specifically, the issuing unit obtains information such as the instruction type and source register number from the decoding unit, detects the data dependency between the issuing unit's instruction and all instructions in the pipeline, and generates a control signal to fetch source operands from a bypass based on the above information. Regardless of whether the source operands are ready, the issuing unit issues the instruction. If the source operands are not ready at the time of issuance, the dependency is dynamically detected at each stage of the subsequent pipeline based on the current instruction state, and the bypass control signal is updated in real time to ensure the correctness of the operands during instruction execution. Based on the asymmetric distribution of functional units in the pipeline, the issuing unit can schedule dependent instructions of the same type to be executed in different functional units within the same issuance cycle without causing pipeline stalls. The issuing method of this application decouples data dependency and instruction issuance to the greatest extent possible, allowing instructions to be issued in advance even if the dependency is not resolved, and decoupling the dependency in the pipeline, significantly improving instruction issuance efficiency and facilitating the optimization of the issuing unit's timing.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to an instruction issuing method and apparatus based on asymmetric functional units and dynamic detection. Background Technology

[0002] "Deployment" refers to the crucial step where an instruction moves from the waiting queue to a functional unit (such as the ALU or Load / Store unit) to begin execution. The core tenet of traditional sequential deployment is that deployment must maintain the original program order. This tenet introduces a fundamental constraint: deployment not only involves scheduling execution but also assumes full responsibility for ensuring data integrity.

[0003] Current technical solutions employ various approaches, such as deep optimization of sequential addressing and lightweight simplification of out-of-order addressing. For example, patent application number 201911147499.8 discloses an instruction issue processing circuit for a RISC processor. Internally, the circuit mainly includes an instruction fetch module, a pre-decode module, a decode module, and a scoreboard module. External interfaces include an instruction cache (Icache), a register file (RF), and an execution unit. Specifically, the instruction fetch module is connected to the pre-decode module, the decode module, and the Icache; the pre-decode module is connected to the instruction fetch module, the decode module, and the scoreboard module; the decode module is connected to the pre-decode module, the instruction fetch module, and the execution unit; and the scoreboard module is connected to the pre-decode module and the execution unit. This instruction issue processing circuit for a RISC processor effectively meets and improves the timing performance requirements for instruction issuance in RISC processors and facilitates their physical design and implementation.

[0004] For example, patent document with patent application number 202010827436.3 discloses a method, apparatus, electronic device, and storage medium for issuing commands, relating to the fields of processors (digital chips), data processing, and voice processing. The specific implementation is as follows: a decoding unit acquires the transmission status of two transmission channels within a transmission cycle; the decoding unit generates transmission control signals for the two transmission channels based on the combination of their transmission statuses; the decoding unit controls the two transmission channels to issue commands to the execution unit according to the transmission control signals. The transmission method of this application can determine the transmission control signals for the two transmission channels based on the combination of their transmission statuses, and can control the two transmission channels to issue commands according to the transmission control signals. It can achieve out-of-order transmission. Compared to some out-of-order transmission architectures that use reserved stations in hardware, this method has advantages such as simple hardware structure, small processor footprint and power consumption, and low development cost.

[0005] The existing technologies described above still have some shortcomings, specifically: 1. In sequential processors, traditional issue methods detect data dependencies in the issue unit and obtain source operands through a bypass network. Issue can only proceed after data dependencies are resolved, resulting in low issue efficiency; 2. If RAW data dependencies exist between instructions within the same issue cycle, it means that the subsequent instruction depends on the execution result of the previous instruction. Traditional issue methods cannot issue the subsequent instruction, leading to low issue efficiency; 3. Traditional issue methods detect dependencies in the issue unit and control instruction issuance based on the dependency results, causing the issue unit to be on the processor's critical path, limiting processor frequency increases. Furthermore, the timing of the issue unit deteriorates as pipeline depth increases. Summary of the Invention

[0006] Therefore, it is necessary to provide an instruction issuing method and apparatus based on asymmetric functional units and dynamic detection to address the existing technical problems and improve the processor's issuing efficiency.

[0007] To address the problems in the existing technology, the present invention adopts the following technical solution:

[0008] A command issuance method based on asymmetric functional units and dynamic detection includes:

[0009] During the launch cycle, the launch unit acquires information about the command to be launched and all commands in the pipeline, and detects the data correlation between the command to be launched and the commands in the pipeline;

[0010] For a command to be transmitted that has data correlation, the transmitting unit generates control information containing bypass control information and execution stage information based on the type of the command to be transmitted and the execution status of the commands it depends on.

[0011] The transmitting unit transmits the instruction to be transmitted along with the control information into the pipeline, regardless of whether the source operand of the instruction to be transmitted is ready.

[0012] At each stage of the pipeline, the instruction to be issued dynamically updates the control information based on the state of the instruction that the current stage depends on, and is issued to the functional unit for execution when the execution conditions are met.

[0013] Furthermore, the correlation of the detection data includes:

[0014] Compare the source register of the instruction to be issued with the destination registers of all instructions in the pipeline to identify the producer instruction that the instruction to be issued depends on;

[0015] Obtain the instruction type and execution cycle information of the producer instruction.

[0016] Furthermore, the generation control information includes:

[0017] If the producer instruction has been executed at the time of launch, control information for directly obtaining source operands from the bypass is generated, and the lifecycle of the control information terminates at the end of the launch cycle.

[0018] If the producer instruction is not completed at launch, control information containing the expected bypass path and suggested execution stage is generated, and the instruction to be launched carries the control information into the pipeline.

[0019] Furthermore, the dynamic updating of control information at each execution stage of the pipeline includes:

[0020] The execution status of the producer instruction is detected during the current execution phase;

[0021] If the producer instruction has been executed in the current stage, the source operand is obtained from the bypass according to the original control information, and it is determined whether there is a usable functional unit in the current stage.

[0022] If a functional unit is available, the command to be transmitted is sent to that functional unit for execution;

[0023] If no functional unit is available, the command to be launched will be paused and waited in the current stage until a functional unit becomes available in a subsequent stage.

[0024] Furthermore, the method also includes:

[0025] If the producer instruction is not executed in the current stage, it is determined whether there is an opportunity to execute the instruction to be launched in the subsequent pipeline stage.

[0026] If there is an execution opportunity in a subsequent stage, the control information is dynamically modified according to the status of the producer instruction in the current stage, and the detection and judgment process is repeated in the next pipeline stage.

[0027] If there is no opportunity to execute in subsequent stages and the producer instruction has not yet been completed, the instruction to be issued is paused in the current pipeline stage, and the status of the producer instruction is continuously monitored until the source operand is ready for execution.

[0028] Furthermore, the dynamically modified control information includes:

[0029] Because of cavitation in the pipeline and the independent pauses at each stage, when the command to be issued and the producer command it depends on are not moving synchronously in the pipeline, the bypass path and the effective range of the control information are modified according to their actual relative position.

[0030] Furthermore, a command transmitting device includes:

[0031] The launch unit is used to acquire information about the instruction to be launched and all instructions in the pipeline during the launch cycle, and to detect the data correlation between the instruction to be launched and the instructions in the pipeline; for the instruction to be launched that has data correlation, it generates control information including bypass control information and execution stage information according to the type of the instruction to be launched and the execution status of the instructions it depends on; and launches the instruction to be launched together with the control information into the pipeline, regardless of whether the source operand of the instruction to be launched is ready;

[0032] The pipeline execution unit comprises multiple pipeline stages, each of which includes:

[0033] The status detection module is used to detect the execution status of the instructions that the current stage depends on;

[0034] A control information update module is used to dynamically update the control information based on the detected status.

[0035] The execution condition judgment module is used to determine whether the execution conditions are met in the current stage;

[0036] The functional unit interface is used to send the instruction to be issued to the functional unit for execution when the execution conditions are met.

[0037] Furthermore, the transmitting unit includes:

[0038] The correlation detection module is used to compare the source register of the instruction to be issued with the destination register of all instructions in the pipeline to identify the producer instruction that the instruction to be issued depends on.

[0039] A control information generation module is used to generate control information based on the execution status of the producer instructions, including:

[0040] When the producer command has been executed at launch, direct bypass control information is generated;

[0041] If the producer instruction is not completed at launch, control information containing the expected bypass path and suggested execution phase is generated.

[0042] Therefore, the control information update module includes:

[0043] The status monitoring submodule is used to listen to the result bus and obtain the completion signal of the producer instruction;

[0044] The bypass path calculation submodule is used to recalculate the optimal bypass path based on the current position of the producer instruction and the current position of the instruction to be emitted.

[0045] The control information storage submodule is used to store the original and updated control information.

[0046] Therefore, the execution condition judgment module includes:

[0047] The data readiness determination submodule is used to determine whether all source operands of the command to be transmitted are ready.

[0048] The resource availability judgment submodule is used to determine whether the functional unit corresponding to the current pipeline stage is idle;

[0049] The opportunity assessment submodule is used to assess whether there is an opportunity to execute in subsequent pipeline stages when the current stage cannot be executed.

[0050] The pause control submodule is used to control a partial pause of the current pipeline stage when there is no subsequent execution opportunity and the data is not ready.

[0051] Furthermore, a processor includes the aforementioned instruction issuing device.

[0052] Furthermore, an electronic device includes:

[0053] At least one of the aforementioned processors;

[0054] And a memory for storing instructions executable by the processor.

[0055] Furthermore, a chip integrates the aforementioned command issuing device.

[0056] Furthermore, a computer-readable storage medium storing a computer program that, when executed by a processor, implements the instruction issuance method described above.

[0057] The beneficial effects of this invention are as follows:

[0058] 1. Since the instruction issue condition does not depend on the instruction to remove data dependencies, instructions can be issued even if the source operand is not ready, thus improving the processor's issue efficiency.

[0059] 2. Since the instruction issuance conditions do not depend on the instruction to de-data dependency, it is beneficial to the timing convergence of the issuing unit, which in turn helps the processor to increase its frequency.

[0060] 3. By using functional units with an asymmetric structure, the processor's issue efficiency is improved in scenarios where instructions in the same issue cycle have data dependencies. Attached Figure Description

[0061] Figure 1 This is a flowchart of the first phase of launch.

[0062] Figure 2 This is a flowchart of the second phase of the launch process;

[0063] Figure 3This is a schematic diagram of an asymmetrically distributed functional unit. Detailed Implementation

[0064] To further understand the features, technical means, and specific objectives and functions achieved by the present invention, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0065] like Figure 1 Figure 2 As shown, the instruction issuance method based on the correlation (or dependence) of asymmetric functional units and dynamic detection data described in this application can be divided into two stages:

[0066] In the first stage, the command is relevance detected in the launch unit, control information is generated, and the command is launched into the pipeline;

[0067] In the second stage, the instructions dynamically modify the control information in the pipeline based on the original control information of the sending unit and the current status of the dependent instructions, and are sent to the specific functional unit for execution according to the conditions.

[0068] The issuing unit acquires information about the instruction to be issued and all instructions in the pipeline, including instruction type, source register, destination register, and execution cycle. It detects RAW data correlation by comparing the source register of the instruction to be issued with the destination register of the instructions in the pipeline.

[0069] For a RAW-dependent instruction to be issued (hereinafter referred to as the consumer), control information for obtaining source operands from the bypass and pipeline stage information for sending the instruction to the functional unit for execution are generated based on the type of the instruction to be issued and the execution cycle of the instruction it depends on (hereinafter referred to as the producer). If the producer has already completed execution when the instruction is to be issued, the consumer will select its execution result as the source operand, and the lifecycle of the above control information will end. If the producer has not yet completed execution, the consumer's source operand is not ready, but it will be issued carrying the above control information.

[0070] In the issuance method described in this application, instructions are issued to the pipeline regardless of whether the source operand is ready at the time of issuance. Consumers whose source operands are not ready, upon entering the pipeline, dynamically detect the producer's status during the current execution phase and update the control information for obtaining the source operand from the bypass, as follows:

[0071] If the producer completes execution in the current execution phase, the consumer uses the raw control information generated by the emitter unit to obtain the source operand from the bypass, and then determines whether there is a corresponding functional unit in the current execution phase that can execute the consumer. If there is, the consumer is sent to the functional unit for execution; otherwise, the consumer will continue to paddle in the pipeline until an available functional unit is found, and then the consumer is sent to the functional unit for execution.

[0072] If the producer has not finished executing, it is determined whether the consumer's functional unit can still be executed in the subsequent pipeline stage. If there is still an execution opportunity in the subsequent pipeline stage (there is a functional unit available later), the current stage makes a dynamic judgment based on the producer's status. Since there are cavitation bubbles in the pipeline and the pipeline pauses in each stage are independent, the consumer and producer may not be synchronously stepping forward in the pipeline. When there is no synchronous stepping, the initial control information generated by the launch unit will be modified, and then the consumer will enter the next pipeline stage and repeat the above dynamic judgment process.

[0073] If the consumer has no more execution opportunities after the current pipeline stage, and the producer has not yet finished executing, the consumer will pause the current pipeline stage and dynamically modify the control information as the producer's state changes, until the source operands are ready.

[0074] In traditional processor designs, functional units are typically distributed symmetrically, meaning the same type and number of functional units are configured in each pipeline stage. The processor of this invention employs an asymmetrical distribution structure, where different types and numbers of functional units are configured in different pipeline stages.

[0075] like Figure 3 As shown, taking the ALU as an example, in this embodiment, two ALUs are configured in the EX1 stage of the pipeline, one ALU is configured in the EX2 stage, one ALU is configured in the EX3 stage, and no ALU is configured in the EX4 stage. This asymmetric distribution has the following advantages:

[0076] 1. Resource optimization configuration: Based on the execution characteristics of instructions, configure more frequently used functional units in the early stages to reduce instruction waiting time;

[0077] 2. Provides more opportunities for dynamic scheduling: When the consumer cannot execute in an early stage because the producer has not completed, there are still functional units available in subsequent stages, avoiding premature pipeline stalls;

[0078] 3. Supports the issuance of related instructions within the same issuance cycle: Two related instructions within the same issuance cycle can be scheduled to be executed by the same type of functional unit at different stages without waiting.

[0079] The asymmetric distribution of different functional units can be optimized according to the processor's target application scenario. For example:

[0080] • For compute-intensive applications, ALUs and multipliers can be configured at multiple stages;

[0081] • For memory-intensive applications, LSUs can be configured in multiple stages;

[0082] • For control-intensive applications, branch processing units can be configured at an early stage.

[0083] In this embodiment, the control information carried by each instruction includes the following fields:

[0084] Word Bit Width Description producer_tag log2(ROB depth) Tag of the producer instruction to identify the instruction it depends on original_bypass_path 3 bits Original bypass path encoding generated by the issue unit current_bypass_path 3 bits Currently active bypass path encoding, which can be dynamically modified latest_exec_stage 4 bits Number of the latest execution stage in which the instruction can be executed remaining_opportunities 3 bits Remaining execution opportunity count modified_flag 1 bit Flag whether it has been modified

[0085] The hardware implementation for dynamically modifying control information is shown in the table. At each pipeline stage, after an instruction enters, the status detection module first listens to the result bus to obtain the producer's completion signal. If the producer has completed, the bypass path calculation submodule recalculates the optimal bypass path based on the producer's current position and the current position of this instruction, and updates the current_bypass_path field.

[0086] If the producer has not completed, the opportunity assessment submodule checks the remaining_opportunities field. If the remaining opportunities > 0, the field is decremented and the instruction is passed to the next pipeline stage; if the remaining opportunities = 0, the pause control submodule is triggered, pausing locally in the current stage until the producer completes.

[0087] To ensure the correctness of the modified control information, each pipeline stage updates the modified_flag along with the control information and verifies the validity of the control information before using it in subsequent stages. If the control information is found to be outdated (e.g., the producer label does not match), the latest information is retrieved from the result bus.

[0088] Specifically, the processor using the above-described instruction issuance method employs an asymmetric functional unit structure to further improve the instruction issuance efficiency of the method. The asymmetric functional units serve the following purposes:

[0089] 1. Commands within the same launch cycle that have data correlation can be launched together, improving launch efficiency;

[0090] 2. Provide execution opportunities for instructions at each stage of the pipeline. When the producer is an instruction that takes multiple cycles to produce a result, the execution of the consumer can be postponed as much as possible. When using a dynamic decision-making issue method, the pipeline will not be stopped prematurely, thereby improving processor performance.

[0091] Example 1: Command Issuance in a Simple Scenario

[0092] In this embodiment, the sequence of instructions to be executed is as follows:

[0093] load x7, (8)x2

[0094] Add x3, x7, x8

[0095] In cycle 1, the add instruction checks for dependencies during the issue phase and finds a RAW data dependency with the memory access instruction load. Since the memory access instruction requires at least 3 clock cycles to return its result after issue, the source operand for the add instruction cannot be obtained at this time. The issue unit determines that the add instruction will obtain its source operand in the next phase and will issue the add instruction carrying this control information.

[0096] In cycle 2, the load instruction has not yet returned a result. At this point, it is determined that the add instruction still has a chance to be executed in a later stage. The control information is modified to determine whether the add instruction will obtain the source operand in the next stage.

[0097] In cycle 3, the load instruction completes its execution and returns the result, while the add instruction obtains the source operand through a bypass and is emitted to the ALU for execution.

[0098] The above process is shown in the table below:

[0099] Issue Exec 0 Exec 1 Exec 2 cycle 1 add load cycle 2 add load cycle 3 add load

[0100] Example 2: Command Issuance in Complex Scenarios

[0101] In this embodiment, the sequence of instructions to be executed is as follows:

[0102] load x7, (8)x2

[0103] mul x10, x15 x16

[0104] store x9, (0)x20

[0105] Add x3, x7, x8

[0106] Assuming the above instruction sequence is executed in a dual-processor system, the process is as shown in the table below:

[0107] Issue Exec 0 Exec 1 Exec 2 cycle 1 store add load mul cycle 2 store add load mul cycle 3 store add empty load mul cycle 4 store add load mul … store add load mul cycle N store add

[0108] In cycle 1, consistent with Example 1, the add instruction checks for correlations and finds a RAW correlation with the memory access instruction. It then carries control information for fetching operands from the bypass and sends a store instruction in tandem.

[0109] In cycle 2, the store and add instructions enter the pipeline, while the load and mul instructions also move backward synchronously in the pipeline.

[0110] In cycle 3, due to insufficient LSU resources for executing memory access instructions, the store instruction cannot be issued to the LSU. Therefore, the add instruction and the store instruction are paused together, while the load instruction and the mul instruction continue to be executed in the pipeline. At this time, it is necessary to modify the control information of the add instruction to obtain operands from the bypass.

[0111] In cycle 4, the LSU releases resources, the store is successfully launched, and the add instruction continues to press forward. At this time, the load instruction does not return the execution result due to a miss when accessing the cache. The load instruction is paused in the pipeline, while the add instruction continues to modify the control information of the operand obtained from the bypass, and then carries the control information into the next stage of the pipeline.

[0112] After multiple cycles, the load instruction returns a result, the add instruction successfully retrieves the source operand, and then is emitted to the ALU for execution.

[0113] As the examples above illustrate, various situations can cause pauses in the pipeline, leading to a lack of synchronization between the consumer and producer. If the control information for obtaining operands from the bypass is not dynamically modified in cycle 2 and cycle 3, the add instruction will retrieve incorrect source operands, resulting in execution errors. The dynamic modification mechanism of this invention ensures the correctness of instruction execution under various complex scenarios.

[0114] The core logic of this invention:

[0115] A hybrid strategy of "predictive launch + dynamic conditional execution"

[0116] Key technical features

[0117] 1. Two-phase architecture:

[0118] Phase 1 (Launching Unit): Detect correlations and generate a "Conditional Execution Plan".

[0119] Phase Two (Pipeline): Dynamically modify the plan based on real-time status and execute according to conditions.

[0120] 2. Instructions are always issued: even if operands are not ready, the "scheme" is carried into the pipeline.

[0121] 3. Distributed dynamic decision-making: Each stage of the pipeline can monitor the producer status, determine resource availability, and modify control information.

[0122] 4. Multi-level condition processing:

[0123] Data ready + resources available → Execute immediately

[0124] Data ready + resources busy → waiting for processing

[0125] Data not ready + further opportunities available → Proceed and modify dynamically

[0126] Data not ready + no further opportunities → Partial pause

[0127] Innovation points:

[0128] Decoupling launch and execution: removing "waiting" from the launch phase and postponing it to the execution phase.

[0129] Intelligent production lines: Each production stage has scheduling capabilities.

[0130] Opportunistic execution: Instructions "wander" through the assembly line, seeking opportunities to be carried out.

[0131] Essential positioning:

[0132] By distributing the scheduling logic from the centralized launch unit to every stage of the pipeline, more fine-grained dynamic scheduling can be achieved.

[0133] Furthermore, this application also provides a command issuing apparatus that applies the above-described command issuing method, comprising:

[0134] The launch unit is used to acquire information about the instruction to be launched and all instructions in the pipeline during the launch cycle, and to detect the data correlation between the instruction to be launched and the instructions in the pipeline; for the instruction to be launched that has data correlation, it generates control information including bypass control information and execution stage information according to the type of the instruction to be launched and the execution status of the instructions it depends on; and launches the instruction to be launched together with the control information into the pipeline, regardless of whether the source operand of the instruction to be launched is ready;

[0135] The pipeline execution unit comprises multiple pipeline stages, each of which includes:

[0136] The status detection module is used to detect the execution status of the instructions that the current stage depends on;

[0137] A control information update module is used to dynamically update the control information based on the detected status.

[0138] The execution condition judgment module is used to determine whether the execution conditions are met in the current stage;

[0139] The functional unit interface is used to send the instruction to be issued to the functional unit for execution when the execution conditions are met.

[0140] Preferably, the transmitting unit includes:

[0141] The correlation detection module is used to compare the source register of the instruction to be issued with the destination register of all instructions in the pipeline to identify the producer instruction that the instruction to be issued depends on.

[0142] A control information generation module is used to generate control information based on the execution status of the producer instructions, including:

[0143] When the producer command has been executed at launch, direct bypass control information is generated;

[0144] If the producer instruction is not completed at launch, control information containing the expected bypass path and suggested execution phase is generated.

[0145] Preferably, the control information update module includes:

[0146] The status monitoring submodule is used to listen to the result bus and obtain the completion signal of the producer instruction;

[0147] The bypass path calculation submodule is used to recalculate the optimal bypass path based on the current position of the producer instruction and the current position of the instruction to be emitted.

[0148] The control information storage submodule is used to store the original and updated control information.

[0149] Preferably, the execution condition judgment module includes:

[0150] The data readiness determination submodule is used to determine whether all source operands of the command to be transmitted are ready.

[0151] The resource availability judgment submodule is used to determine whether the functional unit corresponding to the current pipeline stage is idle;

[0152] The opportunity assessment submodule is used to assess whether there is an opportunity to execute in subsequent pipeline stages when the current stage cannot be executed.

[0153] The pause control submodule is used to control a partial pause of the current pipeline stage when there is no subsequent execution opportunity and the data is not ready.

[0154] This application also provides a processor, including the aforementioned instruction issuing device.

[0155] This application also provides an electronic device, including:

[0156] At least one of the aforementioned processors;

[0157] And a memory for storing instructions executable by the processor.

[0158] This application also provides a chip that integrates the aforementioned command issuing device.

[0159] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the instruction issuance method described above.

[0160] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. An instruction launch method based on asymmetric functional units and dynamic detection, characterized by, include: During the launch cycle, the launch unit acquires information about the command to be launched and all commands in the pipeline, and detects the data correlation between the command to be launched and the commands in the pipeline; For a command to be transmitted that has data correlation, the transmitting unit generates control information containing bypass control information and execution stage information based on the type of the command to be transmitted and the execution status of the commands it depends on. The transmitting unit transmits the instruction to be transmitted along with the control information into the pipeline, regardless of whether the source operand of the instruction to be transmitted is ready. At each stage of the pipeline, the instruction to be issued dynamically updates the control information based on the state of the instruction that the current stage depends on, and is issued to the functional unit for execution when the execution conditions are met.

2. The method of claim 1, wherein, The correlation of the detection data includes: Compare the source register of the instruction to be issued with the destination registers of all instructions in the pipeline to identify the producer instruction that the instruction to be issued depends on; Obtain the instruction type and execution cycle information of the producer instruction.

3. The method of claim 1, wherein, The generated control information includes: If the producer instruction has been executed at the time of launch, control information for directly obtaining source operands from the bypass is generated, and the lifecycle of the control information terminates at the end of the launch cycle. If the producer instruction is not completed at launch, control information containing the expected bypass path and suggested execution stage is generated, and the instruction to be launched carries the control information into the pipeline.

4. The method of claim 1, wherein, The dynamic updating of control information at each execution stage of the pipeline includes: The execution status of the producer instruction is detected during the current execution phase; If the producer instruction has been executed in the current stage, the source operand is obtained from the bypass according to the original control information, and it is determined whether there is a usable functional unit in the current stage. If a functional unit is available, the command to be transmitted is sent to that functional unit for execution; If no functional unit is available, the command to be launched will be paused and waited in the current stage until a functional unit becomes available in a subsequent stage.

5. The method of claim 4, wherein, Also includes: If the producer instruction is not executed in the current stage, it is determined whether there is an opportunity to execute the instruction to be launched in the subsequent pipeline stage. If there is an execution opportunity in a subsequent stage, the control information is dynamically modified according to the status of the producer instruction in the current stage, and the detection and judgment process is repeated in the next pipeline stage. If there is no opportunity to execute in subsequent stages and the producer instruction has not yet been completed, the instruction to be issued is paused in the current pipeline stage, and the status of the producer instruction is continuously monitored until the source operand is ready for execution.

6. The method of claim 5, wherein, The dynamically modified control information includes: Because of cavitation in the pipeline and the independent pauses at each stage, when the command to be issued and the producer command it depends on are not moving synchronously in the pipeline, the effective range of the bypass path control information is modified according to their actual relative position.

7. An instruction transmitting apparatus characterized by comprising: include: The launch unit is used to acquire information about the command to be launched and all commands in the pipeline during the launch cycle, and to detect the data correlation between the command to be launched and the commands in the pipeline. For a to-be-transmitted instruction with data dependency, control information including bypass control information and execution stage information is generated according to the type of the to-be-transmitted instruction and the execution state of an instruction relied on by the to-be-transmitted instruction; And the to-be-transmitted instruction is transmitted to the pipeline together with the control information, regardless of whether the source operand of the to-be-transmitted instruction is ready or not; The pipeline execution unit comprises a plurality of pipeline stages, and each pipeline stage comprises: a state detection module configured to detect the execution state of an instruction relied on by the current stage; a control information updating module configured to dynamically update the control information according to the detected state; an execution condition judgment module configured to judge whether the current stage meets an execution condition; a functional unit interface configured to send the to-be-transmitted instruction to a functional unit for execution when the execution condition is met.

8. The apparatus of claim 7, wherein, The transmission unit comprises: a dependency detection module configured to compare the source register of the to-be-transmitted instruction with the destination register of all instructions in the pipeline, and identify a producer instruction relied on by the to-be-transmitted instruction; a control information generation module configured to generate control information according to the execution state of the producer instruction, including: generating direct bypass control information when the producer instruction has completed execution at the time of transmission; generating control information including a bypass path expected to be used and a suggested execution stage when the producer instruction has not completed execution at the time of transmission.

9. The apparatus of claim 7, wherein, The control information updating module comprises: a state monitoring submodule configured to listen to a result bus and obtain a completion signal of the producer instruction; a bypass path calculation submodule configured to recalculate an optimal bypass path according to the current position of the producer instruction and the current position of the to-be-transmitted instruction; a control information storage submodule configured to store original and updated control information.

10. The apparatus of claim 7, wherein, The execution condition judgment module comprises: a data readiness judgment submodule configured to judge whether all source operands of the to-be-transmitted instruction are ready; a resource availability judgment submodule configured to judge whether a functional unit corresponding to the current pipeline stage is idle; an opportunity evaluation submodule configured to evaluate whether there is an execution opportunity in a subsequent pipeline stage when the current stage cannot execute; a pause control submodule configured to control the current pipeline stage to locally pause when there is no execution opportunity in the subsequent stage and the data is not ready.

11. A processor, comprising: An instruction transmission device according to any one of claims 7 to 10.

12. An electronic device, comprising: It comprises: at least one processor according to claim 11; and a memory for storing instructions executable by the processor.

13. A chip, characterized by An instruction transmission device according to any one of claims 7 to 10 is integrated.

14. A computer-readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the instruction transmission method according to any one of claims 1 to 6.

15. The apparatus of claim 7, wherein, The functional units in the pipeline execution unit adopt an asymmetric distribution structure, comprising: Different types and / or different numbers of functional units are configured in different pipeline stages, so that multiple instructions with data dependency in the same transmission period can be executed on the functional units in different stages without waiting.

16. The apparatus of claim 15, wherein, The functional units include at least one of an arithmetic logic unit ALU, a load store unit LSU, a multiply divide unit MDU, a branch instruction execution unit BRU, and have different distribution densities at different stages of the pipeline.

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