Method and apparatus for accelerating exact probability simulation in combinational equivalence checking

Abstract

This invention discloses an accelerated method and apparatus for precise probabilistic simulation in combinatorial equivalence checking, relating to the fields of electronic design automation (EDA) and high-performance computing. The method includes: parsing the input circuit combinational logic netlist to form an EPS operator graph and corresponding data distribution configuration, transmitting this data to a GPU; starting the GPU to distribute the EPS operator graph to a processing unit array for EPS calculation based on the data distribution configuration using a data flow-driven approach; and collecting the running status information of each round of calculation and feeding it back to the CPU for dynamic optimization of the next round of calculation. This method can transform circuit calculation tasks into data flow-driven EPS operator graphs and execute them on the GPU, efficiently utilizing the GPU's massively parallel computing capabilities to overcome performance bottlenecks. The pipelined task advancement based on superblocks and the dynamic optimization mechanism based on performance reports can adapt to the computational characteristics of different circuit structures, balance the load, optimize resource allocation, and significantly shorten the verification cycle of combinatorial equivalence checking.

Description

Technical Field

[0001] This invention relates to the fields of electronic design automation (EDA) and high-performance computing, and in particular to an accelerated method and apparatus for accurate probabilistic simulation in combinatorial equivalence checking. Background Technology

[0002] In chip design, Combinatorial equivalence checking (CEC) is a crucial step in EDA (Electronic Design Automation) for verifying the functional equivalence of two logic circuits. Its efficiency and reliability directly impact chip verification cycle time and tape-out success rate. Within the CEC process, the precise probabilistic simulation (EPS) stage is a critical process. It generates a signature by generating random inputs and tracking the probability differences of circuit outputs. This process requires bit-level probability propagation calculations across hundreds of millions of circuit nodes, accompanied by millions of memory accesses per cycle. Therefore, the EPS stage becomes the most time-consuming part of the entire verification process, accounting for over 60% of overall computational resources and becoming the performance bottleneck of CEC.

[0003] The advantage of GPUs in massively parallel processing lies in scenarios where computational overhead is high and most node operations within the same level are independent, enabling efficient concurrent execution of probability calculations for massive gate nodes in the circuit. Simultaneously, the high-bandwidth memory and multi-level storage hierarchy effectively handle frequent memory access demands. Combined with a hierarchical computing strategy, GPUs can efficiently complete the forward probability propagation process, significantly improving the execution efficiency and throughput of the EPS stage. However, due to the complex circuit structure, frequent pointer jumps in the circuit representation structure, and scattered data layout, GPU memory access is random and cache hit rate is low. Especially in the EPS stage, which must be calculated layer by layer according to the circuit topology, there are strict dependencies, making it difficult for GPUs to easily achieve full parallelization. Furthermore, the latency overhead of moving circuit data from host memory to the GPU and retrieving results from the GPU is high. Summary of the Invention

[0004] This invention provides a method and apparatus for accelerating precise probabilistic simulation in combinatorial equivalence checking, in order to solve the technical problem of ^.

[0005] In a first aspect, embodiments of the present invention provide a method for accelerating precise probabilistic simulation in combinatorial equivalence checking, comprising: S101, using the CPU main core to parse the input circuit combinational logic netlist, forming an EPS operator graph and corresponding data distribution configuration based on a preset conversion strategy, and transmitting it to the GPU cache. The EPS operator graph corresponds to the circuit hierarchical topology, and the data distribution configuration indicates the data storage location. S102: The CPU main core starts the GPU kernel, which uses a data stream-driven approach and advances in superblocks. Based on the data distribution configuration, it retrieves the metadata of the EPS operator graph in the GPU cache and distributes it to the GPU's processing unit array to perform EPS calculations. S103 collects the running status information of the current round of calculation after each round of EPS operator graph calculation is completed, forms a performance analysis report of the current round of calculation and sends it to the CPU main core, and performs hierarchical division and dynamic optimization for the next round of calculation.

[0006] Secondly, embodiments of the present invention provide an acceleration device for precise probabilistic simulation in combinatorial equivalence checking, comprising: The combinational logic netlist parsing module is used to parse the input circuit comparison combinational logic netlist pairs and convert them into EPS operator diagrams and corresponding data distribution configurations; The EPS calculation module is used to retrieve the metadata of the EPS operator graph in a data stream-driven and superblock-based manner and distribute it to the GPU processing unit array to perform EPS calculations. The feedback optimization module is used to collect running status information after each round of EPS operator graph calculation and provide feedback to dynamically optimize the next round of calculation by hierarchical division.

[0007] Thirdly, embodiments of the present invention provide an electronic device, including: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the accelerated method for accurate probabilistic simulation in the above-described combinatorial equivalence check.

[0008] Fourthly, embodiments of the present invention provide a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform an accelerated method for accurate probabilistic simulation in the above-described combinatorial equivalence check.

[0009] This invention provides an accelerated method and apparatus for precise probabilistic simulation in combinatorial equivalence checking. The method uses a CPU core to parse the circuit netlist and generate an EPS operator graph and data distribution configuration corresponding to the circuit hierarchy topology. Then, computation is advanced on a GPU using data flow-driven and superblock-based methods. After each round of computation, runtime status information is collected to generate a performance analysis report for feedback and dynamic optimization of the next round of computation. This method transforms circuit computation tasks into data flow-driven EPS operator graphs executed on the GPU, efficiently utilizing the GPU's massively parallel computing capabilities, improving the core computational throughput of the EPS stage, and overcoming the performance bottlenecks of CPU serial or simple parallel processing. The superblock-based pipelined task advancement and the performance report-based dynamic optimization mechanism can adapt to the computational characteristics of different circuit structures, balance the load, optimize resource allocation, significantly shorten the verification cycle of combinatorial equivalence checking, and improve the tape-out success rate. Attached Figure Description

[0010] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a flowchart of an accelerated method for precise probabilistic simulation in combinatorial equivalence checking, as described in Embodiment 1 of the present invention. Figure 2 This is a flowchart of an accelerated method for precise probabilistic simulation in combinatorial equivalence checking, as described in Embodiment 2 of the present invention. Figure 3 This is a schematic diagram of the performance analysis report described in Embodiment 2 of the present invention; Figure 4 This is a schematic diagram of the structure of an acceleration device for precise probabilistic simulation in combinatorial equivalence checking as described in Embodiment 3 of the present invention; Figure 5 This is a schematic diagram of the EPS calculation module described in Embodiment 3 of the present invention; Figure 6 This is a structural diagram of the electronic device described in Embodiment 4 of the present invention. Detailed Implementation

[0011] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0012] Example 1 Figure 1The flowchart below shows an accelerated method for precise probabilistic simulation in combinatorial equivalence checking according to Embodiment 1 of the present invention, which specifically includes the following steps: S101, using the CPU main core to parse the input circuit combinational logic netlist, forming an EPS operator graph and corresponding data distribution configuration based on a preset conversion strategy, and transmitting it to the GPU cache. The EPS operator graph corresponds to the circuit hierarchical topology, and the data distribution configuration indicates the data storage location.

[0013] Upon receiving a combinational logic netlist to be verified, typically consisting of a standard reference netlist and an optimized netlist, a combinational equivalence check compares the standard reference netlist and the optimized netlist. The CPU core parses the combinational logic netlist, identifying each logic gate instance in the circuit and their port connections and data dependencies, thereby reconstructing the circuit topology hierarchy. Based on this circuit topology hierarchy, the CPU core uses a preset transformation strategy to model each logic gate as an independent computation node. According to the data dependencies between nodes (i.e., the output of the previous level node is the input of the next level node), a directed acyclic EPS operator graph is generated. This operator graph is essentially a data flow representation of the circuit computation task, where nodes represent computations and edges represent signal or data flow between gates. Simultaneously, the CPU core allocates a storage location for each data point in the operator graph based on the GPU's memory hierarchy, forming a data distribution configuration. Finally, the prepared EPS operator graph, its metadata, and the corresponding data distribution configuration are transferred to the GPU's on-chip cache, preparing data for subsequent computations.

[0014] S102: The CPU main core starts the GPU kernel, which uses a data stream-driven approach and advances in superblocks. Based on the data distribution configuration, it retrieves the metadata of the EPS operator graph in the GPU cache and distributes it to the GPU's processing unit array to perform EPS calculations.

[0015] The CPU core starts the GPU kernel and submits the superblock execution queue to the GPU's streaming execution engine. At this point, all the metadata required for computation (including memory pointers, processing unit array configuration parameters, total number of superblocks, etc.) is ready. The CPU core then releases control and enters a state waiting for performance reports, no longer interfering with the GPU's internal execution. Execution then proceeds concurrently in a data-driven mode, no longer controlled by a central instruction, but automatically triggered by the readiness of the data. Computation is advanced in units of basic scheduling units (superblocks) aggregated from multiple consecutive circuit layers. The superblock currently being computed reads data from the GPU's on-chip cache and distributes it to the GPU's PE processing unit array according to the data distribution configuration. Once the input data for a processing unit is ready, that unit automatically triggers its internal probability propagation computation without waiting for a unified scheduling command.

[0016] S103 collects the running status information of the current round of calculation after each round of EPS operator graph calculation is completed, forms a performance analysis report of the current round of calculation and sends it to the CPU main core, and performs hierarchical division and dynamic optimization for the next round of calculation.

[0017] After one round of EPS operator graph calculation is completed, all superblocks have been executed. During the process, based on a hardware performance feedback loop, the actual running status information of each processing unit in this round of calculation is collected, such as computational load rate, data waiting time, cache hit / miss count, and the actual completion time of each superblock. After summarizing and analyzing, a structured performance analysis report is generated. To avoid occupying the main computational data bandwidth, this report is sent back to the CPU main core through a dedicated low-bandwidth channel. The CPU main core parses this report and identifies the performance bottlenecks, such as a superblock becoming a computational long tail due to excessive size, or some processing units being in an idle state. Based on this, the task partitioning strategy for the next round of calculation is dynamically adjusted, re-partitioning to a more suitable superblock size and adjusting the data mapping relationship. This forms a closed loop with the aforementioned preset transformation strategy, and optimization is performed when generating the EPS operator graph and corresponding data distribution configuration in the next round to improve computational efficiency.

[0018] This embodiment parses the circuit netlist using the CPU main core and generates an EPS operator graph and data distribution configuration corresponding to the circuit hierarchical topology. It then advances computation on the GPU using a data-flow-driven, superblock-based approach. After each round of computation, it collects runtime status information to generate a performance analysis report for feedback, dynamically optimizing the next round of computation. This approach transforms circuit computation tasks into data-flow-driven EPS operator graphs executed on the GPU, efficiently utilizing the GPU's massively parallel computing capabilities, improving the core computational throughput of the EPS stage, and overcoming the performance bottlenecks of CPU serial or simple parallel processing. The superblock-based pipelined task advancement and the performance report-based dynamic optimization mechanism adapt to the computational characteristics of different circuit structures, balance the load, optimize resource allocation, significantly shorten the verification cycle of combinatorial equivalence checks, and improve the tape-out success rate.

[0019] Example 2 Figure 2 This is a flowchart of an accelerated method for precise probabilistic simulation in combinatorial equivalence checking as described in Embodiment 2 of the present invention. This embodiment is based on the above embodiment and optimized. In this embodiment, S101 is specifically optimized as follows: The input combinational logic netlist is parsed to obtain the circuit topology hierarchy. The combinational logic netlist is either a standard reference combinational logic netlist or an optimized combinational logic circuit netlist. Based on the circuit topology hierarchy, the circuit logic gates are modeled as logic nodes and divided into multiple superblocks to form an EPS operator graph and corresponding data distribution configuration. The EPS operator graph is mapped to the GPU cache according to the corresponding data distribution configuration.

[0020] Accordingly, the accelerated method for precise probabilistic simulation in combinatorial equivalence checking provided in this embodiment specifically includes: S201, parse the input combinational logic netlist to obtain the circuit topology hierarchy. The combinational logic netlist is a standard reference combinational logic netlist or an optimized combinational logic circuit netlist.

[0021] The CPU core uses a standard EDA netlist parsing library to extract all logic gate instances and their interconnections. A graph theory algorithm is then used to traverse the input combinational logic netlist, clarifying the logic gate levels each signal must pass through from its initial input to its final output, thus obtaining the precise circuit topology hierarchy. The input combinational logic netlist can be a pair of standard reference combinational logic netlists and an optimized combinational logic circuit netlist to be verified. The standard reference netlist is the unoptimized RTL synthesis result, while the optimized netlist is a gate-level netlist after mapping, constant propagation, and redundancy elimination using logic synthesis tools. The two netlists are functionally equivalent but may have different structures. The verification task is to determine whether the probability distributions of their main output ports are consistent under a given random input stimulus.

[0022] S202, based on the circuit topology hierarchy, models the circuit logic gates as logic nodes and divides them into multiple superblocks, forming an EPS operator graph and corresponding data distribution configuration.

[0023] Based on the circuit topology hierarchy, each circuit logic gate is first modeled as a logic node. Then, all logic gate nodes at the same topology level without direct data dependencies are grouped into the same computation set. Next, based on the execution characteristics of GPU thread bundles and the capacity limitations of on-chip shared memory, multiple consecutive computation sets are aggregated into a superblock, resulting in multiple superblocks. These superblocks serve as the basic unit for task scheduling and data prefetching, forming the EPS operator graph and corresponding data distribution configuration. The operator graph, as the basis for modeling circuit logic gates as logic nodes to form a directed acyclic graph, is formed by aggregating complex nodes into superblocks. The data distribution configuration defines in detail the specific address layout of various types of data within each superblock in GPU memory, cache, and the on-chip cache to be prefetched. As the basic unit for GPU computation and scheduling, the superblock divides the EPS operator graph hierarchically into units suitable for GPU parallel processing, avoiding the deficiency of small-scale and granular nodes in the operator graph that cannot fully utilize the powerful computing capabilities of the GPU.

[0024] An optional implementation of this embodiment is that, during the initial EPS calculation, logical nodes at the same level that have no data dependency are divided into a parallel task block according to the circuit topology hierarchy, and multiple parallel task blocks at consecutive levels are aggregated into a superblock as the basic scheduling unit.

[0025] Since there is no historical data to refer to during the initial EPS calculation, the preset conversion strategy can divide the circuit topology into multiple calculation stages based on the preset target superblock computational complexity limit (such as the number of logic gates). Starting from the first level of the circuit topology, the calculation is performed in a topological hierarchy. All nodes in each calculation stage have no data dependencies and can be fully parallelized, forming a parallel task block. Multiple consecutive calculation stages can be further aggregated until the target superblock computational complexity limit is reached, forming the initial superblock partition. This maximizes the load balance of the initial calculation tasks, dynamically matching the computational throughput of each PE with the on-chip storage capacity.

[0026] When EPS calculation is not performed for the first time, the hierarchical division strategy for the next round of calculation is dynamically adjusted based on the performance analysis report of the previous round of operation and the dynamic task division driven by feedback.

[0027] When EPS calculations are not performed for the first time, a feedback-driven dynamic task partitioning approach is used to analyze the performance analysis report from the previous run. This analysis includes data such as the actual computation latency of each superblock, the hit rate and miss latency of the on-chip cache, the computational load balancing of each PE, DRAM bandwidth utilization, and data prefetching efficiency. The CPU core dynamically adjusts the hierarchical task partitioning strategy for the next run: when the superblock computation latency is too high, the core will split the superblock into smaller superblocks to reduce the computational intensity on each PE; when the PE load is uneven, the core will redistribute the mapping relationship between each superblock and parallel task block to PEs to fully utilize the computational power of the PEs. For example, if the performance analysis report shows that two consecutive superblocks have very short execution times and frequent data exchange between them, they will be merged to reduce the overhead of GPU kernel startup and context switching; if a superblock is identified as a performance bottleneck and its execution time is significantly longer than average, it will be split into two or more smaller superblocks to distribute the computational load more evenly across more PE processing units, effectively avoiding the bottleneck effect.

[0028] Specifically, based on the performance analysis report from the previous round of operation, and combined with the comparative combination logic netlist, the hierarchical partitioning strategy is dynamically optimized. Layers with fewer logic gates are merged with adjacent layers, while layers with more logic gates are split, forming an optimized EPS operator graph and corresponding optimized data distribution configuration.

[0029] Starting from the second round of EPS calculation (not the first time), after each round of calculation, the hierarchical partitioning strategy is dynamically optimized based on the performance analysis report from the previous round of operation. The mapping relationship between superblocks and GPU processing units is readjusted to improve hardware computing power utilization and form an optimized EPS operator graph and corresponding optimized data distribution configuration.

[0030] S203 maps the EPS operator graph to the GPU cache according to the corresponding data distribution configuration.

[0031] When constructing the EPS operator, the hierarchical dependency of EPS calculation can be abstracted into a phased execution model based on the number of levels n in the circuit topology: Let the circuit topology level l i The location contains w(l) i If there are ) logical nodes, then this w(l) i The nodes are inherently independent, meaning they can be executed in complete parallel. Furthermore, thanks to the hierarchical nature of the EPS operator, the l-th node in the operator's construction... i+1 At the same time, it can be known that the lth layer of the operator i The data required by the layer can be transferred in parallel to the GPU's cache via DMA. This asynchronous transfer achieves an overlap strategy between communication and computation, effectively alleviating communication bandwidth bottlenecks. The mapping process generates a GPU memory address table, recording the starting GPU address, size, and storage level of each superblock of data for subsequent lookup by the streaming execution engine.

[0032] S204: The CPU main core starts the GPU kernel, which uses a data stream-driven approach and advances in superblocks. Based on the data distribution configuration, it retrieves the metadata of the EPS operator graph in the GPU cache and distributes it to the GPU's processing unit array to perform EPS calculations.

[0033] Specifically, a look-ahead pipelined three-level cache prefetch strategy is adopted. When computing the current superblock, the next superblock is asynchronously prefetched from off-chip storage to the GPU's on-chip storage. When the current superblock is completed, the prefetched next superblock is distributed from the on-chip storage to the local buffer of the corresponding processing unit via the on-chip network. After the data in the buffer of each processing unit is ready, the probability propagation calculation is automatically triggered.

[0034] The three-tier storage architecture consists of off-chip DRAM → on-chip cache → PE local buffer (register file). During superblock execution, the DMA engine asynchronously initiates a prefetch request to transfer the next superblock from DRAM to the cache's reserved area. DMA transfer and the computation of the current superblock are parallel, and the overlap of computation and prefetching hides communication latency. For example, if superblock S is currently being executed... k It contains levels l1 to l mAt this point, the corresponding PE reads the node input data allocated to it from the m levels in the local buffer, performs EPS probability propagation, and writes the result back to the buffer. Simultaneously, it retrieves the S data from DRAM. k+1 The required input node data is loaded into the reserved area in the cache to ensure superblock S k+1 Before execution begins, its input data is already ready in the cache. When superblock S... k Execution complete, S k+1 When it is about to start, S in the cache k+1 The input data is transmitted point-to-point to the corresponding PE's buffer via the on-chip network. Once the data is ready, the PE is immediately driven to start execution, automatically triggering the S k+1 The calculation.

[0035] S205 collects the running status information of the current round of calculation after each round of EPS operator graph calculation is completed, forms a performance analysis report of the current round of calculation and sends it to the CPU main core, and performs hierarchical division and dynamic optimization for the next round of calculation.

[0036] Specifically, after each round of EPS operator graph calculation is completed, the performance monitor integrated in the GPU is used to collect the resource status information fed back by each processing unit at the execution boundary of each superblock, forming a performance analysis report for this round of calculation.

[0037] The performance monitor is a lightweight hardware module integrated on the GPU, embedded at the interface between the PE array and the on-chip network. It collects resource status data during execution at the execution boundaries of each superblock, specifically at the start and end of execution, while avoiding interference with the computation process. The collected resource status information includes the computational activity cycle (utilization) of each PE, data wait time, cache hit / miss counts and latency, and superblock task completion time. The collected information is compressed and structured to generate a performance analysis report for this round of computation, such as... Figure 3 As shown.

[0038] The performance analysis report of this round of computation is sent back to the CPU main core through a dedicated low-bandwidth channel. The CPU main core parses the performance analysis report and dynamically adjusts the superblock partitioning strategy and data distribution strategy to dynamically optimize the hierarchical partitioning strategy, superblock size and processing unit mapping relationship for the next round of computation.

[0039] The performance analysis report is sent back to the CPU via a dedicated low-bandwidth channel. After parsing the report, the CPU core identifies performance bottlenecks in the current operator based on resource status information, such as severely unevenly loaded PE groups, superblocks with frequent cache misses, or critical paths delayed due to excessively long data dependencies. Based on this, the CPU core dynamically adjusts the superblock partitioning and data distribution strategies for the next round of computation. It performs fine-grained splitting of excessively large or poorly localized superblocks, merges lightweight and adjacent layers to reduce scheduling overhead, and prioritizes mapping newly identified bottleneck tasks to more computing resources. The optimized layer partitioning, superblock size, data distribution, and PE mapping relationships are updated in the configuration file for the initialization of the next round of computation. This allows for continuous improvement of task partitioning and resource scheduling strategies across multiple rounds, preventing the recurrence of similar performance bottlenecks.

[0040] This embodiment provides GPUs with task units exhibiting good parallelism and data locality by modeling logic gates as nodes and aggregating them into superblocks according to circuit topology hierarchy, thus providing a data distribution foundation for efficient parallel computing. The dynamic task partitioning strategy based on performance feedback can eliminate performance bottlenecks caused by uneven load distribution in real time, ensuring that the GPU's PE computing array always maintains high utilization and achieving adaptive optimal allocation of computing resources. The look-ahead pipelined L3 cache prefetching strategy effectively hides the high latency of accessing data from off-chip memory by overlapping the data prefetching of the next superblock with the computation execution of the current superblock in time, allowing computing units to work continuously, thereby improving data provisioning efficiency and computational throughput. Utilizing a performance monitor to collect fine-grained resource status indicators at the superblock task boundaries and feeding them back through a low-overhead dedicated channel provides precise data support for dynamic optimization, enabling continuous optimization of the EPS process and maintaining consistently high-efficiency operation.

[0041] Example 3 Figure 4 This is a schematic diagram of the structure of an acceleration device for precise probabilistic simulation in combinatorial equivalence checking according to Embodiment 3 of the present invention. In this embodiment, the acceleration device for precise probabilistic simulation in combinatorial equivalence checking includes: Combinational logic netlist parsing module 810 is used to parse the input combinational logic netlist and convert it into EPS operator diagram and corresponding data distribution configuration; EPS calculation module 820 is used to retrieve the metadata of the EPS operator graph in a data stream-driven and superblock-based manner and distribute it to the GPU processing unit array to perform EPS calculations. The feedback optimization module 830 is used to collect running status information after each round of EPS operator graph calculation and provide feedback to dynamically optimize the next round of calculation by hierarchical division.

[0042] This embodiment uses the combinational logic netlist input by the combinational logic netlist parsing module to perform EPS calculations in a data-driven manner through the EPS calculation module. A feedback tuning module collects runtime status information to dynamically tune the next round of calculations through hierarchical partitioning. This transforms circuit calculation tasks into data-driven EPS operator graphs and executes them on the GPU, efficiently utilizing the GPU's massively parallel computing capabilities, improving the core computational throughput of the EPS stage, and overcoming the performance bottlenecks of CPU serial or simple parallel processing. The pipelined task advancement based on superblocks and the dynamic tuning mechanism based on performance reports can adapt to the computational characteristics of different circuit structures, balance the load and optimize resource allocation, significantly shorten the verification cycle of combinational equivalence checks, and improve the tape-out success rate.

[0043] Optionally, the EPS calculation module includes off-chip memory (DRAM), a processing element (PE) array, on-chip memory (Cache), a local buffer (Buffer), an on-chip network (NoC), a performance monitor, and a flow execution engine.

[0044] The PE array is configured to run the aforementioned EPS acceleration method; NoC is responsible for data interaction between the PE array and on-chip memory; on-chip memory includes cache, and local buffer is also part of on-chip memory. On-chip memory and off-chip memory (DRAM) together form a three-level memory architecture of DRAM-Cache-Buffer; the performance monitor is responsible for collecting and summarizing hardware information of the operator execution device (PE array) and generating performance reports for the main core to optimize; the flow execution engine is responsible for task pipeline advancement and data prefetching coordination, such as... Figure 5 As shown. Off-chip DRAM, as a system-level storage device, is managed by the CPU core and is used to persistently store all the data required for the entire circuit simulation task, including the complete combinational logic netlist, metadata of the EPS operator graph, probabilistic states of all nodes, and input stimulus vectors for multiple rounds of simulation. On-chip storage is divided into two levels: Cache and Buffer. The Cache is a software-manageable on-chip SRAM array, jointly managed by the CPU core and the prefetch controller. During task initialization, the CPU pre-plans the layout of the data required for each computation superblock in the Cache based on the hierarchical task partitioning results. The Buffer is a local storage resource shared by each PE group, automatically managed by the system during PE array runtime, without CPU intervention.

[0045] The performance monitor is deployed on the critical path between the PE processing unit array and the on-chip network to collect runtime resource status information in real time during EPS calculation, including a configurable counter array, preset event triggering logic, and local status registers. The monitor consists of a set of configurable counter arrays, event triggering logic, and local status registers. It does not rely on external software instrumentation or interrupt mechanisms and can continuously track key performance events such as the computational activity cycle of each PE, idle waiting time, buffer data readiness latency, cache hit / miss counts, and superblock-level task completion time without interfering with the normal computational pipeline. The monitor's data collection granularity is aligned with the task execution structure, i.e., statistical aggregation is performed on a superblock basis. At the end of each batch of calculations, a compressed performance summary is sent to the CPU main core via a dedicated low-bandwidth backhaul channel. Due to its simple logic, small area overhead, and the fact that data is reported only at task boundaries, this monitor provides high-value feedback information while introducing almost no additional power consumption or latency overhead.

[0046] The streaming execution engine is electrically connected to the PE processing unit array and is used to control the pipelined advancement and data prefetching of superblock computation tasks, as well as manage the execution boundaries and resource release between superblocks. The streaming execution engine is responsible for coordinating the pipelined advancement and data prefetching of superblock-level tasks. Based on the current superblock position, it dynamically initiates look-ahead prefetching of the data required for the next superblock, loads the data from DRAM to the on-chip cache, and distributes the data to the local buffers of each PE at superblock switching boundaries. Simultaneously, it manages the execution boundaries and resource release between superblocks to ensure continuous computation pipeline advancement. Specific node-level computation is performed autonomously by the PE array. Once the input data in each PE's local buffer is ready, it automatically starts the corresponding operation based on the resident operator graph data, without external scheduling intervention.

[0047] It also includes a prefetch controller, electrically connected to the streaming execution engine and off-chip memory, for asynchronously prefetching the next superblock from off-chip DRAM to on-chip memory while computing the current superblock. During PE array operation, the prefetch controller loads data from DRAM into the cache asynchronously according to this plan and maintains its contents during superblock execution. During execution, the data prefetch controller distributes the data corresponding to the subtasks allocated to each PE in the current superblock from the cache to their dedicated buffer; once the input data in the buffer is ready, the PE automatically triggers computation, completes probability propagation, and temporarily stores the results locally. After computation, the results are written back to the cache for subsequent use.

[0048] The acceleration device for precise probabilistic simulation in combinatorial equivalence checking provided in this embodiment of the invention can execute the acceleration method for precise probabilistic simulation in combinatorial equivalence checking provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0049] Example 4 Figure 6 This is a structural diagram of an electronic device according to Embodiment 4 of the present invention. Figure 6 A block diagram is shown of an exemplary electronic device 12 suitable for implementing embodiments of the present invention. Figure 6 The electronic device 12 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of the present invention.

[0050] like Figure 6 As shown, the electronic device 12 is represented in the form of a general-purpose computing device. The components of the electronic device 12 may include, but are not limited to: one or more processors or processing units 16, system memory 28, and bus 18 connecting different system components (including system memory 28 and processing unit 16).

[0051] Bus 18 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. For example, these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0052] Electronic device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by electronic device 12, including volatile and non-volatile media, removable and non-removable media.

[0053] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Electronic device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write non-removable, non-volatile magnetic media (… Figure 6 Not shown; usually referred to as a "hard drive"). Although Figure 6Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 via one or more data media interfaces. System memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0054] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in system memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 42 typically perform the functions and / or methods described in the embodiments of the present invention.

[0055] Electronic device 12 can also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), and with one or more devices that enable a user to interact with the electronic device 12 / server / computer, and / or with any device that enables the electronic device 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). This communication can be performed through input / output (I / O) interface 22. Furthermore, electronic device 12 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 20. Figure 6 As shown, network adapter 20 communicates with other modules of electronic device 12 via bus 18. It should be understood that, although... Figure 6 As not shown, other hardware and / or software modules may be used in conjunction with electronic device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0056] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the accelerated method for accurate probabilistic simulation in combinatorial equivalence checking provided in the embodiments of the present invention.

[0057] Example 5 Embodiment 5 of the present invention also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform an accelerated method for accurate probabilistic simulation in combinatorial equivalence checking as provided in the above embodiments.

[0058] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0059] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0060] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0061] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0062] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for accelerating precise probabilistic simulation in combinatorial equivalence checking, characterized in that, include: S101, using the CPU main core to parse the input circuit combinational logic netlist, forming an EPS operator graph and corresponding data distribution configuration based on a preset conversion strategy, and transmitting it to the GPU cache. The EPS operator graph corresponds to the circuit hierarchical topology, and the data distribution configuration indicates the data storage location. S102: The CPU main core starts the GPU kernel, which uses a data stream-driven approach and advances in superblocks. Based on the data distribution configuration, it retrieves the metadata of the EPS operator graph in the GPU cache and distributes it to the GPU's processing unit array to perform EPS calculations. S103 collects the running status information of the current round of calculation after each round of EPS operator graph calculation is completed, forms a performance analysis report of the current round of calculation and sends it to the CPU main core, and performs hierarchical division and dynamic optimization for the next round of calculation.

2. The method according to claim 1, characterized in that, S101 includes: The input combinational logic netlist is parsed to obtain the circuit topology hierarchy. The combinational logic netlist is either a standard reference combinational logic netlist or an optimized combinational logic circuit netlist. Based on the circuit topology hierarchy, the circuit logic gates are modeled as logic nodes and divided into multiple superblocks to form an EPS operator graph and corresponding data distribution configuration. The EPS operator graph is mapped to the GPU cache according to the corresponding data distribution configuration.

3. The method according to claim 2, characterized in that, S101 further includes: When performing EPS calculation for the first time, logical nodes at the same level that have no data dependency are divided into a parallel task block according to the circuit topology hierarchy, and multiple parallel task blocks at consecutive levels are aggregated into a super block as the basic scheduling unit. When EPS calculation is not performed for the first time, the hierarchical division strategy for the next round of calculation is dynamically adjusted based on the performance analysis report of the previous round of operation and the dynamic task division driven by feedback.

4. The method according to claim 3, characterized in that, The strategy for dynamically adjusting the hierarchical partitioning for the next round of calculation includes: Based on the performance analysis report from the previous round of operation, and combined with the comparative combinational logic netlist, the hierarchical partitioning strategy is dynamically optimized. Hierarchies with fewer logic gates are merged with adjacent layers, while hierarchies with more logic gates are split, forming an optimized EPS operator graph and corresponding optimized data distribution configuration.

5. The method according to claim 1, characterized in that, The data stream driver includes: A look-ahead pipelined three-level cache prefetch strategy is adopted. When computing the current superblock, the next superblock is asynchronously prefetched from off-chip storage to the GPU's on-chip storage. When the current superblock is completed, the prefetched next superblock is distributed from the on-chip storage to the local buffer of the corresponding processing unit via the on-chip network. Once the data in each processing unit's buffer is ready, probability propagation calculation is automatically triggered.

6. The method according to claim 1, characterized in that, S103 includes: After each round of EPS operator graph calculation is completed, the performance monitor integrated in the GPU is used to collect the resource status information fed back by each processing unit at the execution boundary of each superblock, forming a performance analysis report for this round of calculation; The performance analysis report of this round of computation is sent back to the CPU main core through a dedicated low-bandwidth channel. The CPU main core parses the performance analysis report and dynamically adjusts the superblock partitioning strategy and data distribution strategy to dynamically optimize the hierarchical partitioning strategy, superblock size and processing unit mapping relationship for the next round of computation.

7. An acceleration device for precise probabilistic simulation in combinatorial equivalence checking, used to implement the acceleration method for precise probabilistic simulation in combinatorial equivalence checking as described in any one of claims 1-6, characterized in that, include: The combinational logic netlist parsing module is used to parse the input circuit comparison combinational logic netlist pairs and convert them into EPS operator diagrams and corresponding data distribution configurations; The EPS calculation module is used to retrieve the metadata of the EPS operator graph in a data stream-driven and superblock-based manner and distribute it to the GPU processing unit array to perform EPS calculations. The feedback optimization module is used to collect running status information after each round of EPS operator graph calculation and provide feedback to dynamically optimize the next round of calculation by hierarchical division.

8. The apparatus according to claim 7, characterized in that: The EPS calculation module includes off-chip DRAM, PE processing unit array, on-chip storage, local buffer, on-chip network, performance monitor, and streaming execution engine; The performance monitor is deployed on the critical path between the PE processing unit array and the on-chip network to collect runtime resource status information during the EPS calculation process in real time, including a configurable counter array, preset event triggering logic, and local status registers. The streaming execution engine is electrically connected to the PE processing unit array and is used to control the pipelined advancement of superblock computing tasks and data prefetching, as well as manage the execution boundaries and resource release between superblocks; It also includes a prefetch controller, electrically connected to the streaming execution engine and off-chip memory, for asynchronously prefetching the next superblock from off-chip DRAM to on-chip memory while computing the current superblock.

9. An electronic device, characterized in that, The electronic device includes: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the accelerated method for accurate probabilistic simulation in combinatorial equivalence checking as described in any one of claims 1-6.

10. A storage medium comprising computer-executable instructions, which, when executed by a computer processor, are used to perform an accelerated method for accurate probabilistic simulation in combinatorial equivalence checking as described in any one of claims 1-6.

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