An optimal modular multiplication algorithm selection method, encryption and decryption method and related device

Abstract

This invention discloses an optimal modular multiplication algorithm selection method, encryption / decryption method, and related apparatus. In the optimal modular multiplication algorithm selection method, if the operand type is a constant multiplied by a variable or a variable multiplied by a constant, or if the operand type is a variable multiplied by a variable and the bit width of the modulus is less than or equal to a preset threshold (i.e., for resource-constrained embedded devices or scenarios requiring frequent NTT / INTT transformations in the algorithm), the Plantard modular multiplication algorithm is used to perform modular multiplication on the two multipliers. For operand types of variable multiplication with an odd modulus and a bit width less than or equal to the preset threshold, the Montgomery modular multiplication algorithm is used. For operand types of variable multiplication with an even modulus and a bit width less than or equal to the preset threshold, the Barrett modular multiplication algorithm is used. Using this invention facilitates dynamic evaluation and switching to the optimal modular multiplication implementation path for the current scenario based on the bit width of the input modulus and the operand type.

Description

Technical Field

[0001] This invention relates to the field of public-key cryptography, and more specifically, to a method for selecting an optimal modular multiplication algorithm, an encryption / decryption method, and related apparatus. Background Technology

[0002] In current mainstream public-key cryptosystems (including traditional RSA / ECC and post-lattice cryptography such as Kyber and Dilithium), modular multiplication is the core computational unit, and its efficiency directly determines the performance of overall encryption / decryption, signature, and verification operations. However, existing technical solutions typically employ a fixed, single modular multiplication algorithm, failing to dynamically evaluate and switch to the optimal modular multiplication implementation path for the current scenario based on key runtime parameters—such as the bit width of the input modulus (e.g., non-standard prime numbers like 128-bit, 256-bit, or 329-bit), operand types (variable × variable, constant × variable, or constant × constant), target processor architecture (e.g., ARM Cortex-M series, RISC-V, or x86), and whether it is in a specific computational context such as Number Theoretic Transform (NTT) or Inverse Number Theoretic Transform (INTT). This "one-size-fits-all" strategy prevents the underlying algorithms and hardware platforms from reaching their full potential in many typical application scenarios, resulting in unnecessary computational overhead, increased energy consumption, and higher latency, which significantly affects average performance and energy efficiency. Summary of the Invention

[0003] To address the aforementioned problems in existing technologies, the present invention aims to provide an optimal modular multiplication algorithm selection method, encryption / decryption method, and related apparatus, which facilitates dynamic evaluation and switching to the optimal modular multiplication implementation path for the current scenario based on the bit width of the input modulus and the operand type.

[0004] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0005] A method for selecting an optimal modular multiplication algorithm, the method comprising: If one of the two input multipliers is a constant and the other is a variable, then the Plantard modular multiplication algorithm is used to perform modular multiplication on the two multipliers. If both multipliers are variables, then determine whether the bit width of the input modulus is less than or equal to a preset threshold. If the bit width of the modulus is less than or equal to a preset threshold, then the Plantard modular multiplication algorithm is used to perform modular multiplication on the two multipliers as described in step [1]. If the bit width of the modulus is greater than a preset threshold, then it is determined whether the modulus is odd or even. If the modulus is odd, the Montgomery modular multiplication algorithm is used to perform modular multiplication on the two multipliers; If the modulus is even, the Barrett modular multiplication algorithm is used to perform modular multiplication on the two multipliers.

[0006] In this embodiment, if the operand type is a constant multiplied by a variable or a variable multiplied by a constant, or if the operand type is a variable multiplied by a variable and the bit width of the modulus is less than or equal to a preset threshold (i.e., for resource-constrained embedded devices or scenarios where NTT / INTT transformations need to be frequently performed in the algorithm), the Plantard modular multiplication algorithm is used to perform modular multiplication on the two multipliers. For operand types of variable multiplication with an odd modulus and a bit width less than or equal to a preset threshold, the Montgomery modular multiplication algorithm is used to perform modular multiplication on the two multipliers. For operand types of variable multiplication with an even modulus and a bit width less than or equal to a preset threshold, the Barrett modular multiplication algorithm is used to perform modular multiplication on the two multipliers. This is beneficial for dynamically evaluating and switching to the modular multiplication implementation path with the best performance in the current scenario based on the bit width of the input modulus and the operand type.

[0007] Optionally, the method for selecting the optimal modular multiplication algorithm further includes: A modular multiplication algorithm is implemented using a Karatsuba multiplier with an adaptive bit width and a reusable configuration. The modular multiplication algorithm includes at least one of the following: Plantard modular multiplication algorithm, Montgomery modular multiplication algorithm, and Barrett modular multiplication algorithm.

[0008] In this embodiment, a modular multiplication algorithm is implemented using a reconfigured adaptive bit-width Karatsuba multiplier. This modular multiplication algorithm includes any one of the Plantard modular multiplication algorithm, the Montgomery modular multiplication algorithm, and the Barrett modular multiplication algorithm. Different modular multiplication algorithms are implemented through a unified multiplier, which greatly expands the adaptability of the modular multiplication algorithm.

[0009] Optionally, the multiplexed configuration of the adaptive bit-width Karatsuba multiplier implements the modular multiplication algorithm, including: Generate multiple candidate recursive termination thresholds; Determine the quotient of the bit width of the modulus and the multiple candidate recursion termination thresholds respectively; The candidate recursion termination threshold corresponding to the quotient that is closest to the preset threshold is used as the recursion termination threshold. The multiplication operation in the modular multiplication algorithm is implemented based on the recursion termination threshold and the Karatsuba multiplier.

[0010] In this embodiment, multiple candidate recursion termination thresholds are generated, and the quotient of the modulus bit width and the multiple candidate recursion termination thresholds is determined respectively. The candidate recursion termination threshold corresponding to the quotient closest to the preset threshold is taken as the recursion termination threshold. By selecting the recursion termination threshold, the sub-word bit width calculated based on the modulus bit width and the quotient of the recursion termination threshold is made close to 32, thereby maximizing hardware efficiency.

[0011] Optionally, the method for selecting the optimal modular multiplication algorithm further includes: If the bit width of the modulus is not an integer multiple of the candidate recursion termination threshold, then the bit width of the modulus is made to be an integer multiple of the candidate recursion termination threshold by padding with zeros.

[0012] In this embodiment, if the bit width of the modulus is not an integer multiple of the candidate recursion termination threshold, the bit width of the operand is padded with zeros to make it an integer multiple of the candidate recursion termination threshold, thereby making the recursive decomposition method of this invention applicable to any modulus bit width.

[0013] Optionally, the step of implementing the multiplication operation in the modular multiplication algorithm based on the recursion termination threshold and the Karatsuba multiplier includes: Determine whether the modular multiplication algorithm requires a partial bit width multiplication operation or a full bit width multiplication operation. Based on the recursion termination threshold, the multiplication operations that require partial bit width and the multiplication operations that require full bit width are iteratively decomposed respectively. Multiplication operations requiring partial bit width are implemented by using a half multiplier as a base multiplier for the Karatsuba multiplier, and multiplication operations requiring full bit width are implemented by using a full multiplier as a base multiplier for the Karatsuba multiplier.

[0014] In the embodiments of this application, the base multiplier in the Karatsuba multiplier implements the multiplication operation that requires taking part of the bit width after iterative decomposition by using a half multiplier as the base multiplier, and implements the multiplication operation that requires taking the full bit width after iterative decomposition by using a full multiplier as the base multiplier. Compared with using a full multiplier to implement all multiplication operations, the half multiplier can reduce the hardware area.

[0015] The present invention also provides an encryption / decryption method, the encryption / decryption method comprising: Based on the above-mentioned optimal modular multiplication algorithm selection method, a modular multiplication algorithm is selected to implement the encryption and decryption algorithm; The data is encrypted and decrypted according to the encryption and decryption algorithm to obtain the encrypted and decrypted data.

[0016] The present invention also provides an optimal modular multiplication algorithm selection device, the optimal modular multiplication algorithm selection device comprising: The modular multiplication unit is used to perform modular multiplication on the two input multipliers if one of the input multipliers is a constant and the other multiplier is a variable. The threshold determination unit is used to determine whether the bit width of the input modulus is less than or equal to a preset threshold if both of the multipliers are variables. The modular multiplication unit is used to perform modular multiplication on the two multipliers by using the Plantard modular multiplication algorithm if the bit width of the modulus is less than or equal to a preset threshold. A parity determination unit is used to determine whether the modulus is odd or even if the bit width of the modulus is greater than a preset threshold. The modular multiplication unit is used to perform modular multiplication on the two multipliers using the Montgomery modular multiplication algorithm if the modulus is odd. The modular multiplication unit is used to perform modular multiplication on the two multipliers using the Barrett modular multiplication algorithm if the modulus is even.

[0017] The present invention also provides an encryption / decryption device, the encryption / decryption device comprising: The algorithm implementation unit is used to select a modular multiplication algorithm according to the above-mentioned optimal modular multiplication algorithm selection method to implement the encryption and decryption algorithm; The encryption / decryption unit is used to encrypt and decrypt data according to the encryption / decryption algorithm to obtain encrypted and decrypted data.

[0018] The present invention also provides an electronic device, comprising: a processor and a memory; The processor is connected to the memory, wherein the memory is used to store computer programs and the processor is used to call the computer programs to execute methods such as the optimal modular multiplication algorithm selection method or encryption / decryption method in the embodiments of this application.

[0019] The present invention also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, perform a method such as the optimal modular multiplication algorithm selection method or encryption / decryption method as described in the embodiments of this application.

[0020] For the beneficial effects on the device side, please refer to the beneficial effects on the method side described above. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 An example hardware architecture block diagram of an optimal modular multiplication algorithm selection system provided in one embodiment of this application is shown; Figure 2 A flowchart illustrating the optimal modular multiplication algorithm selection method provided in one embodiment of this application is shown. Figure 3 The pseudocode diagram of the Plantard modular multiplication algorithm provided in one embodiment of this application is shown; Figure 4 The pseudocode diagram of the Montgomery modular multiplication algorithm provided in one embodiment of this application is shown; Figure 5 The pseudocode diagram of the Barrett modular multiplication algorithm provided in one embodiment of this application is shown; Figure 6 A flowchart illustrating an embodiment of the encryption / decryption method provided in this application is shown. Figure 7 This invention provides a schematic diagram of the structure of an optimal modular multiplication algorithm selection device according to an embodiment of the present application. Figure 8 A schematic diagram of the encryption / decryption apparatus provided in one embodiment of this application is shown; Figure 9 This application shows a schematic diagram of the structure of a computer device according to an embodiment of the present application. Detailed Implementation The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] Please refer to Figure 1 This diagram illustrates an example hardware architecture block diagram of an optimal modular multiplication algorithm selection system according to an embodiment of this application. The optimal modular multiplication algorithm selection system includes an input / output interface, a data preprocessing module, and a modular multiplication operation module. Wherein: The input / output interface is responsible for communicating with the outside world, receiving data to be processed (such as modular multiplication operands), and outputting the results (modular multiplication results) to external or internal storage.

[0024] The data preprocessing module includes: a finite state machine (FSM), a preprocessing unit, a reduction unit, and a result verification unit.

[0025] FSM is responsible for coordinating the entire modular multiplication system's operation process. Based on the characteristics of the input data and the current state of the system, it dynamically schedules different processing paths and algorithm modules to achieve the goal of intelligently selecting the optimal modular multiplication algorithm.

[0026] The preprocessing unit is used to preprocess the input data, such as format conversion, bit width alignment, sign extension, range checking, etc.

[0027] Modular reduction simple elements are used to perform one of the modular multiplication algorithms to reduce intermediate results to the standard residue system of the modulus.

[0028] The result verification unit is used to verify the correctness of the modular multiplication result.

[0029] The modular multiplication module includes: a first-in-first-out buffer (FIFO), a first register (R1) storing the Montgomery modular multiplication algorithm, a second register (R2) storing the Barrett modular multiplication algorithm, and a third register (R3) storing the Plantard modular multiplication algorithm.

[0030] The first-in-first-out buffer is used to smooth the data flow, avoid data blocking caused by mismatch in calculation speed, and temporarily store the preprocessing numbers for subsequent modular multiplication modules to read on demand.

[0031] The right side of this optimal modular multiplication algorithm selection system provides an example data path and algorithm selection process: If one input data point is a constant and the other is a variable (Constants & Variables), the Plantard modular multiplication algorithm stored in R3 is directly selected. If both are variables (Variables & Variables), the bit width N of the modulus is further determined, with a preset threshold of 32. If the bit width is less than 32, the Plantard modular multiplication algorithm stored in R3 is still selected. If the bit width is greater than 32, the parity of the modulus is further determined. If it is odd, the Montgomery modular multiplication algorithm stored in R1 is selected; if it is even, the Barrett modular multiplication algorithm stored in R2 is selected.

[0032] Please refer to Figure 2 This document illustrates a flowchart of an embodiment of the optimal modular multiplication algorithm selection method provided in this application. The optimal modular multiplication algorithm selection method includes the following steps: Step 201: Obtain the two input multipliers.

[0033] Step 202: Determine whether one of the two multipliers is a constant and the other is a variable, or whether both multipliers are variables; If one multiplier is a constant and the other multiplier is a variable, then proceed to step 203: If both multipliers are variables, then proceed to step 204.

[0034] Step 203: Perform modular multiplication on the two multipliers using the Plantard modular multiplication algorithm.

[0035] Step 204: Determine whether the bit width of the input modulus is less than or equal to a preset threshold; If so, proceed to step 203; If not, proceed to step 205.

[0036] Step 205: Determine whether the modulus is odd or even; If the number is odd, proceed to step 206; If the number is even, proceed to step 207.

[0037] Step 206: Perform modular multiplication on the two multipliers using the Montgomery modular multiplication algorithm; Step 207: Perform modular multiplication on the two multipliers using the Barrett modular multiplication algorithm.

[0038] It should be noted that the preset threshold can be 32, 64, 128, or other values, which are not limited here.

[0039] In this embodiment, if the operand type is a constant multiplied by a variable or a variable multiplied by a constant, or if the operand type is a variable multiplied by a variable and the bit width of the modulus is less than or equal to a preset threshold (i.e., for resource-constrained embedded devices or scenarios where NTT / INTT transformations need to be frequently performed in the algorithm), the Plantard modular multiplication algorithm is used to perform modular multiplication on the two multipliers. For operand types of variable multiplication with an odd modulus and a bit width less than or equal to a preset threshold, the Montgomery modular multiplication algorithm is used to perform modular multiplication on the two multipliers. For operand types of variable multiplication with an even modulus and a bit width less than or equal to a preset threshold, the Barrett modular multiplication algorithm is used to perform modular multiplication on the two multipliers. This is beneficial for dynamically evaluating and switching to the modular multiplication implementation path with the best performance in the current scenario based on the bit width of the input modulus and the operand type.

[0040] Furthermore, the optimal modular multiplication algorithm selection method also includes: A modular multiplication algorithm is implemented using a Karatsuba multiplier with an adaptive bit width and a reusable configuration. The modular multiplication algorithm includes at least one of the following: Plantard modular multiplication algorithm, Montgomery modular multiplication algorithm, and Barrett modular multiplication algorithm.

[0041] A Karatsuba multiplier is a high-efficiency hardware or software implementation of large integer multiplication based on the Karatsuba algorithm. It is widely used in cryptography (such as RSA, ECC, and lattice ciphers) to accelerate multiplication operations on large-bit-width integers or polynomials. To reduce hardware costs, fast multiplication techniques such as the Karatsuba algorithm have been introduced, reducing the number of multiplications by recursively decomposing operands. For example: If the bit width of the modulus is N, and the recursion termination threshold k=2, Karatsuba's principle is to split two integers A and B into: A=A1×r+A0 and B=B1×r+B0, and then reduce multiplication operations by representing the intermediate term in C=A×B=(A1×r+A0)(B1×r+B0)=A1B1×r²+(A1B0+A0B1)×r+A0B0 as (A1B0+A0B1)=(A0+A1)×(B0+B1)-A0×B0-A1×B1. The latest Karatsuba research (reference Zhang, Bo, M. Zhang, and S. Yan. "Exploration of Karatsuba Algorithm for Efficient Barrett Modular Multiplication." {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems} 45.) proposes several decomposition methods and points out that if the input bit width is N, the hardware area efficiency is optimal when the bit width of each sub-multiplier is decomposed into m = N / k, which is close to 32 bits, through recursive decomposition.

[0042] In this embodiment, a modular multiplication algorithm is implemented using a reconfigured adaptive bit-width Karatsuba multiplier. This modular multiplication algorithm includes any one of the Plantard modular multiplication algorithm, the Montgomery modular multiplication algorithm, and the Barrett modular multiplication algorithm. Different modular multiplication algorithms are implemented through a unified multiplier, which greatly expands the adaptability of the modular multiplication algorithm.

[0043] Specifically, the modular multiplication algorithm is implemented by reusing the adaptive bit-width Karatsuba multiplier, including: Generate multiple candidate recursive termination thresholds; Determine the quotient of the bit width of the modulus and the multiple candidate recursion termination thresholds respectively; The candidate recursion termination threshold corresponding to the quotient that is closest to the preset threshold is used as the recursion termination threshold. Implement the multiplication operation in the modular multiplication algorithm based on the recursion termination threshold and the Karatsuba multiplier.

[0044] The candidate recursion termination threshold k is typically a power of 2 or a small composite number, such as 2, 3, 4, 5, 6, 8, etc. After determining the candidate k, the system calculates the sub-word width m = N / k corresponding to each candidate k, where N is the bit width of the modulus. Then, the k corresponding to m that is closest to the preset threshold is used as the recursion termination threshold. The modular multiplication algorithm then uses this recursion termination threshold and the Karatsuba multiplier to perform the multiplication operation.

[0045] In this embodiment, multiple candidate recursion termination thresholds are generated, and the quotient of the modulus bit width and the multiple candidate recursion termination thresholds is determined respectively. The candidate recursion termination threshold corresponding to the quotient closest to the preset threshold is taken as the recursion termination threshold. By selecting the recursion termination threshold, the sub-word bit width calculated based on the modulus bit width and the quotient of the recursion termination threshold is made close to 32, thereby maximizing hardware efficiency.

[0046] Optionally, the method for selecting the optimal modular multiplication algorithm also includes: If the bit width of the modulus is not an integer multiple of the candidate recursion termination threshold, then the bit width of the modulus is padded with zeros to make it an integer multiple of the candidate recursion termination threshold.

[0047] In this embodiment, if the bit width of the modulus is not an integer multiple of the candidate recursion termination threshold, the bit width of the operand is padded with zeros to make it an integer multiple of the candidate recursion termination threshold, thereby making the recursive decomposition method of this invention applicable to any modulus bit width.

[0048] Specifically, the multiplication operation in the modular multiplication algorithm is implemented based on the recursion termination threshold and the Karatsuba multiplier, including: Determine whether the modular multiplication algorithm requires a partial bit width multiplication operation or a full bit width multiplication operation. Based on the recursion termination threshold, the multiplication operations that require partial bit width and the multiplication operations that require full bit width are iteratively decomposed respectively. Multiplication operations requiring partial bit width are implemented by using a half multiplier as a base multiplier for the Karatsuba multiplier, and multiplication operations requiring full bit width are implemented by using a full multiplier as a base multiplier for the Karatsuba multiplier.

[0049] Please see Figures 3 to 5The diagrams show pseudocode illustrations of the Plantard modular multiplication algorithm, the Montgomery modular multiplication algorithm, and the Barrett modular multiplication algorithm provided in one embodiment of this application. In the Plantard modular multiplication algorithm, This can be achieved using a semimultiplier. This can be achieved using a full multiplier. In Montgomery's modular multiplication algorithm... and This can be achieved using a full multiplier. This can be implemented using a semi-multiplier, where express In Barrett's modular multiplication algorithm, This can be achieved using a full multiplier. This can be achieved using a semi-multiplier.

[0050] In the embodiments of this application, the base multiplier in the Karatsuba multiplier implements the multiplication operation that requires taking part of the bit width after iterative decomposition by using a half multiplier as the base multiplier, and implements the multiplication operation that requires taking the full bit width after iterative decomposition by using a full multiplier as the base multiplier. Compared with using a full multiplier to implement all multiplication operations, the half multiplier can reduce the hardware area.

[0051] Please refer to Figure 6 The diagram illustrates a flowchart of an encryption / decryption method provided in one embodiment of this application.

[0052] Step 601: Select the modular multiplication algorithm according to the optimal modular multiplication algorithm selection method to implement the encryption / decryption algorithm; Step 602: Encrypt and decrypt the data according to the encryption and decryption algorithm to obtain the encrypted and decrypted data.

[0053] The encryption and decryption algorithm includes an encryption algorithm and a decryption algorithm. When the optimal modular multiplication algorithm selection method is used to implement the encryption algorithm, the data is encrypted according to the encryption algorithm to obtain the encrypted data. When the optimal modular multiplication algorithm selection method is used to implement the decryption algorithm, the data is decrypted according to the decryption algorithm to obtain the decrypted data.

[0054] Please refer to Figure 7 This illustration shows a schematic diagram of the structure of an optimal modular multiplication algorithm selection device according to an embodiment of this application. The optimal modular multiplication algorithm selection device includes: The modular multiplication unit 701 is used to perform modular multiplication on the two input multipliers if one of the two multipliers is a constant and the other is a variable. The threshold judgment unit 702 is used to determine whether the bit width of the input modulus is less than or equal to a preset threshold if both multipliers are variables. The modular multiplication unit 701 is used to perform modular multiplication on the two multipliers by using the Plantard modular multiplication algorithm if the bit width of the modulus is less than or equal to a preset threshold. The parity determination unit 703 is used to determine whether the modulus is odd or even if the bit width of the modulus is greater than a preset threshold. Modular multiplication unit 701 is used to perform modular multiplication on two multipliers using the Montgomery modular multiplication algorithm if the modulus is odd. Modular multiplication unit 701 is used to perform modular multiplication of two multipliers using the Barrett modular multiplication algorithm if the modulus is even.

[0055] Please refer to Figure 8 This illustration shows a schematic diagram of an encryption / decryption device provided in one embodiment of this application. The encryption / decryption device includes: The algorithm implementation unit 801 is used to select a modular multiplication algorithm according to the optimal modular multiplication algorithm selection method to implement the encryption and decryption algorithm; The encryption / decryption unit 802 is used to encrypt and decrypt data according to the encryption / decryption algorithm to obtain the encrypted / decrypted data.

[0056] For the beneficial effects on the device side, please refer to the beneficial effects on the method side described above.

[0057] Figure 9 The diagram illustrates the structure of a computer device according to an embodiment of this application. The computer device includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the functions of the computer system of the optimal modular multiplication algorithm selection method or encryption / decryption method in any of the above embodiments.

[0058] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the functions of the computer system of the optimal modular multiplication algorithm selection method or encryption / decryption method in any of the above embodiments.

[0059] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the functions of the computer system of the optimal modular multiplication algorithm selection method or encryption / decryption method in any of the above embodiments.

[0060] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0061] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0062] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0063] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0064] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0065] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0066] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0067] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0068] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0069] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0070] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0071] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0072] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A method for selecting the optimal modular multiplication algorithm, characterized in that, The method for selecting the optimal modular multiplication algorithm includes: If one of the two input multipliers is a constant and the other is a variable, then the Plantard modular multiplication algorithm is used to perform modular multiplication on the two multipliers. If both multipliers are variables, then determine whether the bit width of the input modulus is less than or equal to a preset threshold. If the bit width of the modulus is less than or equal to a preset threshold, then the Plantard modular multiplication algorithm is used to perform modular multiplication on the two multipliers as described in step [1]. If the bit width of the modulus is greater than a preset threshold, then it is determined whether the modulus is odd or even. If the modulus is odd, the Montgomery modular multiplication algorithm is used to perform modular multiplication on the two multipliers; If the modulus is even, the Barrett modular multiplication algorithm is used to perform modular multiplication on the two multipliers.

2. A method for selecting the optimal modular multiplication algorithm according to claim 1, characterized in that, The method for selecting the optimal modular multiplication algorithm also includes: A modular multiplication algorithm is implemented using a Karatsuba multiplier with an adaptive bit width and a reusable configuration. The modular multiplication algorithm includes at least one of the following: Plantard modular multiplication algorithm, Montgomery modular multiplication algorithm, and Barrett modular multiplication algorithm.

3. A method for selecting the optimal modular multiplication algorithm according to claim 2, characterized in that, The multiplexed configuration of the adaptive bit-width Karatsuba multiplier implements the modular multiplication algorithm, including: Generate multiple candidate recursive termination thresholds; Determine the quotient of the bit width of the modulus and the multiple candidate recursion termination thresholds respectively; The candidate recursion termination threshold corresponding to the quotient that is closest to the preset threshold is used as the recursion termination threshold. The multiplication operation in the modular multiplication algorithm is implemented based on the recursion termination threshold and the Karatsuba multiplier.

4. A method for selecting the optimal modular multiplication algorithm according to claim 3, characterized in that, The method for selecting the optimal modular multiplication algorithm also includes: If the bit width of the modulus is not an integer multiple of the candidate recursion termination threshold, then the bit width of the modulus is made to be an integer multiple of the candidate recursion termination threshold by padding with zeros.

5. A method for selecting the optimal modular multiplication algorithm according to claim 4, characterized in that, The step of implementing the multiplication operation in the modular multiplication algorithm based on the recursion termination threshold and the Karatsuba multiplier includes: Determine whether the modular multiplication algorithm requires a partial bit width multiplication operation or a full bit width multiplication operation. Based on the recursion termination threshold, the multiplication operations that require partial bit width and the multiplication operations that require full bit width are iteratively decomposed respectively. Multiplication operations requiring partial bit width are implemented by using a half multiplier as a base multiplier for the Karatsuba multiplier, and multiplication operations requiring full bit width are implemented by using a full multiplier as a base multiplier for the Karatsuba multiplier.

6. An encryption / decryption method, characterized in that, The encryption / decryption methods include: The optimal modular multiplication algorithm selection method according to any one of claims 1-5 selects a modular multiplication algorithm to implement the encryption / decryption algorithm; The data is encrypted and decrypted according to the encryption and decryption algorithm to obtain the encrypted and decrypted data.

7. A device for selecting the optimal modular multiplication algorithm, characterized in that, The optimal modular multiplication algorithm selection device includes: The modular multiplication unit is used to perform modular multiplication on the two input multipliers if one of the input multipliers is a constant and the other multiplier is a variable. The threshold determination unit is used to determine whether the bit width of the input modulus is less than or equal to a preset threshold if both of the multipliers are variables. The modular multiplication unit is used to perform modular multiplication on the two multipliers by using the Plantard modular multiplication algorithm if the bit width of the modulus is less than or equal to a preset threshold. A parity determination unit is used to determine whether the modulus is odd or even if the bit width of the modulus is greater than a preset threshold. The modular multiplication unit is used to perform modular multiplication on the two multipliers using the Montgomery modular multiplication algorithm if the modulus is odd. The modular multiplication unit is used to perform modular multiplication on the two multipliers using the Barrett modular multiplication algorithm if the modulus is even.

8. An encryption / decryption device, characterized in that, The encryption / decryption device includes: The algorithm implementation unit is used to select a modular multiplication algorithm according to the optimal modular multiplication algorithm selection method according to any one of claims 1-5 to implement the encryption and decryption algorithm; The encryption / decryption unit is used to encrypt and decrypt data according to the encryption / decryption algorithm to obtain encrypted and decrypted data.

9. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to call the computer program to execute the optimal modular multiplication algorithm selection method as described in any one of claims 1-5 or the encryption / decryption method as described in claim 6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which includes program instructions that, when executed by a processor, perform the optimal modular multiplication algorithm selection method as described in any one of claims 1-5 or the encryption / decryption method as described in claim 6.

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