A reliable transmission method for RDMA cross wide area network transmission

Abstract

This invention relates to a reliable transmission method for RDMA cross-WAN transmission, comprising the following steps: Step 1: Detecting and obtaining the basic physical packet loss rate and the average duration of micro-burst packet loss of the WAN link; Step 2: Constructing a probability-based lower bound model for packet loss recovery theoretical requirements; Step 3: Constructing a nonlinear congestion penalty model based on queuing theory; Step 4: Multiplying the ideal number of redundant packets by the congestion resistance penalty coefficient to obtain a deterministic analytical solution for the theoretically optimal number of redundant packets; Step 5: Deriving the safe time interval during which redundant packets must be delayed; Step 6: After the sending end continuously sends k original data packets on the underlying physical link, time-domain interleaving is achieved; This scheme enables the redundant packets to be physically isolated from the original data stream on the time axis, effectively avoiding the long-tail coverage effect of micro-burst packet loss.

Description

Technical Field

[0001] This invention relates to the field of computer network transmission protocol stack optimization and underlying hardware traffic shaping technology. Specifically, it relates to a method for deploying RDMA (Remote Direct Memory Access) protocols across Wide Area Networks (WANs), which constructs a nonlinear mathematical expectation model based on probability theory and queuing theory to derive the theoretically optimal FEC (Forward Error Correction) redundancy ratio, and combines the physical time characteristics of microbursts to perform physical time-domain interleaving (Pacing) of redundant packets through the underlying hardware network interface card descriptor (WQE). Background Technology

[0002] With the cross-regional deployment of distributed storage and AI computing networks, RDMA technology has been widely adopted in wide area networks (WANs) due to its advantages of high throughput and low CPU overhead. However, network congestion under WAN multiplexing often leads to intermittent microburst packet loss. RDMA is inherently extremely sensitive to packet loss and highly dependent on a lossless network environment. Traditional forward error correction (FEC) mechanisms suffer from two fatal underlying flaws when introduced into RDMA:

[0003] First, blind redundancy lacking mathematical theoretical support can easily lead to "RDMA congestion collapse". Traditional FEC mechanisms usually adopt empirical static configuration ratios (such as a 10:8 ratio, that is, 2 redundant packets are always sent for every 8 data packets). When the network is already congested and the switch queue level is high, blindly injected redundant packets will instantly fill the switch's shallow buffer, directly inducing a hardware-level PFC (Priority Flow Control) pause frame storm, causing a precipitous drop in RDMA throughput, and even leading to deadlock.

[0004] Second, continuous back-to-back transmissions greatly increase the likelihood of FEC failure under micro-burst conditions. Wide area network packet loss often exhibits continuous micro-burst characteristics. Existing mechanisms typically transmit the original data packet and its generated redundant packet tightly contiguously in the network interface card's (NIC) transmission queue (back-to-back). Once the link encounters micro-burst congestion, the data packet and the redundant packet providing protection will be completely discarded, resulting in a loss of rank in the error correction matrix and rendering the FEC mechanism completely ineffective.

[0005] This method mainly operates on the RDMA transport layer protocol stack of the end-side software or hardware, aiming to solve the problems of limited throughput, retransmission storms and congestion collapse of RDMA in lossy network environments from the perspective of rigorous mathematical analysis and underlying physical hardware timing execution. Summary of the Invention

[0006] The problem this invention aims to solve is how to establish an objective mathematical derivation model in RDMA cross-WAN transmission to accurately quantify "what redundancy ratio should be used under what packet loss probability and congestion level", and how to increase the transmission interval between data packets and redundant packets from the underlying physical timing, so as to avoid the loss of data packets and redundant packets together due to congestion caused by micro-bursts.

[0007] This invention proposes a reliable transmission method for RDMA cross-WAN transmission. This method abandons the blind trial-and-error configuration approach used in engineering, derives a deterministic analytical solution formula based on probability theory and queuing theory, and performs padding time-domain interleaving in conjunction with the delay injection mechanism of the underlying transmission queue.

[0008] The main steps of this method are as follows:

[0009] Step 1: Establish an end-to-end RDMA transport layer connection. Define the data stream submitted by the sending application layer as being sequentially divided into fixed-length data blocks, each containing... One raw data packet. The protocol stack probes and obtains the physical state of the current WAN link. Input: basic physical packet loss rate. Average duration of micro-burst packet loss And the current transmit queue depth at the underlying layer of the RDMA network card or switch. and the waterline threshold for trigger priority flow control (PFC) pause frames And establish the physical transmission time of a single packet. .

[0010] Step 2: Calculation and memory allocation of dynamic forward error correction redundancy lower limit based on real-time physical packet loss rate. To establish the optimal protection baseline under the current network conditions and prepare underlying computing resources, the sending protocol stack performs the following sub-operations:

[0011] Step 2-1: Link State Extraction and Algebraic Expectation Instruction Calculation. The encoding management module of the sending end protocol stack reads the basic physical packet loss rate obtained in Step 1 from the connection context of the current queue pair (QP). The central processing unit (CPU) calls the standard arithmetic logic unit (ALU) to process the... Substituting the preset binomial probability function, calculate the minimum theoretical number of redundant packets required to satisfy the full rank of the receiver's error correction matrix under the current channel conditions. The calculation formula is:

[0012]

[0013] in, To ensure a safety margin for decoding full rank, and This operation transforms the macroscopic probability of packet loss in the link into a precise numerical benchmark within the protocol stack through a basic arithmetic instruction stream.

[0014] Step 2-2: Zero-copy allocation of the memory pool based on the redundancy lower bound. To avoid latency jitter introduced by dynamic memory allocation, the protocol stack pre-allocates and registers a memory region (MR) with direct memory access (DMA) permissions in the host memory as a memory pool with the RDMA network card. The protocol stack's memory management module allocates memory based on the calculated lower bound. The numerical value is directly delineated from the circular buffer structure of the pre-registered memory pool, and a contiguous memory block of the corresponding capacity is used as the redundancy matrix calculation buffer area for the current data block.

[0015] Step 2-3: Initialization of the data structure for the error correction generation matrix. After the buffer area is defined, the encoding scheduling module initializes the data structure based on the number of original data packets. With the number of redundant packets The dimension parameters are used to initialize the forward error correction generator matrix in the allocated memory space. This operation completes the addressing preparation at the data structure level of the core algorithm.

[0016] Step 3: Calculation of congestion penalty coefficient and state registration based on hardware transmit queue level. To prevent hardware-level deadlock caused by redundant traffic introduced by FEC, the sender protocol stack performs the following cross-layer collaborative operations:

[0017] Step 3-1: Nonlinear mapping calculation of hardware water level ratio. The congestion awareness module of the sending end protocol stack uses the sending queue depth obtained in Step 1. With the waterline threshold Calculate the relative saturation of the current physical cache. Subsequently, the processor invokes the floating-point unit (FPU) to execute operations based on the natural base. The exponential decay algorithm is calculated using the following formula:

[0018]

[0019] in, The attenuation slope factor, For curvature control parameters, and This operation quantifies the backlog state of physical hardware through nonlinear curve fitting.

[0020] Step 3-2: Connection context registration for dynamic control weights. The protocol stack will calculate the penalty coefficient. The value is written in real-time to the control domain of the connection context in the current processing cycle. This weight serves as a global state variable, indicating the current underlying channel's resistance to carrying additional redundant payloads.

[0021] Step 3-3: Establishment of a cross-level "software-hardware mapping" feedback mechanism. When the sending queue depth... When the water level is low, the penalty coefficient As the value approaches 1, the system maintains full redundancy in its distribution; with Approaching the waterline threshold The control weight generates a nonlinear response that is forced to decay toward zero, thereby forming a virtual "physical braking signal" at the software layer to preemptively suppress the generation logic of subsequent redundant feature data.

[0022] Step 4: Dynamic Redundant Feature Packet Generation and Degradation Execution Based on Node Physical Bearing Capacity. This step is specifically divided into three sub-operations: parameter calculation and state registration, zero-redundant code bypass and memory reclamation, and redundant feature packet entity assembly.

[0023] Step 4-1: Execute instruction operations and register context state. The encoding scheduling module of the sending end protocol stack reads the minimum theoretical redundant packet count from system memory. With the penalty coefficient The arithmetic logic unit is invoked to execute multiplication instructions and round-down operations to determine the final number of redundant packets that are actually allowed to be sent within the current communication cycle. The calculation formula is:

[0024]

[0025] After completing the calculation, the protocol stack will... The value is used as a dynamic flag bit and written into the status control register of the connection context, which serves as the underlying decision input for subsequent system stream processing branches.

[0026] Step 4-2: Trigger code bypass and memory reclamation under extreme congestion conditions. The protocol stack's code scheduling flow continuously reads the state control register. When the above is detected... When the value is 0, the protocol stack determines that the queuing depth of the underlying physical network card is approaching the congestion and collapse threshold. At this time, the processor triggers a conditional branch jump instruction (Bypass) at the code execution layer, actively skipping the time-consuming Galois field matrix multiplication operation code segment in the forward error correction module; simultaneously, the memory management module sends a release instruction to the memory pool, immediately reclaiming the pre-allocated redundant matrix buffer blocks. This sub-step relinquishes all processor clock cycles and main memory space to the forwarding and scheduling of the core service's raw data stream.

[0027] Step 4-3: Perform algebraic coding and entity message construction under normal conditions. When the protocol stack detects the... When the value is greater than 0, the encoding scheduling module uses the memory pointer maintained within the system to set the corresponding value. The payload of each raw data packet is loaded into the processor's cache, a generator matrix is ​​constructed, and algebraic operations are performed to generate... The system generates a set of redundant check data segments. Subsequently, it allocates and encapsulates network packet headers and checksums for each set of check data segments, completes the construction of the redundant feature data packet entity, and submits it to the subsequent physical transmission scheduling module.

[0028] Step 5: Redundancy packet isolation parameter conversion based on physical medium delay characteristics. To ensure that the generated redundant characteristic data packets can safely traverse the contiguous packet loss intervals caused by micro-bursts in the wide area network, this step specifically includes the following sub-operations:

[0029] Step 5-1: Discretization mapping of the congestion time window. The sending end protocol stack extracts the average duration of the detected micro-burst packet loss. Compared with the physical transmission time of the single packet The scheduling module will... Divide by And perform the floor operation, that is, calculate This operation discretizes the congestion time into the maximum number of packet slots that can be continuously consumed.

[0030] Step 5-2: Eliminate jitter compensation and derive absolute delay. The protocol stack introduces a preset interval packet count constant. ( An addition operation is performed to absorb wide area network tail jitter. Then, the compensated total number of packets is compared with the stated... Multiply by this to calculate the safe time interval for redundant data packets. The formula is defined as:

[0031]

[0032] Step 5-3: Dimensional conversion of the underlying hardware clock cycle. The protocol stack will calculate the security time interval. The time dimension is converted into discrete tick cycles that are adapted to the high-precision clock of the underlying network card hardware or into hardware rate limit register parameters, providing instruction input for subsequent direct physical delay.

[0033] Step 6: Time-domain interleaving injection and self-healing decoding based on the underlying network interface card (NIC) transmit queue descriptor. This step specifically includes the following sub-operations:

[0034] Step 6-1: Descriptor delivery of the raw data stream. The sending end protocol stack reconstructs the delivery timing of the work queue elements (WQEs), and continuously writes the descriptors corresponding to the data stream to the ring buffer of the host-side send queue. Sending descriptor for each raw data packet.

[0035] Step 6-2: Hardware-level clock suspension instruction injection. During the execution gap between the descriptors of the original data stream and the redundant data stream, the protocol stack loads a no-operation (NOP) descriptor carrying the clock tick cycle parameter calculated in step 5-3 into the circular buffer, or writes the corresponding network card rate limiting register control instruction. The network card's DMA engine sequentially fetches descriptors and performs packet sending operations, forcibly executing a physical suspension for the corresponding clock cycle when encountering the no-operation descriptor.

[0036] Step 6-3: Redundant message staggered transmission and receiver decoding. After the underlying hardware clock wakes up, the protocol stack loads the... The system sends a descriptor for each redundant data packet and triggers a doorbell mechanism on the network interface card (NIC) to inject redundant packets into the physical link. The delayed redundant packets fall into the network clearing period after micro-burst congestion. Upon receiving the packets, the receiver directly performs inverse matrix decoding, achieving effective self-healing of data blocks.

[0037] Compared with the prior art, the advantages of the present invention are as follows:

[0038] 1) This solution achieves adaptive coordination between the underlying hardware congestion state and the forward error correction mechanism at the transport layer, effectively avoiding system deadlock and significantly reducing unnecessary computing power overhead. Existing technologies, when congestion occurs in a wide area network, blindly inject redundant packets at a fixed ratio, which further exacerbates the backlog in the switch buffer, easily triggering a Priority Flow Control (PFC) pause frame storm and system deadlock. This invention uses the queue backlog level of the physical network card as a feedback control quantity for the protocol stack to dynamically adjust the redundancy strategy; when the network queuing depth approaches the congestion threshold, the system actively stops generating redundant feature packets. This mechanism not only cuts off the secondary impact of redundant traffic on congested nodes from the physical link, but also releases the CPU and memory buffer resources occupied by the invalid error correction matrix operation on the host side, thereby maximizing the effective forwarding bandwidth of core service flows under extreme congestion conditions.

[0039] 2) This scheme constructs a hardware-level nanosecond timing isolation mechanism based on underlying network interface card (NIC) descriptor scheduling, achieving zero-retransmission self-healing in micro-burst packet loss scenarios. Addressing the technical deficiency that micro-burst packet loss in wide area networks often results in the simultaneous discarding of both the original packet and the immediately following redundant packet, this invention overcomes the problem of coarse-grained rate limiting in traditional operating system software. By quantifying the actual micro-burst lifecycle and converting it into discrete tick periods of a high-precision hardware clock, no-operation instructions are directly injected into the work queue element (WQE) of the NIC's circular buffer, or the hardware rate limiter is invoked. The aforementioned underlying time-domain interleaving operation effectively isolates the delayed redundant packets from the original packets in physical timing, allowing them to cross the congestion and packet loss window of the physical link at off-peak times. The receiving end can directly complete the inverse matrix decoding using the redundant packets arriving at off-peak times, avoiding triggering the time-consuming RDMA end-to-end retransmission mechanism and significantly reducing the average flow completion time (FCT).

[0040] 3) This scheme provides a lightweight, reliable transmission architecture that combines no out-of-band probe overhead with strict zero-copy characteristics. During the link state awareness phase, this invention directly reuses the out-of-order characteristics of native RDMA response messages and the status of local physical registers to obtain congestion information, avoiding the additional bandwidth occupation of traditional out-of-band probes. During the memory scheduling phase, based on dynamically calculated redundancy benchmarks, a buffer area is directly allocated in the pre-registered memory pool, ensuring that the entire process of algebraic coding and data delivery strictly adheres to the zero-copy characteristic of RDMA. This scheme achieves highly reliable cross-domain error-correcting transmission while fully maintaining the underlying architectural advantages of RDMA technology, namely low CPU consumption and low memory bandwidth usage. Attached Figure Description

[0041] Figure 1 This is a flowchart illustrating a reliable transmission method for RDMA cross-wide area network transmission provided in an embodiment of the present invention;

[0042] Figure 2 This is a diagram of the FEC redundancy expectation model calculation framework and time-domain interleaving system architecture in an embodiment of the present invention.

[0043] Figure 3 This is a comparison diagram of traditional continuous transmission and Pacing time-domain interleaving to resist micro-burst packet loss in an embodiment of the present invention;

[0044] Figure 4 This is a performance comparison chart of the relationship between average flow completion time and link packet loss rate under different FEC mechanisms in this embodiment of the invention;

[0045] Figure 5 This is a comparison chart showing the effective throughput changes of the Pacing time-domain interleaving mechanism and the traditional mechanism in the case of micro-burst packet loss in this embodiment of the invention. Detailed Implementation

[0046] To enhance understanding of the present invention, the embodiments will be described in detail below with reference to the accompanying drawings.

[0047] Example: Combining Figure 1 The method flowchart shown and Figure 2 The FEC redundancy expectation model calculation framework and time-domain interleaved system architecture diagram shown are illustrated. A reliable transmission method for RDMA cross-WAN transmission is presented, and its specific implementation process, as a complete method embodiment, includes the following steps:

[0048] Step 1: Establish an end-to-end RDMA transport layer connection; sequentially divide the data stream submitted by the sending application layer into fixed-length data blocks, each data block containing... One raw data packet; the protocol stack probes and obtains the physical state input of the current WAN link: basic physical packet loss rate. Average duration of micro-burst packet loss And the current transmit queue depth at the underlying layer of the RDMA network card or switch. and trigger priority flow control pause frame waterline threshold And establish the physical transmission time of a single packet. .

[0049] Specifically, in the scenario of RDMA interconnection across wide area networks, this embodiment designs a bypass state detection module at the RDMA transport layer. For queue state acquisition, the transmitting protocol stack directly addresses and reads the hardware status register of the local RDMA network card through the memory-mapped input / output (MMIO) mechanism to extract the descriptor backlog value actually mounted in the current transmitting queue as the transmitting queue depth. Simultaneously, the waterline threshold is obtained by reading the network card or preset configuration register. Based on this, and combined with the link relay node buffer occupancy rate fed back by the receiving end through Congestion Notification Messages (CNP), cross-level perception of physical link congestion levels is achieved. and The duration of a micro-burst event is estimated by using the packet sequence number characteristics in the acknowledgment (ACK) message returned by the receiver. When consecutive sequence numbers are missing, the amount of data corresponding to the missing window is divided by the link line speed and recorded as the duration of one micro-burst event. Then, the exponentially weighted moving average (EWMA) algorithm is used to smooth multiple events to filter out high-frequency jitter noise, thereby obtaining the statistically significant average duration. The specific formula for the Exponentially Weighted Moving Average (EWMA) is as follows:

[0050]

[0051] in A smoothing factor (typically between 0.125 and 0.25) is used to filter out high-frequency network jitter noise while preserving the congestion trend. Additionally, the physical transmission time of a single packet is also considered. The protocol stack is based on the line speed bandwidth of the current physical link. With the maximum transmission unit size Establish the serialization delay of the message on the physical medium:

[0052]

[0053] This serves as the basis for the discrete-time scale of subsequent underlying physical scheduling.

[0054] Step 2: Calculation of the redundancy lower limit for dynamic forward error correction based on real-time physical packet loss rate and memory allocation.

[0055] Step 2-1: Link State Extraction and Algebraic Expectation Instruction Calculation. The encoding management module of the sending end protocol stack reads the obtained basic physical packet loss rate from the connection context of the current queue pair. The central processing unit calls the arithmetic logic unit to process the... Substituting the preset binomial probability function, calculate the minimum theoretical number of redundant packets required to satisfy the full rank of the receiver's error correction matrix under the current channel conditions. The calculation formula is:

[0056]

[0057] in, To ensure a safety margin for decoding full rank, and .

[0058] Step 2-2: Zero-copy allocation of memory pool based on redundancy lower bound. The sending end protocol stack pre-allocates a memory region with direct memory access permissions in the host memory and registers it with the RDMA network card as a memory pool; the encoding management module allocates memory pools based on the calculated redundancy lower bound. The numerical values ​​are directly derived from the pre-registered circular buffer structure of the memory pool, and a contiguous memory block of corresponding capacity is delineated as the redundancy matrix calculation buffer area for the current business data block.

[0059] Step 2-3: Initialization of the data structure for the error correction generation matrix. After the buffer area is defined, the encoding management module initializes the data structure based on the number of original data packets. With the number of redundant packets The dimension parameters are used to initialize the forward error correction generator matrix in the allocated memory space.

[0060] Specifically, this calculation process establishes a mathematical expectation based on the algebraic properties of forward error correction: to achieve data self-healing, the receiving end only needs to contain redundant packets. Successfully received any message Each independent message (i.e., the total number of packets sent) The decoding matrix satisfies the full-rank condition. At a base packet loss rate of... In a given channel, the expected number of messages arriving at the receiver should satisfy the following:

[0061]

[0062] The theoretical minimum redundancy lower bound is derived through simplification and derivation:

[0063]

[0064] Based on this mathematical expectation model, this step further introduces a constant. To compensate for random fluctuations in network packet loss, a rounding-up function is used to ensure the discrete legitimacy of physical packet transmission. Buffer blocks are directly allocated based on memory regions pre-registered with the network card, avoiding latency jitter introduced by dynamic memory allocation via the operating system kernel. This ensures that subsequent data interaction during error correction coding strictly adheres to the zero-copy characteristics of RDMA.

[0065] Step 3: Calculate the congestion penalty coefficient and register the status based on the hardware sending queue level.

[0066] Step 3-1: Nonlinear mapping calculation of hardware water level ratio. The congestion awareness module of the transmitting end protocol stack utilizes the transmitting queue depth. With the waterline threshold Calculate the relative saturation of the current physical cache. Subsequently, the processor calls the floating-point unit to execute operations based on the natural base. The exponential decay algorithm is used to calculate the congestion resistance penalty coefficient. The formula is:

[0067]

[0068] in, The attenuation slope factor, For curvature control parameters, and ;

[0069] Step 3-2: Connection context registration for dynamic control weights. The protocol stack will calculate the penalty coefficient. Write the queue to the control domain of the connection context in real time during the current processing cycle;

[0070] Step 3-3: Establishment of a cross-level "software-hardware mapping" feedback mechanism. When the sending queue depth... When the water level is low, the penalty coefficient As the value approaches 1, the system maintains full redundancy in its distribution; with Approaching the waterline threshold The control weight generates a non-linear response that is forced to decay toward 0, thus preemptively suppressing the generation logic of subsequent redundant feature data.

[0071] Specifically, this step constructs a queuing theory-based suppression model, exhibiting differentiated constraint performance for different link congestion levels: when the network load is light, the system allows the transmission of theoretically required redundant packets; when the queue level crosses the moderate congestion range, ... It exhibits a downward decay, actively suppressing redundant data injection; when the queuing level approaches or reaches the congestion threshold... The non-linear exponential decay occurs and approaches 0, actively cutting off the bandwidth occupied by additional protection messages to prevent triggering secondary congestion and collapse.

[0072] Step 4: Generate and degrade dynamic redundant feature packets based on node physical carrying capacity.

[0073] Step 4-1: Execute instruction operations and register context state. The encoding scheduling module of the sending end protocol stack reads the minimum theoretical redundant packet count from system memory. With the penalty coefficient The arithmetic logic unit is invoked to execute multiplication instructions and round-down operations to determine the final number of redundant packets that are actually allowed to be sent within the current communication cycle. The calculation formula is:

[0074] ,

[0075] After completing the calculation, the sending protocol stack will... The value is used as a dynamic flag bit and written into the status control register of the connection context;

[0076] Step 4-2: Trigger code bypass and memory reclamation under extreme congestion conditions. The code scheduling stream of the sending protocol stack continuously reads the state control register; when the state control register is detected... When the value is 0, the sending end protocol stack determines that the queuing depth of the underlying physical network card is approaching the congestion and collapse threshold, triggers a conditional branch jump instruction, and skips the matrix multiplication operation code segment in the forward error correction module; at the same time, it sends a release instruction to the memory pool to immediately reclaim the pre-allocated redundant matrix buffer block.

[0077] Step 4-3: Perform algebraic coding and entity message construction under normal conditions. When the above is detected... When the value is greater than 0, the corresponding memory pointer is used according to the memory pointer maintained within the system. The payload of each raw data packet is loaded into the processor's cache, a generator matrix is ​​constructed, and algebraic operations are performed to generate... The system generates a set of redundant check data segments. Subsequently, it allocates and encapsulates network packet headers and checksums for each generated set of check data segments, completes the construction of the redundant feature data packet entity, and submits it to the physical transmission scheduling module.

[0078] Specifically, in combination Figure 4 The chart showing the performance comparison of average flow completion time and link packet loss rate under different FEC mechanisms illustrates that, in the absence of theoretical support, the traditional static FEC mechanism is prone to exponential divergence in retransmission delay due to redundancy exhaustion when the packet loss rate deteriorates. In contrast, this embodiment calculates the actual optimal number of redundant packets based on an analytical solution model. With the corresponding code bypass mechanism, the average flow completion time can be stably controlled at a low level under various severe packet loss conditions, ensuring the forwarding of core business flows.

[0079] Step 5: Calculation of redundant message isolation parameters based on physical medium delay characteristics.

[0080] Step 5-1: Discretization mapping of the congestion time window. The sending end protocol stack extracts the average duration of the micro-burst packet loss. Compared with the physical transmission time of the single packet The above Divide by And perform the round-up operation to calculate ;

[0081] Step 5-2: Derivation of jitter compensation and absolute delay. Introduce a preset interval packet count constant. and Perform addition; then, combine the compensated total number of packages with the stated... Multiply by this to calculate the safe time interval for redundant data packets. The formula is defined as:

[0082]

[0083] Step 5-3: Dimensional conversion of the underlying hardware clock cycle. Convert the aforementioned security time interval... The time dimension is converted into discrete tick period values ​​or hardware rate limit register parameters that are adapted to the underlying network card hardware clock.

[0084] Specifically, for the transmission time of a single packet on the physical link, the protocol stack determines the serialization delay of the message on the physical medium based on the line-rate bandwidth and the maximum transmission unit size. As a fundamental discrete-time scale. Due to the average microburst duration In a physical sense, this represents the "congestion lifecycle" of a switch's buffer overflow. If packets are sent consecutively within this time window, all packets within this period will be indiscriminately consumed. Therefore, the protocol stack must accurately derive the expected number of consecutive packets that need to be avoided across this lifecycle. The round-up operation maps micro-burst congestion time to the expected number of slots of packets that are most likely to be dropped consecutively. (Constant) This is used to absorb tail jitter and emptying delay present in real wide area networks, thereby constructing a rigid physical time isolation boundary, which decouples the original data stream from the redundant data stream in the time domain.

[0085] Step 6: Time-domain interleaving injection and self-healing decoding based on the underlying network card's transmit queue descriptor.

[0086] Step 6-1: Descriptor distribution of the raw data stream. The sending end protocol stack reconstructs the distribution sequence of work queue elements, continuously writing the descriptors corresponding to the original data stream into the circular buffer of the sending queue. The send descriptor for each raw data packet;

[0087] Step 6-2: Hardware-level clock suspension instruction injection. During the execution gap between the send descriptors of the original data stream and the redundant data stream, a no-operation descriptor carrying the discrete tick cycle value is loaded into the circular buffer, or the corresponding network card rate limiting register control instruction is written; the network card's direct memory access engine sequentially fetches descriptors and executes packet sending actions, and when the no-operation descriptor is encountered, a physical suspension of the corresponding clock cycle is forcibly executed;

[0088] Step 6-3: Redundant message staggered transmission and receiver decoding. After the underlying hardware clock wakes up, the [process / function] is loaded. The redundant characteristic data packet is sent as a descriptor and triggers the doorbell mechanism of the network card to inject redundant packets into the physical link; the redundant packets that are delayed in transmission fall into the network clearing period after micro-burst congestion, and the receiving end directly performs inverse matrix decoding after collecting the packets.

[0089] Specifically, in combination Figure 3 The comparison chart shown is Figure 5 The comparison chart of effective throughput changes shows that in traditional continuous transmission mechanisms, when encountering intermittent micro-burst congestion, both the preceding original packets and the immediately following redundant packets, which are closely connected in time, are easily dropped simultaneously into the congestion window, leading to FEC failure and a sharp drop in throughput. This embodiment transparently injects a virtual waiting period into the descriptor linked list through the above steps. During this period, the transmission of the current data stream is physically suspended but does not occupy host CPU computation cycles. This underlying delay barrier allows the delayed redundant packets to fall into the emptying phase of the network buffer at off-peak times. The receiving end can recover data blocks using algebraic inverse matrix operations without triggering the time-consuming RDMA end-to-end retransmission mechanism, achieving data self-healing and stable throughput performance in micro-burst packet loss scenarios.

[0090] It should be noted that the above embodiments are not intended to limit the scope of protection of the present invention. Equivalent transformations or substitutions made based on the above technical solutions all fall within the scope of protection of the claims of the present invention.

Claims

1. A method for reliable transport for RDMA across a wide area network transport, the method comprising: Includes the following steps: Step 1: Establish an end-to-end connection, obtain the physical state variables of the WAN link and the underlying hardware transmission queue status information, and determine the physical transmission time of a single packet. Step 2: Calculate the theoretical redundancy lower limit that meets the decoding requirements based on the physical packet loss rate, and allocate a redundancy matrix calculation buffer area in the host-side memory. Step 3: Calculate the congestion penalty coefficient based on the ratio of hardware queue depth to waterline threshold, and map the hardware backlog state to a braking signal in the transport layer. Step 4: Combine the redundancy lower limit and penalty coefficient to determine the final actual number of redundant packets, and perform error correction coding operations or trigger code bypass execution accordingly. Step 5: Calculate the redundant message isolation delay parameters based on the micro-burst duration, and convert them into physical control commands adapted to the underlying hardware clock. Step 6: Reconstruct the timing of sending descriptors and inject physical suspend commands between the original and redundant packets to achieve staggered transmission of redundant packets.

2. The method of claim 1, wherein, The specific process of step 1 is as follows: Establish an end-to-end RDMA transport layer connection; sequentially divide the data stream submitted by the sending application layer into fixed-length data blocks, each data block containing... One raw data packet; the protocol stack probes and obtains the physical state input of the current WAN link: basic physical packet loss rate. Average duration of micro-burst packet loss And the current transmit queue depth at the underlying layer of the RDMA network card or switch. and trigger priority flow control pause frame waterline threshold And establish the physical transmission time of a single packet. .

3. The reliable transmission method for RDMA cross-wide area network transmission according to claim 2, characterized in that, Step 2 is as follows: Step 2-1: Link state extraction and algebraic expectation instruction calculation. The encoding management module of the sending end protocol stack reads the basic physical packet loss rate from the connection context of the current queue pair. ; The central processing unit calls the arithmetic logic unit to... Substituting the preset binomial probability function, calculate the minimum theoretical number of redundant packets required to satisfy the full rank of the receiver's error correction matrix under the current channel conditions. The calculation formula is: in, To ensure a safety margin for decoding full rank, and , This represents the original number of data packets; Step 2-2: Zero-copy allocation of memory pool based on redundancy lower bound. The sending end protocol stack pre-allocates a memory region with direct memory access permissions in the host memory and registers it with the RDMA network card as a memory pool; the encoding management module allocates memory pools based on the calculated redundancy lower bound. The numerical values ​​are directly delineated from the circular buffer structure of the pre-registered memory pool, and a continuous memory block of corresponding capacity is used as the redundancy matrix calculation buffer area for the current business data block. Steps 2-3: Initialize the data structure of the error correction generation matrix. After the buffer area is defined, the encoding management module initializes the data structure based on the number of original data packets. With the number of redundant packets The dimension parameters are used to initialize the forward error correction generator matrix in the allocated memory space.

4. The method of claim 3, wherein, Step 3 is as follows: Step 3-1: Nonlinear mapping calculation of hardware water level ratio; the congestion awareness module of the sending protocol stack utilizes the sending queue depth. With waterline threshold Calculate the relative saturation of the current physical cache. ; Subsequently, the processor invokes the floating point operation unit to perform an exponential decay algorithm based on the natural base to calculate the congestion resistance penalty coefficient , the formula is: wherein is a decay slope factor, is a curvature control parameter, and ; Step 3-2: Connection context registration with dynamic control weight value, the protocol stack will calculate the penalty coefficient Real-time writing into the control field of the connection context under the current processing cycle; Step 3-3: Establishing a cross-level "software-hardware mapping" feedback mechanism, when the sending queue depth... Penalty coefficient when at low water level As the value approaches 1, the system maintains full redundancy in its distribution; with Approaching the waterline threshold The control weights generate a non-linear response that is forced to decay toward zero, thus preemptively suppressing the generation logic of subsequent redundant feature data.

5. A reliable transmission method for RDMA cross-wide area network transmission according to claim 4, characterized in that, Step 4 is as follows: Step 4-1: Execute instruction operations and register context state. The encoding and scheduling module of the sending end protocol stack reads the minimum theoretical redundant packet count from the system memory. With penalty coefficient The arithmetic logic unit is invoked to execute multiplication instructions and round-down operations to determine the final number of redundant packets that are actually allowed to be sent within the current communication cycle. The calculation formula is: ； After completing the calculation, the sending protocol stack will determine the final number of redundant packets. The value is used as a dynamic flag bit and written into the status control register of the connection context; Step 4-2: Trigger code bypass and memory reclamation under extreme congestion conditions; the code scheduling flow of the sending protocol stack continuously reads the status control register; when detected... When the value is 0, the sending protocol stack determines that the queuing depth of the underlying physical network card is approaching the congestion and collapse threshold, triggers the conditional branch jump instruction, skips the matrix multiplication operation code segment in the forward error correction module; at the same time, it sends a release instruction to the memory pool to immediately reclaim the pre-allocated redundant matrix buffer block. Step 4-3: Perform algebraic coding and entity message construction under normal conditions. When detected... When the value is greater than 0, the corresponding memory pointer is used according to the memory pointer maintained within the system. The payload of each raw data packet is loaded into the processor's cache, a generator matrix is ​​constructed, and algebraic operations are performed to generate... Group redundancy check data segments; Subsequently, network message headers and checksums are allocated and encapsulated for each group of generated check data segments, completing the construction of redundant feature data packet entities, and submitting them to the physical transmission scheduling module.

6. The method of claim 5, wherein, Step 5 is as follows: Step 5-1: Discretization mapping of congestion time windows, extraction of the average duration of micro-burst packet loss from the sending protocol stack. Compared to the time consumed by physical transmission of a single packet ,in, This represents the transmission time of a single data packet over the physical link. Divide by And perform the floor function to calculate ; Step 5-2: Derivation of jitter compensation and absolute delay, introducing a preset interval packet number constant. and Perform the addition operation; then, combine the compensated total number of packages with... Multiply by this to calculate the safe time interval for redundant data packets. The formula is defined as: Step 5-3: Quantization conversion of the underlying hardware clock cycle, converting the safety time interval... The time dimension is converted into discrete tick period values ​​or hardware rate limit register parameters that are adapted to the underlying network card hardware clock.

7. A reliable transmission method for RDMA cross-wide area network transmission according to claim 6, characterized in that, Step 6 is as follows: Step 6-1: Descriptor of original data stream is issued, the sending end protocol stack reconstruction work queue element is issued in time sequence, and the sending descriptors corresponding to one original data packet are written into the ring buffer of the sending queue continuously; Step 6-2: Inject hardware-level clock suspension instructions. During the execution gap between the send descriptors of the original data stream and the redundant data stream, load the no-operation descriptor carrying the discrete tick cycle value into the circular buffer, or write the corresponding network card rate limit register control instruction; the network card's direct memory access engine grabs the descriptors in sequence and executes the packet sending action. When encountering a no-operation descriptor, it forcibly executes the physical suspension of the corresponding clock cycle. Step 6-3: Redundant messages are transmitted and decoded at the receiving end. After being woken up by the underlying hardware clock, the data is loaded. The redundant characteristic data packet is sent as a descriptor and triggers the doorbell mechanism of the network card, injecting redundant packets into the physical link; the delayed transmission of redundant packets falls into the network clearing period after micro-burst congestion, and the receiving end directly performs inverse matrix decoding after collecting the packets.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements a reliable transmission method for RDMA cross-wide area network transmission as described in any one of claims 1 to 7.

9. A computer-readable storage medium storing computer instructions thereon, characterized in that, When executed by the processor, the computer instructions implement a reliable transmission method for RDMA cross-wide area network transmission as described in any one of claims 1-7.

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