Method and apparatus for transmitting data packet

Abstract

This application provides a method and apparatus for transmitting data packets, relating to the field of communications, to improve the utilization of transmission resources. The method includes: encapsulating the data to be transmitted to obtain data packets; filling the encapsulated data packets into the block body of a logical block according to byte order; wherein, when FEC is enabled, the logical block includes a block body and a block tail filled with checksum data; when FEC is disabled, all bytes within the LLB are the block body.

Description

Method and device for transmitting data message Technical Field

[0001] The present application relates to the field of communications, and in particular to a method and device for transmitting data messages. Background Art

[0002] With the rapid development of communication technology, the requirements for transmission accuracy when transmitting data (business data or management data) between interconnected devices are becoming increasingly higher.

[0003] In order to ensure the accuracy of data transmission, adding verification information to the data transmission unit (the basic unit of data transmission) is widely used. However, verification information will occupy bandwidth and waste transmission resources.

[0004] Summary of the Invention

[0005] The method and device for transmitting data messages provided in the present application solve the problem of fixed occupation of transmission resources by verification information, thereby improving the utilization rate of transmission resources.

[0006] To achieve the above objectives, the present invention adopts the following technical solutions:

[0007] In a first aspect, a method for transmitting a data message is provided, which may include: packetizing the data to be transmitted to obtain a data message; filling the encapsulated data message into a block body of a logical layer block (LLB) in byte order; wherein, when forward error correction (FEC) is enabled, the logical block includes a block body and a block tail filled with check data; when FEC is not enabled, all bytes in the LLB are block bodies.

[0008] The solution provided in this application can enable or disable FEC as needed by configuring a flexible LLB structure, so that when the link transmission quality meets the requirements, FEC is not enabled to avoid the verification data occupying transmission resources. When the link transmission quality is insufficient, FEC is enabled on demand to improve the link transmission quality, taking into account both transmission resource utilization and link quality.

[0009] In one possible implementation, when FEC is enabled, the method provided in this application may further include: evenly arranging the 240 bytes of the LLB into five Reed-Solomon (RS) blocks in byte order, with each RS block corresponding to an RS coding work area, and each RS coding work area containing 46 bytes of data and a 2-byte placeholder; encoding the 46 bytes of data in each of the five RS blocks to generate 2-byte check data, thereby obtaining five sets of RS check data; de-mapping the data in each of the five RS blocks byte by byte to the LLB in the order of the RS coding work area; after de-mapping, the first 230 bytes of the LLB block body are the same as the block body of the LLB before RS mapping, and the placeholder in the last 10 bytes of the block tail is replaced with five sets of RS check data. This implements error correction for any 1-byte data within the RS block.

[0010] Another possible implementation method, when FEC is enabled, the method provided in this application may also include: evenly arranging the 480 bytes of the LLB into 10 RS blocks in byte order, each RS block corresponds to an RS coding work area, and each RS coding work area contains 46 bytes of data and 2 bytes of placeholders; encoding the 46 bytes of data in each of the 10 RS blocks separately to generate 2 bytes of check data, thereby obtaining 10 sets of RS check data; inversely mapping the data in each of the 10 RS blocks byte by byte to the LLB in the order of the RS coding work area; after inverse mapping, the LLB block body of the first 460 bytes in the LLB is the same as the block body of the LLB before RS mapping, and the placeholder in the last 20 bytes of the block tail is replaced with 10 sets of RS check data. This implements error correction for any 1-byte data in the RS block.

[0011] In another possible implementation, the 2-byte check data is obtained by RS (48, 46) encoding based on Galois Fields (GF) (256).

[0012] Another possible implementation is to use the full channel bandwidth for transmission. A single LLB is distributed across multiple lanes for transmission, and all data uses the same RS encoder and decoder, improving encoding and decoding efficiency and reducing transmission latency.

[0013] In another possible implementation, the data to be transmitted includes: logical layer management messages and transport layer data, and the data packets include: logical layer main link management packets (Logical Layer Main Link Management Packet, LLMMP) and logical layer data packets (Logical Layer Data Packet, LLDP).

[0014] In another possible implementation, the logic block includes at most two logic layer management messages.

[0015] Another possible implementation is to first fill the logical layer management message in the LLB and then fill the logical layer data message to ensure the timeliness of link management.

[0016] In another possible implementation, the LLB includes a logical layer data message to improve the transmission efficiency of business data.

[0017] In a second aspect, another method for transmitting a data message is provided. The method includes: receiving an LLB, wherein when FEC is enabled, the logical block includes a block body for filling the data message and a block trailer for filling check data; when FEC is disabled, all bytes in the LLB constitute the block body. If FEC is enabled, after checking and correcting the data in the block body and the check data in the block trailer of the LLB, the LLB is parsed to obtain the data message encapsulated in the LLB.

[0018] Through the solution provided in this application, by configuring a flexible LLB structure, FEC can be enabled or disabled according to demand, so that when the link transmission quality meets the requirements, FEC is not enabled to avoid the verification information occupying transmission resources. When the link transmission quality is insufficient, FEC is enabled on demand to improve the link transmission quality, taking into account both transmission resource utilization and link quality.

[0019] One possible implementation, when FEC is enabled, performs checksum and error correction on the data in the LLB block body and the check data in the block footer. This includes: evenly distributing the 240 bytes of the LLB into five RS blocks in byte order, with each RS block corresponding to an RS decoding workspace containing 46 bytes of data and 2 bytes of check data; performing checksum and error correction on the 48 bytes of data and check data in each of the five RS blocks; de-mapping the data in each of the five RS blocks byte by byte into the LLB in the order of the RS decoding workspaces; replacing the first 230 bytes of the LLB block body with the checked and corrected block body after de-mapping, and disusing the check data in the last 10 bytes of the block footer. This allows for error correction of any 1-byte data within the RS block.

[0020] Another possible implementation, when FEC is enabled, performs checksum and error correction on the data in the LLB block body and the check data in the block footer. This includes: evenly distributing the 480 bytes of the LLB into 10 RS blocks in byte order, with each RS block corresponding to an RS decoding workspace containing 46 bytes of data and 2 bytes of check data; performing checksum and error correction on the 48 bytes of data and check data in each of the 10 RS blocks; de-mapping the data in each of the 10 RS blocks byte by byte into the LLB in the order of the RS decoding workspaces; replacing the first 460 bytes of the LLB block body with the checked and corrected block body after de-mapping, and disusing the check data in the last 20 bytes of the block footer. This allows for error correction of any 1-byte data within the RS block.

[0021] Another possible implementation of the above-mentioned verification and error correction includes: using GF(256)-based RS(48,46) decoding to perform verification and error correction.

[0022] In another possible implementation, the method provided in the present application may further include: if FEC is not enabled, parsing the LLB to obtain the data message encapsulated in the LLB.

[0023] Another possible implementation is to use the full channel bandwidth for LLB transmission. A single LLB is distributed across multiple lanes for transmission, and all data uses the same RS encoder and decoder, improving encoding and decoding efficiency and reducing transmission latency.

[0024] In another possible implementation, the data message includes: LLMMP and LLDP.

[0025] In another possible implementation, the LLB includes at most two logical layer management messages.

[0026] Another possible implementation is to fill the LLB with the logical layer management message first and then with the logical layer data message.

[0027] In another possible implementation, the LLB includes a logical layer data message.

[0028] In a third aspect, a device for transmitting data packets is provided, the device comprising: a packaging unit and a filling unit.

[0029] The packetizing unit is used to perform packet processing on the data to be transmitted to obtain a data message.

[0030] The padding unit is used to fill the data message obtained from the packet unit into the block body of the LLB in byte order. When FEC is enabled, the logical block includes the block body and the block trailer used to fill the check data. When FEC is disabled, all bytes in the LLB are the block body.

[0031] In another possible implementation, when FEC is enabled, the device further includes an encoding unit configured to: evenly distribute the 240 bytes of the LLB into five RS blocks in byte order, with each RS block corresponding to an RS coding work area, each RS coding work area containing 46 bytes of data and a 2-byte placeholder; encode the 46 bytes of data in each of the five RS blocks to generate 2-byte check data, thereby obtaining five sets of RS check data; and de-map the data in each of the five RS blocks byte by byte into the LLB in the order of the RS coding work areas; after de-mapping, the first 230 bytes of the LLB block are identical to the LLB block before RS mapping, and the placeholder in the last 10 bytes of the block tail is replaced with five sets of RS check data. This enables error correction of any 1-byte data within the RS block.

[0032] In another possible implementation, when FEC is enabled, the device further includes an encoding unit configured to: evenly distribute the 480 bytes of the LLB into 10 RS blocks in byte order, with each RS block corresponding to an RS encoding work area, each RS encoding work area containing 46 bytes of data and a 2-byte placeholder; encode the 46 bytes of data in each of the 10 RS blocks to generate 2-byte check data, resulting in 10 sets of RS check data; and de-map the data in each of the 10 RS blocks byte by byte to the LLB in the order of the RS encoding work areas; after de-mapping, the LLB block body of the first 460 bytes within the LLB is the same as the LLB block body before RS mapping, and the placeholder in the last 20 bytes of the block tail is replaced with 10 sets of RS check data. This enables error correction of any 1-byte data within the RS block.

[0033] In another possible implementation, the 2-byte check data is obtained by RS(48,46) encoding based on GF(256).

[0034] Another possible implementation is to use the full channel bandwidth for transmission. A single LLB is distributed across multiple lanes for transmission, and all data uses the same RS encoder and decoder, improving encoding and decoding efficiency and reducing transmission latency.

[0035] In another possible implementation, the data to be transmitted includes: a logical layer management message and transport layer data, and the data message includes: LLMMP and LLDP.

[0036] In another possible implementation, the logic block includes at most two logic layer management messages.

[0037] Another possible implementation is to fill the LLB with logical layer management messages first and then with logical layer data messages, to ensure timely link management.

[0038] In another possible implementation, the LLB includes a logical layer data message to improve the transmission efficiency of business data.

[0039] It should be noted that the device for transmitting data packets provided in the third aspect is used to implement the method for transmitting data packets provided in the above-mentioned first aspect or any possible implementation method. Its specific implementation can refer to the first aspect or any possible implementation method of the first aspect, and will not be repeated here.

[0040] In a fourth aspect, another device for transmitting data messages is provided, the device comprising: a receiving unit and a processing unit.

[0041] The receiving unit receives the LLB. When FEC is enabled, the logical block includes a block body for filling data messages and a block tail for filling check data; when FEC is not enabled, all bytes in the LLB are block bodies.

[0042] The processing unit is configured to, if FEC is enabled, perform check and error correction on the data in the body of the LLB and the check data in the end of the block, and then parse the LLB to obtain the data message encapsulated in the LLB.

[0043] In one possible implementation, when FEC is enabled, the processing unit is specifically configured to: evenly distribute the 240 bytes of the LLB into five RS blocks in byte order, with each RS block corresponding to an RS decoding workspace containing 46 bytes of data and 2 bytes of check data; perform check and error correction on the 48 bytes of data and check data in each of the five RS blocks; de-map the data in each of the five RS blocks byte by byte to the LLB in the order of the RS decoding workspaces; and replace the first 230 bytes of the LLB with the checked and corrected block after de-mapping, disusing the check data in the last 10 bytes of the block footer. This allows for error correction of any 1-byte data within the RS block.

[0044] In another possible implementation, when FEC is enabled, the processing unit is specifically configured to: evenly distribute the 480 bytes of the LLB into 10 RS blocks in byte order, with each RS block corresponding to an RS decoding workspace containing 46 bytes of data and 2 bytes of check data; perform check and error correction on the 48 bytes of data and check data in each of the 10 RS blocks; de-map the data in each of the 10 RS blocks byte by byte to the LLB in the order of the RS decoding workspaces; and replace the first 460 bytes of the LLB with the checked and corrected block after de-mapping, disusing the check data in the last 20 bytes of the block footer. This allows for error correction of any 1-byte data within the RS block.

[0045] Another possible implementation of the above-mentioned verification and error correction includes: using GF(256)-based RS(48,46) decoding to perform verification and error correction.

[0046] In another possible implementation, the processing unit is further configured to: if FEC is not enabled, parse the LLB to obtain the data message encapsulated in the LLB.

[0047] Another possible implementation is to use the full channel bandwidth for LLB transmission. A single LLB is distributed across multiple lanes for transmission, and all data uses the same RS encoder and decoder, improving encoding and decoding efficiency and reducing transmission latency.

[0048] In another possible implementation, the data message includes: LLMMP and LLDP.

[0049] In another possible implementation, the LLB includes at most two logical layer management messages.

[0050] Another possible implementation is to fill the LLB with the logical layer management message first and then with the logical layer data message.

[0051] In another possible implementation, the LLB includes a logical layer data message.

[0052] It should be noted that the device for transmitting data packets provided in the fourth aspect is used to implement the method for transmitting data packets provided in the above-mentioned second aspect or any possible implementation method. Its specific implementation can refer to the second aspect or any possible implementation method of the second aspect, and will not be repeated here.

[0053] In a fifth aspect, a computing device is provided, which includes a memory and at least one processor, the memory being used to store a set of computer instructions; when the processor executes this set of computer instructions, the operations of the method described in the first aspect or the second aspect or any possible implementation method are performed.

[0054] In a sixth aspect, a data transmission system is provided, comprising a data sending device and / or a data receiving device. The data sending device is configured to execute the method for transmitting a data message as described in the first aspect or any possible implementation of the first aspect, and the data receiving device is configured to execute the method for transmitting a data message as described in the second aspect or any possible implementation of the first aspect. Alternatively, the data sending device comprises the device for transmitting a data message as described in the third aspect or any possible implementation of the third aspect, and the data receiving device comprises the device for transmitting a data message as described in the fourth aspect or any possible implementation of the fourth aspect.

[0055] In a seventh aspect, a chip is provided, comprising one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from a memory of an electronic device and transmit the received signals to the processors, the signals comprising computer instructions stored in the memory. When the processors execute the computer instructions, the electronic device performs the steps of the method described in the first aspect, the second aspect, or any possible implementation.

[0056] In an eighth aspect, a computer-readable storage medium is provided, comprising: computer software instructions; when the computer software instructions are executed in a computer, the computer executes the operations of the method described in the first aspect or the second aspect or any possible implementation method.

[0057] In a ninth aspect, a computer program product, when running on a computer, enables the computer to execute the operating steps of the method described in the first aspect or the second aspect or any possible implementation method.

[0058] In a tenth aspect, a chip system is provided, which includes a processor and may also include a memory, for implementing the functions in the above method. The chip system can be composed of a chip or include a chip and other discrete devices.

[0059] The solutions provided in the third to tenth aspects are used to implement the methods provided in the first or second aspects, and therefore can achieve the same beneficial effects as the first or second aspects, and will not be repeated here.

[0060] It should be noted that various possible implementations of any of the above aspects can be combined under the premise that the solutions are not contradictory. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] FIG1 is a schematic diagram of the architecture of a multimedia data transmission system provided in an embodiment of the present application;

[0062] FIG2 is a schematic diagram of the architecture of another multimedia data transmission system provided in an embodiment of the present application;

[0063] FIG3 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0064] FIG4 is a flow chart of a method for transmitting data packets provided in an embodiment of the present application;

[0065] FIG5a is a schematic flow chart of another method for transmitting data packets provided in an embodiment of the present application;

[0066] FIG5 b is a schematic flow chart of another method for transmitting data packets provided in an embodiment of the present application;

[0067] FIG6 is a schematic diagram of the structure of a logic block provided in an embodiment of the present application;

[0068] FIG7 is a schematic diagram of the structure of another logic block provided in an embodiment of the present application;

[0069] FIG8 is a schematic diagram of a sending and receiving sequence of a logic block provided in an embodiment of the present application;

[0070] FIG9 is a schematic diagram of a unified multimedia interconnection interface logical layer main link architecture provided in an embodiment of the present application;

[0071] FIG10 is a schematic structural diagram of an RS encoding work area provided in an embodiment of the present application;

[0072] FIG11 is a schematic diagram of a mapping relationship between an LLB and an RS block provided in an embodiment of the present application;

[0073] FIG12 is a schematic diagram of another mapping relationship between LLB and RS blocks provided in an embodiment of the present application;

[0074] FIG13 is a schematic diagram of a mapping relationship between an RS block and an LLB provided in an embodiment of the present application;

[0075] FIG14 is a schematic diagram of another mapping relationship between RS blocks and LLBs provided in an embodiment of the present application;

[0076] FIG15a is a schematic structural diagram of an apparatus for transmitting logical layer management messages provided in an embodiment of the present application;

[0077] FIG15b is a schematic structural diagram of another apparatus for transmitting logical layer management messages provided in an embodiment of the present application;

[0078] FIG16 is a schematic structural diagram of another apparatus for transmitting logical layer management messages according to an embodiment of the present application;

[0079] FIG17 is a structural diagram of another device for transmitting logical layer management messages provided in an embodiment of the present application. DETAILED DESCRIPTION

[0080] In the embodiments of the present application, in order to clearly describe the technical solutions of the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity or execution order, and words such as "first" and "second" do not necessarily mean different. There is no order of precedence or priority between the technical features described by "first" and "second".

[0081] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.

[0082] In the embodiments of the present application, at least one can also be described as one or more, and multiple can be two, three, four or more, which is not limited in this application.

[0083] In addition, the network architecture and scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0084] The solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0085] FIG1 illustrates a multimedia data transmission system. As shown in FIG1 , the multimedia data transmission system may include a source device 101 and a sink device 102 .

[0086] The source device 101 and the sink device 102 may be connected directly or through a routing device (this scenario is not shown in FIG. 1 ).

[0087] In the multimedia data transmission system shown in FIG1 , a source device 101 transmits multimedia data to a sink device 102 .

[0088] In one scenario, source device 101 and sink device 102 are unified multimedia interconnect devices that deploy a unified multimedia interconnect interface. The multimedia data transmission system illustrated in Figure 1 enables data exchange between unified multimedia interconnect devices. For example, high-speed signal transmission between unified multimedia interconnect devices enables bidirectional audio and video transmission, meeting the audio and video transmission needs of devices such as televisions, computers, and mobile phones.

[0089] In one scenario, either the source device 101 or the sink device 102 is a unified multimedia interconnection device deployed with a unified multimedia interconnection interface, and the other is a third-party protocol device merged with the unified multimedia interconnection, realizing data interaction between the third-party protocol device and the unified multimedia interconnection device.

[0090] In one scenario, the source device 101 may be a set-top box device. The sink device 102 may be a device with a screen. For example, the set-top box device may obtain multimedia data from a data server via a network through a router, a switch, or other network devices.

[0091] Exemplarily, the set-top box device may also be called a digital video converter box (set top box, STB), or set-top box, or other. The set-top box device is a device that connects a multimedia player device and an external signal source. This application does not limit the specific product form of the set-top box device.

[0092] The sink device 102 may be a smart TV, tablet, smart screen, or other device for receiving and playing multimedia data. This application does not limit the specific product form of the sink device 102.

[0093] In one possible implementation, the internal architecture of the multimedia data transmission system shown in FIG1 may be as shown in FIG2 . As shown in FIG2 , the source device 101 and the sink device 102 include a router and a transceiver, and the router includes an adapter and a port.

[0094] The router uses the adapter to encapsulate the data generated by the external component into a unified multimedia interconnection message, forming a unified multimedia interconnection service flow and forwarding it to the port. The port then sends it to the router of the peer device. The peer device's router obtains the unified multimedia interconnection service flow restored by the port and forwards it to the adapter for processing. The adapter processes it into data and sends it to the external component.

[0095] For example, when the end device is a third-party protocol device, the adapter in the router can be a third-party protocol adapter. The third-party protocol adapter receives third-party protocol data from the third-party protocol component, encapsulates it into a tunnel message (specifically, a unified multimedia interconnection protocol message), forms a service flow, and sends it to the corresponding port, which then forwards it to the router of the opposite device. The router of the opposite device obtains the service flow restored by the port (such as the unified multimedia interconnection service flow) and forwards it to the corresponding third-party protocol adapter for processing. The third-party protocol adapter processes it into third-party protocol data and sends it to the third-party protocol component.

[0096] In one aspect, an embodiment of the present application provides a schematic structural diagram of a computing device 30. The computing device 30 can implement the functions of the source device 101 or the sink device 102 shown in FIG. 1 or FIG. 2 .

[0097] Exemplarily, the computing device 30 may implement the functions of the source device 101 or the sink device 102 illustrated in FIG. 1 or FIG. 2 at the logic layer.

[0098] 3 , the computing device 30 may include a processor 3010 , a bus 3020 , a memory 3030 , and a communication interface 3040 . The processor 3010 , the memory 3030 , and the communication interface 3040 are connected via the bus 3020 .

[0099] It should be understood that in this embodiment, the processor 3010 may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0100] The processor 3010 may also be a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the present application.

[0101] The communication interface 3040 is used to implement communication between the computing device 30 and external devices or components.

[0102] The bus 3020 may include a path for transmitting information between the above-mentioned components (such as the processor 3010 and the memory 3030). In addition to the data bus, the bus 3020 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are labeled as bus 3020 in the figure. The bus 3020 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 3020 can be divided into an address bus, a data bus, a control bus, etc.

[0103] As an example, computing device 30 may include multiple processors. The processor may be a multi-core (multi-CPU) processor. A processor herein may refer to one or more devices, circuits, and / or computing units for processing data (e.g., computer program instructions).

[0104] It is worth noting that FIG3 only takes the computing device 30 including 1 processor 3010 and 1 memory 3030 as an example. Here, the processor 3010 and the memory 3030 are respectively used to indicate a type of device or equipment. In a specific embodiment, the number of each type of device or equipment can be determined according to business requirements.

[0105] Memory 3030 may be a volatile memory pool or a non-volatile memory pool, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0106] For example, the processor 3010 may perform the following functions by running or executing the software programs and / or modules stored in the memory 3030:

[0107] The data to be transmitted is packaged to obtain a data message; the encapsulated data message is filled into the block body of the LLB in byte order; when FEC is enabled, the logical block includes the block body and the block tail filled with check data; when FEC is not enabled, all bytes in the LLB are the block body.

[0108] For example, the processor 3010 may perform the following functions by running or executing the software programs and / or modules stored in the memory 3030:

[0109] When receiving an LLB, if FEC is enabled, the logical block consists of a body filled with data packets and a footer filled with checksum data. If FEC is disabled, all bytes in the LLB constitute the body. If FEC is enabled, the data in the body and the checksum data in the footer are checked and corrected, and then the LLB is parsed to obtain the data packet encapsulated in the LLB.

[0110] On the other hand, embodiments of the present application provide a method for transmitting data packets, which is applied to a source device 101 or a sink device 102 in the multimedia data transmission system illustrated in FIG1 or 2 , or a chip in the source device 101, or a chip in the sink device 102, to implement transmission of data packets at a logical layer. The transmitting device described below may be the source device 101 or a chip therein, and the receiving device may be the sink device 102 or a chip therein.

[0111] As shown in FIG4 , the data transmission method provided by this application may include:

[0112] S401: Packetize the data to be transmitted to obtain a data message.

[0113] The data to be transmitted may be data transmitted by the logical layer of the unified multimedia interconnection interface. The data to be transmitted may include only transport layer data (when there is no link management requirement), or the data to be transmitted may include both transport layer data and logical layer management messages (when there is a link management requirement).

[0114] The transport layer data is packaged and processed to obtain the logical layer data packet LLDP. Specifically, the transport layer data is packaged according to the LLDP structure to obtain LLDP. The embodiment of the present application does not limit the structure of LLDP and the packaging process.

[0115] The logical layer management message is packaged and processed to obtain a logical layer data message LLMMP. Specifically, the logical layer management message is packaged according to the structure of LLMMP to obtain LLMMP. The embodiment of the present application does not limit the structure of LLMMP and the packaging process.

[0116] In a possible implementation, the data to be transmitted is transport layer data of the unified multimedia interconnection interface, and the data message is LLDP.

[0117] In another possible implementation, the data to be transmitted includes: logical layer management messages and transport layer data, and the data packets include: LLMMP and LLDP.

[0118] S402: Fill the encapsulated data message into the block body of the LLB in byte order. When FEC is enabled, the logical block includes the block body and the block trailer for filling the check data; when FEC is not enabled, all bytes in the LLB are the block body.

[0119] Specifically, in S402, the data message may be filled in the LLB according to the structure of the LLB.

[0120] Exemplarily, when filling a logical block, one or more of the following rules may be satisfied: a logical block includes at most two logical layer management messages; in an LLB, the logical layer management message is filled first, followed by the logical layer data message; the LLB includes one logical layer data message.

[0121] In one possible implementation, in Type-C mode, an LLB consists of 240 bytes. When FEC is disabled, the entire 240 bytes in the LLB constitute the LLB block body. When FEC is enabled, the first 230 bytes constitute the LLB block body, and the remaining 10 bytes constitute the LLB block trailer. The LLB block body is padded with LLDP and LLMMP, and the LLB block trailer corresponds to the FEC-encoded check bytes.

[0122] In one possible implementation, in Type-B mode, an LLB consists of 480 bytes. When FEC is disabled, the entire 480 bytes in the LLB constitute the LLB block body. When FEC is enabled, the first 460 bytes constitute the LLB block body, and the remaining 20 bytes constitute the LLB block trailer. The LLB block body is padded with LLDP and LLMMP, and the LLB block trailer corresponds to the FEC-encoded check bytes.

[0123] The solution provided in the embodiment of the present application is configured with a flexible LLB structure, which can enable or disable FEC according to demand, so that when the link transmission quality meets the requirements, FEC is not enabled to avoid the verification information occupying transmission resources. When the link transmission quality is insufficient, FEC is enabled on demand to improve the link transmission quality, taking into account both transmission resource utilization and link quality.

[0124] Furthermore, after the transmitting end device executes the above S401 and S402 and fills and constructs the logic block, the logic block is transmitted in the link.

[0125] In one possible implementation, the LLB uses all channel bandwidth during transmission.

[0126] For example, the data in the LLB is evenly distributed byte by byte to all enabled channels for transmission. The distribution process can be configured according to actual needs and is not limited in the embodiment of the present application.

[0127] When the logic block is transmitted to the receiving end, the receiving end device parses it and obtains the data message therein. As shown in FIG5a, the method for transmitting data messages provided by the present application may further include S403 to S404.

[0128] S403 , receiving an LLB. When FEC is enabled, the logic block includes a block body for filling data messages and a block footer for filling check data; when FEC is not enabled, all bytes in the LLB are block bodies.

[0129] It should be noted that the LLB received in S403 may be the LLB constructed in S402, and the content of the LLB will not be described in detail here.

[0130] S404: If FEC is enabled, after checking and correcting the data in the body of the LLB and the check data in the end of the block, the LLB is parsed to obtain the data message encapsulated in the LLB.

[0131] Specifically, the scheme for performing verification and error correction in S404 depends on the scheme for generating the verification data in the LLB. The two correspond to each other and are the same encoding and decoding scheme. The embodiment of the present application does not specifically limit the encoding and decoding scheme.

[0132] The parsing process of the LLB includes: parsing the LLB according to the structure of the LLB to obtain the filled data message. The embodiment of the present application does not limit the parsing process.

[0133] Furthermore, as shown in FIG5 a , the method provided in the embodiment of the present application may further include S405 .

[0134] S405: If FEC is not enabled, parse the LLB to obtain the data message encapsulated in the LLB.

[0135] Specifically, in S405, since FEC is not enabled, the LLB is filled with data messages, and no check and error correction is required. The LLB can be directly parsed according to the structure of the LLB to obtain the filled data messages.

[0136] Furthermore, when FEC is enabled, the method for transmitting a data message provided in an embodiment of the present application further includes an FEC encoding process. As shown in FIG5b , the FEC encoding process may include steps 1 through 3 to obtain an FEC-encoded LLB, wherein the LLB footer is filled with the check data obtained by the FEC encoding.

[0137] Step 1: Perform RS mapping on the bytes in the LLB and map them into multiple RS blocks.

[0138] Among them, each RS block corresponds to an RS coding work area, and each RS coding work area contains 46 bytes of data and 2 bytes of placeholder.

[0139] A placeholder is a field that is added to the end of an LLB block before generating checksum data. The placeholder content can be configured based on actual needs or can be left empty.

[0140] For example, the placeholder may be 0x00.

[0141] In one possible implementation, when performing RS mapping in step 1, the bytes in the LLB can be arranged in sequence to multiple RS blocks in the order of the bytes in the LLB from low to high (starting from B0). When arranging the bytes in the LLB to the RS blocks, the RS work areas are polled in sequence in the order of the RS work areas corresponding to the RS blocks, and 1 byte of data in the LLB is arranged to one RS work area at a time.

[0142] Among them, the order of the RS working area is used to indicate the order in which data is arranged in the corresponding RS block. This order can be called a mapping order or other names, and the embodiments of the present application are not limited to this. In addition, the embodiments of the present application do not limit the content of the order of the RS working area, as long as the RS mapping and RS inverse mapping use the same order, that is, to ensure that a byte of data in the LLB is still in the original byte position after FEC encoding and inverse mapping back to the LLB.

[0143] For example, an LLB has 240 bytes, corresponding to 5 RS blocks, one RS block corresponds to one RS encoding work area, and the order of the 5 RS encoding work areas is from small to large. The result of arranging the 240 bytes in the LLB (data B0 to B229, placeholders RS0 to RS9) into 5 RS blocks can be: the first RS block includes B0, B5, B10...B215, B220, B225, and placeholders RS0 and RS5; the second RS block includes B1, B6, B11...B216, B221, B226, and placeholders RS1 and RS6; and so on, the fifth RS block includes B4, B8, B14...B219, B224, B229, and placeholders RS4 and RS9.

[0144] Step 2: Encode the data in each RS block to generate 2-byte check data, and obtain multiple groups of RS check data.

[0145] Specifically, in step 2, the same operation is performed on each RS block respectively.

[0146] The 46 data in a Reed-Solomon (RS) block are encoded to generate 2-byte check data, which is used as a set of RS check data. The number of sets of RS check data is the same as the number of RS blocks.

[0147] Specifically, the 2-byte check data is obtained by RS(48,46) encoding based on the Galois Field GF(256).

[0148] The primitive polynomial of RS (48, 46) coding is: p(x) = x 8 +x 4 +x 3 +x 2 +1; the generating polynomial is: g(x) = x 2 +3x+2. The specific process of RS (48, 46) encoding in this embodiment of the present application will not be described in detail.

[0149] Step 3: Inversely map the data in each RS block to the LLB byte by byte according to the RS encoding work area order.

[0150] Among them, the inverse mapping is to fill the data in the RS block back into the LLB, so that the data in the LLB is updated to the FEC-encoded data.

[0151] The order of the RS encoding workspace is described in detail in step 1 above and will not be repeated here. RS mapping and RS demapping use the same order, ensuring that a byte of data in the LLB remains in its original byte position after FEC encoding and demapping back into the LLB.

[0152] The LLB block in the LLB after inverse mapping is the same as the block of the LLB before RS mapping, and the placeholder in the last 10 bytes of the block tail is replaced by RS check data.

[0153] For example, for a Type-C port link, one LLB has a total of 240 bytes. According to the FEC encoding scheme of steps 1 to 3 above, the FEC encoding process may include:

[0154] The 240 bytes of the LLB are evenly arranged into 5 RS blocks in byte order. Each RS block corresponds to an RS coding work area. Each RS coding work area contains 46 bytes of data and 2 bytes of placeholders. The 46 bytes of data in each of the 5 RS blocks are encoded separately to generate 2 bytes of check data, and 5 sets of RS check data are obtained. According to the order of the RS coding work area, the data in each of the 5 RS blocks are reverse mapped byte by byte to the LLB. After reverse mapping, the LLB block body of the first 230 bytes in the LLB is the same as the block body of the LLB before RS mapping, and the placeholder in the last 10 bytes of the block tail is replaced by 5 sets of RS check data.

[0155] For example, for a Type-B port link, one LLB has a total of 480 bytes. According to the FEC encoding scheme of steps 1 to 3 above, the FEC encoding process may include:

[0156] The 480 bytes of the LLB are evenly arranged into 10 RS blocks in byte order. Each RS block corresponds to an RS coding work area. Each RS coding work area contains 46 bytes of data and 2 bytes of placeholders. The 46 bytes of data in each of the 10 RS blocks are encoded separately to generate 2 bytes of check data, and 10 groups of RS check data are obtained. According to the order of the RS coding work area, the data in each of the 10 RS blocks are reverse mapped byte by byte to the LLB. After reverse mapping, the LLB block body of the first 460 bytes in the LLB is the same as the block body of the LLB before RS mapping, and the placeholder in the last 20 bytes of the block tail is replaced by 10 groups of RS check data.

[0157] Furthermore, when FEC is enabled, the data in the block body of the LLB and the check data in the block tail are checked and corrected in the above S404, as shown in Figure 5b. This can be specifically implemented as the following steps a to c to obtain the LLB after FEC decoding, thereby improving the accuracy of the data in the LLB.

[0158] Step a: Perform RS mapping on the bytes in the LLB and map them into multiple RS blocks.

[0159] Each RS block corresponds to an RS decoding work area, and each RS decoding work area contains 46 bytes of data and 2 bytes of check data.

[0160] It should be noted that the order of RS mapping in step a can refer to the RS mapping in the above step 1 and will not be repeated here.

[0161] Step b: decode the data in each RS block to obtain a decoded RS block.

[0162] Specifically, in step b, the same operation is performed on each RS block respectively.

[0163] The 46 data and 2-byte check data in an RS block are decoded to obtain a decoded RS block. The decoding scheme corresponds to the encoding scheme in step 2 and is a coding and decoding scheme.

[0164] Specifically, RS(48,46) decoding based on GF(256) may be used to execute step b.

[0165] Step c: Inversely map the data in each RS block to the LLB byte by byte according to the RS encoding work area order.

[0166] Specifically, the inverse mapping is to fill the data in the RS block back into the LLB so that the data in the LLB is updated to the data after FEC decoding.

[0167] It should be noted that the order of RS inverse mapping in step C can refer to the RS mapping in the above step 1 and will not be repeated here. The difference is that the check data in the block tail is no longer used.

[0168] For example, for a Type-C port link, one LLB has a total of 240 bytes. According to the FEC decoding scheme of steps a to c above, the data in the block body and the check data in the block footer of the LLB are checked and corrected. Specifically, it can be implemented as follows:

[0169] The 240 bytes of the LLB are evenly distributed across five RS blocks in byte order. Each RS block corresponds to an RS decoding workspace, containing 46 bytes of data and 2 bytes of checksum. The 48 bytes of data and checksum in each of the five RS blocks are checked and corrected. The data in each of the five RS blocks is de-mapped byte by byte to the LLB in the order of the RS decoding workspaces. After de-mapping, the first 230 bytes of the LLB are replaced with the checked and corrected block, and the checksum data in the last 10 bytes of the block footer is no longer used.

[0170] For example, for a Type-B port link, one LLB has a total of 480 bytes. According to the FEC decoding scheme of steps a to c above, the data in the block body and the check data in the block footer of the LLB are checked and corrected. Specifically, it can be implemented as follows:

[0171] The 480 bytes of the LLB are evenly distributed across 10 RS blocks in byte order. Each RS block corresponds to an RS decoding workspace, containing 46 bytes of data and 2 bytes of check data. The 48 bytes of data and check data in each of the 10 RS blocks are checked and error-corrected. The data in each of the 10 RS blocks is de-mapped byte by byte to the LLB in the order of the RS decoding workspaces. After de-mapping, the first 460 bytes of the LLB are replaced with the checked and error-corrected block, and the check data in the last 20 bytes of the block tail is no longer used.

[0172] The above embodiment describes the process of transmitting a data message. The following examples illustrate the contents involved in the above embodiment, but do not constitute specific limitations.

[0173] The links established between devices configured with the unified multimedia interconnection interface can include the main link (ML) and the sideband link (SL). The transmission rate of the ML is higher than that of the SL.

[0174] In the unified multimedia interconnection interface, a logic block is used as a basic unit of transmission, and the logic block is filled by LLDP, or by LLMMP and LLDP. The embodiment of the present application does not limit the message structure of LLDP and LLMMP.

[0175] The following is an example of the structure of the logic block.

[0176] In TYPE-C mode, an LLB consists of 240 bytes, as shown in Figure 6. When FEC is disabled, the entire 240 bytes within the LLB constitute the LLB block body. When FEC is enabled, the first 230 bytes constitute the LLB block body, and the remaining 10 bytes constitute the LLB block trailer. The LLB block body is populated by LLDP and Logical Layer Management Messages (LLMMPs), and the LLB block trailer corresponds to the FEC-encoded check bytes. It should be noted that in the figures of the embodiments of this application, B represents a byte.

[0177] In TYPE-B mode, an LLB consists of 480 bytes, as shown in Figure 7. When FEC is disabled, the entire 480 bytes in the LLB constitute the LLB body. When FEC is enabled, the first 460 bytes constitute the LLB body, and the remaining 20 bytes constitute the LLB trailer. The LLB body is padded with LLDP and LLMMP, and the LLB trailer corresponds to the FEC-encoded check bytes.

[0178] At the electrical layer, data transmission within an LLB is sent and received byte by byte according to the LLB arrangement. By default, individual bytes are sent and received starting with the lowest bit. The LLB send and receive sequence in Type-C mode is shown in Figure 8. Byte-by-byte transmission and reception begins at bit B0. Within a single byte, transmission and reception begins at bit 0 by default. The LLB send and receive sequence in Type-B mode is similar to that in Type-C mode.

[0179] The following describes the main link architecture of the unified multimedia interconnection interface logical layer.

[0180] As shown in Figure 9, the unified multimedia interconnection interface logic layer main link architecture, at the sending end, the logic layer is responsible for multiplexing and encoding, FEC encoding, channel distribution, scrambling and precoding the data passed to it by the transport layer, and then passing it to the electrical layer; at the receiving end, the logic layer is responsible for de-precoding, descrambling, channel combination, FEC decoding and error correction, and multiplexing decoding of the data passed to it by the electrical layer, and then passing the data to the transport layer. The details are as follows:

[0181] Multiplexing and demultiplexing: Implements the encapsulation and parsing functions of LLDP and LLMMP, and the conversion between data packets and LLB.

[0182] FEC encoding and decoding: Implements the conversion function between LLB and FEC encoding and decoding workspaces, and implements data encoding and decoding functions in the FEC encoding and decoding workspaces.

[0183] Channel distribution and combination: Based on the enabled channel configuration, the data distribution and combination functions on each channel are realized.

[0184] Scrambling and descrambling: Each channel independently implements data scrambling and descrambling functions.

[0185] Precoding and de-precoding: Each channel independently implements data precoding and de-precoding functions.

[0186] The following examples illustrate FEC encoding and decoding, primarily describing the forward error correction (FEC) encoding specification in the unified multimedia interconnection interface, including the encoding method at the transmitter, the decoding (checking and error correction) method at the receiver, and its performance.

[0187] The main link of the unified multimedia interconnection interface uses the Reed-Solomon (48,46) code based on GF(256), namely the RS(48,46) code. As shown in Figure 10, each RS code work space (RS_ws) contains 46 bytes of data and 2 bytes of check information.

[0188] The number of RS codec workspaces in the FEC codec layer varies depending on the link architecture. In a Type-C port link architecture, the FEC codec layer contains a fixed five RS codec workspaces, enabling encoding and decoding of 230-byte LLB blocks. In a Type-B port link architecture, the FEC codec layer contains a fixed ten RS codec workspaces, enabling encoding and decoding of 460-byte LLB blocks.

[0189] The FEC encoding and decoding process may include three steps: RS mapping, RS encoding and decoding, and RS inverse mapping.

[0190] First, the RS mapping is described as follows:

[0191] Before performing RS encoding and decoding, the transmission LLB needs to be mapped into RS blocks, and then encoding and decoding is performed in the RS encoding and decoding work area corresponding to the RS blocks.

[0192] A Type-C port link contains 240 bytes in an LLB, which is evenly distributed across five RS blocks in byte order. Each RS block performs RS encoding and decoding independently in its corresponding RS encoding and decoding workspace. Figure 11 shows the mapping from LLBs to RS blocks.

[0193] A Type-B port link contains 480 bytes in an LLB, which is evenly distributed across 10 RS blocks in byte order. Each RS block performs RS encoding and decoding independently in its corresponding RS encoding and decoding workspace. Figure 12 shows the mapping from LLBs to RS blocks.

[0194] The following describes the detailed process of RS encoding and decoding at the FEC encoding and decoding layer:

[0195] The FEC encoding and decoding layer uses RS (48, 46) for encoding and decoding, and the primitive polynomial is: p(x) = x 8 +x 4 +x 3 +x 2 +1; the generating polynomial is: g(x) = x 2 +3x+2.

[0196] In the encoding area, the RS encoding workspace encodes the 46-byte data in the RS block and generates 2 bytes of check data. In the decoding area, the RS decoding workspace verifies and corrects the 48-byte data and check data in the RS block, achieving error correction for any 1-byte data in the RS block.

[0197] The RS inverse mapping is described as follows:

[0198] After completing RS encoding and decoding, the RS block needs to be inversely mapped into LLB.

[0199] The Type-C port link contains five RS blocks. Following the RS encoding and decoding workspace order, the data in the RS blocks is reverse-mapped byte by byte to the transmission LLB. In the encoding area, the first 230 bytes of the LLB block after reverse mapping are the same as the LLB block before RS mapping, and the last 10 bytes of the LLB block tail are replaced with five sets of RS checksum data. In the decoding area, the first 230 bytes of the LLB after reverse mapping are the LLB block after error correction, and the last 10 bytes of the LLB block tail are five sets of RS checksum data. After RS ​​error correction is completed, the checksum data is no longer used. The reverse mapping relationship between RS blocks and LLBs is shown in Figure 13.

[0200] A Type-B port link contains 10 RS blocks. The data in the RS blocks is reverse-mapped byte by byte to the transmission LLB in the order of the RS encoding and decoding workspace. In the encoding area, the first 460 bytes of the LLB block after reverse mapping are the same as the LLB block before RS mapping, and the last 20 bytes of the LLB block tail are replaced with 10 sets of RS check data. In the decoding area, the first 460 bytes of the LLB after reverse mapping are the LLB block after error correction, and the last 20 bytes of the LLB block tail are 10 sets of RS check data. After RS ​​error correction is completed, the check data is no longer used. The reverse mapping relationship between RS blocks and LLBs is shown in Figure 14.

[0201] The above mainly introduces the solution provided by the embodiment of the present invention from the perspective of the working principle of the device. It can be understood that in order to realize the above functions, the computing device, etc. includes hardware structures and / or software modules corresponding to the execution of each function. It should be easy for those skilled in the art to realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present invention can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0202] In the embodiments of the present invention, computing devices, etc., can be divided into functional modules according to the above-described method examples. For example, functional modules can be divided according to respective functions, or two or more functions can be integrated into a single processing module. The above-described integrated modules can be implemented in the form of hardware or software functional modules. It should be noted that the module division in the embodiments of the present invention is illustrative and is merely a logical functional division. In actual implementation, other division methods may be used.

[0203] In the case of dividing each functional module according to each function, Figure 15a illustrates a device 150 for transmitting data messages provided in an embodiment of the present application, and the device 150 for transmitting data messages is used to implement the functions in the above-mentioned method embodiment. As shown in Figure 15a, the device 150 for transmitting data messages may include: a packetizing unit 1501 and a padding unit 1502. The packetizing unit 1501 is used to execute the process S401 in Figure 4 or Figure 5, and the padding unit 1502 is used to execute the process S402 in Figure 4 or Figure 5. Among them, all relevant contents of each step involved in the above-mentioned method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0204] In another possible implementation, when FEC is enabled, as shown in FIG15b , the apparatus 150 for transmitting a data message further includes an encoding unit 1503 configured to: evenly distribute the 240 bytes of the LLB into five RS blocks in byte order, with each RS block corresponding to an RS encoding work area, each RS encoding work area containing 46 bytes of data and a 2-byte placeholder; encode the 46 bytes of data in each of the five RS blocks to generate 2-byte check data, thereby obtaining five sets of RS check data; and de-map the data in each of the five RS blocks byte by byte into the LLB in the order of the RS encoding work areas; after de-mapping, the first 230 bytes of the LLB block remain the same as the LLB block before RS mapping, and the placeholder in the last 10 bytes of the block tail is replaced with five sets of RS check data. This implements error correction for any 1-byte data within the RS block.

[0205] In another possible implementation, when FEC is enabled, the encoding unit 1503 is further configured to: evenly distribute the 480 bytes of the LLB into 10 RS blocks in byte order, with each RS block corresponding to an RS coding work area, each RS coding work area containing 46 bytes of data and a 2-byte placeholder; encode the 46 bytes of data in each of the 10 RS blocks to generate 2-byte check data, resulting in 10 sets of RS check data; and de-map the data in each of the 10 RS blocks byte by byte to the LLB in the order of the RS coding work areas; after de-mapping, the first 460 bytes of the LLB block within the LLB are the same as the LLB block before RS mapping, and the placeholder in the last 20 bytes of the block tail is replaced with 10 sets of RS check data. This implements error correction for any 1-byte data within the RS block.

[0206] In the case of dividing each functional module according to each function, Figure 16 illustrates another device 160 for transmitting data messages provided in an embodiment of the present application. The device 160 for transmitting data messages is used to implement the functions of the receiving device in the above method embodiment. As shown in Figure 16, the device 160 for transmitting data messages may include: a receiving unit 1601 and a processing unit 1602. The receiving unit 1601 is used to execute the process S403 in Figure 4; the processing unit 1602 is used to execute the process S404 in Figure 4. Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0207] In one possible implementation, when FEC is enabled, processing unit 1602 is specifically configured to: evenly distribute the 240 bytes of the LLB into five RS blocks in byte order, with each RS block corresponding to an RS decoding workspace containing 46 bytes of data and 2 bytes of check data; perform check and error correction on the 48 bytes of data and check data in each of the five RS blocks; de-map the data in each of the five RS blocks byte by byte to the LLB in the order of the RS decoding workspaces; and replace the first 230 bytes of the LLB with the checked and corrected block after de-mapping, disusing the check data in the last 10 bytes of the block footer. This allows for error correction of any 1-byte data within the RS block.

[0208] In another possible implementation, when FEC is enabled, processing unit 1602 is specifically configured to: evenly distribute the 480 bytes of the LLB into 10 RS blocks in byte order, with each RS block corresponding to an RS decoding work area, each RS decoding work area containing 46 bytes of data and 2 bytes of check data; perform check and error correction on the 48 bytes of data and check data in each of the 10 RS blocks; de-map the data in each of the 10 RS blocks byte by byte to the LLB in the order of the RS decoding work areas; and replace the first 460 bytes of the LLB with the checked and corrected block after de-mapping, disusing the check data in the last 20 bytes of the block footer. This allows for error correction of any 1-byte data within the RS block.

[0209] Another possible implementation of the above-mentioned verification and error correction includes: using GF(256)-based RS(48,46) decoding to perform verification and error correction.

[0210] In another possible implementation, the processing unit 1602 is further configured to: if FEC is not enabled, parse the LLB to obtain the data message encapsulated in the LLB.

[0211] In the case of adopting an integrated unit, as shown in Figure 17, another device 170 for transmitting data messages provided in an embodiment of the present application is used to implement the functions of the computing device or receiving device in the above-mentioned embodiment. The device 170 for transmitting data messages includes a processing module 1701 and a communication module 1702. The processing module 1701 is used to control and manage the actions of the device 170 for transmitting data messages, and the communication module 1702 is used to communicate with other devices. For example, the processing module 1701 is used to execute any of the processes S401-S404 in Figure 4; the communication module 1702 is used for the device 170 for transmitting data messages to interact with other devices. The device 170 for transmitting data messages may also include a storage module 1703 for storing program code and data of the device 170 for transmitting data messages.

[0212] The processing module 1701 may be the processor 3010 in the physical structure of the computing device 30 shown in FIG3 , and may be a processor or controller. For example, it may be a CPU, a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processing module 1701 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on. The communication module 1702 may be the communication interface 3040 in the physical structure of the computing device 30 shown in FIG3 . The communication module 1702 may be a communication port, or may be a transceiver, a transceiver circuit, or a communication interface. Alternatively, the communication interface may enable communication with other devices through the aforementioned transceiver components. The transceiver components may be implemented by antennas and / or radio frequency devices. The storage module 1703 may be the memory 3030 in the physical structure of the computing device 30 shown in FIG3 .

[0213] As mentioned above, the device 150 for transmitting data packets, the device 160 for transmitting data packets, and the device 170 for transmitting data packets provided in the embodiments of the present application can be used to implement the functions of the computing device or the receiving device in the above-mentioned embodiments of the present application. For ease of explanation, only the parts related to the embodiments of the present application are shown. For specific technical details not disclosed, please refer to the embodiments of the present application.

[0214] On the other hand, an embodiment of the present application provides a data transmission system, including the above-mentioned device for transmitting data packets 150 and / or the device for transmitting data packets 160.

[0215] On the other hand, an embodiment of the present application provides a data transmission system, including a data sending device and / or a data receiving device, the data sending device is used to perform the functions of the sending end device in the above method embodiment, and the data receiving device is used to perform the functions of the receiving end device in the above method embodiment.

[0216] As another form of this embodiment, a computer-readable storage medium is provided, on which instructions are stored. When the instructions are executed, the method for transmitting logical layer management messages in the above method embodiment is executed.

[0217] As another form of this embodiment, a computer program product containing instructions is provided. When the computer program product is run on a computer, the computer is caused to execute the method for transmitting logical layer management messages in the above method embodiment.

[0218] As another form of this embodiment, a chip is provided, comprising one or more interface circuits and one or more processors. The interface circuits are configured to receive signals from a memory of an electronic device and transmit the received signals to the processors, the signals comprising computer instructions stored in the memory. When the processors execute the computer instructions, the electronic device performs the operational steps of the method described in the first aspect or any possible implementation.

[0219] The embodiment of the present application further provides a chip system, which includes a processor for implementing the technical method of the embodiment of the present application. In one possible design, the chip system also includes a memory for storing the necessary program instructions and / or data of the embodiment of the present invention. In one possible design, the chip system also includes a memory for the processor to call the application code stored in the memory. The chip system can be composed of one or more chips, or can include chips and other discrete devices, which is not specifically limited in the embodiment of the present application.

[0220] Those skilled in the art will readily appreciate that, in conjunction with the various exemplary units and method steps described in the embodiments disclosed herein, this application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in hardware or in a hardware-driven manner by computer software depends on the specific application scenario and design constraints of the technical solution.

[0221] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present application of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be an SSD.

[0222] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for transmitting data packets, characterized in that, the method includes: performing packet processing on the data to be transmitted to obtain a data packet; filling the data packet into the body of a logical block LLB in byte order; wherein, when forward error correction FEC is enabled, the logical block includes the body and a block tail for filling check data; when FEC is not enabled, all bytes in the LLB are the body.

2. The method according to claim 1, characterized in that, when FEC is enabled, the method further includes: uniformly arranging 240 bytes of the LLB in byte order into 5 Reed - Solomon RS blocks, each RS block corresponding to an RS encoding work area, and each RS encoding work area containing 46 bytes of data and 2 bytes of placeholder; encoding the 46 - byte data in each of the 5 RS blocks respectively to generate 2 - byte check data, obtaining 5 groups of RS check data; in the order of the RS encoding work areas, inversely mapping the data in each of the 5 RS blocks byte by byte to the LLB; after inverse mapping, the first 230 - byte LLB body in the LLB is the same as the body of the LLB before RS mapping, and the placeholders in the last 10 - byte block tail are replaced by the 5 groups of RS check data.

3. The method according to claim 1, characterized in that, when FEC is enabled, the method further includes: uniformly arranging 480 bytes of the LLB in byte order into 10 RS blocks, each RS block corresponding to an RS encoding work area, and each RS encoding work area containing 46 bytes of data and 2 bytes of placeholder; encoding the 46 - byte data in each of the 10 RS blocks respectively to generate 2 - byte check data, obtaining 10 groups of RS check data; in the order of the RS encoding work areas, inversely mapping the data in each of the 10 RS blocks byte by byte to the LLB; after inverse mapping, the first 460 - byte LLB body in the LLB is the same as the body of the LLB before RS mapping, and the placeholders in the last 20 - byte block tail are replaced by the 10 groups of RS check data.

4. The method according to claim 2 or 3, characterized in that, the 2 - byte check data is obtained by RS(48,46) encoding based on Galois field GF(256).

5. The method according to any one of claims 1 - 4, characterized in that, the LLB uses all channel bandwidths during transmission.

6. The method according to any one of claims 1 - 5, characterized in that, the data to be transmitted includes: logical layer management messages and transport layer data, and the data packet includes: logical layer main link management packet LLMMP and logical layer data packet LLDP.

7. The method according to claim 6, characterized in that, the logical block includes at most two logical layer management messages.

8. The method according to claim 6 or 7, characterized in that, in the LLB, the logical layer management packet is filled first, and then the logical layer data packet is filled.

9. The method according to any one of claims 6-8, wherein, the LLB includes a logical layer data packet.

10. A method for transmitting a data packet, wherein, the method includes: receiving a logical block LLB, when forward error correction FEC is enabled, the logical block includes a block body for filling the data packet and a block tail for filling check data; when FEC is not enabled, all bytes in the LLB are the block body; if FEC is enabled, after checking and correcting the data in the block body of the LLB and the check data in the block tail, parsing the LLB to obtain the data packet encapsulated in the LLB.

11. The method according to claim 10, wherein, when FEC is enabled, the checking and correcting the data in the block body of the LLB and the check data in the block tail includes: arranging 240 bytes of the LLB in 5 Reed-Solomon RS blocks in byte order, each RS block corresponds to an RS decoding work area, and each RS decoding work area contains 46 bytes of data and 2 bytes of check data; checking and correcting the 48 bytes of data and check data in each of the 5 RS blocks; in the order of the RS decoding work areas, mapping the data in each of the 5 RS blocks byte by byte in reverse to the LLB; after reverse mapping, the first 230-byte block body in the LLB is replaced with the block body after checking and correcting, and the check data in the last 10-byte block tail is no longer used.

12. The method according to claim 10, wherein, when FEC is enabled, the checking and correcting the data in the block body of the LLB and the check data in the block tail includes: arranging 480 bytes of the LLB in 10 RS blocks in byte order, each RS block corresponds to an RS decoding work area, and each RS decoding work area contains 46 bytes of data and 2 bytes of check data; checking and correcting the 48 bytes of data and check data in each of the 10 RS blocks; in the order of the RS decoding work areas, mapping the data in each of the 10 RS blocks byte by byte in reverse to the LLB; after reverse mapping, the first 460-byte block body in the LLB is replaced with the block body after checking and correcting, and the check data in the last 20-byte block tail is no longer used.

13. The method according to claim 11 or 12, wherein, the checking and correcting includes: performing checking and correcting using RS(48,46) decoding based on Galois field GF(256).

14. The method according to any one of claims 10-13, wherein, the method further includes: if FEC is not enabled, parsing the LLB to obtain the data packet encapsulated in the LLB.

15. The method according to any one of claims 10-14, wherein, the LLB uses all channel bandwidths during transmission.

16. The method according to any one of claims 10-15, wherein, The data packet includes: a logical layer main link management message LLMMP and a logical layer data message LLDP.

17. The method according to claim 16, wherein, The LLB includes at most two logical layer management messages.

18. The method according to claim 16 or 17, wherein, In the LLB, the logical layer management message is filled first, and then the logical layer data message is filled.

19. The method according to any one of claims 16-18, wherein, The LLB includes a logical layer data message.

20. A device for transmitting data packets, wherein, The device includes: A packetizing unit for packetizing the data to be transmitted to obtain a data packet; A filling unit for filling the data packet into the block body of a logical block LLB in byte order; wherein, when forward error correction FEC is enabled, the logical block includes the block body and a block tail for filling check data; when FEC is not enabled, all bytes in the LLB are the block body.

21. The device according to claim 20, wherein, When FEC is enabled, the device further includes an encoding unit for: Arranging 240 bytes of the LLB in 5 Reed-Solomon RS blocks in byte order, each RS block corresponding to an RS encoding working area, and each RS encoding working area containing 46 bytes of data and 2 bytes of placeholder; Encoding the 46 bytes of data in each of the 5 RS blocks respectively to generate 2 bytes of check data, obtaining 5 groups of RS check data; In the order of the RS encoding working areas, mapping the data in each of the 5 RS blocks byte by byte in reverse to the LLB; after reverse mapping, the first 230 bytes of the LLB block body in the LLB is the same as the block body of the LLB before RS mapping, and the placeholders in the last 10-byte block tail are replaced by the 5 groups of RS check data.

22. The device according to claim 20, wherein, When FEC is enabled, the device further includes an encoding unit for: Arranging 480 bytes of the LLB in 10 RS blocks in byte order, each RS block corresponding to an RS encoding working area, and each RS encoding working area containing 46 bytes of data and 2 bytes of placeholder; Encoding the 46 bytes of data in each of the 10 RS blocks respectively to generate 2 bytes of check data, obtaining 10 groups of RS check data; In the order of the RS encoding working areas, mapping the data in each of the 10 RS blocks byte by byte in reverse to the LLB; after reverse mapping, the first 460 bytes of the LLB block body in the LLB is the same as the block body of the LLB before RS mapping, and the placeholders in the last 20-byte block tail are replaced by the 10 groups of RS check data.

23. The device according to claim 21 or 22, wherein, The 2-byte check data is obtained by RS(48,46) encoding based on the Galois field GF(256).

24. The device according to any one of claims 20-23, It is characterized in that the LLB uses all channel bandwidths during transmission.

25. The device according to any one of claims 20-24, It is characterized in that the data to be transmitted includes: logical layer management messages and transport layer data, and the data packet includes: logical layer main link management packet LLMMP and logical layer data packet LLDP.

26. The device according to claim 25, It is characterized in that the logical block includes at most two logical layer management packets.

27. The device according to claim 25 or 26, It is characterized in that in the LLB, the logical layer management packet is filled first, and then the logical layer data packet is filled.

28. The device according to any one of claims 25-27, It is characterized in that the LLB includes one logical layer data packet.

29. A device for transmitting data packets, It is characterized in that the device includes: a receiving unit that receives a logical block LLB. When forward error correction FEC is enabled, the logical block includes a block body for filling data packets and a block tail for filling check data; when FEC is not enabled, all bytes in the LLB are block bodies; a processing unit for, if FEC is enabled, performing check and error correction on the data in the block body of the LLB and the check data in the block tail, and then parsing the LLB to obtain the data packets encapsulated in the LLB.

30. The device according to claim 29, It is characterized in that when FEC is enabled, the processing unit is specifically used for: arranging 240 bytes of the LLB in order of bytes and evenly distributing them into 5 Reed-Solomon RS blocks. Each RS block corresponds to an RS decoding work area, and each RS decoding work area contains 46 bytes of data and 2 bytes of check data; performing check and error correction on the 48 bytes of data and check data in each of the 5 RS blocks; in order of the RS decoding work area, mapping the data in each of the 5 RS blocks to the LLB byte by byte in reverse; after reverse mapping, the block body of the first 230 bytes in the LLB is replaced with the block body after check and error correction, and the check data in the block tail of the last 10 bytes is no longer used.

31. The device according to claim 29, It is characterized in that when FEC is enabled, the processing unit is specifically used for: arranging 480 bytes of the LLB in order of bytes and evenly distributing them into 10 RS blocks. Each RS block corresponds to an RS decoding work area, and each RS decoding work area contains 46 bytes of data and 2 bytes of check data; performing check and error correction on the 48 bytes of data and check data in each of the 10 RS blocks; in order of the RS decoding work area, mapping the data in each of the 10 RS blocks to the LLB byte by byte in reverse; after reverse mapping, the block body of the first 460 bytes in the LLB is replaced with the block body after check and error correction, and the check data in the block tail of the last 20 bytes is no longer used.

32. The device according to claim 30 or 31, It is characterized in that the processing unit is specifically used for: RS(48, 46) decoding based on Galois field GF(256) is adopted for checksum and error correction.

33. The apparatus according to any one of claims 29 - 32, wherein, the processing unit is further configured to: if FEC is not enabled, parse the LLB to obtain the data packet encapsulated in the LLB.

34. The apparatus according to any one of claims 29 - 33, wherein, the LLB uses all channel bandwidths during transmission.

35. The apparatus according to any one of claims 29 - 34, wherein, the data packet includes: logical layer main link management packet LLMMP and logical layer data packet LLDP.

36. The apparatus according to claim 35, wherein, the LLB includes at most two logical layer management packets.

37. The apparatus according to claim 35 or 36, wherein, in the LLB, the logical layer management packet is filled first, and then the logical layer data packet is filled.

38. The apparatus according to any one of claims 35 - 37, wherein, the LLB includes one logical layer data packet.

39. A computing device, wherein, the computing device includes a memory and at least one processor, and the memory is used to store a set of computer instructions; when the processor executes the set of computer instructions, the operation steps of the method according to any one of claims 1 - 19 above are executed.

40. A data transmission system, wherein, the data transmission system includes a data sending device and / or a data receiving device, the data sending device is used to execute the method of transmitting a data packet according to any one of claims 1 - 9, and the data receiving device is used to execute the method of transmitting a data packet according to any one of claims 10 - 29.

41. A chip, wherein, includes one or more interface circuits and one or more processors; the interface circuit is used to receive a signal from the memory of the electronic device and send the signal to the processor, and the signal includes computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device is caused to execute the operations of the method according to any one of claims 1 - 19.

42. A computer - readable storage medium, wherein, includes: computer software instructions; when the computer software instructions run on a computer, the computer is caused to execute the operation steps of the method according to any one of claims 1 - 19 above.

43. A computer program product, wherein, the computer program product includes a software program, and when the software program is executed by a computer or a processor, the computer or the processor is caused to execute the operation steps of the method according to any one of claims 1 - 19.

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