High energy efficiency task scheduling system for heterogeneous many-core network-on-chip based on multi-armed bandit

Abstract

This invention discloses a high-efficiency task scheduling system for heterogeneous multi-core on-chip networks based on a multi-armed slot machine, relating to the field of task scheduling in heterogeneous multi-core systems. It addresses the problem of high power consumption in existing scheduling technologies by proposing this solution. During runtime, the following scheduling steps are periodically executed using time slices as the cycle: S1. Status acquisition of the underlying hardware platform and upper-layer application load; S2. Time and power consumption estimation based on on-chip network prediction; S3. Calculation of priority index and net gain; S4. Allocation of heterogeneous cores based on integer linear programming; S5. Runtime closed-loop feedback and control parameter updates. The advantage is that when the scheduler calculates the net gain, it imposes a strong mathematical penalty on applications with high packet injection rates that excessively distribute core allocation. This forces the system to perceive NoC traffic hotspots during runtime and intelligently converge applications with high communication demands to core configurations that are physically closer. This avoids problems such as virtual channel deadlock and bus congestion in NoC routers.

Description

Technical Field

[0001] This invention relates to the field of task scheduling in heterogeneous multi-core systems, and in particular to an energy-efficient task scheduling method based on a combination of a Network-on-Chip (NoC) end-to-end latency prediction model and a multi-armed slot machine algorithm. Background Technology

[0002] Currently, to address the complexity and scalability of scheduling problems in heterogeneous multi-core systems, hierarchical management has become a mainstream research framework. This framework decomposes the problem into two levels: Global Management and Hierarchical Management. Figure 1 The first layer, denoted by `C`, is responsible for allocating applications to the most suitable cluster and setting the cluster's voltage / frequency; this is a macro-level decision that directly determines the baseline of system energy consumption. The second layer, `Local Management`, is responsible for mapping specific application tasks to the core within the cluster; this is a micro-level resource optimization.

[0003] Academic research on this problem can be broadly categorized into several approaches. The first category consists of simple, fixed-priority strategies, such as Low-Power-First (LPF) and Low-Energy-First (LEF). The core idea of ​​LPF is that it always prioritizes allocating applications to the cluster with the lowest power consumption. If a small-core cluster cannot meet performance requirements, then a large-core cluster is considered. LEF, on the other hand, selects the cluster with the lowest overall energy consumption. While these strategies are simple and intuitive, research shows that as the platform scales (number of cores, number of clusters), their drawbacks quickly become apparent. Because they always prioritize a specific type of cluster, it easily leads to that cluster being overloaded and forced to operate at high frequencies, while other clusters are left idle, resulting in significant energy waste and performance bottlenecks.

[0004] The second category is optimized heuristic search strategies, such as the GSACA (Greedy Search Application-to-Cluster Assignment) strategy. GSACA is a greedy algorithm that no longer follows fixed cluster preferences. Instead, when making assignment decisions for each application, it dynamically evaluates the total system power consumption increment resulting from assigning it to different clusters and selects the option with the smallest increment. Simultaneously, it avoids clustering of applications with similar performance requirements through special application sorting and allows for limited application migration for further optimization. GSACA represents a significant improvement over LPF / LEF; experiments have shown that it significantly reduces power consumption and has better scalability. However, as a greedy strategy, it pursues "local optima" at each step, which cannot guarantee a "globally optimal" solution. When the scheduling decision space is extremely complex, it still risks getting trapped in local optima.

[0005] Furthermore, as multi-core clusters expand, on-chip networks replace the traditional shared bus, becoming the data communication backbone of heterogeneous multi-core systems. Existing scheduling strategies (such as LPF, LEF, and even GSACA) often assume ideal on-chip communication when mapping tasks, ignoring the surge in NoC packet routing traffic caused by tasks being split and executed across multiple cores. This neglect prevents the scheduler from detecting virtual channel (VC) allocation conflicts and crossbar congestion on NoC routers. When a large number of data-intensive applications are distributed across multiple cores, it can trigger severe NoC congestion storms, significantly increasing end-to-end communication latency, rendering the original execution time estimates invalid, and causing NoC routers to generate huge dynamic power consumption, becoming the energy efficiency bottleneck of the entire heterogeneous cluster.

[0006] In today's mobile devices, data centers, and IoT fields, energy consumption is a core design constraint. For mobile devices such as smartphones, lower power consumption means longer battery life, directly improving the user experience. For large-scale server clusters, even small improvements in energy efficiency can accumulate to save huge amounts of electricity and cooling costs. On power-constrained edge devices, efficient energy management enables them to perform more complex computing tasks within a limited energy budget. Therefore, existing technologies urgently need an effective means of controlling energy efficiency. Summary of the Invention

[0007] The purpose of this invention is to provide a high-efficiency task scheduling system based on a heterogeneous multi-core on-chip network using a multi-armed slot machine. By using a better scheduling algorithm, the long-term average power consumption of the system can be directly reduced, thereby solving the problems existing in the prior art.

[0008] The high-efficiency task scheduling system based on heterogeneous multi-core on-chip network described in this invention periodically executes the following scheduling steps in a time-slice cycle:

[0009] S1. Collect the status of the underlying hardware platform and the upper-layer application load; S2. Estimate time and power consumption based on on-chip network prediction; S3. Calculate the priority index and net income; S4. Assign heterogeneous cores based on integer linear programming; S5. Runtime closed-loop feedback and control parameter update.

[0010] The high-efficiency task scheduling system for heterogeneous multi-core on-chip networks based on a multi-armed slot machine described in this invention has the advantage that each application to be scheduled is regarded as an arm whose state changes dynamically over time, and the scheduling decision is to select the arm that maximizes long-term cumulative benefits at each moment. On-chip network latency prediction, including the NoC topology congestion index and zero-load latency, is integrated into the underlying Markov state transition and benefit evaluation. When the scheduler calculates net benefits, it imposes a strong mathematical penalty on the behavior of excessively dispersing core allocation for applications with high packet injection rates (data-intensive). This forces the system to perceive NoC traffic hotspots at runtime and intelligently converge applications with high communication demands to core configurations that are physically closer (with fewer routing hops). This not only effectively avoids virtual channel deadlock and bus congestion in NoC routers but also significantly reduces the dynamic power consumption of NoC routers caused by frequent packet forwarding, achieving dual energy efficiency optimization for computing and on-chip network communication while improving system throughput under high load. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the global management of heterogeneous multi-core systems in existing technologies.

[0012] Figure 2 This is a flowchart of the system described in this invention.

[0013] Figure 3 This is a schematic diagram of the workflow of the scheduler described in this invention.

[0014] Figure 4 This is a curve showing the task failure rate versus load factor of the system described in this invention and a comparative example.

[0015] Figure 5 This is a task-normalized average power consumption-load factor curve of the system described in this invention and a comparative example.

[0016] Figure 6 This is a curve showing the average core utilization rate versus load factor of the system described in this invention and a comparative example. Detailed Implementation

[0017] The high-efficiency task scheduling system based on heterogeneous multi-core on-chip network described in this invention decouples the complex scheduling problem into sub-problems for individual applications and optimizes them. This decomposition method provides a good scalability framework for dealing with more complex many-core systems in the future.

[0018] like Figure 2 , Figure 3 As shown, during runtime, the following scheduling steps are executed periodically, with time slices as the period: S1. Collect the status of the underlying hardware platform and the upper-layer application load; For the entire system, the first step is to obtain the platform status, read the hardware information of J heterogeneous clusters, and obtain the number N of homogeneous cores in each cluster j. j and the supported independent discrete frequency set F j Next, the task status is acquired, the arrival status of different types of applications i is monitored, and the arrival rate is recorded as λ. i And extract the feature parameters for each application instance, including the remaining workload and the remaining time τ until the deadline. i .

[0019] S2. Estimate time and power consumption based on on-chip network prediction; Estimate the system cost for each application to be scheduled under different allocation decisions: Power coefficient based on task and assignment core types The power consumption calculation for the core's dynamic power consumption is as follows: Where f is the frequency and w is the number of cores.

[0020] Unlike traditional schedulers that assume ideal communication, this system innovatively introduces a lightweight on-chip network (NoC). The overall computational overhead is... The formula is: ; in, This is the overhead of thread synchronization waiting in the operating system; It is the on-chip network end-to-end latency prediction term, calculated using the following formula: ; It is a log-normal distribution; and It is the mean and variance of a log-normal distribution obtained by fitting real data; the NoC message injection rate of the application is obtained based on offline benchmark tests to determine the communication contention penalty coefficient. ; Combining the topological congestion index with nonlinear deterioration under specific NoC topologies and zero-load data transmission latency constant based on routing hop count. This leads to the final communication overhead evaluation value.

[0021] Based on the fundamental routing theory of on-chip networks, when there are no contention data packets in the network... This represents the pure physical time it takes for a packet to travel from the source core to the destination core. Its analytical derivation involves three hardware dimensions: hop count, router pipeline delay (e.g., buffer writes, route calculations, virtual channel allocation, and crossbar switching traversal), and link traversal delay. For specific application instances… The baseline size of this constant is determined by the amount of basic data transported during the initial task distribution.

[0022] Based on the aforementioned time model that incorporates NoC delay prediction, the minimum permissible frequency required to complete the task within a given time period is further derived.

[0023] S3. Calculate the priority index and net income; Each individual application instance is modeled as one arm of a multi-armed slot machine, and the expected benefit of pulling the corresponding arm (i.e., immediately executing the task) is evaluated at each time slice: Retrieve two key dynamic feedback parameters currently in operation: dynamic resource pricing factor Resource costs, representing the current level of cluster resource congestion; and on-time completion reward factors. This indicates the urgency of meeting the deadline for this type of task.

[0024] Calculation in state The next step is to make an immediate decision versus waiting for a period of time. The decision involves considering the difference in expected costs between the two decisions. Using a first-order approximation with a probability density function, a priority index is derived to quantify the marginal benefit of immediate execution. .

[0025] ; For each waiting application instance and all possible combinations of decisions, calculate the corresponding net profit. The formula is: Net income = Priority index - (Estimated power consumption cost + Estimated communication latency cost + Resource usage cost) When an application generates an extremely high message injection rate due to excessively distributed core allocation, a strong mathematical penalty is imposed on the application by estimating the cost of communication latency.

[0026] S4. Assign heterogeneous cores based on integer linear programming; like Figure 3 As shown, an ILP problem is constructed to find the globally optimal allocation scheme in a complex decision space: the ILP problem is a 0-1 integer linear programming problem.

[0027] Set to maximize the total net benefit of all selected application instances: ; The solver strictly enforces the following hard constraints during operation: each application can only be allocated once; the total number of cores allocated to each cluster does not exceed the maximum number of cores in each cluster; each cluster executes at a single frequency and meets the minimum allowed frequency requirement. The optimal allocation matrix is ​​obtained by solving the ILP problem, and the task is then officially distributed to the corresponding physical core clusters for execution.

[0028] S5. Runtime closed-loop feedback and control parameter update; This is the core step in achieving high energy efficiency and adaptive congestion control in this system. After the current time slice ends, the control parameters are updated in a closed loop using a drift and penalty term based on the actual execution situation.

[0029] Resource congestion penalty update: Detect the actual core usage of cluster j; if the core usage exceeds the safety threshold... This will automatically increase the dynamic resource pricing factor for the corresponding cluster. (That is, increase resource prices); conversely, decrease the dynamic resource pricing factor. This mechanism causes the system to tend to run tasks on configurations with fewer cores but higher efficiency when parallelism is inefficient, thereby converging applications with high communication requirements to cores that are physically closer, effectively preventing bus deadlock.

[0030] ; Task completion rate feedback update: Detect the long-term actual on-time completion rate of application type i; if the completion rate is lower than the target threshold... This will increase the on-time completion bonus factor. This will directly affect the priority index of this type of task in the next part of the film. The increased load prompts the allocation of more resources to the task, thereby maintaining an extremely low task failure rate over long-term operation. Experiments have shown that it can remain below 1% even under high load.

[0031] ; This invention's technical approach starts with system data acquisition, uses Lagrange relaxation and MDP theory for decomposition and analysis, and its core lies in deriving and applying the index to guide forward-looking scheduling decisions. It then implements specific resource allocation through ILP and finally achieves adaptive control using a dynamic price update mechanism. The entire process constitutes a closed-loop, theory-driven runtime scheduling framework.

[0032] Analysis of Experimental Results Based on Index Scheduler: The experiments in this embodiment were mainly conducted under heavy video surveillance conditions. This scenario consists of a stable H.263 video stream and occasional JPEG snapshot tasks, which can reflect the typical workload of a real-world work scenario. The IBEAS algorithm (Index-Based Energy-AwareScheduling) of this invention was also compared with two other algorithms: Energy-aware Greedy Algorithm: A heuristic algorithm that prioritizes more difficult tasks and assigns them to cluster-core configurations that result in the least increase in power consumption.

[0033] Greedy-EDF (Earliest Deadline First): A variant of the Greedy algorithm, but it prioritizes tasks with the earliest deadlines during scheduling.

[0034] Figure 4 The diagram illustrates the change in task failure rate as the Load Scaling Factor increases from 0.3 to 1.0. Clearly, the IBEAS algorithm of this invention maintains an extremely low task failure rate (<1%) consistently across low to high loads. In contrast, both Greedy algorithms exhibit higher failure rates, fluctuating between 15% and 30%. Neither Greedy algorithm considers overall overhead. Energy-aware greedy algorithms tend to prioritize tasks with high difficulty and low power consumption. Greedy-EDF prioritizes deadline-sensitive tasks, but both ignore the significant decrease in parallel efficiency, leading to resource congestion and a high task failure rate. The algorithm of this invention, guided by an index, accurately recognizes when the marginal effect of adding cores diminishes, thus prioritizing decisions that balance failure rate and low power consumption in the long run. Furthermore, because the index in this invention includes price updates, in... In the dynamic feedback mechanism, the IBEAS algorithm increases when the application completion rate falls below a set standard. This leads to an increase in the index value, causing the scheduler to classify the task as more difficult to complete on time and allocate more resources and higher priority to it in subsequent encounters. Conversely, the opposite occurs when the application completion rate exceeds the standard. This is why the scheduler in this invention can maintain an extremely low failure rate.

[0035] Figure 5The diagram illustrates the relationship between average power consumption and load intensity when completing a task. Greedy-EDF, by only considering the urgency of the remaining task time and completely ignoring power consumption, has a significantly higher average power consumption than the other two algorithms. While the energy-aware greedy algorithm is very similar to the IBEAS algorithm in the diagram, it comes at the cost of a large portion of the task completion rate. The IBEAS algorithm, while ensuring a near-zero task failure rate, still maintains a lower average power consumption than the energy-aware greedy algorithm, demonstrating the high efficiency of the algorithm presented in this invention.

[0036] Figure 6 The curves showing the average core occupancy ratio as a function of the load scaling factor were plotted. The graph clearly shows that both Greedy and Greedy-EDF quickly saturate the system, with core occupancy approaching 100% as the load increases. However, the IBEAS algorithm maintains a much lower occupancy rate, remaining stable at around 45% even under full load. In order to minimize instantaneous power consumption or meet local deadlines, Greedy and Greedy-EDF blindly allocate the maximum available cores to tasks, leading to severe resource contention and high overall overhead. The IBEAS algorithm is based on Lagrange prices. The driver, when parallelization is inefficient, will penalize multi-core allocation. The scheduler, for example, will... Price updates keep core utilization near or below a set threshold, thus favoring tasks running on fewer, more parallel cores rather than inefficiently utilizing all cores. This strategy effectively prevents system congestion.

[0037] For those skilled in the art, various other corresponding changes and modifications can be made based on the technical solutions and concepts described above, and all such changes and modifications should fall within the protection scope of the claims of this invention.

Claims

1. A high-energy-efficiency task scheduling system based on a heterogeneous multi-core on-chip network using a multi-armed slot machine, characterized in that, During runtime, the following scheduling steps are executed periodically, with time slices as the period: S1. Collect status data on the underlying hardware platform and the upper-layer application load; S2. Estimate time and power consumption based on on-chip network prediction; S3. Calculate the priority index and net income; S4. Assign heterogeneous cores based on integer linear programming; S5. Runtime closed-loop feedback and control parameter update.

2. The high-efficiency task scheduling system based on a heterogeneous multi-core on-chip network according to claim 1, characterized in that, The specific process of step S1 is as follows: Read the hardware information of J heterogeneous clusters, obtain the number of homogeneous cores Nj in each cluster j, and the supported independent discrete frequency set Fj; then obtain the task status, monitor the arrival status of different types of applications i, record the arrival rate as λi, and extract the characteristic parameters of each application instance, including the remaining workload and the remaining time τi before the deadline.

3. The high-efficiency task scheduling system based on a heterogeneous multi-core on-chip network according to claim 2, characterized in that, The specific process of step S2 is as follows: Estimate the system cost for each application to be scheduled under different allocation decisions: Power coefficients based on task and assignment core types The power consumption calculation for the core's dynamic power consumption is as follows: ; Where f is the frequency and w is the number of cores; Based on the lightweight on-chip network NoC, the overall overhead is calculated. The formula is: ； in, This is the overhead of thread synchronization waiting in the operating system; It is the on-chip network end-to-end latency prediction term, calculated using the following formula: ; It is a log-normal distribution; and These are the mean and variance of a log-normal distribution obtained by fitting the real data; The NoC message injection rate of this application was obtained based on offline benchmark tests to determine the communication contention penalty coefficient. ; Combining the topological congestion index with nonlinear deterioration under specific NoC topologies and zero-load data transmission latency constant based on routing hop count. This leads to the final communication overhead evaluation value.

4. The high-efficiency task scheduling system based on a heterogeneous multi-core on-chip network according to claim 3, characterized in that, The specific process of step S3 is as follows: Each individual application instance is modeled as one arm of a multi-armed slot machine, and the expected reward of pulling the corresponding arm is evaluated at each time slice: Retrieve two key dynamic feedback parameters currently in operation: dynamic resource pricing factor The resource cost that represents the current level of resource congestion in the cluster; and on-time completion bonus factor This indicates the urgency of meeting the deadline for this type of task; Calculation in state The next step is to make an immediate decision versus waiting for a period of time. The difference in expected costs between the two decisions; By using a first-order approximation of the probability density function, a priority index for quantifying the immediate marginal benefit of execution is derived. ; ； For each waiting application instance and all its possible decision combinations, calculate the corresponding net profit; the formula is: Net income = Priority index - (Estimated power consumption cost + Estimated communication latency cost + Resource usage cost) When an application generates an extremely high message injection rate due to excessively distributed core allocation, a mathematical penalty is imposed on the application based on the estimated communication latency cost.

5. The high-efficiency task scheduling system based on a heterogeneous multi-core on-chip network according to claim 4, characterized in that, The specific process of step S4 is as follows: Construct an ILP problem to find the globally optimal allocation scheme in a complex decision space: the ILP problem is a 0-1 integer linear programming problem; Set to maximize the total net benefit of all selected application instances: ； The solver executes the following hard constraints during operation: each application can only be allocated once; the total number of cores allocated to each cluster does not exceed the maximum number of cores in each cluster; each cluster executes at a single frequency and meets the minimum allowed frequency requirement; the solver solves the ILP problem to obtain the optimal allocation matrix and then officially distributes the task to the corresponding physical core cluster for execution.

6. The high-efficiency task scheduling system based on a heterogeneous multi-core on-chip network according to claim 5, characterized in that, The specific process of step S5 is as follows: After the current time slice ends, the control parameters are updated in a closed loop using drift and penalty terms based on the actual execution situation. Resource congestion penalty update: Detect the actual core usage of cluster j; if the core usage exceeds the safety threshold... This will automatically increase the dynamic resource pricing factor for the corresponding cluster. Conversely, it reduces the dynamic resource pricing factor. The calculation formula is: ； Task completion rate feedback update: Detect the long-term actual on-time completion rate of application type i; if the completion rate is lower than the target threshold... This will increase the on-time completion bonus factor. The calculation formula is: ； Adaptive control is achieved by utilizing a dynamic price update mechanism.

Images