Switching network boards, servers, and computer clusters

Abstract

This application provides a switching network board, a server, and a computer cluster. The server includes at least one switching network board and at least two computing network boards, which are communicatively connected. The plane of the at least one switching network board is perpendicular to the plane of each computing network board. The at least one switching network board includes at least two recesses located on the same side of the at least one switching network board. Each recess penetrates the at least one switching network board along its thickness direction and is used to fix one computing network board. The depths of the at least two recesses are unequal. This application can utilize the redundant space of the switching network board to improve the overall internal space utilization and the rational layout of the internal space of the server.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a switching network board, a server, and a computer cluster. Background Technology

[0002] Servers employing orthogonal architecture typically refer to servers where the switching network board and compute network board are perpendicular to each other in space and connected via direct connectors. This eliminates the need for backplane cabling as in traditional backplane architectures, thus minimizing the connection distance between the compute and switching network boards. The orthogonal connection method between the switching and compute network boards within the server meets the high-speed requirements of the switching links, effectively improving the bandwidth scalability and board compatibility of the switching network boards.

[0003] Because different types of computing network boards have different numbers of chips, their space layout requirements also differ. Furthermore, existing servers have redundant space on their switching boards, leading to an inefficient space layout and low space utilization. Summary of the Invention

[0004] This application provides a switching network board, a server, and a computer cluster. The server provided in this application, through targeted optimization of the structural design of the switching network board within the server, can utilize the redundant space of the switching network board to improve the layout space of functional devices on different types of computing network boards, thereby achieving the effect of improving the overall internal space utilization and rationalizing the internal space layout of the server. This application specifically includes the following technical solutions:

[0005] In a first aspect, this application provides a server including at least one switching network board and at least two computing network boards, the at least one switching network board and the at least two computing network boards being communicatively connected, the plane of the at least one switching network board being perpendicular to the plane of each computing network board, wherein the at least one switching network board includes at least two grooves located on the same side of the at least one switching network board, each groove penetrating the at least one switching network board along the thickness direction of the at least one switching network board, each groove being used to fix one computing network board, wherein the groove depths of the at least two grooves are unequal.

[0006] The server provided in this application features grooves on the side of the switching network board facing the computing network board, with each groove penetrating the switching network board along its thickness. This allows the computing network board to be inserted into and fixed within the grooves, thereby improving the connection stability between the switching network board and the computing network board. At least two grooves on the switching network board have unequal depths. Grooves of different depths are used to insert computing network boards of different functional types. For example, computing network boards with relatively high layout space requirements can be inserted into grooves with relatively larger depths, while those with relatively lower layout space requirements can be inserted into grooves with relatively smaller depths. This fully utilizes the redundant space of the switching network board to meet the spatial layout requirements of the computing network boards. In other words, the server in this application differentiates the groove depths of the switching network board to rationally utilize its redundant space. Grooves of different depths are used to secure computing network boards of different functional types, thereby meeting the spatial layout requirements of different types of computing network boards and improving the internal space utilization and rational layout of the server.

[0007] One implementation involves aligning at least two computing tessellations with their sides facing away from at least one switching tessellation along the direction in which at least two computing tessellations are arranged.

[0008] In this implementation, due to the small spacing between adjacent computing lattice boards, by aligning the side surface of the computing lattice board connected to the switching lattice board away from the groove with the direction in which at least two computing lattice boards are arranged, the installation and replacement of the computing lattice boards can be facilitated, improving the installation efficiency and convenience. Simultaneously, because the groove depths of the at least two grooves are different, by aligning the side surface of the computing lattice board connected to the switching lattice board away from the groove with the direction in which at least two computing lattice boards are arranged, the overall surface areas of the at least two computing lattice boards are different. In this case, a computing lattice board with a relatively larger surface area can be inserted into the groove with a relatively larger groove depth, and a computing lattice board with a relatively smaller surface area can be inserted into the groove with a relatively smaller groove depth. This allows the grooves of the switching lattice board to be used for installing and inserting computing lattice boards of different surface areas, improving the adaptability and applicability of the switching lattice board while making reasonable use of its redundant space.

[0009] In one implementation, each computing network board includes a first connector, each switching network board includes at least two second connectors, each second connector is disposed at the bottom of a groove, and the first connector of each computing network board is coupled to one of the second connectors for communication connection.

[0010] In this implementation, each second connector of each switching network board is positioned at the bottom of a groove, with the connection port of each second connector facing outwards from the groove opening. This means the connection port of the second connector protrudes from the groove opening. When the first connector of the computing network board is inserted into the groove, the first connector can quickly and accurately connect to a second connector, achieving a communication connection between the switching network board and the computing network board. In other words, positioning the second connector at the bottom of the groove facilitates the connection between the second connector and the first connector, improving their efficiency.

[0011] In one implementation, along the connection direction between the first connector and the second connector, at least two of the at least two computing tessellation boards have unequal widths.

[0012] In this implementation, at least two computing PCBs connected to the switching PCB have unequal widths along the direction of connection between the first and second connectors. This allows for differentiated surface areas of the computing PCBs. For computing PCBs with relatively larger surface areas, there is sufficient space to accommodate a relatively large number of chips, fully meeting the space layout requirements of computing PCBs with a large number of chips. Furthermore, by differentiating the widths of at least two computing PCBs along the direction of connection between the first and second connectors, the wider computing PCB can be inserted into a deeper groove, while the narrower computing PCB can be inserted into a shallower groove. This ensures that the side surface of the computing PCB connected to the switching PCB facing away from the groove is flush with the direction in which the at least two computing PCBs are arranged, facilitating the installation and replacement of the computing PCBs and improving installation efficiency and convenience.

[0013] In one implementation, the planar orientation of each computing PCB is parallel to the connection direction between the first connector and the second connector.

[0014] One implementation involves arranging at least two computational meshes, wherein the thickness of each computational mesh is greater than or equal to the distance between the two groove walls of its corresponding groove.

[0015] In this implementation, the portion of the computing stencil inserted into the groove forms an interference fit with the two groove walls, which can further improve the connection stability and reliability between the computing stencil and the switching stencil.

[0016] In one implementation, at least two computing tessellation boards include a first computing tessellation board and a second computing tessellation board, wherein the number of chips in the first computing tessellation board is greater than the number of chips in the second computing tessellation board, and at least two grooves include a first groove and a second groove, wherein each first groove is used to fix a first computing tessellation board and each second groove is used to fix a second computing tessellation board, wherein the groove depth of the first groove is greater than the groove depth of the second groove.

[0017] In this implementation, the first computing network board has more chips than the second computing network board. Therefore, the width of the first computing network board along the connection direction of the two connectors can be increased to increase its surface area. This provides sufficient space for the chips on the first computing network board with the relatively larger number of chips, preventing a reduction in performance due to space constraints. Furthermore, by differentiating the depths of the first and second recesses, with the first recess being deeper than the second, the first recess can be used to insert and install the first computing network board with its relatively larger surface area. This achieves a more rational layout within the server and further improves the space utilization rate inside the server.

[0018] One implementation involves alternating first and second grooves along the direction in which at least two computational tessellation plates are arranged.

[0019] In this implementation, the first and second grooves with different groove depths are alternately arranged along the direction of at least two computing network boards, which can be applied to computing network boards with different deployment requirements, realize flexible layout of computing network boards, improve the utilization rate of internal server space, and further enhance the adaptability and applicability of switching network boards.

[0020] In one implementation, along the direction in which at least two computational tessellation plates are arranged, the first groove is located on the same side of the second groove.

[0021] In this implementation, the first groove with a relatively larger groove depth is located on the same side of the second groove with a relatively smaller groove depth. This allows for the adaptation of computing network boards with different deployment requirements, enabling flexible layout of the computing network boards. This improves the utilization of internal server space while further enhancing the adaptability and applicability of the switching network boards. Furthermore, along the direction in which at least two computing network boards are arranged, the grooves with relatively larger groove depths are arranged adjacently on the same side, and the grooves with relatively smaller groove depths are also arranged adjacently on the same side. This facilitates the installation and replacement of computing network boards with different functional types, improving the installation efficiency and convenience of the computing network boards.

[0022] In one implementation, along the direction in which at least two computing PCBs are arranged, the second groove is located at both ends of the server.

[0023] In this implementation, the second groove with a relatively smaller groove depth is located at the top and bottom of the server, while the first groove with a relatively larger groove depth is arranged in the middle of the server. This facilitates the installation and replacement of computing PCBs with different widths, further improving the installation efficiency and convenience of the computing PCBs.

[0024] In one implementation, along the direction where the opening and bottom of a groove are opposite, the width of the first computational mesh is greater than the width of the second computational mesh.

[0025] In this implementation, by differentiating the width of the computing reticle along the opposite direction of the groove opening and the groove bottom, i.e., the first computing reticle and the second computing reticle are designed with unequal widths, the chips on the first computing reticle, which has a relatively large number of chips, can have enough space to be arranged, thus avoiding a reduction in the working performance of the first computing reticle due to space constraints.

[0026] In one implementation, a first computing board includes a neural network processor, and a second computing board includes a central processing unit.

[0027] In one implementation, the switching network board includes a first chip and at least two second chips, each first chip being interconnected with a chip within the computing network board, and the at least two second chips being interconnected, wherein, along the direction opposite to the opening and bottom of the groove, the distance between each first chip and the bottom of the groove is greater than the distance between each second chip and the bottom of the groove.

[0028] In this implementation, some chips on the switching network board need to interconnect with chips on the computing network board, while others do not need to interconnect with chips on the computing network board but still need to be internally interconnected. Since the recesses on the switching network board are designed differently, classifying and arranging the chips in these two categories avoids the cross-traffic or continuous bends that can easily occur with long-distance routing. That is, classifying the chips within the switching network board, chips that need to interconnect with the computing network board are placed on the side of the switching network board away from the computing network board, avoiding continuous bends that would occur if they were placed near the recesses. Chips within the switching network board that do not need to interconnect with the computing network board, and power supply, clock, and other chips that only connect to chips within the same board, are placed on the side of the switching network board closer to the computing network board. This avoids space occupation on the side of the switching network board away from the recesses, thereby improving the spatial layout rationality of the switching network board. Improving the spatial layout rationality of the switching network board also reduces the fabrication difficulty and enhances its performance.

[0029] Secondly, this application provides a switching network board, including a main board, the main board including at least two grooves, the at least two grooves being located on the same side of the main board, and the grooves having different depths.

[0030] The switching network board provided in this application differentiates the groove depths, meaning at least two grooves on the switching network board have unequal depths. Grooves of different depths are used to insert computing network boards of different functional types. For example, computing network boards with relatively high layout space requirements can be inserted into grooves with relatively larger depths, while computing network boards with relatively lower layout space requirements can be inserted into grooves with relatively smaller depths. This fully utilizes the redundant space of the switching network board to meet the spatial layout requirements of the computing network boards. In other words, by differentiating the groove depths of the switching network board, redundant space can be rationally utilized, and grooves of different depths are used to accommodate computing network boards of different functional types, thereby meeting the spatial layout requirements of different types of computing network boards, improving the internal space utilization and rational layout of the server.

[0031] In one implementation, the switching board includes at least two second connectors, each second connector being fixed to the bottom of a groove, and the at least two second connectors are used to enable communication between the motherboard and the outside.

[0032] In one implementation, the switching board further includes a housing for housing and securing the motherboard, wherein the housing includes at least two openings along the opposite direction of the bottom and opening of the groove, each opening corresponding to a second connector, and each second connector communicating with the outside through its corresponding opening.

[0033] In this implementation, the housing supports and secures the motherboard, ensuring its assembly stability. Simultaneously, the motherboard and other functional components of the switching network board are housed within the housing, providing protection against external dust and foreign objects that could damage the internal components. By creating openings corresponding to the recesses, the switching network board can establish communication with external computing network boards, enhancing protection for the internal components and further improving assembly efficiency between them.

[0034] Thirdly, this application provides a computer cluster, which includes servers as provided in any of the above implementations, wherein there are multiple servers, and the multiple servers communicate and connect with each other to collaboratively process tasks.

[0035] Because the computer cluster in this application is equipped with the server provided by any of the above implementation methods, the computer cluster in this application possesses all the beneficial effects that the server provided by any of the above implementation methods may have. Attached Figure Description

[0036] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the planar structure of any one server in a computer cluster provided in an embodiment of this application;

[0038] Figure 2 A schematic diagram illustrating the connection structure of computing network boards and switching network boards in a server, provided for related technologies;

[0039] Figure 3 A schematic diagram of the planar structure connecting the computing network board and the switching network board provided for related technologies;

[0040] Figure 4 This is a schematic diagram of the planar structure of the switching network board provided in the embodiments of this application;

[0041] Figure 5 This is a schematic diagram of the planar structure of the computing network board and the switching network board provided in the embodiments of this application;

[0042] Figure 6 This is a schematic diagram of the planar structure connecting the computing network board and the switching network board provided in an embodiment of this application.

[0043] Figure 7 This is a schematic diagram of the planar structure of the switching network board provided in the embodiments of this application;

[0044] Figure 8 This is a schematic diagram of the planar structure of the switching network board provided in the embodiments of this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are merely some, and not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection claimed in this application.

[0046] This application provides a computer cluster, which includes multiple servers that communicate and connect with each other to collaboratively process tasks.

[0047] Please see Figure 1 , Figure 1This is a schematic diagram of the planar structure of any one server 100 in the computer cluster provided in this application embodiment. To clearly illustrate the internal planar structure of each server, in... Figure 1 The illustrated embodiment uses only one server in a computer cluster as an example for illustrative purposes. Figure 1 In the illustrated embodiments, the multiple servers can be at least one of chassis servers, blade servers, rack servers, and tower servers. This application specification uses a chassis server as an example and illustrates server 100 as the chassis server, but it does not limit the servers provided in this application embodiment to chassis servers.

[0048] exist Figure 1 In the illustrated embodiment, each server 100 includes at least two computing network boards 10 and at least one switching network board 20. The computing network board 10 can be understood as a computing device with computing capabilities, which can serve as a computing node in a computer cluster, providing computing power to the computer cluster. Exemplarily, each computing network board 10 includes at least one first switching chip 11 and at least one computing chip 12, with the at least one first switching chip 11 coupled to the at least one computing chip 12.

[0049] For example, computing chip 12 can be understood as a chip that processes computing tasks in a computer cluster. For instance, computing chip 12 can be a central processing unit (CPU), graphics processing unit (GPU), neural network processing unit (NPU), data processing unit (DPU), etc. It can also be a computing chip 12 used in cluster processing in application scenarios such as high performance computing (HPC) and artificial intelligence (AI), or it can be a storage chip used by storage nodes in a distributed storage scenario.

[0050] For example, the first switching chip 11 can be understood as a chip having the function of transmitting electrical signals and / or optical signals and transmitting data based on rules. One first switching chip 11 can be coupled to at least two computing chips 12, that is, at least two computing chips 12 are connected to the first switching chip 11. It is understood that when a first switching chip 11 is coupled to at least two computing chips 12, the first switching chip 11 is used to provide a dedicated electrical or optical signal path for any two of the at least two computing chips 12 connected to it.

[0051] For example, the first switching chip 11 may store a routing table or a media access control (MAC) address table. This routing table or MAC address table may include multiple entries, each representing a forwarding path. Each entry may include at least a source address, a destination address, and a corresponding next-hop address. For example, after receiving a data packet from the computing chip 12, the first switching chip 11 can query the routing table or MAC address table based on the source and destination addresses carried in the data packet to obtain the forwarding path of the data packet, determine the next-hop address, and then forward the data packet to the next-hop address.

[0052] For example, when the first switching chip 11 is a Layer 2 switch (link layer switch) switching chip, a MAC address table can be generated by relying on switch forwarding algorithms such as Address Resolution Protocol (ARP), and the source address and destination address can be MAC addresses.

[0053] For example, when the first switching chip 11 is a Layer 3 switch (network layer switch) switching chip, a routing table can be generated through routing algorithms such as Routing Information Protocol (RIP) and Border Gateway Protocol (BGP), and the source address and destination address mentioned above can be IP addresses.

[0054] For example, each first switching chip 11 can be connected to all computing chips 12 simultaneously. Figure 1 In the illustrated embodiment, the plurality of computing chips 12 include computing chips 1 to 32, and the plurality of first switching chips 11 are two in number. Any one of the first switching chips 11 can simultaneously establish a communication connection with computing chips 1 to 32.

[0055] For example, each first switching chip 11 may be connected to at least a portion of the computing chip 12. Figure 1 In the embodiment shown, one of the first switching chips 11 can establish a communication connection with computing chips 1 to 16, and the other first switching chip 11 can establish a communication connection with computing chips 17 to 32.

[0056] For example, the number of computing chips 12 connected to each first switching chip 11 can be determined based on the bandwidth requirements of the computing chip 12, as well as the number of ports and switching capacity of the first switching chip 11. For example, but not limited to, when the bandwidth requirement of the computing chip 12 is 100Gb and the switching capacity of the first switching chip 11 is 12.8Tbps, the first switching chip 11 can provide 32 downlink ports, each of which can provide a maximum bandwidth of 200Gb. That is, the 100Gb bandwidth requirement of the computing chip 12 can be met as long as the number of computing chips 12 connected to the first switching chip 11 does not exceed 64.

[0057] For example, the number of computing chips 12 connected to each first switching chip 11 can be adjusted according to other conditions such as the capacity of server 100 and the computer scale required by the user.

[0058] For example, multiple first switching chips 11 can also establish communication connections with each other.

[0059] For example, the first switching chip 11 and the computing chip 12 can establish a communication connection through the bus inside the computing device, such as the Peripheral Component Interconnect Express (PCIe) bus, or the extended industry standard architecture (EISA) bus, unified bus (Ubus or UB), compute express link (CXL), cachecoherent interconnect for accelerators (CCIX), etc., which are not specifically limited in this application.

[0060] It should be noted that, in Figure 1 The embodiments shown are merely illustrative examples of one possible type, function, arrangement, and connection method of functional structural components within the computing network board 10. However, this application does not limit the types, functions, arrangement, and connection methods of possible functional structural components within each computing network board to this specific embodiment. In other embodiments of this application, the types, functions, arrangement, and connection methods of functional structural components within each computing network board 10 can be adjusted according to the actual design requirements and application scenarios of the server 100. This application does not impose specific limitations in this regard. For example, but not limited to, the computing network board 10 includes several chips and interfaces, and may also include more components depending on the actual application scenario, such as a motherboard, memory, hard drive, heat sink, graphics card, PCIe, etc. This application does not impose specific limitations.

[0061] The number of switching panels 20 is at least one. Figure 1 The illustrated embodiment uses one switching board 20 as an example. The switching board 20 is used to implement communication connections between at least two computing boards 10. Specifically, the switching board 20 can be understood as a network device with electrical or optical signal forwarding capabilities. The switching board 20 includes at least one second switching chip 21 and multiple computing chips (not shown in the figure), and the number of second switching chips 21 can be one or more.

[0062] The second switching chip 21 is used to transmit electrical signals and / or optical signals, and has the function of transmitting data based on forwarding rules. When at least two computing chips are connected to the second switching chip 21, the second switching chip 21 is used to provide a dedicated electrical signal or optical signal path for any two of the at least two computing chips connected to it.

[0063] For example, the second switching chip 21 in the switching network board 20 and the first switching chip 11 in the computing network board 10 can be the same or different models, types, and specifications of switching chips, or they can be switching chips with completely or partially the same functions.

[0064] The second switching chip 21 may also store a routing table or a MAC address table. This table may include multiple entries, each representing a forwarding path. Each entry may include at least a source address, a destination address, and a corresponding next-hop address. After receiving a data packet, the second switching chip 21 can query the routing table or MAC address table based on the source and destination addresses carried in the data packet to obtain the forwarding path, determine the next-hop address, and then forward the data packet to the next-hop address.

[0065] For example, each server 100 includes multiple enclosures. An enclosure can be understood as a chassis or other enclosure that houses and secures components, and supports and protects the various components within the chassis. The enclosure may include a shell, a bracket, various switches, indicator lights, etc. on the panel. The enclosure may be made of a combination of steel plate and plastic, and this application does not make specific limitations.

[0066] Specifically, a housing can be used to house at least one computing spool 10 or at least one switching spool 20, meaning the computing spool 10 and the switching spool 20 can be housed in different housings. Figure 1 In the embodiment shown, a computing PCB 10 can be housed in a single housing, and a switching PCB 20 can be housed in a single housing.

[0067] In this application Figure 1In the illustrated embodiments, a switching network board 20 housed in a single enclosure and a computing network board 10 housed in a single enclosure 101 are used as examples for illustrative description. The enclosure used to house the switching network board 20 is illustrated as the first enclosure 101a, which can be understood as the outer shell of the switching network board 20, used to support and fix functional components such as the motherboard within the switching network board 20. Similarly, the enclosure used to house the computing network board 10 is illustrated as the first enclosure 101a, which can be understood as the outer shell of the computing network board 10, used to support and fix functional components such as the motherboard within the computing network board 10.

[0068] exist Figure 1 In the illustrated embodiment, data exchange between multiple computing chips 12 within a single computing network board 10 can be achieved using a first switching chip 11 located within the same housing 101. Data exchange between different computing network boards 10 can be achieved using a second switching chip 21 within a switching network board 20 of the same server 100. Each first switching chip 11 connects to multiple computing chips, and each switching network board 20 connects to multiple first switching chips 11.

[0069] Understandably, the housing 101 is used to support and fix the motherboard to ensure the stability of the motherboard assembly. At the same time, the motherboard and other functional components of the computing network board 10 or the switching network board 20 are all housed inside the housing 101, so that the housing 101 can protect the motherboard and other possible functional components of the computing network board 10 or the switching network board 20, preventing external dust, foreign objects, etc. from entering the housing 101 and potentially damaging the internal functional components of the computing network board 10 or the switching network board 20.

[0070] For example, each server 100 also includes a power module, a management module, a fan, and so on.

[0071] For example, a communication connection can be established between the switching network board 20 and the computing network board 10 via a connector 30. The connector 30 can be understood as a physical line used to realize the communication connection between the switching network board 20 and the computing network board 10, and the connector 30 can be at least one of an electrical connector or an optical connector.

[0072] For example, the computing network board 10 and the switching network board 20 are connected by an electrical connector. This electrical connector can be a backplane-less orthogonal connector. It is understood that connecting the computing network board 10 and the switching network board 20 using an electrical connector enables a direct orthogonal connection between them, without requiring connections via cables or fiber optic cables. In other words, the electrical connector allows for direct coupling between the computing network board 10 and the switching network board 20, thereby improving assembly efficiency and connection accuracy, and further enhancing the performance and lifespan of the server 100.

[0073] The computing network board 10 and the switching network board 20 establish a communication connection through an orthogonal architecture via electrical connectors. This reduces the structural size of the connector 30 between the computing network board 10 and the switching network board 20, thereby reducing the possibility of cable connection errors due to an excessive number of cables or optical fibers. In other words, by setting the computing network board 10 and the switching network board 20 to an orthogonal architecture, the internal structure design of the server 100 can be simplified, and the miniaturization design of the server 100 can be achieved. At the same time, the assembly efficiency and accuracy of the computing network board 10 and the switching network board 20 can be improved, as well as the working performance and lifespan of the server 100.

[0074] Please refer to the following: Figure 2 and Figure 3 , Figure 2 A schematic diagram of the connection structure between the computing network board 10' and the switching network board 20' in the server 100' provided for related technologies. Figure 3 A schematic diagram of the planar structure connecting the computing network board 10' and the switching network board 20' provided for related technologies. (See diagram below.) Figure 2 and Figure 3 As shown, the computing network board 10' and the switching network board 20' are orthogonal, meaning they are mutually orthogonal and connected via connector 30'. The orthogonality can be understood as the computing network board 10' and the switching network board 20' being perpendicular to each other in space.

[0075] For example, in Figure 2 and Figure 3 In the embodiment shown, the planar direction of the calculation screen 10' is parallel to the vertical direction, such as... Figure 2 and Figure 3 The plane containing the Z direction is shown. The plane of the switching network board 20 is parallel to the horizontal direction, and the computing network board 10' and the switching network board 20' are interconnected, as shown. Figure 2 and Figure 3The plane containing the X and Y directions is shown. The X, Y, and Z directions are mutually perpendicular and form a Cartesian coordinate system. The Z direction can be vertical, while the X and Y directions can be horizontal.

[0076] Understandably, when the plane of the computational stencil 10' is vertical and the plane of the exchange stencil 20' is horizontal, the computational stencil 10' and the exchange stencil 20' are perpendicular to each other in space. Alternatively, the plane of the computational stencil 10' can be set to be parallel to the horizontal direction, and the plane of the exchange stencil 20' can be set to be parallel to the vertical direction.

[0077] Figure 2 and Figure 3 The switching network board 20' provided by the relevant technology has all grooves of the same size structure, which can only be used to install computing network boards 10' of the same length. However, since the number of chips in computing network boards 10' varies depending on their functional type, the space layout requirements of different types of computing network boards 10' are different. In the existing server 100', the switching network board 20' has redundant space, resulting in an unreasonable space layout and low space utilization within the server 100'.

[0078] The server 100 provided in this application, through targeted optimization of the structural design of the internal switching network board 20, can utilize the redundant space of the switching network board 20 to improve the layout space of functional devices on different types of computing network boards 10, thereby achieving the effect of improving the overall internal space utilization rate and rational internal space layout of the server 100.

[0079] Next, this application will describe in detail the server 100 and the switching network board 20 provided in the embodiments of this application with reference to the accompanying drawings and specific embodiments.

[0080] Please see Figure 4 , Figure 4 This is a schematic diagram of the planar structure of the switching network board 20 provided in an embodiment of this application. Figure 4 As shown, the exchange mesh plate 20 includes at least two grooves 22, which are located on the same side of at least one exchange mesh plate 20. Each groove 22 penetrates at least one exchange mesh plate 20 along its thickness direction. Figure 4 In the illustrated embodiment, each groove 22 extends through the switching stencil 20 along the Z direction. Each groove 22 is used to fix a computing stencil 10.

[0081] It is understandable that by opening grooves 22 on the side of the switching grid 20 facing the computing grid 10, and each groove 22 penetrating the switching grid 20 along the thickness direction of the switching grid 20, the computing grid 10 can be inserted into the grooves 22 for fixation, thereby improving the connection stability between the switching grid 20 and the computing grid 10.

[0082] For example, the groove 22 can be formed on the main board of the switching network plate 20 or on the housing 101 of the switching network plate 20. Alternatively, the groove 22 can be formed on both the main board and the housing 101 of the switching network plate 20, and the grooves 22 on the main board and the housing 101 correspond one-to-one.

[0083] For example, at least two of the grooves 22 have unequal depths. Specifically, in Figure 4 In the illustrated embodiment, each switching network plate 20 includes a plurality of grooves 22, which are arranged sequentially along the Y direction. At least two of the grooves 22 have different depths. The depth of each groove 22 can be understood as the distance between the opening 221 and the bottom 222 of each groove 22 along the X direction. Figure 4 The diagram shows that the groove depth of each groove 22 is the first depth D1.

[0084] Understandably, the grooves 22 of the switching stencil 20 have different depths. Grooves 22 with different depths are used to insert computing stencils 10 with different functional types. For example, computing stencils 10 with relatively high layout space requirements can be inserted into grooves 22 with relatively large groove depths, while computing stencils 10 with relatively low layout space requirements can be inserted into grooves 22 with relatively small groove depths, so as to make full use of the redundant space of the switching stencil 20 and thus meet the spatial layout requirements of the computing stencils 10.

[0085] That is, by differentiating the groove depth of the groove 22 of the switching network board 20, the redundant space of the switching network board 20 can be made reasonable. Grooves 22 with different groove depths are used to connect computing network boards 10 with different functional types, thereby meeting the space layout requirements of computing network boards 10 with different functional types, and improving the space utilization and rational layout inside the server 100.

[0086] Furthermore, since the computer cluster of this application is equipped with the server 100 provided by any of the above implementations or the switching network board 20 provided by any of the above implementations, the computer cluster of this application possesses all the beneficial effects that the server 100 or the switching network board 20 provided by any of the above implementations may have.

[0087] Please refer to the following: Figure 5 , Figure 5This is a schematic diagram of the planar structure of the computing stencil 10 and the switching stencil 20 provided in an embodiment of this application. Figure 5 In the illustrated embodiment, the plane of at least one switching stencil 20 is perpendicular to the plane of each computing stencil 10, meaning the switching stencil 20 and each computing stencil 10 are orthogonal. Specifically, the switching stencil 20 is placed horizontally, and at least two computing stencils 10 are placed vertically.

[0088] That is, in Figure 5 In the embodiment shown, the plane of the switching stencil 20 is parallel to the X and Y directions and perpendicular to the Z direction, and at least two computing stencils 10 are arranged sequentially along the X or Y direction, with the plane of each computing stencil 10 being parallel to the Z direction.

[0089] For example, along the direction in which at least two computational stencils 10 are arranged, the thickness of each computational stencil 10 is greater than or equal to the distance between the two groove bottoms 223 of its corresponding groove 22.

[0090] Specifically, the thickness of each computational stencil 10 can be understood as the distance between two opposite planes of each computational stencil 10, or as the width of the side of each computational stencil 10. Figure 5 In the illustrated embodiment, the thickness of each computational stencil 10 is schematically represented by a first distance H1 (e.g., ...). Figure 4 (As shown). The distance between the two groove bottoms 223 of each groove 22 can be understood as the distance between the two opposite groove bottoms 223 of the groove 22 along the plane of the exchange mesh plate 20. Figure 5 In the embodiment shown, the distance between the two opposite groove bottoms 223 of each groove 22 is schematically represented as the second distance H2.

[0091] That is, the first distance H1 is greater than the second distance H2. It can be understood that the thickness of each computing stencil 10 is greater than or equal to the distance between the two groove bottoms 223 of its corresponding groove 22, so that the computing stencil 10 and its corresponding groove 22 form an interference fit, which can further improve the connection stability and reliability between the computing stencil 10 and the switching stencil 20.

[0092] For example, along the direction in which at least two computing stencils 10 are arranged, at least two computing stencils 10 are flush with the side facing away from at least one switching stencil 20.

[0093] Understandably, since the spacing between two adjacent computing stencils 10 is small, by setting the side surface of the computing stencil 10 connected to the exchange stencil 20 away from the groove 22 to be flush with the direction in which at least two computing stencils 10 are arranged, it is easy to install and replace the computing stencils 10, thereby improving the installation efficiency and convenience of the computing stencils 10.

[0094] Meanwhile, since the groove depths of at least two grooves 22 are different, and the side surface of the computing grid 10 connected to the switching grid 20 is aligned with the direction in which the at least two computing grids 10 are arranged, the overall surface areas of the at least two computing grids 10 are different. In this case, a computing grid 10 with a relatively large surface area can be inserted into the groove 22 with a relatively large groove depth, and a computing grid 10 with a relatively small surface area can be inserted into the groove 22 with a relatively small groove depth. This allows the grooves 22 of the switching grid 20 to be used for installing and inserting computing grids 10 with different surface areas. By making reasonable use of the redundant space of the switching grid 20, the adaptability and applicability of the switching grid 20 are improved.

[0095] Please see Figure 6 , Figure 6 This is a schematic diagram of the planar structure connecting the computing network board 10 and the switching network board 20 provided in an embodiment of this application. Figure 6 As shown, each computing network board 10 includes a first connector 31, and each switching network board 20 includes at least two second connectors 32. Each second connector 32 is disposed at the bottom 222 of a groove 22, and the first connector 31 of each computing network board 10 is coupled to a second connector 32 for communication connection.

[0096] Understandably, by placing each second connector 32 of each switching network board 20 in the bottom 222 of the groove 22, with the connection port of each second connector 32 facing from the bottom 222 of the groove 22 towards the opening 221 (i.e., the connection port of the second connector 32 is exposed from the opening 221 of the groove 22), when the first connector 31 of the computing network board 10 is inserted into the groove 22, the first connector 31 can be quickly and accurately connected to a second connector, thereby achieving the effect of communication connection between the switching network board 20 and the computing network board 10. In other words, by placing the second connector 32 in the bottom 222 of the groove 22, the connection between the second connector 32 and the first connector 31 can be facilitated, and the efficiency between them can be improved.

[0097] For example, the planar orientation of each computing network board 10 is parallel to the connection direction between the first connector 31 and the second connector 32. It can be understood that by setting the planar orientation of each computing network board 10 to be parallel to the connection direction between the first connector 31 and the second connector 32, multiple computing network boards 10 can be arranged on the same side of the switching network board 20 as much as possible, further improving the space utilization inside the server 100.

[0098] For example, such as Figure 6As shown, at least two computing PCBs 10 have unequal widths along the connection direction of the first connector 31 and the second connector 32. Specifically, among the computing PCBs 10 connected to the switching PCB 20, at least two computing PCBs 10 have unequal widths along the connection direction of the first connector 31 and the second connector 32, thereby achieving differentiated surface area settings for the computing PCBs 10. For computing PCBs 10 with relatively larger surface areas, there is sufficient space to arrange a relatively large number of chips, fully meeting the space layout requirements of computing PCBs 10 with a large number of chips.

[0099] Meanwhile, by differentiating the widths of at least two computing PCBs 10 along the direction of connection between the first connector 31 and the second connector 32, the computing PCB 10 with a relatively larger width can be inserted into the groove 22 with a relatively larger groove depth, and the computing PCB 10 with a relatively smaller width can be inserted into the groove 22 with a relatively smaller groove depth. This makes the side surface of the computing PCB 10 connected to the exchange PCB 20 facing away from the groove 22 flush with the direction of arrangement of at least two computing PCBs 10, which facilitates the installation and replacement of the computing PCBs 10 and improves the installation efficiency and convenience of the computing PCBs 10.

[0100] For example, at least two computing stencils 10 include at least one first computing stencil 10a and at least one second computing stencil 10b, wherein the number of chips in at least one first computing stencil 10a is greater than the number of chips in at least one second computing stencil 10b.

[0101] For example, at least one first computing screen 10a includes a neural network processor, and at least one second computing chip includes a central processing unit. Figure 6 In the illustrated embodiment, the first computing network board 10a is used as an NPU node and the second computing network board 10b is used as a CPU computing network board 10 for illustrative purposes. It is understood that the number of chips in the NPU node is greater than the number of chips in the CPU node.

[0102] exist Figure 6 In the illustrated embodiment, at least two grooves 22 include at least one first groove 22a and at least one second groove 22b. Each first groove 22a is used to fix a first computing reticle 10a, and each second groove 22b is used to fix a second computing reticle 10b. The groove depth of at least one first groove 22a is greater than the groove depth of at least one second groove 22b.

[0103] Understandably, the first computing PCB 10a has more chips than the second computing PCB 10b. This allows for an increase in the width of the first computing PCB 10a along the connection direction of the two connectors, thereby increasing the surface area of ​​the first computing PCB 10a. This ensures that the chips on the first computing PCB 10a, which has a relatively large number of chips, have sufficient space for layout, avoiding a reduction in the working performance of the first computing PCB 10a due to space constraints.

[0104] At this time, by differentiating the groove depth of the first groove 22a and the groove depth of the second groove 22b, and setting the groove depth of the first groove 22a to be greater than the groove depth of the second groove 22b, the first groove 22a can be used to insert and install the first computing network board 10a with a relatively large surface area, thereby realizing a rational layout inside the server 100 and further improving the space utilization rate inside the server 100.

[0105] For example, along the direction opposite to the opening 221 and bottom 222 of a groove 22, the width of at least one first computing stencil 10a is greater than the width of at least one second computing stencil 10b. Specifically, the width of the computing stencil 10 can be understood as the distance between two opposite sides of each computing stencil 10 along the direction in which the computing stencil 10 is connected to the switching stencil 20. Figure 6 The diagram illustrates that the width of the first computational stencil 10a is the first width W1, and the width of the second computational stencil 10b is the second width W2, meaning that the first width W1 is greater than the second width W2.

[0106] Understandably, by differentiating the width of the computing stencil 10 along the opposite direction of the groove opening 221 and the groove bottom 222 of the groove 22, i.e. the first computing stencil 10a and the second computing stencil 10b are designed with unequal widths, the chips on the first computing stencil 10a, which has a relatively large number of chips, can have enough space to be arranged, and the working performance of the first computing stencil 10a is avoided due to the compact space.

[0107] For example, the groove 22 can be formed on the same side of the main board of the switching network board 20. The housing 101 for accommodating the switching network board 20 includes at least two openings (not shown in the figure). Along the opposite direction of the groove bottom 222 and the groove opening 221 of the groove 22, each opening corresponds to a second connector 32. Each second connector 32 passes through its corresponding opening and communicates with the outside. That is, each opening is used to expose one of its corresponding second connectors 32 to the outside. It can be understood that by forming the openings corresponding to the groove 22, the switching network board 20 can achieve communication connection with the external computing network board 10, which improves the protection effect of the internal functional components of the switching network board 20 and further improves the assembly efficiency between the switching network board 20 and the external computing network board 10.

[0108] Please see Figure 7 , Figure 7 This is a schematic diagram of the planar structure of the switching network board 20 provided in an embodiment of this application. Figure 7 As shown in (a), at least one first groove 22a and at least one second groove 22b are alternately arranged along the direction in which at least two computational meshes 10 are arranged.

[0109] Understandably, the first groove 22a and the second groove 22b with different groove depths are arranged alternately along the direction of at least two computing network boards 10, which can be adapted to computing network boards 10 with different deployment requirements, realize the flexible layout of computing network boards 10, improve the internal space utilization of server 100, and further improve the adaptability and applicability of switching network board 20.

[0110] like Figure 7 As shown in (b), along the direction in which at least two computing network boards 10 are arranged, at least one first groove 22a is located on the same side of at least one second groove 22b. Specifically, the first groove 22a with a relatively larger groove depth is located on the same side of the second groove 22b with a relatively smaller groove depth, which can be adapted to computing network boards 10 with different deployment requirements, realize flexible layout of computing network boards 10, improve the internal space utilization of server 100, and further improve the adaptability and applicability of switching network board 20.

[0111] Meanwhile, along the direction in which at least two computing reticles 10 are arranged, the grooves 22 with relatively larger groove depths are arranged adjacently on the same side, and the grooves 22 with relatively smaller groove depths are arranged adjacently on the same side, which facilitates the installation and replacement of computing reticles 10 with different functional types, and improves the installation efficiency and convenience of computing reticles 10.

[0112] like Figure 7 As shown in (c), at least one second groove 22b is located at both ends of the server 100 along the direction in which at least two computing tessellation plates 10 are arranged. That is, along the vertical direction, the second grooves 22b with relatively smaller groove depths are located at the top and bottom ends of the server 100, respectively. The multiple second grooves 22b can be symmetrically distributed or asymmetrically distributed. The first grooves 22a with relatively larger groove depths are arranged in the middle of the server 100, which facilitates the installation and replacement of computing tessellation plates 10 with different widths, further improving the installation efficiency and convenience of the computing tessellation plates 10.

[0113] It should be noted that, in Figures 4-7In the illustrated embodiments, the possible deployment quantity and structural shape of the computing network boards 10 and switching network boards 20 within each 100 are described as an example. However, it is not limited to the fact that the deployment quantity and structural shape of the computing network boards 10 and switching network boards 20 within each server 100 must be the same, nor is it limited to the deployment quantity and structural shape of the computing network boards 10 and switching network boards 20 as shown in the figure. In other embodiments of this application, the deployment quantity and structural shape of the computing network boards 10 and switching network boards 20 may be the same or different, and the deployment quantity and structural shape of the computing network boards 10 and switching network boards 20 may be adjusted according to the actual application scenario and design requirements of the server 100. This application embodiment does not specifically limit this.

[0114] Please see Figure 8 , Figure 8 This is a schematic diagram of the planar structure of the switching network board 20 provided in an embodiment of this application. Figure 8 In the illustrated embodiment, at least one switching board 20 includes at least one first chip C1 and at least two second chips C2. Each first chip C1 is interconnected with a chip within at least one computing board 10, and the at least two second chips C2 are interconnected. For example, the first chip C1 may be a switching chip interconnected with a chip on the computing board 10, and the second chip C2 may be a clock chip interconnected with a chip inside the switching board 20, etc.

[0115] For example, along the direction of the groove opening 221 and the groove bottom 222 of the groove 22, the distance between each first chip C1 and the groove bottom 222 of the groove 22 is greater than the distance between each second chip C2 and the groove bottom 222 of the groove 22.

[0116] Understandably, some chips on the switching network board 20 need to be interconnected with at least one chip on the computing network board 10, while some chips do not need to be interconnected with the chips on the computing network board 10 but need to be interconnected internally. Since the grooves 22 on the switching network board 20 are designed differently, the two parts of the chips on the switching network board 20 can be sorted and laid out to avoid the cross-traffic or continuous bending of long-distance traces.

[0117] In other words, by classifying the chips within the switching network board 20, chips that need to interconnect with the computing network board 10 are placed on the side of the switching network board 20 away from the computing network board 10, thus avoiding continuous curved traces caused by placing them near the recess 22. Chips within the switching network board 20 that do not need to interconnect with the computing network board 10, such as power supply and clock chips that only connect to the chips within this board, are placed on the side of the switching network board 20 closer to the computing network board 10. This avoids space occupation on the side of the switching network board 20 away from the recess 22, thereby improving the rationality of the spatial layout on the switching network board 20. While improving the rationality of the spatial layout of the switching network board 20, it also reduces the manufacturing difficulty of the switching network board 20 and improves the working performance of the switching network board 20.

[0118] It should be noted that, in Figure 8 The embodiments shown are merely illustrative examples illustrating one possible arrangement, interconnection, structural shape, and size of chips of different connection types on the switching network board 20. However, this application does not limit the possible arrangement, interconnection, structural shape, and size of chips of different connection types on the switching network board 20 to this specific example, nor does it limit the actual structural shape, size, arrangement, interconnection, and wiring of multiple chips on the switching network board 20 to the figures shown. In other embodiments of this application, the possible arrangement, interconnection, structural shape, and size of chips of different connection types on the switching network board 20 can be adjusted according to actual design requirements, and this application does not specifically limit these aspects.

[0119] Of course, the above-described embodiments can be applied individually or in combination. The above description is the preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A server, characterized by It includes at least one switching network board and at least two computing network boards, the at least one switching network board and the at least two computing network boards being communicatively connected, wherein the plane of the at least one switching network board is perpendicular to the plane of each of the computing network boards, wherein: The at least one switching grid plate includes at least two grooves located on the same side of the at least one switching grid plate. Each groove extends through the at least one switching grid plate along its thickness direction. Each groove is used to fix one of the computing grid plates. The grooves at least two of the grooves have different depths.

2. The server of claim 1, wherein, Along the direction in which the at least two computing stencils are arranged, the sides of the at least two computing stencils are flush with the sides of the at least one switching stencil.

3. The server of claim 1 or 2, wherein, Each of the computing network boards includes a first connector, each of the switching network boards includes at least two second connectors, each of the second connectors is disposed at the bottom of one of the grooves, and the first connector of each computing network board is coupled to one of the second connectors for communication connection.

4. The server of claim 3, wherein, Along the connection direction between the first connector and the second connector, at least two of the at least two computing PCBs have unequal widths.

5. The server according to any one of claims 1-4, characterized by, The planar orientation of each of the computing PCBs is parallel to the connection direction between the first connector and the second connector.

6. The server of any of claims 1-5, wherein, Along the direction in which the at least two computational reticles are arranged, the thickness of each computational reticle is greater than or equal to the distance between the two groove walls of the corresponding groove.

7. The server of any of claims 1-6, wherein, The at least two computing tessellations include a first computing tessellation and a second computing tessellation, wherein the number of chips in the first computing tessellation is greater than the number of chips in the second computing tessellation. The at least two grooves include a first groove and a second groove. The first groove is used to fix the first computing reticle, and the second groove is used to fix the second computing reticle. The groove depth of the first groove is greater than the groove depth of the second groove.

8. The server according to claim 7, characterized in that, Along the direction in which the at least two computational stencils are arranged: The first groove and the second groove are arranged alternately; Alternatively, the first groove may be located on the same side as the second groove.

9. The server according to claim 7 or 8, characterized in that, Along the direction where the opening and bottom of one of the grooves are opposite, the width of the first computational stencil is greater than the width of the second computational stencil.

10. The server according to any one of claims 1-9, characterized in that, The switching network board includes a first chip and at least two second chips. Each first chip is interconnected with a chip within the computing network board, and the at least two second chips are interconnected, wherein: Along the direction where the groove opening and the groove bottom are opposite, the distance between each first chip and the groove bottom is greater than the distance between each second chip and the groove bottom.

11. A switching network panel, characterized in that, The device includes a motherboard, which includes at least two recesses located on the same side of the motherboard, and the recesses have different depths.

12. The switching network board according to claim 11, characterized in that, The switching network board includes at least two second connectors, each of which is fixed to the bottom of one of the grooves. The at least two second connectors are used to enable communication between the motherboard and the outside.

13. The switching network board according to claim 11 or 12, characterized in that, The switching network board also includes a housing for housing and securing the motherboard, wherein: The housing includes at least two openings along the opposite direction of the bottom and opening of the groove. Each opening corresponds to a second connector, and each second connector communicates with the outside through its corresponding opening.

14. A computer cluster, characterized in that, The computer cluster includes a server as provided in any one of claims 1-10, wherein there are multiple servers, and the multiple servers communicate with each other to collaboratively process tasks.

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