An ultra-wideband high-precision instantaneous frequency measurement circuit and method

Abstract

This invention discloses an ultra-wideband, high-precision instantaneous frequency measurement circuit and method, belonging to the field of frequency measurement technology. It includes a power divider group, multiple frequency measurement channels, an analog switch group, an SP3T switch, a direct digital frequency synthesizer (DDS), and an FPGA. The input RF signal is divided into four channels by the power divider group, corresponding to four frequency measurement channels. Each frequency measurement channel corresponds to a different frequency range, and the channels operate in parallel. Each channel signal is output as an LVTTL level to the FPGA after passing through a detector and comparator. The FPGA determines the frequency range based on the level combination and controls the analog switch and SP3T to select the corresponding channel. The frequency of the signal generated by the DDS is measured by the FPGA, and the input RF signal frequency is calculated inversely based on the division ratio and frequency control word. This invention achieves DC-20GHz ultra-wideband frequency measurement. The measurement speed depends on the DDS frequency switching speed. After the measurement is completed, the power to the divider is turned off to eliminate spurious interference. The circuit structure is simple and low-cost.

Description

Technical Field

[0001] This invention belongs to the field of frequency measurement technology, specifically, it relates to an ultra-wideband high-precision instantaneous frequency measurement circuit and frequency measurement method. Background Technology

[0002] Frequency measurement technology plays a crucial role in modern electronic systems, with widespread applications in radar, communications, and electronic warfare. With the rapid development of electronic technology, the electromagnetic environment is becoming increasingly complex, placing ever higher demands on frequency measurement technology. Especially in modern electronic warfare environments, various microwave signals change rapidly across an extremely wide frequency spectrum, and signal durations are becoming increasingly shorter, making traditional frequency measurement techniques insufficient to meet practical application requirements.

[0003] In the field of frequency measurement technology, traditional frequency measurement schemes mainly include frequency measurement techniques based on search-type superheterodyne receivers, channelization-based frequency measurement schemes, and phase detection-based receiver schemes. While these traditional schemes can achieve frequency measurement functions to a certain extent, they have significant limitations in practical applications. First, traditional schemes struggle to meet the requirements for fast frequency measurement in terms of measurement time, resulting in slow measurement speeds. Second, achieving shorter measurement times and obtaining wide frequency coverage typically requires adding a large number of channels, leading to a significant increase in system complexity, size, and cost. This contradicts the current trend of developing equipment towards miniaturization, lightweight design, and high reliability.

[0004] In modern electronic warfare, the reconnaissance and analysis of enemy radar signals requires the rapid and accurate extraction of signal characteristics such as carrier frequency, amplitude, pulse width, and repetition rate. Among these signal characteristics, carrier frequency is one of the most important parameters. However, existing conventional frequency measurement techniques generally suffer from problems such as large frequency errors, slow measurement speed, and narrow measurement bandwidth, failing to meet the stringent requirements of modern electronic warfare for rapid, accurate, and wideband frequency measurement. Especially under complex electromagnetic environments, the limitations of traditional frequency measurement techniques become even more pronounced when facing rapidly changing microwave signals across a wide frequency spectrum.

[0005] Therefore, the industry urgently needs a frequency measurement technology that can simultaneously achieve wide frequency bandwidth, high frequency accuracy, and fast frequency measurement speed, while also having a simple and low-cost frequency measurement circuit, in order to meet the application requirements of modern electronic systems for high-precision and fast frequency measurement. Summary of the Invention

[0006] The purpose of this invention is to provide a high-precision instantaneous frequency measurement circuit and method for ultra-wideband frequency measurement, which mainly solves the technical defects of existing ultra-wideband frequency measurement technology, such as narrow frequency measurement bandwidth, low frequency measurement accuracy, slow frequency measurement speed, and complex and costly frequency measurement circuits.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A high-precision instantaneous frequency measurement circuit with ultra-wideband capability includes a power divider group, multiple frequency measurement channels, an analog switch group, a direct digital frequency synthesizer, an FPGA, and a switch selection circuit, wherein:

[0009] The power divider group is used to split the input radio frequency signal into multiple signals, which are then transmitted to different frequency measurement channels for processing; each frequency measurement channel outputs a corresponding LVTTL level signal to the FPGA;

[0010] The multiple frequency measurement channels include a first frequency measurement channel, a second frequency measurement channel, a third frequency measurement channel, and a fourth frequency measurement channel. Each frequency measurement channel corresponds to a different frequency measurement range, and each frequency measurement channel works in parallel.

[0011] The FPGA determines the frequency range of the current input RF signal based on the received multiple LVTTL level signals, and controls the on / off state of the analog switch group and the selection state of the switch selection circuit accordingly.

[0012] The analog switch group is used to control the on / off state of the first frequency measurement channel and the second frequency measurement channel;

[0013] The switch selection circuit is used to select one signal from the first frequency measurement channel, the second frequency measurement channel and the third frequency measurement channel as the reference clock input for the direct digital frequency synthesizer;

[0014] The direct digital frequency synthesizer generates a frequency-programmable output signal to the FPGA under the drive of a reference clock. The FPGA calculates the frequency value of the input radio frequency signal based on the measured frequency of the direct digital frequency synthesizer output signal, combined with the division ratio of the currently selected frequency measurement channel and the frequency control word of the direct digital frequency synthesizer.

[0015] Furthermore, in this invention, the power divider group includes a first power divider to a fourth power divider; the first power divider is used to divide the radio frequency input signal into two paths, one for external output and one for input to the second power divider; the second power divider is used to divide the radio frequency signal into two paths, one for input to the third power divider and one for input to the fourth power divider; the third power divider is used to divide the radio frequency signal into two paths, one for input to the first frequency measurement channel and one for input to the second frequency measurement channel; the fourth power divider is used to divide the radio frequency signal into two paths, one for input to the third frequency measurement channel and one for input to the fourth frequency measurement channel.

[0016] Furthermore, in this invention, the first frequency measurement channel includes a 20-fold divider, a sixth power divider, a first detector, and a first comparator; the radio frequency signal is divided by the 20-fold divider, and the output signal enters the sixth power divider. The sixth power divider divides the output signal into two paths, one of which enters the first detector and the other enters the switch selection circuit. The first detector detects the signal, and the detected output voltage enters the first comparator. The first comparator compares and outputs the voltage from the first detector and feeds it back to the FPGA.

[0017] Furthermore, in this invention, the second frequency measurement channel includes a ÷2 divider, a first low-pass filter, a seventh power divider, a second detector, and a second comparator; the ÷2 divider divides the radio frequency signal, and the output signal enters the first low-pass filter, which controls the output of the highest frequency signal; the seventh power divider divides the output signal of the first low-pass filter into two paths, one of which enters the second detector and the other enters the switch selection circuit; the second detector detects the signal, and the detected output voltage enters the second comparator; the second comparator compares and detects the voltage output of the second detector and feeds it back to the FPGA.

[0018] Furthermore, in this invention, the third frequency measurement channel includes a second low-pass filter, an eighth power divider, a third detector, and a third comparator; the radio frequency signal enters the second low-pass filter, which controls the output of the highest frequency signal; the eighth power divider splits the output signal of the second low-pass filter into two paths, one of which enters the third detector and the other enters the switch selection circuit; the third detector detects the signal, and the detected output voltage enters the third comparator; the third comparator compares and outputs the voltage from the third detector and feeds it back to the FPGA.

[0019] Furthermore, in this invention, the fourth frequency measurement channel comprises a third low-pass filter, a fifth power divider, a fourth detector, and a fourth comparator; the radio frequency signal enters the third low-pass filter, which controls the output of the highest frequency signal; the fifth power divider splits the output signal of the third low-pass filter into two paths, one of which enters the fourth detector and the other enters the FPGA; the fourth detector detects the signal, and the detected output voltage enters the fourth comparator; the fourth comparator feeds back the voltage output of the fourth detector to the FPGA.

[0020] Furthermore, in this invention, the analog switch group includes a first analog switch and a second analog switch; the first analog switch is powered by a power supply through a first linear regulator, and the first analog switch controls the on / off state of the ÷20 frequency divider through an FPGA, and the first analog switch is also grounded through a resistor R1; the second analog switch is powered by a power supply through a second linear regulator, and the second analog switch controls the on / off state of the ÷2 frequency divider through an FPGA, and the second analog switch is also grounded through a resistor R2.

[0021] Furthermore, in this invention, the switch selection circuit is an SP3T switch, which is used to select one of the output signals of the first frequency measurement channel, the second frequency measurement channel, and the third frequency measurement channel as a reference clock signal for the direct digital frequency synthesizer.

[0022] This invention also provides a high-precision instantaneous frequency measurement method for ultra-wideband applications, implemented based on the aforementioned frequency measurement circuit, comprising the following steps:

[0023] S1, the FPGA receives LVTTL level signals from the outputs of four comparators;

[0024] S2, the FPGA determines the frequency range of the input radio frequency signal based on the received LVTTL level signal combination;

[0025] S3, the FPGA controls the on / off state of the analog switch group and the selection state of the switch selection circuit according to the frequency range determined in step S2;

[0026] S4, the direct digital frequency synthesizer generates an output signal to the FPGA under the drive of a reference clock input;

[0027] S5, after the frequency measurement is completed, the FPGA controls the first analog switch and the second analog switch to return to the power-off state, shuts off the power supply of the ÷20 frequency divider and the ÷2 frequency divider, and eliminates the interference of the stray signals generated by the frequency divider on subsequent measurements;

[0028] S6, the frequency measurement process has ended, waiting for the next frequency measurement trigger.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] (1) This invention employs a four-channel parallel frequency measurement architecture, dividing the ultra-wide frequency range from DC to 20GHz into four interconnected sub-bands. Each frequency measurement channel corresponds to an appropriate division ratio and filtering parameters, achieving ultra-wideband frequency coverage while avoiding the technical contradiction of bandwidth and accuracy being difficult to balance in traditional single-channel frequency measurement schemes. With each frequency measurement channel working in parallel, the FPGA can quickly determine the frequency band to which the signal belongs through multi-channel level combinations, eliminating the need for band-by-band scanning and significantly shortening the frequency determination time.

[0031] (2) This invention uses the output signal of the gating channel as the reference clock of the direct digital frequency synthesizer. Combining the high frequency resolution characteristics of the direct digital frequency synthesizer with the high-precision frequency measurement capability of the FPGA, the original RF signal frequency is obtained by inverse calculation using the frequency control word. No additional high-stability reference clock source is required, which simplifies the circuit structure and significantly improves the frequency measurement accuracy. Compared with the traditional superheterodyne frequency measurement scheme, it does not require the configuration of a large number of narrowband channels and mixing links, effectively reducing circuit complexity and hardware cost, which is in line with the development trend of miniaturization and lightweight electronic devices.

[0032] (3) This invention controls the power supply status of the frequency divider through an analog switch. After the frequency measurement is completed, the power supply of the unused or measured frequency divider is immediately turned off, eliminating the interference of spurious signals generated during the operation of the frequency divider on the receiving link from the root, and improving the frequency measurement stability in complex electromagnetic environments. At the same time, the frequency measurement speed depends only on the frequency switching speed of the direct digital frequency synthesizer. The entire frequency measurement process can be completed in microseconds, achieving instantaneous frequency measurement effect. It can effectively capture rapidly changing radio frequency signals such as frequency agile signals, meeting the application requirements of high-speed and high-precision frequency measurement in modern electronic warfare, spectrum monitoring and other scenarios. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the frequency measurement circuit of the present invention.

[0034] Figure 2 This is a flowchart of the frequency measurement method of the present invention. Detailed Implementation

[0035] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0036] like Figure 1As shown, this invention discloses an ultra-wideband high-precision instantaneous frequency measurement circuit. This circuit mainly consists of a power divider group, multiple frequency measurement channels, an analog switch group, a direct digital frequency synthesizer (DDS), an FPGA, and a switch selection circuit. The switch selection circuit is an SP3T, which selects one of the output signals from the first, second, and third frequency measurement channels as a reference clock signal for the DDS. When the RF signal to be measured is input, the RF input signal RFin first enters the first power divider. The first power divider splits the RF input signal RFin into two signals. One signal is directly output as the RF output RFO of the frequency measurement circuit for use by subsequent equipment. The other signal is transmitted to the second power divider for further distribution. The distribution ratio of the first power divider is set to 10:1, meaning that the signal power distributed to the second power divider accounts for approximately one-tenth of the total input power. This ensures that the frequency measurement branch has sufficient signal power for detection and measurement, while also allowing the output branch to retain most of its signal power for external equipment.

[0037] After receiving the RF signal from the first power divider, the second power divider also splits the signal into two paths: one path is transmitted to the third power divider, and the other path is transmitted to the fourth power divider. The third power divider further splits the received RF signal into two paths: one path is sent to a 20-way divider for frequency division, and the other path is sent to a 2-way divider for frequency division. The fourth power divider then splits the received RF signal into two paths: one path is sent to the second low-pass filter, and the other path is sent to the third low-pass filter.

[0038] Multiple frequency measurement channels include a first, second, third, and fourth frequency measurement channel, each corresponding to a different frequency range, and all channels operate in parallel. In the first frequency measurement channel, the first signal output from the third power divider is fed into a 20-divider. The 20-divider divides the input RF signal by 20 and outputs the divided signal to the sixth power divider. The 20-divider can be implemented by cascading a 4-divider and a 5-divider, first dividing the input signal by 4, then dividing the 4-divider signal by 5, finally obtaining a 20-divider output signal. The output signal frequency range of the 20-divider is 70MHz to 1000MHz, corresponding to the input RF signal frequency range of 1.4GHz to 20GHz. The sixth power divider splits the output signal of the 20-divider into two paths: one path is sent to the first detector for signal detection, and the other path is sent to the SP3T as the output signal of the first frequency measurement channel. The first detector processes the received signal, converting the radio frequency signal into a corresponding detected voltage. This detected voltage, along with a preset comparison threshold, is sent to the first comparator for comparison. The first comparator compares the detected voltage with a preset reference voltage. When the detected voltage is higher than the reference voltage, the first comparator outputs a high-level LVTTL4 signal to the FPGA, indicating that the first frequency measurement channel has detected valid signal power, meaning the input radio frequency signal frequency is in the 1.4GHz to 20GHz band. When the detected voltage is lower than the reference voltage, the first comparator outputs a low-level LVTTL4 signal to the FPGA.

[0039] In the second frequency measurement channel, the second signal output from the third power divider is fed into a 2-divider. The 2-divider divides the input RF signal by 2 and outputs the divided signal to the first low-pass filter. The first low-pass filter is a MINI LFCG-700+ low-pass filter with a cutoff frequency of 700MHz. Its function is to filter out high-frequency image components and other spurious signals from the output signal of the 2-divider, ensuring that the output signal frequency range is 70MHz to 700MHz, corresponding to the input RF signal frequency range of 140MHz to 1.4GHz. The output signal of the first low-pass filter is fed into the seventh power divider, which splits the signal into two paths. One path is sent to the second detector for signal detection, and the other path is sent to the SP3T as the output signal of the second frequency measurement channel. The second detector performs detection processing on the received signal, converting the RF signal into a corresponding detection voltage. This detection voltage is then compared with a preset comparison threshold by the second comparator. The second comparator compares the detected voltage with a preset reference voltage. When the detected voltage is higher than the reference voltage, the second comparator outputs a high-level LVTTL3 signal to the FPGA, indicating that the second frequency measurement channel has detected effective signal power, that is, the input RF signal frequency is in the 140MHz to 1.4GHz band.

[0040] In the third frequency measurement channel, the first signal output from the fourth power divider is fed into the second low-pass filter. This second low-pass filter is an LC low-pass filter with a cutoff frequency of 140MHz. Its function is to extract the signal components in the 70MHz to 140MHz frequency band from the input RF signal, filtering out signal components below 70MHz and above 140MHz. The output signal of the second low-pass filter is fed into the eighth power divider, which splits the signal into two paths. One path is fed into the third detector for signal detection, and the other path is fed into the SP3T as the output signal of the third frequency measurement channel. The third detector performs detection processing on the received signal, converting the RF signal into a corresponding detection voltage. This detection voltage is then compared with a preset comparison threshold by the third comparator. The third comparator compares the detection voltage with a preset reference voltage. When the detection voltage is higher than the reference voltage, the third comparator outputs a high-level LVTTL2 signal to the FPGA, indicating that the third frequency measurement channel has detected valid signal power, meaning the input RF signal frequency is in the 70MHz to 140MHz frequency band.

[0041] In the fourth frequency measurement channel, the second signal output from the fourth power divider is fed into the third low-pass filter. This third low-pass filter is an LC low-pass filter with a cutoff frequency of 70MHz. Its function is to extract the signal components from the DC to 70MHz frequency band of the input RF signal and filter out signal components higher than 70MHz. The output signal of the third low-pass filter is fed into the fifth power divider, which splits the signal into two paths. One path is fed into the fourth detector for signal detection, and the other path is directly fed into the FPGA for frequency measurement. The fourth detector performs detection processing on the received signal, converting the RF signal into a corresponding detection voltage. This detection voltage is then compared with a preset comparison threshold by the fourth comparator. The fourth comparator compares the detection voltage with a preset reference voltage. When the detection voltage is higher than the reference voltage, the fourth comparator outputs a high-level LVTTL1 signal to the FPGA, indicating that the fourth frequency measurement channel has detected valid signal power, meaning the input RF signal frequency is in the DC to 70MHz frequency band.

[0042] The SP3T three-throw switch has three input ports and one output port. The three input ports are connected to the output signals of the first, second, and third frequency measurement channels, respectively. The output port is connected to the reference clock input of the direct digital frequency synthesizer. The SP3T switch selects one of the input signals as the reference clock for the direct digital frequency synthesizer based on the control signal output by the FPGA, while disconnecting the other two input signals.

[0043] The direct digital frequency synthesizer uses the Analog Devices AD9910BSVZ chip, which integrates a 32-bit phase accumulator and supports system clock frequency inputs from 60MHz to 1000MHz. The output signal frequency of the direct digital frequency synthesizer is determined by the frequency control word FTW, and its output frequency is calculated using the formula f. OUT =(FTW / 2 32 )×f SYSCLK , where f SYSCLK The system clock frequency is FTW, a 32-bit frequency control word with a value range of 0 to 4294967295. The output signal of the direct digital frequency synthesizer has a frequency range of DC to 100MHz, and this output signal is sent to the FPGA for frequency measurement.

[0044] The FPGA integrates a frequency measurement module, a control logic module, and a communication interface module. The frequency measurement module measures the frequency of the output signal from the direct digital frequency synthesizer, with an accuracy of ±1Hz. The control logic module determines the frequency range of the input RF signal based on the combination of LVTTL level signals output from the first to fourth comparators, and generates corresponding control signals to control the on / off states of the first and second analog switches, as well as the selection state of the SP3T. The communication interface module exchanges data with external devices, outputting the measured RF signal frequency value to external display or processing devices.

[0045] The first and second analog switches are used to control the power on / off states of the ÷20 and ÷2 frequency dividers, respectively. The FPGA controls whether the ÷20 frequency divider is powered on and off by controlling the opening and closing of the first analog switch. When frequency measurement is required using the first frequency measurement channel, the FPGA controls the first analog switch to close, providing power to the ÷20 frequency divider to enable its normal operation. After the frequency measurement is completed, the FPGA controls the first analog switch to open, cutting off the power to the ÷20 frequency divider and stopping its operation, thereby eliminating the interference of stray signals generated by the ÷20 frequency divider on subsequent measurements. The second analog switch operates on the same principle as the first analog switch, controlling the power on / off state of the ÷2 frequency divider; the first analog switch is also grounded through resistor R1, and the second analog switch is grounded through resistor R2.

[0046] like Figure 2 As shown, the frequency measurement method of the present invention includes the following specific steps:

[0047] At the start of the frequency measurement process, the FPGA first receives LVTTL level signals from four comparators. The FPGA receives LVTTL1 level signals from the fourth comparator, LVTTL2 level signals from the third comparator, LVTTL3 level signals from the second comparator, and LVTTL4 level signals from the first comparator through four parallel input ports. These four LVTTL level signals represent the signal power status detected by each of the four frequency measurement channels; a high level indicates that a valid signal has been detected by the corresponding channel, and a low level indicates that a valid signal has not been detected by the corresponding channel.

[0048] After receiving four LVTTL level signals, the FPGA determines the frequency range of the input RF signal based on the combination of the received LVTTL level signals. The specific determination logic is as follows: When all four level signals LVTTL1, LVTTL2, LVTTL3, and LVTTL4 are high, it indicates that the fourth frequency measurement channel has detected a valid signal. Since the frequency measurement range of the fourth frequency measurement channel is DC to 70MHz, the frequency of the input RF signal is determined to be in the DC to 70MHz band. When LVTTL1 is low and all three level signals LVTTL2, LVTTL3, and LVTTL4 are high, it indicates that the fourth frequency measurement channel has not detected a valid signal, but the third frequency measurement channel has detected a valid signal. Since the frequency measurement range of the third frequency measurement channel is 70MHz to 140MHz, the frequency of the input RF signal is determined to be in the 70MHz to 140MHz band. When LVTTL1 and LVTTL2 are both low and LVTTL3 and LVTTL4 are both high, it indicates that the third and fourth frequency measurement channels have not detected a valid signal, while the second frequency measurement channel has detected a valid signal. Since the frequency measurement range of the second frequency measurement channel is 140MHz to 1.4GHz, the frequency of the input RF signal is determined to be in the 140MHz to 1.4GHz band. When LVTTL1, LVTTL2, and LVTTL3 are all low and LVTTL4 is high, it indicates that the first three frequency measurement channels have not detected a valid signal, while the first frequency measurement channel has detected a valid signal. Since the frequency measurement range of the first frequency measurement channel is 1.4GHz to 20GHz, the frequency of the input RF signal is determined to be in the 1.4GHz to 20GHz band. When all four LVTTL signals are low, it indicates that no valid signal has been detected, and the frequency measurement process enters standby mode.

[0049] After determining the frequency range, the FPGA controls the on / off state of the analog switch and the selection state of the switch selection circuit based on the determined frequency range. The specific control logic is as follows:

[0050] When the input RF signal frequency is determined to be within the DC to 70MHz band, the FPGA controls both the first and second analog switches to be in the open state, cutting off the power to the ÷20 and ÷2 dividers, and simultaneously not outputting a strobe signal to the SP3T, keeping the SP3T in its initial state. At this time, the signal from the fourth frequency measurement channel is directly transmitted to the FPGA for frequency measurement.

[0051] When the input RF signal frequency is determined to be within the 70MHz to 140MHz band, the FPGA controls both the first and second analog switches to be in the open state, cutting off the power to the ÷20 and ÷2 dividers. Simultaneously, it outputs a control signal to the SP3T, enabling it to select the output signal of the third frequency measurement channel as the reference clock input for the direct digital frequency synthesizer. At this time, the 70MHz to 140MHz band signal of the third frequency measurement channel serves as the reference clock for the direct digital frequency synthesizer. Driven by this reference clock, the direct digital frequency synthesizer generates an output signal to the FPGA for frequency measurement.

[0052] When the input RF signal frequency is determined to be in the 140MHz to 1.4GHz band, the FPGA controls the first analog switch to be in the open state, cutting off the power to the ÷20 divider, and simultaneously controls the second analog switch to be in the closed state, providing power to the ÷2 divider to enable its normal operation. The FPGA also outputs a control signal to the SP3T, enabling it to select the output signal of the second frequency measurement channel as the reference clock input for the direct digital frequency synthesizer. At this time, the 140MHz to 1.4GHz band signal of the second frequency measurement channel is divided by the ÷2 divider to obtain a 70MHz to 700MHz band signal. This signal serves as the reference clock for the direct digital frequency synthesizer, which, driven by this reference clock, generates an output signal to the FPGA for frequency measurement.

[0053] When the input RF signal frequency is determined to be in the 1.4GHz to 20GHz band, the FPGA controls the first analog switch to be closed, providing power to the ÷20 divider to ensure its normal operation. Simultaneously, it controls the second analog switch to be open, cutting off power to the ÷2 divider. The FPGA also outputs a control signal to the SP3T, enabling it to select the output signal of the first frequency measurement channel as the reference clock input for the direct digital frequency synthesizer. At this time, the 1.4GHz to 20GHz band signal from the first frequency measurement channel is divided by the ÷20 divider to obtain a 70MHz to 1000MHz band signal. This signal serves as the reference clock for the direct digital frequency synthesizer, which, driven by this reference clock, generates an output signal to the FPGA for frequency measurement.

[0054] After the FPGA completes the above control operations, it measures the frequency of the output signal of the direct digital frequency synthesizer and calculates the frequency of the input radio frequency signal based on the division ratio of the current frequency measurement channel and the frequency control word of the direct digital frequency synthesizer.

[0055] For frequency measurement in the DC to 70MHz band, the FPGA directly measures the frequency of the signal from the fourth frequency measurement channel, and the measured frequency value f1 is the frequency f of the input RF signal. RFin The calculation formula is f RFin =f1.

[0056] For frequency measurement in the 70MHz to 140MHz band, the FPGA first configures a fixed frequency control word NDDS for the direct digital frequency synthesizer, and then measures the frequency f1 of the direct digital frequency synthesizer's output signal. Since the formula for calculating the output frequency of the direct digital frequency synthesizer is f1 = (N... DDS / 2 32 )×(f RFin / 2), therefore, the formula for calculating the frequency of the input RF signal is f. RFin =2 32 ×f1 / N DDS The division by 2 is because the signal from the third frequency measurement channel needs to be divided by 2 when used as a reference clock.

[0057] For frequency measurement in the 140MHz to 1.4GHz band, the FPGA first configures a fixed frequency control word N for the direct digital frequency synthesizer. DDS Then, the frequency f1 of the output signal of the direct digital frequency synthesizer is measured. Since the formula for calculating the output frequency of the direct digital frequency synthesizer is f1 = (N... DDS / 2 32 )×(f RFin / 2), where f RFin The original input frequency before being divided by the ÷2 divider is given by the formula for calculating the frequency of the input RF signal: f. RFin =2 32 ×f1 / N DDS ×2. The reason for multiplying by 2 is that the frequency division factor of the divider needs to be compensated by ÷2.

[0058] For frequency measurement in the 1.4GHz to 20GHz band, the FPGA first configures a fixed frequency control word NDDS for the direct digital frequency synthesizer, and then measures the frequency f1 of the direct digital frequency synthesizer's output signal. The formula for calculating the output frequency of the direct digital frequency synthesizer is f1 = (N... DDS / 2 32 )×(f RFin / 20), where f RFin The original input frequency before being divided by the ÷20 divider is given by the formula for calculating the frequency of the input RF signal: f. RFin =2 32 ×f1 / N DDS ×20. The reason for multiplying by 20 is that the frequency division factor of the divider needs to be compensated by ÷20.

[0059] After the FPGA completes the frequency calculation, it controls the first and second analog switches to return to the off state, cutting off the power supply to the ÷20 divider and the ÷2 divider, thus eliminating the interference of stray signals generated by the dividers on subsequent measurements.

[0060] Finally, the frequency measurement process ends, and we wait for the next frequency measurement trigger signal.

[0061] To verify the frequency measurement accuracy of the frequency measurement circuit of this invention, a detailed explanation is provided using an input radio frequency signal frequency of 20 GHz as an example. The 20 GHz radio frequency signal is divided by a 20 divider to obtain a 1000 MHz signal, which serves as the system clock f of the direct digital frequency synthesizer. SYSCLK The frequency resolution of a direct digital frequency synthesizer is equal to the system clock frequency divided by 2. 32 That is, 1000 / 2 32 ≈0.00000023MHz. The FPGA sets the frequency control word FTW of the direct digital frequency synthesizer to a fixed 429496729, which is 2. 32 The quotient divided by 5 is a commonly used fixed value. The formula for calculating the output frequency of a direct digital frequency synthesizer is f1 = (FTW / 2) / 5. 32 )×f SYSCLK =(429496729 / 2 32 )×(20000 / 20)≈99.9999999MHz. The FPGA calculates the input RF signal frequency based on the measured f1, using the formula f RFin =2 32 ×f1 / N DDS ×20=2 32 ×99.9999999 / 429496729×20≈20.0000000079GHz. The frequency measurement error is 20.0000000079GHz-20GHz=0.0000000079GHz=7.9Hz. This error is much smaller than that of traditional frequency measurement schemes and meets the technical requirements for high-precision frequency measurement.

[0062] The frequency measurement speed of the frequency measurement circuit of this invention depends on the frequency switching speed of the direct digital frequency synthesizer. The frequency switching time of the direct digital frequency synthesizer is less than 1μs. Therefore, the completion time of the entire frequency measurement process can be controlled within a few microseconds, achieving the technical effect of instantaneous frequency measurement.

[0063] In specific application scenarios, the frequency measurement circuit of this invention can be applied to radar signal reconnaissance systems in electronic warfare. When the radio frequency signal emitted by an enemy radar enters the frequency measurement circuit, the circuit completes a precise measurement of the signal frequency within microseconds and transmits the measurement result to the backend signal sorting and identification system. The wide bandwidth coverage of the frequency measurement circuit allows it to simultaneously cover all radar signal frequency bands from DC to 20GHz, its high-precision frequency measurement capability enables it to accurately identify the operating frequencies of different radars, and its fast frequency measurement capability allows it to capture frequency-agile radar signals with rapid frequency jumps. After the frequency measurement is completed, the frequency divider power supply is automatically turned off, avoiding interference from spurious signals generated by the frequency divider to the radar signal receiving link, thus ensuring the overall performance of the reconnaissance system.

[0064] The frequency measurement circuit of this invention can also be applied to frequency monitoring and spectrum management scenarios in communication systems. In communication base stations or radio monitoring stations, the frequency measurement circuit can monitor the frequency of radio frequency signals in space in real time, providing accurate data support for spectrum planning and management. Due to its wide bandwidth, high precision, and fast frequency measurement characteristics, the frequency measurement circuit can meet the stringent requirements of modern communication systems for spectrum monitoring.

[0065] In summary, the ultra-wideband high-precision instantaneous frequency measurement circuit provided by this invention, through a four-channel parallel processing architecture, divides the ultra-wide frequency measurement band from 1.4 GHz to 20 GHz into four sub-bands for separate processing. Each sub-band employs an adapted frequency measurement strategy, achieving accurate and rapid frequency measurement across the entire frequency band from DC to 20 GHz. This frequency measurement circuit possesses technical advantages such as wide frequency bandwidth, high frequency accuracy, fast frequency measurement speed, simple circuitry, and low cost, and can meet the requirements of modern electronic warfare and communication systems for high-performance frequency measurement technology.

[0066] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. A high-precision instantaneous frequency measurement circuit with ultra-wideband capability, characterized in that, It includes a power divider group, multiple frequency measurement channels, an analog switch group, a direct digital frequency synthesizer, an FPGA, and a switch selection circuit, among which: The power divider group is used to split the input radio frequency signal into multiple signals, which are then transmitted to different frequency measurement channels for processing; each frequency measurement channel outputs a corresponding LVTTL level signal to the FPGA; The multiple frequency measurement channels include a first frequency measurement channel, a second frequency measurement channel, a third frequency measurement channel, and a fourth frequency measurement channel. Each frequency measurement channel corresponds to a different frequency measurement range, and each frequency measurement channel works in parallel. The FPGA determines the frequency range of the current input RF signal based on the received multiple LVTTL level signals, and controls the on / off state of the analog switch group and the selection state of the switch selection circuit accordingly. The analog switch group is used to control the on / off state of the first frequency measurement channel and the second frequency measurement channel; The switch selection circuit is used to select one signal from the first frequency measurement channel, the second frequency measurement channel and the third frequency measurement channel as the reference clock input for the direct digital frequency synthesizer; The direct digital frequency synthesizer generates a frequency-programmable output signal to the FPGA under the drive of a reference clock. The FPGA calculates the frequency value of the input radio frequency signal based on the measured frequency of the direct digital frequency synthesizer output signal, combined with the division ratio of the currently selected frequency measurement channel and the frequency control word of the direct digital frequency synthesizer.

2. The ultra-wideband high-precision instantaneous frequency measurement circuit according to claim 1, characterized in that, The power divider group includes a first power divider to a fourth power divider; the first power divider is used to divide the radio frequency input signal into two paths, one for output and one for input to the second power divider; the second power divider is used to divide the radio frequency signal into two paths, one for input to the third power divider and one for input to the fourth power divider; the third power divider is used to divide the radio frequency signal into two paths, one for input to the first frequency measurement channel and one for input to the second frequency measurement channel; the fourth power divider is used to divide the radio frequency signal into two paths, one for input to the third frequency measurement channel and one for input to the fourth frequency measurement channel.

3. The ultra-wideband high-precision instantaneous frequency measurement circuit according to claim 2, characterized in that, The first frequency measurement channel includes a 20-fold divider, a sixth power divider, a first detector, and a first comparator. The radio frequency signal is divided by the 20-fold divider, and the output signal enters the sixth power divider. The sixth power divider divides the output signal into two paths: one path enters the first detector, and the other path enters the switch selection circuit. The first detector detects the signal, and the detected output voltage enters the first comparator. The first comparator compares the voltage output from the first detector and feeds it back to the FPGA.

4. The ultra-wideband high-precision instantaneous frequency measurement circuit according to claim 2, characterized in that, The second frequency measurement channel includes a ÷2 divider, a first low-pass filter, a seventh power divider, a second detector, and a second comparator. The ÷2 divider divides the radio frequency signal, and the output signal enters the first low-pass filter. The first low-pass filter controls the output of the highest frequency signal. The seventh power divider splits the output signal of the first low-pass filter into two paths: one path enters the second detector, and the other path enters the switch selection circuit. The second detector detects the signal, and the detected output voltage enters the second comparator. The second comparator compares the voltage output of the second detector and feeds it back to the FPGA.

5. The ultra-wideband high-precision instantaneous frequency measurement circuit according to claim 2, characterized in that, The third frequency measurement channel includes a second low-pass filter, an eighth power divider, a third detector, and a third comparator. The radio frequency signal enters the second low-pass filter, which controls the output of the highest frequency signal. The eighth power divider splits the output signal of the second low-pass filter into two paths: one path enters the third detector, and the other path enters the switch selection circuit. The third detector detects the signal, and the detected output voltage enters the third comparator. The third comparator compares the voltage output of the third detector and feeds it back to the FPGA.

6. The ultra-wideband high-precision instantaneous frequency measurement circuit according to claim 2, characterized in that, The fourth frequency measurement channel consists of a third low-pass filter, a fifth power divider, a fourth detector, and a fourth comparator. The radio frequency signal enters the third low-pass filter, which controls the output of the highest frequency signal. The fifth power divider splits the output signal of the third low-pass filter into two paths: one path enters the fourth detector, and the other path enters the FPGA. The fourth detector detects the signal, and the detected output voltage enters the fourth comparator. The fourth comparator compares the voltage output of the fourth detector and feeds it back to the FPGA.

7. The ultra-wideband high-precision instantaneous frequency measurement circuit according to claim 6, characterized in that, The analog switch group includes a first analog switch and a second analog switch; the first analog switch is powered by a power supply through a first linear regulator, and the first analog switch is controlled by an FPGA to turn on and off a ÷20 frequency divider, and the first analog switch is also grounded through a resistor R1; the second analog switch is powered by a power supply through a second linear regulator, and the second analog switch is controlled by an FPGA to turn on and off a ÷2 frequency divider, and the second analog switch is also grounded through a resistor R2.

8. The ultra-wideband high-precision instantaneous frequency measurement circuit according to claim 7, characterized in that, The switch selection circuit is an SP3T switch, which is used to select one of the output signals of the first frequency measurement channel, the second frequency measurement channel, and the third frequency measurement channel as a reference clock signal for the direct digital frequency synthesizer.

9. A high-precision instantaneous frequency measurement method for ultra-wideband networks, characterized in that, This is based on the ultra-wideband high-precision instantaneous frequency measurement circuit described in claim 8. Includes the following steps: S1, the FPGA receives LVTTL level signals from the outputs of four comparators; S2, the FPGA determines the frequency range of the input radio frequency signal based on the received LVTTL level signal combination; S3, the FPGA controls the on / off state of the analog switch group and the selection state of the switch selection circuit according to the frequency range determined in step S2; S4, the direct digital frequency synthesizer generates an output signal to the FPGA under the drive of a reference clock input; S5, after the frequency measurement is completed, the FPGA controls the first analog switch and the second analog switch to return to the power-off state, shuts off the power supply of the ÷20 frequency divider and the ÷2 frequency divider, and eliminates the interference of the stray signals generated by the frequency divider on subsequent measurements; S6, the frequency measurement process has ended, waiting for the next frequency measurement trigger.

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