Light emitting diode epitaxial wafer and method of manufacturing the same

Abstract

This invention relates to the field of light-emitting diode (LED) technology and discloses an epitaxial wafer for an LED and its fabrication method. The fabrication method includes the following steps: (1) providing a substrate; (2) depositing an epitaxial layer on the substrate; (3) dry etching the epitaxial layer to form a patterned structure with etched sidewalls; (4) forming a passivation layer in situ on the etched sidewalls of the patterned structure; wherein, forming the passivation layer in situ includes: maintaining a gas atmosphere of N2 and / or NH3 under conditions of 300℃-600℃ and 50mbar-500mbar, introducing a boron source and a phosphorus source for plasma treatment, and generating the passivation layer in situ at the sidewalls. By implementing this application, the formed passivation layer can replenish nitrogen vacancies, significantly reduce carrier trap concentration, passivate residual Ga dangling bonds, wrap the repair layer surface, reduce defect stress, and prevent the re-adsorption of oxygen or water vapor in the atmosphere.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and in particular to a light-emitting diode epitaxial wafer and its fabrication method. Background Technology

[0002] Third-generation semiconductors have shown broad application prospects in fields such as semiconductor lighting, power electronics, and new energy. They possess excellent physical and chemical properties, such as high melting point, strong chemical inertness, high thermal conductivity, high hardness, and high breakdown electric field strength, and are used to manufacture various LED light-emitting devices. Compared with traditional devices, these LED light-emitting devices have outstanding characteristics such as high stability, long service life, and low energy consumption.

[0003] In the fabrication of third-generation semiconductor LED devices, the formation of patterned structures is a crucial step that determines device performance. Dry etching, with its advantages of high etching precision and strong process controllability, has become the core process for realizing device patterning. However, during dry etching, the bombardment of high-energy ions can cause lattice damage to the device sidewalls, resulting in defects such as nitrogen vacancies and dislocations, while also causing surface contamination problems such as polymer residues and natural oxide layers.

[0004] To address the aforementioned issues of etched sidewall damage and surface contamination, existing technologies often employ a single process, primarily including wet cleaning, thermal annealing, or thin-film passivation. These repair methods suffer from incomplete repair, compatibility issues, and difficulty in simultaneously achieving stress compensation and interface state control. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an epitaxial wafer of a light-emitting diode and its preparation method, which can significantly reduce the carrier trap concentration, reduce defect stress, reduce leakage risk, prevent the re-adsorption of oxygen or water vapor in the atmosphere, and improve the electrical and optical performance of the device.

[0006] To address the aforementioned technical problems, the first aspect of this invention provides a method for fabricating a light-emitting diode epitaxial wafer, comprising the following steps: (1) Provide a substrate; (2) Deposit an epitaxial layer on the substrate; (3) Dry etching is performed on the epitaxial layer to form a patterned structure with etched sidewalls; (4) A passivation layer is formed in situ on the etched sidewall of the patterned structure; The in-situ passivation layer includes: The in-situ formation of the passivation layer includes: Under conditions of 300℃-600℃ and 50mbar-500mbar, with the gas atmosphere being N2 and / or NH3, a boron source and a phosphorus source are introduced for plasma treatment to generate a passivation layer in situ on the sidewall.

[0007] As an improvement to the above scheme, the in-situ formation of the passivation layer further includes: performing rapid thermal annealing on the formed passivation layer.

[0008] As an improvement to the above scheme, the annealing temperature of the rapid thermal annealing treatment is 400℃-500℃, the annealing rate is 5℃ / s-20℃ / s, and the time is 30s-300s.

[0009] As an improvement to the above scheme, the ratio of the total flow rate of the boron source and phosphorus source to the total flow rate of the gas is 1:(10-100).

[0010] As an improvement to the above scheme, the flow rate ratio of the boron source to the phosphorus source is 1:(0.1-10), and the flow time is 20s-1000s.

[0011] As an improvement to the above scheme, the flow rate of the boron source is 1 sccm-10 sccm; The flow rate of the phosphorus source is 1 sccm-30 sccm.

[0012] As an improvement to the above scheme, the gas atmosphere is N2 and NH3, the flow rate ratio of N2 and NH3 is 2:1-8:1, and the introduction time is 30s-10min.

[0013] As an improvement to the above scheme, the flow rate of N2 is 40 sccm-1600 scssm; The flow rate of NH3 is 20 sccm-200 sccm.

[0014] As an improvement to the above scheme, the thickness of the passivation layer is 3nm-10nm.

[0015] A second aspect of the present invention provides a light-emitting diode epitaxial wafer, which is prepared according to the aforementioned preparation method.

[0016] Implementing this invention has the following beneficial effects: In this invention, a passivation layer is grown in situ by plasma treatment using boron and phosphorus sources on the etched sidewalls of the epitaxial layer. This process replenishes nitrogen vacancies, restores lattice periodicity, reduces defect stress, significantly lowers carrier trap concentration, and passivates residual Ga dangling bonds, encapsulating the repair layer surface and preventing the re-adsorption of oxygen or water vapor from the atmosphere. Phosphorus radicals (P·) generated during the process are the primary force filling nitrogen vacancies. Since P and N are both Group V elements, P atoms entering nitrogen vacancies provide an electronic density of states comparable to N, compensating for the donor levels (i.e., leakage channels) originally introduced by nitrogen vacancies and reducing leakage rate. Boron radicals (B·) generated during the process, due to their high reactivity, strong electronegativity, and small atomic radius, can efficiently bond with Ga dangling bonds to form stable B-Ga or BN networks. Boron radicals can also enter some nitrogen vacancies, but because of the large difference in atomic radii between B and N, their main role is not simply filling, but rather subsequent bond stabilization. Compared to conventional H passivation, the B passivation in this application forms chemical bonds with higher energy and better thermal stability, which can effectively improve the electrical and optical performance of the device. Attached Figure Description

[0017] Figure 1 : A schematic diagram of the structure of a light-emitting diode epitaxial wafer in this invention.

[0018] Figure reference numerals: 1-substrate; 2-epitaxy layer; 21-N-type semiconductor layer; 22-multiple quantum well layer; 23-P-type semiconductor layer; 3-patterned structure; 4-passivation layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments.

[0020] In the description of this application, it is necessary to understand that the orientation or positional relationship indicated by terms such as "upper", "lower", "top", "bottom", "inner", and "outer" are based on the orientation or positional relationship shown in the accompanying drawings. They are intended only to facilitate the description of the present invention and to simplify the description, and are not intended to indicate or imply that the components referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0021] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of the particular range. The range defined in this way can include or exclude endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range.

[0022] To address the above problems, the first aspect of this invention provides a method for fabricating a light-emitting diode epitaxial wafer, comprising the following steps: (1) Provide a substrate 1; (2) An epitaxial layer 2 is deposited on the substrate 1; (3) Dry etching is performed on the epitaxial layer 2 to form a patterned structure 3 with etched sidewalls; (4) A passivation layer 4 is formed in situ on the etched sidewall of the patterned structure 3; In the plasma-etched sidewalls of GaN, AlGaN, and InGaN, nitrogen atoms, due to their light weight, are preferentially bombarded and escape, forming a large number of nitrogen vacancies. After the formation of nitrogen vacancies, the coordinated Ga atoms lose charge compensation, generating unbonded dangling bonds, introducing deep energy levels in the band gap, and becoming nonradiative recombination centers.

[0023] In this invention, a passivation layer 4 is grown in situ by introducing boron and phosphorus sources into the etched sidewalls of the epitaxial layer 2 for plasma treatment. This process replenishes nitrogen vacancies, restores lattice periodicity, significantly reduces carrier trap concentration, passivates residual Ga dangling bonds, and encapsulates the surface of the repair layer to prevent the re-adsorption of oxygen or water vapor from the atmosphere. Phosphorus radicals (P·) generated during the process are the main force for filling nitrogen vacancies. P and N are both Group V elements; after a P atom enters a nitrogen vacancy, it can provide an electronic state density comparable to that of N, compensating for the donor levels (i.e., leakage channels) originally introduced by the nitrogen vacancy. The repair effect is better than simply passivating with O or Cl. Boron radicals (B·) generated during the process, due to their high reactivity, strong electronegativity, and small atomic radius, can efficiently bond with Ga dangling bonds to form a stable B-Ga or BN network. Boron radicals can also enter some nitrogen vacancies, reducing non-radiative recombination centers and improving luminescence efficiency. However, because of the large difference in atomic radii between B and N, their main role is not simply filling, but rather subsequent bond stabilization. Compared to conventional H passivation, the B passivation in this application forms chemical bonds with higher energy and better thermal stability.

[0024] Specifically, in step (1), the substrate 1 can be a silicon substrate, a sapphire substrate, a silicon carbide substrate, a GaN substrate, etc.

[0025] Specifically, in step (2), the epitaxial layer 2 includes at least an N-type semiconductor layer 21, a multi-quantum well layer 22 and a P-type semiconductor layer 23 stacked sequentially, and may also include a current spreading layer, an ohmic contact layer and other multi-layer structures, which are not specifically limited here.

[0026] The following description uses the epitaxial layer 2, which includes an N-type semiconductor layer 21, a multiple quantum well layer 22, and a P-type semiconductor layer 23 stacked sequentially, as an example.

[0027] Specifically, depositing the epitaxial layer 2 on the substrate 1 includes: (21) An N-type semiconductor layer 21 is deposited on the substrate 1; In this step, the N-type semiconductor layer 21 can be a GaN layer doped with an N-type dopant. The thickness of the N-type semiconductor layer 21 is 1.0 μm-3.0 μm, and the doping concentration of the N-type dopant is 5 × 10⁻⁶. 17 atoms / cm 3 -1×10 19 atoms / cm 3 Among them, N-type dopants include, but are not limited to, Si.

[0028] Specifically, the temperature of the reaction chamber is controlled at 1000℃-1200℃ and the pressure is 150-230 torr. A Ga source, an N source, and an N-type dopant are introduced to grow an N-type doped GaN semiconductor layer on the substrate 1.

[0029] (22) Deposit a multi-quantum-well layer 22 on the N-type semiconductor layer 21; In this step, the multiple quantum well layer 22 is formed by periodically alternating quantum barrier layers and quantum well layers, with a period number greater than or equal to 8. The quantum barrier layer can be a GaN layer, and the quantum well layer can be an InGaN layer. In a single period, the thickness of the quantum well layer is 2nm-4nm, and the thickness of the quantum barrier layer is 8nm-12nm.

[0030] Specifically, the temperature of the reaction chamber is controlled at 760℃-800℃ and the pressure at 150 torr-250 torr, and In source, Ga source and N source are introduced to grow an InGaN multiple quantum well layer; then the temperature of the reaction chamber is adjusted to 860℃-900℃ and the pressure to 150 torr-250 torr, and Ga source and N source are introduced to grow a GaN quantum barrier layer, thus forming one cycle; then the above steps are repeated according to the preset number of alternating cycles to grow an InGaN / GaN multiple quantum well layer on the N-type semiconductor layer 21.

[0031] (33) Deposit a P-type semiconductor layer 23 on the multi-quantum-well layer 22; In this step, the P-type semiconductor layer 23 can be a GaN layer doped with a P-type dopant, the thickness of the P-type semiconductor layer 23 is 15nm-20nm, and the doping concentration of the P-type dopant is 5×10⁻⁶. 18 atoms / cm 3 -5×10 21 atoms / cm 3 Among them, P-type dopants include, but are not limited to, Mg.

[0032] Specifically, the temperature of the reaction chamber is controlled at 980℃-1050℃ and the pressure is 100-250 torr. A Ga source, an N source, and a P-type dopant are introduced in an H2 atmosphere to grow a P-type doped GaN semiconductor layer on the multi-quantum well layer 22.

[0033] It should be noted that in this invention, TEGa (triethylgallium) is used as the Ga source, TMIn (trimethylindium) is used as the In source, NH3 (high-purity ammonia) is used as the N source, Si2H6 (ethoxysilane) is used as the Si source, and CP2Mg is used as the Mg source.

[0034] It is understood that the deposition process of the epitaxial layer 2 can be prepared by deposition method or other existing known methods, such as metal-organic chemical vapor deposition (MOCVD), which will not be described in detail in this document.

[0035] Specifically, in step (3), the epitaxial layer 2 is dry-etched to form a patterned structure 3 with etched sidewalls, which specifically includes: (31) A SiO2 layer is deposited on the surface of the epitaxial layer 2, and then photoresist is coated on the surface of the SiO2 layer. After exposure and development, the exposed part is dry etched, and finally the photoresist is removed to form a patterned mask. In this step, the deposited SiO2 layer can be used as a hard mask. The deposition thickness of the SiO2 layer is 100nm-500nm. The deposition process of the SiO2 layer includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD). The growth temperature of the SiO2 layer is 250℃-300℃, and the growth pressure is 800mtorr-1200mtorr.

[0036] In some specific and preferred embodiments, step (31) specifically includes: spin-coating positive photoresist on the surface of the SiO2 layer, heating and curing it, exposing it to the mask, immersing it in developer, rinsing it with deionized water, and drying it with nitrogen to obtain a photoresist pattern; then using dry etching to etch the SiO2 layer, transferring the photoresist pattern onto the SiO2 layer, and using O2 plasma ashing to remove residual photoresist to obtain a patterned mask.

[0037] Optionally, the coating thickness of the positive photoresist is 1μm-3μm, the spin coating speed is 3000rpm-6000rpm, the curing temperature is 90℃-110℃, and the curing time is 60s-90s. An exemplary positive photoresist may be AZ5214E; the exposure energy may be 50mJ / cm². 2 -150mJ / cm 2The soaking time of the developer can be 30s-90s; the developer can be, for example, AZ 400K (1:4).

[0038] Optionally, the SiO2 layer is etched using dry etching. Specifically, during the dry etching process, the etching gases are CF3 and Ar, with a CF3 to Ar flow rate ratio of 1:2 to 1:4, an etching power of 200W to 500W, and a pressure of 5mTorr to 20mTorr. The dry etching process includes, but is not limited to, RIE etching and ICP etching. (32) Perform nanoimprint patterning on the patterned mask to obtain an etched mask; In this step, a SiO2 nanopillar patterned mask is used as a rigid template for nanoimprint patterning to obtain an etching mask. The pressure during the nanoimprint patterning process is 5MPa-10MPa.

[0039] (33) A mixture of CH4 and H2 gas is introduced to perform RIE etching on the sample obtained in step (3) and the etching mask is removed to form a patterned structure 3 with etched sidewalls.

[0040] In this step, the sample obtained in step (32) can be etched by dry etching to obtain patterned structure 3. The dry etching can be one or more of N-electrode etching, ICP etching, and RIE etching. The patterned structure 3 can be a nanopillar.

[0041] Furthermore, the sample obtained in step (32) can be etched using RIE etching to obtain the patterned structure 3. Specifically, the sample obtained in step (32) is placed in a RIE chamber, and a mixture of CH4 and H2 gas is introduced to etch the sample downwards, thereby obtaining the patterned structure 3 with etched sidewalls. It is understood that the etching depth when etching the sample downwards needs to be less than the thickness of the epitaxial layer 2, just enough to expose the sidewalls. The specific etching depth can be reasonably adjusted according to the actual situation. For example, the sample can be etched downwards until the N-type semiconductor layer 21 is exposed.

[0042] In some specific and preferred embodiments, the total flow rate of the mixed gas is 30 sccm-40 sccm, wherein the flow rate ratio of CH4 to H2 is (1.5-2.5):1, the etching power is 190W-210W, and the etching pressure is 2Pa-3Pa.

[0043] In some specific and preferred embodiments, the etching depth of the patterned structure 3 is 750nm-900nm, and can be 750nm, 775nm, 800nm, 825nm, 850nm, 875nm, or 900nm, but is not limited thereto.

[0044] Specifically, step (4) includes: maintaining a gas atmosphere of N2 and / or NH3 at a temperature of 300℃-600℃ and a pressure of 50mbar-500mbar, and introducing boron and phosphorus sources for plasma treatment to generate a passivation layer 4 in situ on the sidewall. The formed boron free radicals and phosphorus free radicals work synergistically to simultaneously meet the dual requirements of "deep energy level compensation" and "dense surface passivation", which is especially useful for AlGaN and InGaN sidewalls with high Al content, because the Al-N and In-N bond energies are relatively weak, the etched damage layer is usually thicker, and the effect of using single phosphorus passivation or boron passivation is poor. In this invention, the temperature of 300℃-600℃ and the pressure of 50mbar-500mbar are selected so as to fully pyrolyze and generate B· / P· free radicals, control the growth rate, promote the formation of dense film, and avoid thermal damage to the AlGaN / InGaN barrier layer or MQW structure, which would lead to In precipitation.

[0045] Preferably, the ratio of the total flow rate of the boron and phosphorus sources to the total flow rate of the gas is 1:(10-100), which can promote the formation of sufficient boron and phosphorus free radicals, thereby better passivating and repairing the etched sidewalls. If the ratio of the total flow rate of the boron and phosphorus sources to the total flow rate of the gas is less than 1:10, insufficient free radicals are generated, resulting in poor repair effect. If the ratio of the total flow rate of the boron and phosphorus sources to the total flow rate of the gas is greater than 1:100, bulk impurities are easily introduced. Exemplarily, the ratio of the total flow rate of the boron and phosphorus sources to the total flow rate of the gas is 1:10, 1:20, 1:30, 1:40, 1:50, 1:60, 1:70, 1:80, 1:90, or 1:100, but is not limited to these.

[0046] Furthermore, the flow rate ratio of the boron source to the phosphorus source is 1:(0.1-10), and the flow time is 30-300s. When the boron source flow rate is relatively large, a BN protective layer can be formed, resulting in high reliability and suitability for high-voltage LED epitaxial structures. When the phosphorus source flow rate is relatively large, it can focus more on replenishing N vacancies, compensating for charge, and suppressing current collapse.

[0047] In some specific and preferred embodiments, the flow rate of the boron source is 1 sccm-10 sccm. Exemplarily, the flow rate of the boron source is 1 sccm, 2 sccm, 4 sccm, 6 sccm, 8 sccm, or 10 sccm, but is not limited thereto. The boron source can be diborane (B₂H₆), carborane, etc.

[0048] In some specific and preferred embodiments, the flow rate of the phosphorus source is 1 sccm-30 sccm. Exemplarily, the flow rate of the phosphorus source is 1 sccm, 5 sccm, 10 sccm, 20 sccm, or 30 sccm, but is not limited thereto. The phosphorus source can be phosphine (PH3), tert-butylphosphine, trimethylphosphine, etc.

[0049] Furthermore, the gas atmosphere is N2 and NH3, and the flow rate ratio of N2 to NH3 is 2:1-8:1, with an introduction time of 30s-10min. This can improve repair efficiency and assist in cleaning the surface. N2 can provide a large amount of N, resulting in high repair efficiency, while NH3 can play the role of H atoms, assisting in cleaning the surface.

[0050] In some specific and preferred embodiments, the flow rate of N2 is 40 sccm-1600 sccm; for example, the flow rate of N2 is 40 sccm, 100 sccm, 300 sccm, 500 sccm, 1000 sccm, 1500 sccm, or 1600 sccm, but is not limited thereto.

[0051] In some specific and preferred embodiments, the NH3 flow rate is 20 sccm-200 sccm. Exemplarily, the NH3 flow rate is 20 sccm, 50 sccm, 80 sccm, 100 sccm, 120 sccm, 150 sccm, 180 sccm, or 200 sccm, but is not limited thereto.

[0052] Furthermore, the in-situ formation of the passivation layer 4 also includes: performing rapid thermal annealing on the formed passivation layer 4. Rapid thermal annealing provides sufficient energy to allow B and P atoms to migrate to the lowest energy lattice points, forming stable chemical bonds, and effectively releasing the thermal stress at the interface, preventing interface cracking.

[0053] Optionally, the rapid thermal annealing treatment has an annealing temperature of 400℃-500℃, an annealing rate of 5℃ / s-20℃ / s, and a time of 30s-300s, which can further control the migration rate of B atoms and P atoms, thereby controlling the stability and density of the passivation layer 4.

[0054] In some specific and preferred embodiments, the growth thickness of the passivation layer 4 is 3nm-10nm. The thickness of the passivation layer 4 can be controlled by adjusting the introduction time of N2 and / or NH3, boron source, and phosphorus source, as well as the reaction conditions. If the growth thickness of the passivation layer 4 is too thin, the protective film may be discontinuous and unable to effectively isolate external moisture, oxygen, etc.; if the growth thickness of the passivation layer 4 is too thick, it will introduce greater stress, which may lead to sidewall cracks or detachment. For example, the growth thickness of the passivation layer 4 is 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, or 10nm, but is not limited to these.

[0055] Accordingly, the present invention also provides a light-emitting diode epitaxial wafer, prepared according to the aforementioned preparation method, the structure of which is as follows: Figure 1 As shown.

[0056] The present invention will be further described below with reference to specific embodiments: Example 1 This embodiment provides a light-emitting diode epitaxial wafer, the preparation method of which includes: S1. Provide a sapphire substrate; S2. Sequentially deposit a Si-doped GaN semiconductor layer, an InGaN / GaN multiple quantum well layer, and a Mg-doped GaN semiconductor layer on a sapphire substrate. S3. A SiO2 layer is deposited on the surface of a Mg-doped GaN semiconductor layer. Photoresist is then coated on the surface of the SiO2 layer. After exposure and development, dry etching is performed. Finally, the photoresist is removed to form a nanopillar patterned mask. The etching gases are CF3 and Ar, with a CF3 to Ar flow rate ratio of 1:3, an etching power of 350W, and a pressure of 15mTorr. Nanoimprinting patterning is performed on the nanopillar patterned mask to obtain a nanopillar etched mask; A mixture of CH4 and H2 gas was introduced to perform RIE etching on the obtained sample, and the etching mask was removed to form a patterned nanopillar structure. The etching depth of the patterned nanopillar structure was 830 nm. The total flow rate of the mixed gas was 35 sccm, the flow rate ratio of CH4 to H2 was 2:1, the etching power was 200 W, and the pressure was 2.5 Pa.

[0057] S4. Under conditions of 300℃ and 75mbar, maintain the gas atmosphere as N2 and NH3, and introduce B2H6 and PH3 for plasma treatment to grow passivation layers in situ on the inner wall and bottom of the nanopillar patterned structure; wherein the introduction time of N2, NH3, B2H6 and PH3 is 400s. The influent flow rate of B2H6 is 2 sccm, the influent flow rate of PH3 is 5 sccm, the influent flow rate of N2 is 50 sccm, and the influent flow rate of NH3 is 30 sccm.

[0058] Example 2 This embodiment provides a light-emitting diode epitaxial wafer, the preparation method of which is basically the same as that in Embodiment 1, except that: In step S4, under conditions of 600℃ and 75mbar, the gas atmosphere is maintained as N2 and NH3, and B2H6 and PH3 are introduced for plasma treatment to grow a passivation layer in situ on the inner wall and bottom of the nanopillar patterned structure. The influent flow rate of B2H6 is 10 sccm, the influent flow rate of PH3 is 30 sccm, the influent flow rate of N2 is 1500 sccm, and the influent flow rate of NH3 is 200 sccm.

[0059] Example 3 This embodiment provides a light-emitting diode epitaxial wafer, the preparation method of which is basically the same as that in Embodiment 1, except that: In step S4, under conditions of 450℃ and 75mbar, the gas atmosphere is maintained as N2 and NH3, and B2H6 and PH3 are introduced for plasma treatment to grow a passivation layer in situ on the inner wall and bottom of the nanopillar patterned structure. The influent flow rate of B2H6 is 5 sccm, the influent flow rate of PH3 is 15 sccm, the influent flow rate of N2 is 800 sccm, and the influent flow rate of NH3 is 100 sccm.

[0060] Example 4 This embodiment provides a light-emitting diode epitaxial wafer, the preparation method of which is basically the same as that in Embodiment 1, except that: Step S4 also includes performing rapid thermal annealing on the formed passivation layer, wherein the annealing temperature is 450°C, the annealing rate is 11°C / s, and the time is 150s.

[0061] Example 5 This embodiment provides a light-emitting diode epitaxial wafer, the preparation method of which is basically the same as that in Embodiment 1, except that: In step S4, the annealing temperature is 500℃, the annealing rate is 15℃ / s, and the time is 200s.

[0062] Comparative Example 1 This comparative example provides an epitaxial wafer for a light-emitting diode, which is prepared in a manner that is basically the same as that in Example 1, except that step S4 is not included, i.e., no nitride film is formed at the patterned structure.

[0063] The interface stress of the patterned structure in the epitaxial wafer of the light-emitting diode obtained in the examples and comparative examples was tested. The epitaxial wafers of the light-emitting diode obtained in the examples and comparative examples were fabricated into 10mil×24mil chips using the same chip process conditions. 300 LED chips were randomly selected and tested at a current of 120mA to test the luminous efficiency and leakage failure rate.

[0064] The specific test results are shown in Table 1.

[0065] Table 1 Performance test results of the examples and comparative examples

[0066] As can be seen from the above results, in this invention, the in-situ growth of a passivation layer by introducing boron and phosphorus sources into the etched sidewalls of the epitaxial layer for plasma treatment can reduce defect stress, reduce leakage risk, reduce non-radiative recombination centers, and improve the luminous efficiency of the device.

[0067] The above description is merely a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for fabricating a light-emitting diode epitaxial wafer, characterized in that, Includes the following steps: (1) Provide a substrate; (2) Deposit an epitaxial layer on the substrate; (3) Dry etching is performed on the epitaxial layer to form a patterned structure with etched sidewalls; (4) A passivation layer is formed in situ on the etched sidewall of the patterned structure; The in-situ formation of the passivation layer includes: Under conditions of 300℃-600℃ and 50mbar-500mbar, with the gas atmosphere being N2 and / or NH3, a boron source and a phosphorus source are introduced for plasma treatment to generate a passivation layer in situ on the sidewall.

2. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The in-situ formation of the passivation layer also includes: performing rapid thermal annealing on the formed passivation layer.

3. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 2, characterized in that, in, The rapid thermal annealing process has an annealing temperature of 400℃-500℃, an annealing rate of 5℃ / s-20℃ / s, and a time of 30s-300s.

4. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The ratio of the total flow rate of the boron and phosphorus sources to the total flow rate of the gas is 1:(10-100).

5. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 1 or 4, characterized in that, The flow rate ratio of the boron source to the phosphorus source is 1:(0.1-10), and the flow time is 20s-1000s.

6. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 5, characterized in that, The flow rate of the boron source is 1 sccm-10 sccm; The flow rate of the phosphorus source is 1 sccm-30 sccm.

7. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 1 or 4, characterized in that, The gas atmosphere is N2 and NH3, the flow rate ratio of N2 and NH3 is 2:1 to 8:1, and the introduction time is 30s to 10min.

8. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 7, characterized in that, The flow rate of N2 is 40 sccm-1600 sccm; The flow rate of NH3 is 20 sccm-200 sccm.

9. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The passivation layer has a growth thickness of 3nm-10nm.

10. A light-emitting diode epitaxial wafer, characterized in that, It is prepared according to any one of claims 1-9.

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