Photodetector and method of manufacturing the same

Abstract

The application provides a photoelectric detector and a manufacturing method thereof. The manufacturing method of the photoelectric detector comprises the following steps: providing an SOI substrate, wherein the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; forming a first insulating medium layer on the top surface and the sidewall of the semiconductor layer; removing the first insulating medium layer on the top surface of the semiconductor layer; forming a second insulating medium layer covering the semiconductor layer and the first insulating medium layer; etching part of the thickness of the second insulating medium layer by using a dry etching process to form an opening; etching the second insulating medium layer on the bottom wall of the opening by using a wet etching process to expose part of the top surface of the semiconductor layer; and forming a semiconductor absorption layer on the exposed semiconductor layer. The technical scheme of the application can improve the growth quality of the semiconductor absorption layer, thereby reducing the dark current of a silicon optical chip, improving the transmission bandwidth of the silicon optical chip and the like.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a photodetector and its manufacturing method. Background Technology

[0002] Photodetectors are crucial active devices in silicon photonics chips, converting received optical signals into electrical signals. In photodetectors, the fabrication quality of the heterogeneously grown semiconductor absorber layer (e.g., germanium) on the semiconductor layer (e.g., silicon) of the SOI substrate has a significant impact on the performance of the silicon photonics chip.

[0003] An insulating dielectric layer is formed on the semiconductor layer, and an opening is formed in the insulating dielectric layer that exposes part of the top surface of the semiconductor layer. A semiconductor absorption layer is formed on the semiconductor layer exposed by the opening. Damage to the top surface of the semiconductor layer exposed by the opening will cause defects in the semiconductor absorption layer, thereby affecting the performance of the silicon photonics chip. Summary of the Invention

[0004] The purpose of this invention is to provide a photodetector and its manufacturing method, which can improve the growth quality of the semiconductor absorption layer, thereby reducing the dark current of the silicon photonic chip and improving the transmission bandwidth of the silicon photonic chip.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a photodetector, comprising:

[0006] An SOI substrate is provided, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer;

[0007] A first insulating dielectric layer is formed on the top surface and sidewalls of the semiconductor layer;

[0008] Remove the first insulating dielectric layer from the top surface of the semiconductor layer;

[0009] A second insulating dielectric layer is formed to cover the semiconductor layer and the first insulating dielectric layer;

[0010] A portion of the second insulating dielectric layer is etched using a dry etching process to form an opening;

[0011] The second insulating dielectric layer of the bottom wall of the opening is etched using a wet etching process to expose a portion of the top surface of the semiconductor layer;

[0012] A semiconductor absorber layer is formed on the exposed semiconductor layer.

[0013] Optionally, the density of the first insulating dielectric layer is greater than the density of the second insulating dielectric layer.

[0014] Optionally, the first insulating dielectric layer is formed by thermal oxidation, the first insulating dielectric layer on the top surface of the semiconductor layer is removed by wet etching, and the second insulating dielectric layer is formed by deposition.

[0015] Optionally, after forming the first insulating dielectric layer on the top surface and sidewalls of the semiconductor layer, and before removing the first insulating dielectric layer from the top surface of the semiconductor layer, the method of manufacturing the photodetector further includes:

[0016] A first doped region and a second doped region are formed in the semiconductor layer using an ion implantation process. The first doped region and the second doped region are spaced apart and have opposite doping types.

[0017] A first heavily doped region and a second heavily doped region are formed using an ion implantation process. The first heavily doped region is formed within the first doped region, and the second heavily doped region is formed within the second doped region. The first heavily doped region has the same doping type as the first doped region, and the second heavily doped region has the same doping type as the second doped region.

[0018] Optionally, after forming the first insulating dielectric layer on the top surface and sidewalls of the semiconductor layer, and before removing the first insulating dielectric layer from the top surface of the semiconductor layer, the method of manufacturing the photodetector further includes:

[0019] A first doped region is formed in the semiconductor layer using an ion implantation process;

[0020] A first heavily doped region is formed in the first doped region using an ion implantation process, and the doping type of the first heavily doped region is the same as that of the first doped region.

[0021] After forming the semiconductor absorber layer on the exposed semiconductor layer, the method of manufacturing the photodetector further includes:

[0022] A second doped region is formed in the semiconductor absorption layer using an ion implantation process, wherein the doping types of the first doped region and the second doped region are opposite.

[0023] A second heavily doped region is formed in the second doped region using an ion implantation process, and the doping type of the second heavily doped region is the same as that of the second doped region.

[0024] Optionally, before employing the dry etching process, the thickness of the second insulating dielectric layer is 150 nm to 250 nm.

[0025] The present invention also provides a photodetector, comprising:

[0026] SOI substrate, including, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer;

[0027] A first insulating dielectric layer is formed on the sidewall of the semiconductor layer;

[0028] A second insulating dielectric layer is formed on the semiconductor layer and the first insulating dielectric layer, the second insulating dielectric layer having an opening that exposes a portion of the top surface of the semiconductor layer;

[0029] A semiconductor absorber layer is formed on the semiconductor layer exposed by the opening.

[0030] Optionally, the top surfaces of the first insulating dielectric layer and the semiconductor layer are flush.

[0031] Optionally, the density of the first insulating dielectric layer is greater than the density of the second insulating dielectric layer.

[0032] Optionally, the photodetector further includes:

[0033] A first doped region and a second doped region are formed alternately in the semiconductor layer, and the doping types of the first doped region and the second doped region are opposite.

[0034] The first heavily doped region and the second heavily doped region are respectively formed in the first doped region and the second doped region on both sides of the semiconductor absorption layer. The first heavily doped region has the same doping type as the first doped region, and the second heavily doped region has the same doping type as the second doped region.

[0035] Optionally, the photodetector further includes:

[0036] A first doped region and a second doped region, wherein the first doped region is formed in the semiconductor layer and the second doped region is formed in the semiconductor absorption layer, and the doping types of the first doped region and the second doped region are opposite;

[0037] The first doped region and the second doped region correspond to the first doped region and the second doped region, respectively. The first doped region has the same doping type as the first doped region, and the second doped region has the same doping type as the second doped region. Attached Figure Description

[0038] Figure 1 This is a flowchart of a method for manufacturing a photodetector according to an embodiment of the present invention;

[0039] Figures 2a to 2h yes Figure 1 A schematic diagram of the device used in the manufacturing method of the photodetector is shown.

[0040] Among them, the appendixFigures 1 to 2h The annotations in the attached figures are explained as follows:

[0041] 101-Lower substrate; 102-Buried insulating layer; 103-Semiconductor layer; 11-First insulating dielectric layer; 12-Second insulating dielectric layer; 13-Opening; 131-Patterned photoresist layer; 14-Semiconductor absorption layer; 151-First doped region; 152-Second doped region; 153-First heavily doped region; 154-Second heavily doped region. Detailed Implementation

[0042] To make the objectives, advantages, and features of the present invention clearer, the photodetector and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0043] One embodiment of the present invention provides a method for manufacturing a photodetector, see reference. Figure 1 , Figure 1 This is a flowchart of a method for manufacturing a photodetector according to an embodiment of the present invention. The method for manufacturing the photodetector includes:

[0044] Step S1: Provide an SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer;

[0045] Step S2: Form a first insulating dielectric layer on the top surface and sidewalls of the semiconductor layer;

[0046] Step S3: Remove the first insulating dielectric layer on the top surface of the semiconductor layer;

[0047] Step S4: Form a second insulating dielectric layer to cover the semiconductor layer and the first insulating dielectric layer;

[0048] Step S5: Use a dry etching process to etch a portion of the thickness of the second insulating dielectric layer to form an opening;

[0049] Step S6: Use a wet etching process to etch the second insulating dielectric layer on the bottom wall of the opening to expose a portion of the top surface of the semiconductor layer;

[0050] Step S7: Form a semiconductor absorber layer on the exposed semiconductor layer.

[0051] See below. Figures 2a to 2h The manufacturing method of the photodetector provided in this embodiment will be described in more detail.

[0052] Follow step S1, refer to Figure 2aAn SOI (Semiconductor-On-Insulator) substrate is provided, the SOI substrate comprising, from bottom to top, a lower substrate 101, an insulating buried layer 102, and a semiconductor layer 103.

[0053] The semiconductor layer 103 can be made of semiconductor materials such as silicon.

[0054] In one embodiment, the semiconductor layer 103 is formed on a portion of the insulating buried layer 102.

[0055] Follow step S2, see Figure 2b A first insulating dielectric layer 11 is formed on the top surface and sidewalls of the semiconductor layer 103.

[0056] In some embodiments, the first insulating dielectric layer 11 has a dense structure; the first insulating dielectric layer 11 can protect the surface of the semiconductor layer 103 and reduce the degree of damage to the surface of the semiconductor layer 103 during subsequent ion implantation into the semiconductor layer 103; in some embodiments, the first insulating dielectric layer 11 is thinner to avoid the first insulating dielectric layer 11 being too thick, which would prevent ions from penetrating the first insulating dielectric layer 11 and being implanted into the semiconductor layer 103.

[0057] In one embodiment, the first insulating dielectric layer 11 is formed using a thermal oxidation process. When the semiconductor layer 103 is made of silicon, the first insulating dielectric layer 11 is made of silicon oxide.

[0058] In one embodiment, the temperature of the thermal oxidation process can be 1000℃~1200℃.

[0059] In one embodiment, the thickness of the first insulating dielectric layer 11 can be 5nm to 12nm.

[0060] Follow step S3, see [link / reference] Figure 2d Remove the first insulating dielectric layer 11 from the top surface of the semiconductor layer 103.

[0061] In one embodiment, a wet etching process is used to remove the first insulating dielectric layer 11 on the top surface of the semiconductor layer 103, making the first insulating dielectric layer 11 flush with the top surface of the semiconductor layer 103. Because the dry etching process involves plasma bombardment, after the top surface of the semiconductor layer 103 is exposed, plasma bombardment occurs, causing damage to the top surface of the semiconductor layer 103. Therefore, a wet etching process is preferred to remove the first insulating dielectric layer 11 on the top surface of the semiconductor layer 103. In other embodiments, a chemical mechanical polishing process can also be used to remove the first insulating dielectric layer 11 on the top surface of the semiconductor layer 103.

[0062] In one embodiment, the first insulating dielectric layer 11 is made of silicon oxide, and the etching solution used in the wet etching process can be hydrofluoric acid.

[0063] Follow step S4, see Figure 2e A second insulating dielectric layer 12 is formed to cover the semiconductor layer 103 and the first insulating dielectric layer 11.

[0064] The thickness of the second insulating dielectric layer 12 enables the subsequent formation of a semiconductor absorber layer 14 of the required thickness.

[0065] In one embodiment, the thickness of the second insulating dielectric layer 12 is 150 nm to 250 nm before the subsequent dry etching process is applied.

[0066] In one embodiment, the first insulating dielectric layer 11 is formed by a thermal oxidation process, and the second insulating dielectric layer 12 is formed by a deposition process, such that the density of the first insulating dielectric layer 11 is greater than the density of the second insulating dielectric layer 12.

[0067] In one embodiment, the second insulating dielectric layer 12 is formed using a deposition process, such that the second insulating dielectric layer 12 of the desired thickness can be deposited.

[0068] The material of the second insulating dielectric layer 12 can be insulating materials such as silicon oxide or silicon oxynitride.

[0069] Follow step S5, see [link / reference] Figure 2f A portion of the second insulating dielectric layer 12 is etched using a dry etching process to form an opening 13.

[0070] In one embodiment, a patterned photoresist layer 131 may be formed on the second insulating dielectric layer 12, and a portion of the second insulating dielectric layer 12 may be etched using the patterned photoresist layer 131 as a mask to form the opening 13.

[0071] In one embodiment, the patterned photoresist layer 131 is removed after the dry etching process is performed.

[0072] The dry etching process may use an etching gas that includes at least one of CHF3, C4F8, C2F6 and SF6.

[0073] Follow step S6, see Figure 2g The second insulating dielectric layer 12 on the bottom wall of the opening 13 is etched using a wet etching process to expose a portion of the top surface of the semiconductor layer 103. That is, after the wet etching process, the opening 13 penetrates the second insulating dielectric layer 12, and the second insulating dielectric layer 12 surrounding the opening 13 serves to protect areas where the semiconductor absorber layer 14 does not need to be formed during the subsequent formation of the semiconductor absorber layer 14.

[0074] In one embodiment, during the wet etching process, the patterned photoresist layer 131 is not formed on the second insulating dielectric layer 12 surrounding the opening 13. Due to the isotropic nature of the wet etching process, both the inner wall of the opening 13 and the second insulating dielectric layer 12 surrounding the opening 13 are etched until the top surface of the semiconductor layer 103 is partially exposed, at which point the etching stops. Therefore, the thickness of the second insulating dielectric layer 12 formed in step S4 needs to be sufficiently large so that after a portion of the thickness of the second insulating dielectric layer 12 surrounding the opening 13 is etched away in step S6, the remaining thickness of the second insulating dielectric layer 12 is still sufficient to allow for the subsequent formation of the semiconductor absorption layer 14 of the desired shape, preventing the semiconductor absorption layer 14 from growing and extending onto the second insulating dielectric layer 12 surrounding the opening 13.

[0075] Because of the plasma bombardment effect during the dry etching process, the opening 13 is formed by first etching a portion of the second insulating dielectric layer 12 using a dry etching process, and then etching the second insulating dielectric layer 12 on the bottom wall of the opening 13 using a wet etching process. This avoids plasma bombardment on the exposed top surface of the semiconductor layer 103, thereby preventing damage to the top surface of the semiconductor layer 103.

[0076] In one embodiment, the second insulating dielectric layer 12 is made of silicon oxide, and the etching solution used in the wet etching process can be hydrofluoric acid.

[0077] Follow step S7, see Figure 2h A semiconductor absorption layer 14 is formed on the exposed semiconductor layer 103.

[0078] In one embodiment, the semiconductor absorber layer 14 may be made of Ge, InGaAs, or InGaAsP, etc.; in other embodiments, the semiconductor absorber layer 14 may be made of Si, GeAs, or InP, etc.

[0079] In one embodiment, the semiconductor absorption layer 14 is undoped, that is, the semiconductor absorption layer 14 is in an intrinsic state.

[0080] When the semiconductor layer 103 is made of silicon and the semiconductor absorber layer 14 is made of germanium, because the semiconductor absorber layer 14 and the semiconductor layer 103 are made of different materials, the semiconductor absorber layer 14 is epitaxially grown on the semiconductor layer 103 exposed by the opening 13, which is heteroepitaxial growth. This means that the semiconductor absorber layer 14 will not grow along the same direction as the crystal orientation of the semiconductor layer 103. The semiconductor absorber layer 14 will grow along multiple directions with different crystal orientations, such as (110), (100), (001), etc. The growth rate is different on different crystal orientations, and the crystal orientation with a faster growth rate will form sharp corners, making the longitudinal cross-sectional shape of the semiconductor absorber layer 14 polygonal (e.g., Figure 2h (The octagon in the middle).

[0081] In one embodiment, grooves (not shown) are formed in the semiconductor layers 103 on both sides of the semiconductor absorber layer 14, and the second insulating dielectric layer 12 fills the grooves. In other embodiments, such as Figure 2h As shown, the groove may not be formed in the semiconductor layer 103.

[0082] In one embodiment, when the grooves are formed in the semiconductor layers 103 on both sides of the semiconductor absorption layer 14, the light field can be concentrated directly below the semiconductor absorption layer 14, which is more conducive to the semiconductor absorption layer 14 absorbing incident light.

[0083] In one embodiment, such as Figure 2cAs shown, after forming the first insulating dielectric layer 11 on the top surface and sidewalls of the semiconductor layer 103, and before removing the first insulating dielectric layer 11 from the top surface of the semiconductor layer 103, the manufacturing method of the photodetector further includes: forming a first doped region 151 and a second doped region 152 in the semiconductor layer 103 using an ion implantation process, wherein the first doped region 151 and the second doped region 152 are spaced apart, and the doping types of the first doped region 151 and the second doped region 152 are opposite; forming a first heavily doped region 152 using an ion implantation process. 53 and a second heavily doped region 154 are formed, wherein the first heavily doped region 153 is formed in the first doped region 151, and the second heavily doped region 154 is formed in the second doped region 152. The first heavily doped region 153 and the first doped region 151 have the same doping type, and the second heavily doped region 154 and the second doped region 152 have the same doping type. The doping concentration of the first heavily doped region 153 is greater than that of the first doped region 151, and the doping concentration of the second heavily doped region 154 is greater than that of the second doped region 152. The projection of the semiconductor absorption layer 14 onto the semiconductor layer 103 overlaps with a portion of the first doped region 151 and a portion of the second doped region 152. The first heavily doped region 153 and the second heavily doped region 154 are located in the semiconductor layer 103 on both sides of the semiconductor absorption layer 14.

[0084] Wherein, when the doping type of the first doped region 151 is P-type and the doping type of the second doped region 152 is N-type, the first doped region 151, the semiconductor absorption layer 14 and the second doped region 152 form a horizontal PIN junction; when the doping type of the first doped region 151 is N-type and the doping type of the second doped region 152 is P-type, the first doped region 151, the semiconductor absorption layer 14 and the second doped region 152 form a horizontal NIP junction.

[0085] Alternatively, in another embodiment, after forming the first insulating dielectric layer 11 on the top surface and sidewalls of the semiconductor layer 103, and before removing the first insulating dielectric layer 11 from the top surface of the semiconductor layer 103, the method for manufacturing the photodetector further includes: forming a first doped region 151 in the semiconductor layer 103 using an ion implantation process; forming a first heavily doped region 153 in the first doped region 151 using an ion implantation process, wherein the first heavily doped region 153 has the same doping type as the first doped region 151, and the doping concentration of the first heavily doped region 153 is greater than that of the first doped region 151. Wherein, the semiconductor absorber layer 14 is located on a portion of the first doped region 151, and the first heavily doped region 153 is located in the first doped region 151 surrounding the semiconductor absorber layer 14.

[0086] After forming the semiconductor absorber layer 14 on the exposed semiconductor layer 103, the method of manufacturing the photodetector further includes: forming a second doped region 152 in the semiconductor absorber layer 14 using an ion implantation process, wherein the doping types of the first doped region 151 and the second doped region 152 are opposite; and forming a second heavily doped region 154 in the second doped region 152 using an ion implantation process, wherein the doping type of the second heavily doped region 154 is the same as that of the second doped region 152, and the doping concentration of the second heavily doped region 154 is greater than that of the second doped region 152.

[0087] Wherein, when the doping type of the first doped region 151 is P-type and the doping type of the second doped region 152 is N-type, the first doped region 151, the semiconductor absorption layer 14 (i.e., the semiconductor absorption layer 14 outside the second doped region 152) and the second doped region 152 form a vertical PIN junction; when the doping type of the first doped region 151 is N-type and the doping type of the second doped region 152 is P-type, the first doped region 151, the semiconductor absorption layer 14 (i.e., the semiconductor absorption layer 14 outside the second doped region 152) and the second doped region 152 form a vertical NIP junction.

[0088] In one embodiment, the method for manufacturing the photodetector further includes: forming conductive structures (not shown) on the first heavily doped region 153 and the second heavily doped region 154, wherein the conductive structures on the first heavily doped region 153 and the second heavily doped region 154 serve as the cathode and anode of the photodetector, respectively; a metal silicide layer (not shown) may also be formed between the first heavily doped region 153 and the second heavily doped region 154 and the conductive structure, wherein the metal silicide layer is used to reduce contact resistance.

[0089] Specifically, in Figure 2h Taking the formation of conductive structures on the first heavily doped region 153 and the second heavily doped region 154 as an example, the steps include: forming a third insulating dielectric layer (not shown) to cover the second insulating dielectric layer 12 and the semiconductor absorber layer 14; etching the third insulating dielectric layer and the second insulating dielectric layer 12 to form vias (not shown) that expose the first heavily doped region 153 and the second heavily doped region 154 respectively, and forming a metal silicide layer on the surface of the first heavily doped region 153 and the second heavily doped region 154 exposed by the vias; and forming a conductive structure in the vias.

[0090] In the existing photodetector manufacturing process, before growing the semiconductor absorber layer, two insulating dielectric layers with different densities are first formed on the top surface of the semiconductor layer of the SOI substrate. Then, the two insulating dielectric layers are etched to form an opening that exposes the semiconductor layer, so that the semiconductor absorber layer can be formed on the semiconductor layer exposed by the opening. There are two methods for etching to form openings. One method is to directly use a dry etching process to form the opening. However, this method bombards the exposed semiconductor layer with plasma, causing damage and unevenness to the top surface of the exposed semiconductor layer, which in turn leads to unevenness on the bottom surface of the subsequently formed semiconductor absorber layer. The other method is to first use a dry etching process to etch down to the bottom insulating dielectric layer, and then use a wet etching process to etch through the bottom insulating dielectric layer to form the opening. However, because the wet etching process also etches the sidewalls of the opening, and the etching rates of the two insulating dielectric layers with different densities on the sidewalls of the opening are different, uneven concave corners are formed at the junction of the two insulating dielectric layers on the sidewalls of the opening during the wet etching process. That is, the morphology of the formed opening sidewall is irregular, which in turn leads to irregular morphology of the sidewalls of the subsequently formed semiconductor absorber layer.

[0091] In the manufacturing method of the photodetector provided by the present invention, the process involves: forming a first insulating dielectric layer on the top surface and sidewalls of the semiconductor layer in the SOI substrate; removing the first insulating dielectric layer from the top surface of the semiconductor layer; forming a second insulating dielectric layer covering the semiconductor layer and the first insulating dielectric layer; etching a portion of the second insulating dielectric layer using a dry etching process to form an opening; and etching the second insulating dielectric layer on the bottom wall of the opening using a wet etching process to expose a portion of the top surface of the semiconductor layer. Specifically, the method first uses a dry etching process to etch a portion of the second insulating dielectric layer to form the opening, and then uses a wet etching process to etch the second insulating dielectric layer on the bottom wall of the opening until the top surface of the semiconductor layer is exposed. The top surface of the semiconductor layer is designed to prevent plasma bombardment of the exposed top surface, thus avoiding damage and unevenness to the exposed top surface. This prevents unevenness of the bottom surface of the semiconductor absorber layer subsequently formed on the exposed semiconductor layer. Furthermore, since only a single, uniformly dense second insulating dielectric layer is formed on the semiconductor layer, uneven concave corners are avoided on the sidewalls of the opening during the wet etching process, preventing irregular sidewall morphology and thus avoiding irregular sidewall morphology of the semiconductor absorber layer subsequently formed on the exposed semiconductor layer. Therefore, this invention creates an opening with a more ideal morphology, reducing the defect density of the semiconductor absorber layer, improving the growth quality of the semiconductor absorber layer, and consequently reducing the dark current of the silicon photonics chip and improving its transmission bandwidth.

[0092] An embodiment of the present invention provides a photodetector, comprising: an SOI substrate, including a lower substrate, an insulating buried layer, and a semiconductor layer from bottom to top; a first insulating dielectric layer formed on the sidewall of the semiconductor layer; a second insulating dielectric layer formed on the semiconductor layer and the first insulating dielectric layer, the second insulating dielectric layer having an opening exposing a portion of the top surface of the semiconductor layer; and a semiconductor absorption layer formed on the semiconductor layer exposed by the opening.

[0093] See below. Figure 2h The photodetector provided in this embodiment will be described in more detail.

[0094] The SOI (Semiconductor-On-Insulator) substrate includes, from bottom to top, a lower substrate 101, an insulating buried layer 102, and a semiconductor layer 103.

[0095] The semiconductor layer 103 can be made of semiconductor materials such as silicon.

[0096] In one embodiment, the semiconductor layer 103 is formed on a portion of the insulating buried layer 102.

[0097] A first insulating dielectric layer 11 is formed on the sidewall of the semiconductor layer.

[0098] In one embodiment, the top surfaces of the first insulating dielectric layer 11 and the semiconductor layer 103 are flush.

[0099] In one embodiment, the first insulating dielectric layer 11 has a dense structure.

[0100] In one embodiment, the semiconductor layer 103 is made of silicon, and the first insulating dielectric layer 11 is made of silicon oxide.

[0101] A second insulating dielectric layer 12 is formed on the semiconductor layer 103 and the first insulating dielectric layer 11, and the second insulating dielectric layer 12 has an opening that exposes a portion of the top surface of the semiconductor layer 103 (i.e., Figure 2g (Opening 13 in the middle).

[0102] The thickness of the second insulating dielectric layer 12 enables the subsequent formation of the semiconductor absorber layer 14 of the desired shape.

[0103] In one embodiment, the density of the first insulating dielectric layer 11 is greater than the density of the second insulating dielectric layer 12.

[0104] The material of the second insulating dielectric layer 12 can be insulating materials such as silicon oxide or silicon oxynitride.

[0105] The second insulating dielectric layer 12 surrounding the opening 13 is used to protect the area where the semiconductor absorber layer 14 does not need to be formed during the subsequent formation of the semiconductor absorber layer 14.

[0106] A semiconductor absorption layer 14 is formed on the semiconductor layer 103 exposed by the opening 13.

[0107] In one embodiment, the semiconductor absorber layer 14 may be made of Ge, InGaAs, or InGaAsP, etc.; in other embodiments, the semiconductor absorber layer 14 may be made of Si, GeAs, or InP, etc.

[0108] In one embodiment, the semiconductor absorption layer 14 is undoped, that is, the semiconductor absorption layer 14 is in an intrinsic state.

[0109] When the semiconductor layer 103 is made of silicon and the semiconductor absorber layer 14 is made of germanium, because the semiconductor absorber layer 14 and the semiconductor layer 103 are made of different materials, the semiconductor absorber layer 14 is epitaxially grown on the semiconductor layer 103 exposed by the opening 13, which is heteroepitaxial growth. This means that the semiconductor absorber layer 14 will not grow along the same direction as the crystal orientation of the semiconductor layer 103. The semiconductor absorber layer 14 will grow along multiple directions with different crystal orientations, such as (110), (100), (001), etc. The growth rate is different on different crystal orientations, and the crystal orientation with a faster growth rate will form sharp corners, making the longitudinal cross-sectional shape of the semiconductor absorber layer 14 polygonal (e.g., Figure 2h (The octagon in the middle).

[0110] In one embodiment, grooves (not shown) are formed in the semiconductor layers 103 on both sides of the semiconductor absorber layer 14, and the second insulating dielectric layer 12 fills the grooves. In other embodiments, such as Figure 2h As shown, the groove may not be formed in the semiconductor layer 103.

[0111] In one embodiment, when the grooves are formed in the semiconductor layers 103 on both sides of the semiconductor absorption layer 14, the light field can be concentrated directly below the semiconductor absorption layer 14, which is more conducive to the semiconductor absorption layer 14 absorbing incident light.

[0112] In one embodiment, such as Figure 2h As shown, the photodetector further includes:

[0113] A first doped region 151 and a second doped region 152 are formed at intervals in the semiconductor layer 103 below the semiconductor absorption layer 14, and the first doped region 151 and the second doped region 152 extend to the semiconductor layer 103 on both sides of the semiconductor absorption layer 14, and the doping types of the first doped region 151 and the second doped region 152 are opposite.

[0114] The first heavily doped region 153 and the second heavily doped region 154 are respectively formed in the first doped region 151 and the second doped region 152 on both sides of the semiconductor absorption layer 14. The first heavily doped region 153 has the same doping type as the first doped region 151, and the second heavily doped region 154 has the same doping type as the second doped region 152. The doping concentration of the first heavily doped region 153 is greater than the doping concentration of the first doped region 151, and the doping concentration of the second heavily doped region 154 is greater than the doping concentration of the second doped region 152.

[0115] Wherein, when the doping type of the first doped region 151 is P-type and the doping type of the second doped region 152 is N-type, the first doped region 151, the semiconductor absorption layer 14 and the second doped region 152 form a horizontal PIN junction; when the doping type of the first doped region 151 is N-type and the doping type of the second doped region 152 is P-type, the first doped region 151, the semiconductor absorption layer 14 and the second doped region 152 form a horizontal NIP junction.

[0116] Alternatively, in another embodiment, the photodetector further includes:

[0117] A first doped region 151 and a second doped region 152 are formed in the semiconductor layer 103 and the second doped region 152 are formed in the semiconductor absorption layer 14. The doping types of the first doped region 151 and the second doped region 152 are opposite.

[0118] The first heavily doped region 153 and the second heavily doped region 154 correspond to the first doped region 151 and the second doped region 152, respectively. The first heavily doped region 153 has the same doping type as the first doped region 151, and the second heavily doped region 154 has the same doping type as the second doped region 152. The doping concentration of the first heavily doped region 153 is greater than that of the first doped region 151, and the doping concentration of the second heavily doped region 154 is greater than that of the second doped region 152. The semiconductor absorption layer 14 is located on a portion of the first doped region 151, and the first heavily doped region 153 is located in the first doped region 151 surrounding the semiconductor absorption layer 14.

[0119] Wherein, when the doping type of the first doped region 151 is P-type and the doping type of the second doped region 152 is N-type, the first doped region 151, the semiconductor absorption layer 14 (i.e., the semiconductor absorption layer 14 outside the second doped region 152) and the second doped region 152 form a vertical PIN junction; when the doping type of the first doped region 151 is N-type and the doping type of the second doped region 152 is P-type, the first doped region 151, the semiconductor absorption layer 14 (i.e., the semiconductor absorption layer 14 outside the second doped region 152) and the second doped region 152 form a vertical NIP junction.

[0120] In one embodiment, the photodetector further includes: a conductive structure (not shown) formed on the first heavily doped region 153 and the second heavily doped region 154, wherein the conductive structure on the first heavily doped region 153 and the second heavily doped region 154 serves as the cathode and anode of the photodetector, respectively; a metal silicide layer (not shown) may also be formed between the first heavily doped region 153 and the second heavily doped region 154 and the conductive structure, wherein the metal silicide layer is used to reduce contact resistance.

[0121] In the existing photodetector manufacturing process, before growing the semiconductor absorber layer, two insulating dielectric layers with different densities are first formed on the top surface of the semiconductor layer of the SOI substrate. Then, the two insulating dielectric layers are etched to form an opening that exposes the semiconductor layer, so that the semiconductor absorber layer can be formed on the semiconductor layer exposed by the opening. There are two methods for etching to form openings. One method is to directly use a dry etching process to form the opening. However, this method bombards the exposed semiconductor layer with plasma, causing damage and unevenness to the top surface of the exposed semiconductor layer, which in turn leads to unevenness on the bottom surface of the subsequently formed semiconductor absorber layer. The other method is to first use a dry etching process to etch down to the bottom insulating dielectric layer, and then use a wet etching process to etch through the bottom insulating dielectric layer to form the opening. However, because the wet etching process also etches the sidewalls of the opening, and the etching rates of the two insulating dielectric layers with different densities on the sidewalls of the opening are different, uneven concave corners are formed at the junction of the two insulating dielectric layers on the sidewalls of the opening during the wet etching process. That is, the morphology of the formed opening sidewall is irregular, which in turn leads to irregular morphology of the sidewalls of the subsequently formed semiconductor absorber layer.

[0122] In the photodetector provided by this invention, since the first insulating dielectric layer is formed on the sidewall of the semiconductor layer, and the second insulating dielectric layer is formed on the semiconductor layer and the first insulating dielectric layer, the second insulating dielectric layer has an opening that exposes a portion of the top surface of the semiconductor layer. The semiconductor absorption layer is formed on the semiconductor layer exposed by the opening. That is, only a single, uniformly dense second insulating dielectric layer is formed on the semiconductor layer in the SOI substrate. This allows for the fabrication of the opening that exposes a portion of the top surface of the semiconductor layer, by first using a dry etching process to etch a portion of the second insulating dielectric layer, and then using a wet etching process to etch the second insulating dielectric layer. The remaining thickness of the second insulating dielectric layer extends to expose the top surface of the semiconductor layer, thus avoiding plasma bombardment of the exposed top surface of the semiconductor layer. This prevents damage and unevenness to the exposed top surface of the semiconductor layer, and also avoids the formation of uneven concave corners on the sidewalls of the opening during the wet etching process. In other words, it avoids irregular sidewall morphology, thereby preventing unevenness on the bottom surface of the semiconductor absorption layer subsequently formed on the exposed semiconductor layer, and also preventing irregular sidewall morphology of the semiconductor absorption layer subsequently formed on the exposed semiconductor layer. Therefore, the opening morphology of the present invention is more ideal, reducing the defect density of the semiconductor absorption layer, improving the growth quality of the semiconductor absorption layer, and thus reducing the dark current of the silicon photonics chip and improving its transmission bandwidth and other performance characteristics.

[0123] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for manufacturing a photodetector, characterized in that, include: An SOI substrate is provided, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer; A first insulating dielectric layer is formed on the top surface and sidewalls of the semiconductor layer; Remove the first insulating dielectric layer from the top surface of the semiconductor layer; A second insulating dielectric layer is formed to cover the semiconductor layer and the first insulating dielectric layer; A portion of the second insulating dielectric layer is etched using a dry etching process to form an opening; The second insulating dielectric layer of the bottom wall of the opening is etched using a wet etching process to expose a portion of the top surface of the semiconductor layer; A semiconductor absorber layer is formed on the exposed semiconductor layer.

2. The method for manufacturing a photodetector as described in claim 1, characterized in that, The density of the first insulating dielectric layer is greater than that of the second insulating dielectric layer.

3. The method for manufacturing a photodetector as described in claim 1, characterized in that, The first insulating dielectric layer is formed by thermal oxidation, the first insulating dielectric layer on the top surface of the semiconductor layer is removed by wet etching, and the second insulating dielectric layer is formed by deposition.

4. The method for manufacturing a photodetector as described in claim 1, characterized in that, After forming the first insulating dielectric layer on the top surface and sidewalls of the semiconductor layer, and before removing the first insulating dielectric layer from the top surface of the semiconductor layer, the method of manufacturing the photodetector further includes: A first doped region and a second doped region are formed in the semiconductor layer using an ion implantation process. The first doped region and the second doped region are spaced apart and have opposite doping types. A first heavily doped region and a second heavily doped region are formed using an ion implantation process. The first heavily doped region is formed within the first doped region, and the second heavily doped region is formed within the second doped region. The first heavily doped region has the same doping type as the first doped region, and the second heavily doped region has the same doping type as the second doped region.

5. The method for manufacturing a photodetector as described in claim 1, characterized in that, After forming the first insulating dielectric layer on the top surface and sidewalls of the semiconductor layer, and before removing the first insulating dielectric layer from the top surface of the semiconductor layer, the method of manufacturing the photodetector further includes: A first doped region is formed in the semiconductor layer using an ion implantation process; A first heavily doped region is formed in the first doped region using an ion implantation process, and the doping type of the first heavily doped region is the same as that of the first doped region. After forming the semiconductor absorber layer on the exposed semiconductor layer, the method of manufacturing the photodetector further includes: A second doped region is formed in the semiconductor absorption layer using an ion implantation process, wherein the doping types of the first doped region and the second doped region are opposite. A second heavily doped region is formed in the second doped region using an ion implantation process, and the doping type of the second heavily doped region is the same as that of the second doped region.

6. The method for manufacturing a photodetector as described in claim 1, characterized in that, Before employing the dry etching process, the thickness of the second insulating dielectric layer is 150 nm to 250 nm.

7. A photodetector, characterized in that, include: SOI substrate, including, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer; A first insulating dielectric layer is formed on the sidewall of the semiconductor layer; A second insulating dielectric layer is formed on the semiconductor layer and the first insulating dielectric layer, the second insulating dielectric layer having an opening that exposes a portion of the top surface of the semiconductor layer; A semiconductor absorber layer is formed on the semiconductor layer exposed by the opening.

8. The photodetector as described in claim 7, characterized in that, The top surfaces of the first insulating dielectric layer and the semiconductor layer are flush.

9. The photodetector as described in claim 7, characterized in that, The density of the first insulating dielectric layer is greater than that of the second insulating dielectric layer.

10. The photodetector as claimed in claim 7, characterized in that, The photodetector also includes: A first doped region and a second doped region are formed alternately in the semiconductor layer, and the doping types of the first doped region and the second doped region are opposite. The first heavily doped region and the second heavily doped region are respectively formed in the first doped region and the second doped region on both sides of the semiconductor absorption layer. The first heavily doped region has the same doping type as the first doped region, and the second heavily doped region has the same doping type as the second doped region.

11. The photodetector as claimed in claim 7, characterized in that, The photodetector also includes: A first doped region and a second doped region, wherein the first doped region is formed in the semiconductor layer and the second doped region is formed in the semiconductor absorption layer, and the doping types of the first doped region and the second doped region are opposite; The first doped region and the second doped region correspond to the first doped region and the second doped region, respectively. The first doped region has the same doping type as the first doped region, and the second doped region has the same doping type as the second doped region.

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