A piezoelectric MEMS device preparation process and device structure

Abstract

The application discloses a piezoelectric MEMS device preparation process and a device structure, and relates to the technical field of piezoelectric MEMS device preparation. The preparation process comprises the following steps: forming a groove near an edge region on a front surface of a substrate, depositing a sacrifice layer on the front surface of the substrate and patterning the sacrifice layer, so that the sacrifice layer is separated into a center region and an edge support region, forming a piezoelectric-buffer stack on the sacrifice layer and patterning the piezoelectric-buffer stack, and opening a release hole, the release hole being communicated with the center region of the sacrifice layer, introducing etching medium into the release hole to remove the center region of the sacrifice layer, and then etching a back cavity on the back surface of the substrate. The application limits the size of a diaphragm region through the groove, etches the back cavity of the substrate after the sacrifice layer is released, and compared with a traditional method of defining the diaphragm by etching the back cavity, the application completely avoids the size error of the diaphragm caused by the angle deviation of deep silicon etching, accurately locks the profile of the diaphragm, and greatly improves the size consistency and performance stability of devices in the same batch.

Description

Technical Field

[0001] This invention relates to the field of piezoelectric MEMS device fabrication technology, and in particular to a piezoelectric MEMS device fabrication process and device structure. Background Technology

[0002] MEMS piezoelectric devices, as core components in the field of microelectromechanical systems, are widely used in consumer electronics, industrial inspection, intelligent sensing, and other fields. Products such as resonators, microphones, and accelerometers based on piezoelectric materials such as lead zirconate titanate (PZT) are made from these materials. The fabrication of these devices generally adopts a process that combines surface micromachining and bulk micromachining. The industry has put forward stringent requirements on the dimensional consistency, performance stability, and yield of their mass production.

[0003] In existing technologies, the diaphragm area size of piezoelectric MEMS devices largely depends on the etching precision of the back cavity on the back of the substrate, without setting a clear mechanical limiting structure on the front of the substrate. The back cavity etching mainly adopts deep silicon etching technology, which is affected by factors such as the precision of the etching equipment and fluctuations in process parameters. There are etching angle deviations that cannot be completely eliminated, which can easily lead to significant deviations in the diaphragm size of different batches or even the same batch of devices. This directly affects the core performance of the device, such as the resonant frequency and sensitivity, and makes it difficult to meet the batch consistency requirements of high-precision MEMS products.

[0004] Meanwhile, in existing processes, the release of the sacrificial layer is mostly achieved by back-side etching. The etching medium is introduced from the back side of the substrate to remove the sacrificial layer. Due to the lack of an effective limiting and blocking structure, the etching medium is prone to lateral diffusion during the etching process, causing over-etching in the support area at the edge of the sacrificial layer. This damages the integrity of the diaphragm's support structure, leading to diaphragm breakage, warping, or even detachment, resulting in device performance failure and significantly reducing product yield and long-term operational reliability.

[0005] For example, patent document application number 202210746380.8 discloses a method for forming a back cavity, a device with a back cavity, a method for fabricating a MEMS microphone, and a MEMS microphone. In this method, the substrate is etched to form a groove during back cavity formation; a sacrificial layer is filled into the groove; and the sacrificial layer is removed to allow adjacent sub-back cavities to connect through the groove, thus forming the back cavity. This solves the problem of difficult-to-control etching process deep within the back cavity and improves the reliability of the device. However, this solution also has drawbacks: after etching the back cavity, removing the sacrificial layer to connect adjacent sub-back cavities through the groove can easily lead to lateral diffusion during the back cavity etching process, damaging the integrity of the diaphragm's support structure and potentially causing diaphragm damage, warping, or even detachment.

[0006] In summary, existing fabrication processes for piezoelectric MEMS devices suffer from problems such as low precision in diaphragm size control, easy over-etching caused by sacrificial layer release, high process implementation difficulty, and low yield. There is an urgent need for a fabrication process that can precisely limit the diaphragm size, effectively suppress lateral etching diffusion, and offset the influence of back cavity etching errors, so as to improve the performance consistency, yield, and reliability of the devices and meet the mass production needs of high-precision MEMS products. Summary of the Invention

[0007] This invention aims to address the problems mentioned in the background art. One or more embodiments of this specification aim to provide a piezoelectric MEMS device fabrication process and device structure. By setting grooves to achieve precise diaphragm size limitation, and employing a front-side release sacrificial layer method, the advantages of front-side etching—"controllable etching range, no lateral diffusion, and minimal damage to the diaphragm"—are fully utilized, avoiding lateral over-etching and improving device performance and yield. Based on the above objectives, one or more embodiments of this specification provide a piezoelectric MEMS device fabrication process, which includes the following steps:

[0008] S1: Provide a substrate having a front and a back side, wherein a groove is formed on the front side of the substrate near the edge region, the groove being used to define the size of the diaphragm region subsequently formed;

[0009] S2: Deposit and pattern a sacrificial layer on the front side of the substrate to expose the groove, wherein the sacrificial layer is divided by the groove into a central region and an edge support region surrounding the groove;

[0010] S3: A piezoelectric-buffer stack is formed and patterned on the sacrificial layer, and a release hole is opened on the piezoelectric-buffer stack. The release hole passes through the piezoelectric-buffer stack and is connected to the central region of the sacrificial layer.

[0011] S4: An etching medium is introduced through the release hole, and the central region of the sacrificial layer is removed using a front-side etching method; and

[0012] S5: Etch the back side of the substrate to form a back cavity.

[0013] In one embodiment of the present invention, the piezoelectric-buffered stack includes a stress buffer layer and a piezoelectric functional layer sequentially formed on the sacrificial layer.

[0014] In one embodiment of the present invention, the sacrificial layer is a silicon dioxide layer.

[0015] In one embodiment of the present invention, the stress buffer layer is a silicon nitride layer.

[0016] In one embodiment of the present invention, the piezoelectric functional layer includes a first electrode layer, a piezoelectric thin film layer and a second electrode layer sequentially formed on the stress buffer layer.

[0017] In one embodiment of the present invention, the lateral dimension of the back cavity is smaller than the lateral dimension of the diaphragm region.

[0018] The present invention also provides a piezoelectric MEMS device structure, which is fabricated using the above-described fabrication process.

[0019] In one embodiment of the present invention, the piezoelectric MEMS device structure includes:

[0020] A substrate having a front and a back side, wherein a groove is formed on the front side of the substrate near the edge of the substrate; and a diaphragm region defined by the groove, wherein the substrate has a back cavity within the diaphragm region; and

[0021] A sacrificial layer formed on the substrate, the sacrificial layer being located on the outer periphery of the groove in an annular structure; and

[0022] A piezoelectric-buffer stack is formed on the sacrificial layer, and a release hole is formed on the piezoelectric-buffer stack after patterning;

[0023] The release hole is used to introduce an etching medium to release the central region of the sacrificial layer located in the groove from the front.

[0024] In one embodiment of the present invention, the release hole extends through the piezoelectric-buffer stack and is disposed corresponding to the diaphragm region.

[0025] The beneficial effects of this invention are:

[0026] 1. This invention defines the diaphragm area size by pre-setting a groove on the front side of the substrate. Compared with the traditional method of defining the diaphragm by etching the back cavity, it completely avoids the diaphragm size error caused by the deep silicon etching angle deviation, accurately locks the diaphragm outline, and greatly improves the size consistency and performance stability of devices in the same batch.

[0027] 2. This invention uses front etching combined with release holes to remove the central area of ​​the sacrificial layer, giving full play to the advantages of front etching, such as "controllable etching range, no lateral diffusion, and minimal damage to the diaphragm". The etching medium only acts on the designated area to effectively suppress the lateral diffusion of etching, eliminate the problem of over-etching in the support area at the edge of the sacrificial layer, completely preserve the support structure, avoid diaphragm damage and device failure, and significantly improve the yield and reliability.

[0028] 3. In this invention, the front sacrificial layer is first etched and released before the substrate back cavity is etched. The size of the back cavity is controlled by the diaphragm area defined by the groove, which offsets the negative impact of back cavity etching error on the core structure of the device. There is no need to strictly control the back cavity etching accuracy, thus reducing the difficulty of process implementation. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in one or more embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the overall structure of the piezoelectric MEMS device in Embodiment 2 of the present invention;

[0031] Figure 2 For the present invention Figure 1 Exploded view;

[0032] Figure 3 For the present invention Figure 1 Cross-sectional view;

[0033] Figures 4 to 10 This is a process flow diagram of the piezoelectric MEMS device structure in Embodiment 1 of the present invention.

[0034] In the attached diagram:

[0035] 10. Base; 101. Back cavity; 102. Groove;

[0036] 20. Sacrificial layer;

[0037] 30. Piezoelectric-buffered stack;

[0038] 301. Stress buffer layer;

[0039] 302. Piezoelectric functional layer;

[0040] 3021, First electrode layer; 3022, Piezoelectric thin film layer; 3023, Second electrode layer; 30221, Electrode exposure point;

[0041] 40. Release hole. Detailed Implementation

[0042] Embodiments of the present invention are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar symbols denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0043] To make the purpose, technical solution, and advantages of this disclosure clearer, the following is combined with Figures 1 to 10 This disclosure will be further described in detail.

[0044] Example 1:

[0045] This embodiment discloses a fabrication process for piezoelectric MEMS devices, such as... Figures 4 to 10 As shown, the preparation process includes the following steps S1 to S5:

[0046] S1: As Figure 4 As shown, a substrate 10 having a front and a back is provided, and a groove 102 is formed on the front of the substrate 10 near the edge region. The groove 102 is used to define the size of the diaphragm region to be subsequently formed.

[0047] By setting a groove 102 on the front edge of the substrate 10, the outer edge boundary of the diaphragm is clearly defined, the diaphragm size is precisely fixed, the consistency of the diaphragm size is effectively improved, and the stability of the device performance is guaranteed.

[0048] The groove 102 can be formed by DRIE (deep silicon etching technology) or by wet etching.

[0049] The substrate 10 can be a silicon substrate, an SOI substrate, or a substrate 10 made of other materials.

[0050] S2: As Figure 5 As shown, a sacrificial layer 20 is deposited and patterned on the front side of the substrate 10, exposing the groove 102. The sacrificial layer 20 is divided by the groove 102 into a central region and an edge support region surrounding the groove 102.

[0051] Preferably, the sacrificial layer 20 is a silicon dioxide layer.

[0052] S3: As Figure 6 As shown, a piezoelectric-buffered stack 30 is formed and patterned on the sacrificial layer 20, and a release hole 40 is opened on the piezoelectric-buffered stack 30. The release hole 40 penetrates the piezoelectric-buffered stack 30 and is connected to the central region of the sacrificial layer 20.

[0053] Specifically, the piezoelectric-buffered stack 30 includes a stress buffer layer 301 and a piezoelectric functional layer 302. The stress buffer layer 301 and the piezoelectric functional layer 302 are sequentially deposited on the sacrificial layer 20. The piezoelectric functional layer 302 includes a first electrode layer 3021, a piezoelectric thin film layer 3022 and a second electrode layer 3023. The first electrode layer 3021, the piezoelectric thin film layer 3022 and the second electrode layer 3023 are sequentially formed on the stress buffer layer 301.

[0054] This application does not limit the patterning order of the stress buffer layer 301. It can be patterned before the piezoelectric functional layer 302 is deposited, or it can be patterned after the piezoelectric functional layer 302 is deposited and patterned.

[0055] Preferably, the stress buffer layer 301 is a silicon nitride layer. For example... Figure 7 and Figure 8 As shown, the formation of the piezoelectric functional layer 302 includes the following steps:

[0056] In step S31, a first electrode layer 3021, a piezoelectric thin film layer 3022, and a second electrode layer 3023 are sequentially formed on the stress buffer layer 301. The first electrode layer 3021, the piezoelectric thin film layer 3022, and the second electrode layer 3023 can be formed by magnetron sputtering or other processes. Preferably, the material of the piezoelectric thin film layer 3022 is PZT (lead zirconate titanate).

[0057] S32 sequentially patterns the second electrode layer 3023, the piezoelectric thin film layer 3022 and the first electrode layer 3021 to form the piezoelectric functional layer 302.

[0058] Specifically, the piezoelectric thin film layer 3022 has an electrode exposure port 30221 to facilitate the lead wire of the first electrode layer 3021. The release hole 40 extends from the piezoelectric thin film layer 3022 to the stress buffer layer 301, and the release hole 40 is set corresponding to the diaphragm area to ensure that during the subsequent introduction of the etching medium, under the limiting effect of the groove 102, the etching medium only etches the central area of ​​the sacrificial layer 20. The second electrode layer 3023 can be a circular electrode, and the second electrode layer 3023 does not cover the release hole 50.

[0059] S4: As Figure 9 As shown, etching medium is introduced through the release hole 40 to etch and remove the central region of the sacrificial layer 20 from the front. Due to the setting of the groove 102, the lateral diffusion of the etching medium can be restricted, avoiding over-etching of the edge support area of ​​the sacrificial layer 20.

[0060] Specifically, the etching medium is introduced into the release hole 50 and enters the central region of the sacrificial layer 20 through the release hole 50 to contact and release the central region of the sacrificial layer 20, thereby achieving precise removal of the central region of the sacrificial layer 20. The etching medium is a gas phase etching gas, such as VHF (Vapor HF, hydrogen fluoride vapor). Since VHF (Vapor HF, hydrogen fluoride vapor) has an extremely high selectivity for silicon dioxide in the sacrificial layer 20, while causing no damage to silicon, silicon nitride, metal electrodes, and piezoelectric thin film layer 402, the diaphragm structure is released without damage.

[0061] The etching medium can also be a wet etching solution. Wet etching solutions have a high etching rate for the sacrificial layer 20 silicon dioxide, which can quickly remove the central area of ​​the sacrificial layer, greatly improve the preparation efficiency, and are suitable for mass production.

[0062] S5: As Figure 10 As shown, the back surface of the substrate is etched to form a back cavity. Specifically, the back cavity 101 can be formed by etching the back surface of the substrate 10 using DRIE (Deep Silicon Etching) technology. The lateral dimension of the back cavity is smaller than the lateral dimension of the diaphragm region, further ensuring the reliability of the diaphragm support.

[0063] Example 2:

[0064] like Figures 1 to 3 As shown, the present invention also discloses a piezoelectric MEMS device structure, which is fabricated using the fabrication process described in Example 1 above.

[0065] Specifically, the piezoelectric MEMS device structure includes a substrate 10 having a front and a back side, with a groove 102 formed on the front side of the substrate 10 near the edge of the substrate 10 to define the size of the diaphragm region to be formed subsequently.

[0066] Due to the formation of the groove 102, subsequent film deposition will fill the groove 102, so that when the etching medium is introduced through the release hole 40, only the central region of the sacrificial layer 20 is etched. In addition, the substrate 10 has a back cavity 101 to provide vibration space for the diaphragm. The lateral dimension of the back cavity is smaller than the lateral dimension of the diaphragm region, which can further ensure the reliability of the diaphragm support.

[0067] The piezoelectric MEMS device structure also includes a sacrificial layer 20 formed on the substrate 10, which is located on the outer periphery of the groove 102 in a ring structure.

[0068] The sacrificial layer 20 is patterned twice to form a final annular structure, which can be used to enhance the adhesion between the substrate 10 and each film layer.

[0069] After the central region of the sacrificial layer 20 is completely released, the membrane layer above the sacrificial layer 20, corresponding to the central region of the sacrificial layer 20, is suspended relative to the substrate 10.

[0070] Specifically, after the sacrificial layer 20 is deposited on the substrate 10, the sacrificial layer 20 is patterned for the first time to expose the groove 102. At this time, ICP (Inductively Coupled Plasma Etching) technology can be used for etching. After the stress buffer layer 301 is patterned, the central region of the sacrificial layer 20 is completely released by introducing the etching medium through the release hole 40, forming the final annular structure of the sacrificial layer 20.

[0071] Preferably, the sacrificial layer 20 is a silicon dioxide layer. The central region of the sacrificial layer 20 is released by introducing an etching medium through the release hole 40. The etching medium can be a vapor phase etching gas, such as VHF (Vapor HF, hydrogen fluoride vapor). The silicon dioxide layer has excellent compatibility with the functional layers of the piezoelectric MEMS device, is stable at high temperatures, and has no interface diffusion or reaction, which can improve the reliability of the device. Moreover, the silicon dioxide layer can be highly matched with the VHF (Vapor HF, hydrogen fluoride vapor) vapor phase etching process, with stable etching rate and high selectivity. VHF (Vapor HF, hydrogen fluoride vapor) does not damage silicon, silicon nitride, metal electrodes and piezoelectric thin film layer 402, realizing the non-destructive release of the diaphragm structure.

[0072] The etching medium can also be a wet etching solution. Wet etching solutions have a high etching rate for the sacrificial layer 20 silicon dioxide, which can quickly remove the central area of ​​the sacrificial layer, greatly improve the preparation efficiency, and are suitable for mass production.

[0073] The piezoelectric MEMS device structure also includes a piezoelectric-buffer stack 30 formed on the sacrificial layer 20. After patterning, a release hole 40 is formed on the piezoelectric-buffer stack 30 for introducing an etching medium to release the central region of the sacrificial layer 20 from the front.

[0074] The piezoelectric-buffered stack 30 includes a stress buffer layer 301 and a piezoelectric functional layer 302. The piezoelectric functional layer 302 and the stress buffer layer 301 are patterned to form a release hole 40, which is connected to the central region of the sacrificial layer 20.

[0075] Specifically, the piezoelectric functional layer 302 includes a first electrode layer 3021, a piezoelectric thin film layer 3022, and a second electrode layer 3023 sequentially formed on the sacrificial layer 20. The piezoelectric thin film layer 3022 is provided with an electrode exposure port 30221 to facilitate the lead wires of the first electrode layer 3021 to be brought out.

[0076] The release hole 40 penetrates the piezoelectric-buffer stack 30 and is set in the diaphragm area, so that the etching medium only etches the central area of ​​the sacrificial layer 20 and does not cause over-etching of the edge support area of ​​the sacrificial layer 20.

[0077] The number of release holes 40 is at least two and symmetrically distributed, for example, four, which can uniformly etch the central region of the sacrificial layer 20. The second electrode layer 3023 can be a circular electrode, and the second electrode layer 3023 does not cover the release holes 40.

[0078] The stress buffer layer 301 is located between the sacrificial layer 20 and the piezoelectric functional layer 302. It is used to buffer and match the internal stress between the piezoelectric thin film layer 3022, the first electrode layer 3021, the second electrode layer 3022, and the sacrificial layer 20, so as to avoid cracking, warping or falling off of the multilayer film structure due to stress mismatch and improve the structural integrity.

[0079] Preferably, the stress buffer layer 301 is a silicon nitride layer. Silicon nitride has a high selectivity to the etching medium and can serve as a reliable etching barrier layer to protect the upper piezoelectric thin film layer 3022, the first electrode layer 3021, and the second electrode layer 3023 from etching damage during the release of the sacrificial layer 20.

[0080] One or more embodiments of this specification are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of this disclosure.

[0081] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A fabrication process for a piezoelectric MEMS device, characterized in that, The preparation process includes the following steps: S1: Provide a substrate having a front and a back side, wherein a groove is formed on the front side of the substrate near the edge region, the groove being used to define the size of the diaphragm region subsequently formed; S2: Deposit and pattern a sacrificial layer on the front side of the substrate to expose the groove, wherein the sacrificial layer is divided by the groove into a central region and an edge support region surrounding the groove; S3: A piezoelectric-buffer stack is formed and patterned on the sacrificial layer, and a release hole is opened on the piezoelectric-buffer stack. The release hole passes through the piezoelectric-buffer stack and is connected to the central region of the sacrificial layer. S4: The etching medium is introduced through the release hole, and the central region of the sacrificial layer is removed by front etching. S5: Etch the back side of the substrate to form a back cavity.

2. The preparation process according to claim 1, characterized in that, The piezoelectric-buffered stack includes a stress buffer layer and a piezoelectric functional layer formed sequentially on the sacrificial layer.

3. The preparation process according to claim 1, characterized in that, The sacrificial layer is a silicon dioxide layer.

4. The preparation process according to claim 2, characterized in that, The stress buffer layer is a silicon nitride layer.

5. The preparation process according to claim 2, characterized in that, The piezoelectric functional layer includes a first electrode layer, a piezoelectric thin film layer, and a second electrode layer formed sequentially on the stress buffer layer.

6. The preparation process according to claim 1, characterized in that, The lateral dimension of the back cavity is smaller than the lateral dimension of the diaphragm region.

7. A piezoelectric MEMS device structure, characterized in that, It is processed using the preparation process described in any one of claims 1-6.

8. The piezoelectric MEMS device structure according to claim 7, characterized in that, The piezoelectric MEMS device structure includes: A substrate having a front and a back side, wherein a groove is formed on the front side of the substrate near the edge of the substrate; and a diaphragm region defined by the groove, wherein the substrate has a back cavity within the diaphragm region; and A sacrificial layer formed on the substrate, the sacrificial layer being located on the outer periphery of the groove in an annular structure; and A piezoelectric-buffer stack is formed on the sacrificial layer, and a release hole is formed on the piezoelectric-buffer stack after patterning; The release hole is used to introduce an etching medium to release the central region of the sacrificial layer located in the groove from the front.

9. The device structure according to claim 8, characterized in that, The release hole penetrates the piezoelectric-buffer stack and is provided corresponding to the diaphragm region.

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