A front-etching-based MEMS device preparation process and device structure

Abstract

The application discloses a preparation process and a device structure of a MEMS device based on front etching, and relates to the technical field of piezoelectric MEMS device preparation. The process comprises the following steps: forming a first groove and a second groove on the front surface of a substrate at the center of the substrate and near the edge of the substrate respectively; forming an adhesion layer and patterning the same, the adhesion layer is divided into a center region and an edge region by the second groove, a piezoelectric-buffer stack is formed on the adhesion layer and is patterned, a plurality of release holes are formed on the piezoelectric-buffer stack, an etching medium is introduced from the release holes, the center adhesion region of the adhesion layer is removed, and the piezoelectric-buffer stack corresponding to the center region is protruded to the side away from the substrate. The application does not need to etch and release a back cavity from the back of the device, thereby avoiding the size error, the alignment deviation and the substrate damage caused by the deep groove etching of the back cavity, effectively improving the consistency of the device structure size, and significantly improving the performance uniformity and the batch production yield of the piezoelectric MEMS device.

Description

Technical Field

[0001] This invention relates to the field of piezoelectric MEMS device fabrication technology, and in particular to a MEMS device fabrication process and device structure based on front etching. Background Technology

[0002] Piezoelectric MEMS devices, with their advantages of miniaturization, low power consumption, and high integration, are widely used in microelectromechanical products such as resonators, microphones, and accelerometers. The precision and consistency of their fabrication process directly determine the device's performance and mass production yield. Currently, the industry generally uses a process combining surface micromachining and bulk micromachining to fabricate piezoelectric MEMS devices. The core vibration cavity back cavity structure is mainly formed by etching the silicon substrate from the back of the wafer. This traditional process has many difficult-to-solve technical defects in actual mass production, which seriously restricts the performance consistency and production yield of the devices.

[0003] On the one hand, it is difficult to precisely control the dimensional uniformity of back cavity etching. The thickness of silicon substrates is usually hundreds of micrometers. When deep silicon etching equipment etches the back cavity, the etching process will inevitably produce an etching angle tolerance of 1-2° due to factors such as equipment precision and etching gas flow field distribution. This results in irregular tilting of the back cavity sidewalls and significant deviations in the back cavity depth and aperture size at different locations on different wafers and on different locations on the same wafer. The consistency of the back cavity structure is greatly reduced, which in turn causes large dispersion of core performance parameters such as device vibration frequency and sensitivity, making it impossible to meet the standardization requirements for mass application.

[0004] On the other hand, back-side etching is also prone to substrate damage and alignment misalignment. The high-energy etching process of deep silicon etching can cause mechanical stress and ion bombardment damage to the silicon substrate, which may lead to microcracks and lattice distortion in the substrate, affecting the bonding stability between the substrate and the upper film layer, and increasing the risk of film cracking and delamination during later use of the device. At the same time, back-side etching requires precise front-to-back alignment of the wafer. Small deviations during the alignment process can cause the relative position of the back cavity and the front piezoelectric functional layer to shift, disrupting the vibration matching relationship of the device and further reducing the operational reliability of the device.

[0005] For example, patent document application number 202210746380.8 discloses a method for forming a back cavity, a device with a back cavity, a method for fabricating a MEMS microphone, and a MEMS microphone. In this method, the substrate is etched to form a groove during back cavity formation; a sacrificial layer is filled into the groove, and the sacrificial layer is removed to allow adjacent sub-cavities to connect through the groove, thus forming the back cavity. This solves the problem of difficult-to-control etching processes deep within the back cavity, improving the reliability of the device. However, this solution also has drawbacks: it requires substrate etching to release the back cavity, and it is difficult to avoid dimensional errors, alignment deviations, and substrate damage caused by deep groove etching of the back cavity.

[0006] In summary, the existing fabrication process for piezoelectric MEMS devices relies on back-side etching to form a back cavity, which presents technical challenges such as poor structural consistency, easy substrate damage, and high process complexity.

[0007] Therefore, there is an urgent need in the field for a MEMS device manufacturing method that can eliminate the influence of back cavity etching errors, simplify the fabrication process, and improve device performance consistency and batch yield. Summary of the Invention

[0008] This invention aims to solve the problems mentioned in the background art. This specification proposes a MEMS device fabrication process and device structure based on front etching in one or more embodiments. By pre-etching a first groove on the front side of the substrate, and then using a release hole to introduce an etching medium to release the central region of the adhesion layer, the piezoelectric-buffer stack bulges upward due to the warping of the film layer. A vibration cavity is formed between the first groove and the piezoelectric-buffer stack. There is no need to release the back cavity from the back side at the end, eliminating the influence of back cavity etching error, thereby significantly improving the performance consistency and batch yield of the piezoelectric MEMS device.

[0009] To achieve the above objectives, one or more embodiments of this specification provide a MEMS device fabrication process based on front-side etching, the fabrication process comprising the following steps:

[0010] S1: A substrate having a front and a back side is provided, and a first groove and a second groove are formed on the front side of the substrate at the center of the substrate and near the edge of the substrate, respectively.

[0011] S2: An adhesive layer is formed on the front side of the substrate and the adhesive layer is patterned to expose the second groove, the adhesive layer being divided into a central region and an edge region by the second groove;

[0012] S3: A piezoelectric-buffered stack is formed on the adhesive layer and the piezoelectric-buffered stack is patterned. A plurality of release holes are opened on the piezoelectric-buffered stack. The release holes penetrate the piezoelectric-buffered stack and are connected to the central region of the adhesive layer.

[0013] S4: An etching medium is introduced through the release hole to etch away the central adhesion area of ​​the adhesion layer from the front, so that the part of the piezoelectric-buffer stack corresponding to the central area protrudes away from the substrate under stress.

[0014] The groove of the first groove and the lower surface of the raised piezoelectric-buffered stack together form a closed vibration cavity.

[0015] In one embodiment of the present invention, the piezoelectric-buffered stack includes a stress buffer layer and a piezoelectric functional layer, wherein the stress buffer layer and the piezoelectric functional layer are sequentially formed on the adhesive layer.

[0016] In one embodiment of the present invention, the piezoelectric functional layer includes a first electrode layer, a piezoelectric thin film layer, and a second electrode layer, wherein the first electrode layer, the piezoelectric thin film layer, and the second electrode layer are sequentially formed on the stress buffer layer.

[0017] In one embodiment of the present invention, the piezoelectric thin film layer is any one of lead zirconate titanate, aluminum nitride, or zinc oxide piezoelectric thin film.

[0018] In one embodiment of the present invention, the adhesion layer is a silicon dioxide layer.

[0019] In one embodiment of the present invention, the stress buffer layer is a silicon nitride layer.

[0020] In one embodiment of the present invention, the release holes are located on the sidewall of the first groove near the second groove, and are evenly distributed in a ring array around the center of the piezoelectric-buffer stack.

[0021] The present invention also provides a piezoelectric MEMS device structure based on front etching, which is fabricated using the above-mentioned process. The device structure does not require a back cavity, and the portion of the central region of the piezoelectric-buffer stack corresponding to the adhesion layer protrudes away from the substrate.

[0022] In one embodiment of the present invention, the piezoelectric MEMS device structure includes:

[0023] A base having a front and a back side, wherein a first groove and a second groove are formed at the center of the base and near the edge of the base, respectively;

[0024] An adhesion layer formed on the substrate, the adhesion layer being located on the outer periphery of the second groove in a ring-shaped structure; and

[0025] A piezoelectric-buffer stack is formed on the adhesion layer. After being patterned, a release hole is formed on the piezoelectric-buffer stack. The release hole is located on the side wall of the first groove near the second groove and is evenly distributed in a ring array around the center of the piezoelectric-buffer stack.

[0026] The groove of the first groove and the lower surface of the raised piezoelectric-buffered stack together form a closed vibration cavity.

[0027] The beneficial effects of this invention are:

[0028] 1. The method and structure of the present invention pre-etches a first groove on the front side of the substrate. After releasing the central region of the adhesion layer, the piezoelectric-buffer stack bulges upward under the action of film stress and together with the first groove forms a closed vibration cavity. There is no need to etch and release the back cavity from the back of the device, thereby avoiding the dimensional errors, alignment deviations and substrate damage caused by deep groove etching of the back cavity. This effectively improves the consistency of device structure dimensions and significantly enhances the performance uniformity and mass production yield of piezoelectric MEMS devices.

[0029] 2. The method and structure of this invention remove the adhesion layer in the central region by introducing an etching medium through a release hole. Under the action of internal stress, the piezoelectric-buffer stack naturally bulges upward to form a curved structure, which increases the effective strain area of ​​the film layer and makes the d31 / d33 electromechanical coupling effect of the piezoelectric thin film layer more fully converted into mechanical displacement. At the same time, compared with the flat film structure, the bulging curved structure can reduce the mechanical stiffness of the film layer, improve the device sensitivity and vibration amplitude, and generate charge output more efficiently under the action of external vibration.

[0030] 3. The adhesion layer of this invention uses silicon dioxide, which not only enhances the adhesion of the film layer, but also acts as a sacrificial layer that can be efficiently and selectively removed by specific etching media. The piezoelectric thin film layer is preferably PZT, which has extremely high piezoelectric constant and electromechanical coupling coefficient, and its stress characteristics are easily controlled. The stress buffer layer uses silicon nitride, which can achieve good stress matching with the upper and lower film layers, ensuring the stability of the protrusion morphology. Simultaneously, it has extremely high selectivity to the aforementioned etching media, serving as a reliable etching barrier layer. During the release of the adhesion layer, it perfectly protects the upper piezoelectric functional layer and electrodes from damage. This material combination ensures the feasibility of the front-side release process and the long-term reliability of the device. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in one or more embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the overall structure of the piezoelectric MEMS device in Embodiment 3 of the present invention;

[0033] Figure 2 For the present invention Figure 1 Exploded view;

[0034] Figure 3 For the present invention Figure 1 Cross-sectional view;

[0035] Figures 4 to 8This is a process flow diagram of the piezoelectric MEMS device structure in Embodiment 1 of the present invention;

[0036] Figures 9 to 10 This is a process flow diagram of the piezoelectric MEMS device structure in Embodiment 2 of the present invention.

[0037] In the attached diagram:

[0038] 10. Base; 101. First groove; 102. Second groove;

[0039] 20. Adhesive layer;

[0040] 30. Piezoelectric-buffered stack;

[0041] 301. Stress buffer layer;

[0042] 302. Piezoelectric functional layer;

[0043] 3021, First electrode layer; 3022, Piezoelectric thin film layer; 3023, Second electrode layer; 30221, Electrode exposure point;

[0044] 40. Release hole;

[0045] 50. Vibrating cavity. Detailed Implementation

[0046] Embodiments of the present invention are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar symbols denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0047] To make the purpose, technical solution, and advantages of this disclosure clearer, the following is in conjunction with... Figures 1 to 10 The embodiments describe the specific fabrication process and device structure of the MEMS device based on front etching of the present invention.

[0048] Example 1:

[0049] This embodiment discloses a MEMS device fabrication process based on front-side etching, such as... Figures 4 to 8 As shown, the preparation process includes the following steps S1 to S4:

[0050] S1: As Figure 4 As shown, a substrate 10 having a front and a back side is provided, and a first groove 101 and a second groove 102 are formed on the front side of the substrate 10 at the center of the substrate 10 and near the edge of the substrate 10, respectively.

[0051] This application does not limit the type of substrate 10; it can be a silicon substrate, an SOI substrate, or a substrate of other materials.

[0052] The second groove 102 can be formed by DRIE (deep silicon etching technology) or by wet etching. The first groove 101 can be formed using the same process as the second groove 102.

[0053] S2: As Figure 5 As shown, an adhesive layer 20 is formed on the front side of the substrate 10 and patterned, exposing the second groove 102. The adhesive layer 20 is divided into a central region and an edge region by the second groove 102.

[0054] Preferably, the adhesion layer 20 is a silicon dioxide layer, used to enhance the adhesion between the substrate 10 and the upper film layer and prevent film cracking. The central region of the adhesion layer 20 serves as a sacrificial layer, which will be etched and released in subsequent processes, while the edge region of the adhesion layer serves as a support layer to support the film layer on its surface.

[0055] S3: As Figure 6 As shown, a piezoelectric-buffered stack 30 is formed and patterned on the adhered layer 10, and a plurality of release holes 40 are formed on the piezoelectric-buffered stack 30. The release holes 40 penetrate the piezoelectric-buffered stack 30 and are connected to the central region of the adhesion layer 20.

[0056] The release holes 40 are located on the side wall of the first groove 102 near the second groove 102, and are evenly distributed in a ring array around the center of the piezoelectric-buffer stack. The piezoelectric-buffer stack 30 includes a stress buffer layer 301 and a piezoelectric functional layer 302, which are sequentially formed on the adhesion layer 20.

[0057] The stress buffer layer 301 enables good stress matching between the various film layers, ensuring the stability of the diaphragm protrusion shape, preventing diaphragm cracking and deformation, and extending the service life of the device.

[0058] like Figure 6 and 7 As shown, the specific fabrication process of the piezoelectric-buffer stack 30 includes the following steps S31a~S32a:

[0059] S31a first deposits a stress buffer layer 301 on the surface of the adhesion layer 20 using a PECVD (plasma-enhanced chemical vapor deposition) process, and then deposits a piezoelectric functional layer 302 on the surface of the stress buffer layer 301 using a magnetron sputtering process. The piezoelectric functional layer 301 includes a first electrode layer 3021, a piezoelectric thin film layer 3022, and a second electrode layer 3023, which are sequentially deposited on the stress buffer layer 301.

[0060] S32a then sequentially patterns the second electrode layer 3023, the piezoelectric thin film layer 3022, the first electrode layer 3021, and the stress buffer layer 301. After patterning, a release hole 40 and an electrode exposure port 30221 are formed. The release hole 40 extends from the piezoelectric thin film layer 3022 to the stress buffer layer 301, and the electrode exposure port 30221 extends through the piezoelectric thin film layer 3022, serving to lead out the leads of the first electrode layer 3021. The piezoelectric thin film layer can be any one of lead zirconate titanate, aluminum nitride, or zinc oxide piezoelectric thin films.

[0061] Preferably, the piezoelectric thin film layer 3022 is a PZT (lead zirconate titanate) layer. PZT thin films possess extremely high piezoelectric constants (d31) and electromechanical coupling coefficients. Compared to commonly used aluminum nitride (AlN) or zinc oxide (ZnO) materials, their energy conversion efficiency can be improved by more than 10 times, significantly enhancing the device's sensitivity and output performance. Simultaneously, the stress characteristics of PZT thin films are easily controlled, and when combined with a stress buffer layer (silicon nitride layer), a stable upward bulge in the diaphragm region can be precisely achieved.

[0062] S4: As Figure 8 As shown, an etching medium is introduced through the release hole 40 to etch and remove the central adhesion area of ​​the adhesion layer 20 from the front side, causing the portion of the piezoelectric-buffer stack 30 corresponding to the central area to bulge away from the substrate 10 under stress.

[0063] The groove of the first groove 101 and the lower surface of the raised piezoelectric-buffered stack 30 together form a closed vibration cavity 50.

[0064] Specifically, the etching medium is introduced into the release hole 40 and enters through the release hole 40 to contact the central region of the adhesion layer 20, thereby releasing the central region of the adhesion layer 20 and achieving precise removal of the central region of the adhesion layer 20.

[0065] The etching medium can be a gas phase etching gas, such as VHF (Vapor HF, hydrogen fluoride vapor). Since VHF (Vapor HF, hydrogen fluoride vapor) has an extremely high selectivity for the adhesion layer 20 silicon dioxide, while causing no damage to silicon, silicon nitride, metal electrodes and piezoelectric thin film layer 3022, the diaphragm structure can be released without damage.

[0066] The etching medium can also be a wet etching solution. Wet etching solutions have a high etching rate for the 20 silicon dioxide adhesion layer, which can quickly remove the central region of the sacrificial layer, greatly improve the preparation efficiency, and are suitable for mass production.

[0067] Under internal stress, the piezoelectric-buffer stack 302 naturally bulges upward to form a curved structure, which cooperates with the first groove 101 to form a closed vibration cavity 50. This eliminates the need to etch the back cavity from the back of the device, thus avoiding dimensional errors, alignment deviations, and substrate 10 damage caused by deep groove etching of the back cavity. This effectively improves the consistency of the device structure dimensions and significantly enhances the performance uniformity and mass production yield of the piezoelectric MEMS device. The upward bulge of the piezoelectric-buffer stack 302 to form a curved structure increases the effective strain area of ​​the film layer, allowing the d31 / d33 electromechanical coupling effect of the piezoelectric thin film layer 3022 to be more fully converted into mechanical displacement. At the same time, compared with the flat film structure, the bulging curved structure can reduce the mechanical stiffness of the film layer, improve the device sensitivity and vibration amplitude, and generate charge output more efficiently under external vibration.

[0068] Preferably, the stress buffer layer 301 is a silicon nitride layer. Silicon nitride has a high selectivity for VHF (Vapor HF, hydrogen fluoride vapor) gas phase etching and wet etching solutions, and can serve as a reliable etching barrier layer to protect the upper piezoelectric thin film layer 3022, the first electrode layer 3021, and the second electrode layer 3023 from etching damage during the release of the adhesion layer 20.

[0069] Example 2:

[0070] like Figures 9 to 10 As shown, this embodiment, based on Embodiment 1, also provides a fabrication process. Specifically, in S3, the fabrication process of the piezoelectric-buffer stack 30 can also be formed by the following processes, including S31b~S32b:

[0071] S31b first deposits a stress buffer layer 301 on the surface of the adhesion layer 20 using a PECVD (plasma-enhanced chemical vapor deposition) process, and then patterns the stress buffer layer 301.

[0072] S32b then deposits a piezoelectric functional layer 302 on the surface of the stress buffer layer 301 using a magnetron sputtering process. The piezoelectric functional layer 302 includes a first electrode layer 3021, a piezoelectric thin film layer 3022, and a second electrode layer 3023. The first electrode layer 3021, the piezoelectric thin film layer 3022, and the second electrode layer 3023 are sequentially deposited on the stress buffer layer 301. Then, the second electrode layer 3023, the piezoelectric thin film layer 3022, and the first electrode layer 3021 are patterned sequentially to form the final piezoelectric-buffer stack 30.

[0073] The fabrication process of the piezoelectric-buffer stack 30 can be selected according to requirements. Preferably, the process of Example 1 is used to fabricate the piezoelectric-buffer stack 30. The process of Example 1 can ensure the bonding force and stress uniformity of the piezoelectric-buffer stack, accurately control the upward convex shape of the diaphragm, and ensure compatibility with the front vapor phase etching process, thereby improving device consistency and reliability.

[0074] Example 3:

[0075] This embodiment discloses a piezoelectric MEMS device structure based on front etching, which is fabricated using the fabrication process of Embodiment 1 or 2 above.

[0076] Specifically, such as Figures 1 to 3 As shown, the piezoelectric MEMS device structure includes a substrate 10 with a front and a back side. A first groove 101 and a second groove 102 are formed at the center of the substrate 10 and near the edge of the substrate 10, respectively. Due to the formation of the second groove 102, the second groove 102 will be filled during subsequent film deposition. The film will separate the central region and the edge region of the adhesion layer 20, so that when etching gas is introduced through the release hole 40, only the central region of the adhesion layer 20 is etched.

[0077] The piezoelectric MEMS device structure also includes an adhesion layer 20 formed on the substrate 10, which is located on the outer periphery of the second groove 102 in a ring-shaped structure. After the adhesion layer 20 is deposited on the substrate 10, the final ring structure is formed through two patterning processes. The first patterning can be performed using ICP (Inductively Coupled Plasma Etching) technology to form the first groove 101. The second patterning is performed after patterning the piezoelectric-buffer stack 30, by introducing an etching medium through the release hole 40 to completely release the central region of the adhesion layer 20, forming the final ring-shaped adhesion layer. The ring-shaped adhesion layer 20 not only enhances the adhesion between the film layers but also supports the film layers on their surfaces.

[0078] The piezoelectric MEMS device structure also includes a piezoelectric-buffer stack 30 formed on the adhesion layer 20. A release hole 40 is formed on the piezoelectric-buffer stack 30 after patterning. A vibration cavity 50 is formed between the first groove 101 and the piezoelectric-buffer stack 30. The portion of the piezoelectric-buffer stack 30 corresponding to the central region bulges away from the substrate 10 under stress.

[0079] The piezoelectric-buffered stack 30 includes a stress buffer layer 301 and a piezoelectric functional layer 302 sequentially formed on the adhesion layer 20. The piezoelectric functional layer 302 includes a first electrode layer 3021, a piezoelectric thin film layer 3022, and a second electrode layer 3023. The first electrode layer 3021, the piezoelectric thin film layer 3022, and the second electrode layer 3023 are sequentially deposited on the stress buffer layer 301, and then the second electrode layer 3023, the piezoelectric thin film layer 3022, the first electrode layer 3021, and the stress buffer layer 301 are patterned sequentially.

[0080] The release holes 40 penetrate the piezoelectric-buffer stack 30 and are located on the sidewall of the first groove 101 near the second groove 102. They are evenly distributed in a ring array around the center of the piezoelectric-buffer stack 30. Because the release holes 40 are evenly distributed in a ring array around the center of the piezoelectric-buffer stack 30 and are densely distributed, when the central region of the adhesion layer 20 is released, the portion of the piezoelectric-buffer stack 30 corresponding to the central region is more likely to bulge under stress. The cavity of the first groove 102 and the lower surface of the bulging piezoelectric-buffer stack 30 together form a sealed vibration cavity 50.

[0081] The second electrode layer 3023 can be a circular electrode, and the second electrode layer 3023 does not cover the release hole 40.

[0082] The piezoelectric-buffer stack 30 is also provided with an electrode exposure port 30221, which penetrates the piezoelectric thin film layer 3022 and is used to lead out the lead wire of the first electrode layer 3021.

[0083] One or more embodiments of this specification are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of this disclosure.

[0084] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A MEMS device fabrication process based on front-side etching, characterized in that, The preparation process includes the following steps: S1: A substrate having a front and a back side is provided, and a first groove and a second groove are formed on the front side of the substrate at the center of the substrate and near the edge of the substrate, respectively. S2: An adhesive layer is formed on the front side of the substrate and the adhesive layer is patterned to expose the second groove, the adhesive layer being divided into a central region and an edge region by the second groove; S3: A piezoelectric-buffered stack is formed on the adhesive layer and the piezoelectric-buffered stack is patterned. A plurality of release holes are opened on the piezoelectric-buffered stack. The release holes penetrate the piezoelectric-buffered stack and are connected to the central region of the adhesive layer. S4: An etching medium is introduced through the release hole to etch and remove the central adhesion area of ​​the adhesion layer from the front, so that the part of the piezoelectric-buffer stack corresponding to the central area protrudes away from the substrate under stress. The groove of the first groove and the lower surface of the raised piezoelectric-buffered stack together form a closed vibration cavity.

2. The preparation process according to claim 1, characterized in that, The piezoelectric-buffered stack includes a stress buffer layer and a piezoelectric functional layer, wherein the stress buffer layer and the piezoelectric functional layer are sequentially formed on the adhesive layer.

3. The preparation process according to claim 2, characterized in that, The piezoelectric functional layer includes a first electrode layer, a piezoelectric thin film layer, and a second electrode layer, wherein the first electrode layer, the piezoelectric thin film layer, and the second electrode layer are sequentially formed on the stress buffer layer.

4. The preparation process according to claim 3, characterized in that, The piezoelectric thin film layer is any one of lead zirconate titanate, aluminum nitride, or zinc oxide piezoelectric thin film.

5. The preparation process according to claim 1, characterized in that, The adhesion layer is a silicon dioxide layer.

6. The preparation process according to claim 2, characterized in that, The stress buffer layer is a silicon nitride layer.

7. The preparation process according to claim 1, characterized in that, The release holes are located on the side wall of the first groove near the second groove, and are evenly distributed in a ring array around the center of the piezoelectric-buffer stack.

8. A piezoelectric MEMS device structure based on front-side etching, characterized in that, The device is manufactured using the fabrication process described in any one of claims 1-7. The device structure does not require a back cavity, and a portion of the central region of the piezoelectric-buffer stack corresponding to the adhesive layer protrudes away from the substrate.

9. The piezoelectric MEMS device structure according to claim 8, characterized in that, The piezoelectric MEMS device structure includes: A substrate having a front and a back side, wherein a first groove and a second groove are formed at the center of the front side of the substrate and near its edge, respectively; and An adhesion layer formed on the substrate, the adhesion layer being located on the outer periphery of the second groove in a ring-shaped structure; and A piezoelectric-buffered stack is formed on the adhesion layer. After being patterned, the piezoelectric-buffered stack forms a release hole. The release hole is located on the side wall of the first groove near the second groove and is evenly distributed in a ring array around the center of the piezoelectric-buffered stack. The groove of the first groove and the lower surface of the raised piezoelectric-buffered stack together form a closed vibration cavity.

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