An optimized signal path design method for high frequency signal transmission

Abstract

The application relates to an optimized signal path design method for high-frequency signal transmission, comprising the following steps: constructing a 3D model under high-frequency electromagnetic field simulation, taking key geometric dimensions as variables; performing TDR simulation analysis on the 3D model to obtain a capacitive impedance drop result, setting a reverse pad structure according to the capacitive impedance drop result, and removing non-functional pads; fusing the reverse pads in the reverse pad structure by using a differential, performing S parameter simulation on the fused model, taking the optimal return loss in a target frequency band as a preliminary optimization target function, and further adjusting the key geometric dimensions by using an optimizer until the S parameter curve generated by simulation meets the template requirements of a standard, so that an optimal PCB package is obtained.

Description

Technical Field

[0001] This invention relates to the field of electronic interconnection technology, and in particular to an optimized signal path design method for high-frequency signal transmission. Background Technology

[0002] With the explosive growth of 5G communications, cloud computing data centers, and high-performance computing (HPC), the interconnection speed of electronic systems has leaped from the traditional Mbps level to 112 Gbps or even 224 Gbps. In such high-frequency microwave bands (millimeter wave band, 30 GHz-300 GHz), traditional electronic connectors are no longer just mechanical connection components, but must be regarded as complex microwave transmission lines.

[0003] For Ningbo Zhilun Electronic Co., Ltd., a national-level specialized and innovative "little giant" enterprise, although it has deep experience and a major market share in RJ45 communication connectors and I / O interfaces (serving leading customers such as Huawei, ZTE, and H3C), traditional "rule-of-fact" designs are no longer sufficient to meet the stringent signal integrity (SI) requirements in the face of the evolution of new-generation high-speed standards such as Gen-Z and PCIe 6.0. At high frequencies, any tiny geometrical abrupt change (such as pad size, via spacing, and reference layer distance) will trigger significant electromagnetic wave reflection and radiation, leading to an increase in the bit error rate (BER).

[0004] In high-speed interconnect links, the transition region (Launch Region / Breakout Region) from the PCB trace to the connector is known as the "critical inch." This is the region where the electromagnetic field distribution changes most drastically throughout the entire link: the signal is transmitted from the microstrip / strip line (planar field distribution) on the PCB surface or inner layer to the connector contact pins (quasi-coaxial or twisted-pair field distribution). During this transition, it must pass through the plated vias (PTH) on the PCB. In traditional PCB design, connector pads and vias are usually considered lumped-parameter components. However, when the signal frequency exceeds 10GHz, vias exhibit strong distributed-parameter effects: excessive capacitance, the parasitic capacitance formed by the via barrel and the surrounding ground plane causes a sharp drop in characteristic impedance (e.g., from 50Ω to 35Ω), forming a "capacitive valley"; stub resonance: if the connector pins do not need to penetrate the entire PCB thickness, or if the signal is transmitted from an inner layer, the remaining via stub will form an open-circuit stub. When the stub length is 1 / 4 of the signal wavelength, total internal reflection resonance will occur, causing the signal to be completely unable to transmit at a specific frequency point; ground loop discontinuity: if there are not enough ground pins or ground vias around the connector signal pins, the return path of high-frequency current will be blocked, forcing the return current to find a longer path, thereby generating huge loop inductance, causing crosstalk and electromagnetic interference (EMI).

[0005] Currently, existing technical solutions typically only provide the S-parameter model of the connector itself, or a recommended footprint based on a specific reference stack-up. However, in practical applications, customers' PCB stack-up structures vary greatly (different board thicknesses, dielectric constants Dk, and number of layers). This presents two problems: 1. Static design failure: A footprint optimized for a 1.6mm FR4 board, when directly applied to a 3.0mm Megtron 6 backplane, may experience complete impedance mismatch due to variations in via length and dielectric parameters; 2. Lack of system-level optimization: Existing designs often separate the "connector" from the "PCB," lacking a method for parametric co-design that treats both as a unified electromagnetic system.

[0006] Existing technologies also offer various solutions to the signal integrity issues at the connector-PCB interconnection point. However, through in-depth comparative analysis, these existing technologies all have varying degrees of shortcomings, making it difficult to simultaneously meet the requirements of high performance, low cost, and design flexibility.

[0007] Existing Solution 1: Back-Drilling is currently the most common physical method for solving the via stub problem. After PCB lamination and electroplating are completed, a depth-controlled drill is used to drill away the unused metal wall of the via from the backside of the board, thereby shortening the length of the stub.

[0008] Existing drawbacks: 1. High cost: Back-drilling is a complex process requiring high-precision depth control equipment, significantly increasing PCB manufacturing costs (typically by 10%-20%). 2. Stub remnant: Mechanical drilling has depth tolerances (typically + / - 2 mil or greater). To avoid drilling through effective signal layers, a safety margin must be maintained, resulting in 5-10 mil of residual stubs. At speeds of 56Gbps and above (millimeter-wave band), even a 10 mil residual stub can cause significant resonant shift and return loss degradation. 3. Limited routing channels: The diameter of back-drilled holes is usually larger than the original via diameter, which disrupts routing space on adjacent layers and reduces routing efficiency in high-density PCBs.

[0009] Existing Solution 2: Discrete Component Matching discloses the use of small inductor / capacitor components (such as 0201 packages) connected in series or parallel near the connector pads to form an L-type or π-type matching network to cancel the parasitic reactance introduced by the connector (e.g., using inductors to cancel via capacitance).

[0010] Existing drawbacks: 1. High-frequency parasitic effects: This method is effective at low frequencies (<5GHz), but at high frequencies (>10GHz), the pad capacitance and package inductance of the discrete components themselves become significant, and the matching components become a new source of signal degradation. 2. Bandwidth limitation: Lumped parameter matching is usually narrowband. An impedance adjusted at one frequency (e.g., 10GHz) may be severely mismatched at its doubling frequency (20GHz), failing to meet the requirements of broadband digital signals (from DC to Nyquist frequencies). 3. Space occupation: Modern high-density connectors (such as the high-density I / O connectors manufactured by Zhilun Electronics) have extremely small pin pitches, and there is often no physical space on the PCB to place additional matching components.

[0011] 3.3 Existing Solution 3: Blind / Buried Vias discloses the use of laser drilling technology to create blind or buried holes that only connect specific layers, thus completely eliminating residual piles from a physical structural perspective.

[0012] Existing drawbacks: 1. Complex and expensive manufacturing process: Blind and buried vias require multiple lamination processes (HDI process), costing several times more than through-hole boards, making them unsuitable for mass production of consumer or standard industrial electronic products. 2. Reliability issues: Stacked microvias have a higher reliability risk under thermal cycling than through-holes, potentially leading to interlayer fracture.

[0013] Existing Solution 4: Simple Via Fencing discloses drilling a ring of ground vias around the signal vias to form a shielding structure similar to a coaxial cable.

[0014] Existing drawbacks: 1. Inaccurate impedance control: Many designs rely solely on experience to place ground vias. If a ground via is too close to a signal via, it will drastically increase parasitic capacitance, causing the impedance to drop below 40Ω and resulting in severe reflections. 2. Resonant cavity effect: If the spacing of ground vias is not properly designed, the enclosed area may form a resonant cavity in the microwave frequency band, which not only fails to shield but also amplifies noise radiation at specific frequencies.

[0015] In summary, existing technologies are too costly to implement (back drilling, HDI), fail at high frequencies (discrete matching), and lack a systematic parametric design method (empirical shielding). Summary of the Invention

[0016] 1. To address the problems existing in the prior art, the present invention aims to provide an optimized signal path design method for high-frequency signal transmission, solving the impedance drop problem caused by excessive parasitic capacitance in connector pads and via areas. Without relying on expensive HDI processes, it achieves a smooth impedance transition from connector to PCB (target: 50Ω±5% or differential 100Ω±10%). When vias cannot be completely avoided, it optimizes the electromagnetic field distribution around the vias to reduce or mitigate resonance valleys caused by frequency shifting residuals, thereby widening the effective transmission bandwidth. Furthermore, it provides a design method that can adaptively adjust optimization parameters (such as anti-pad size and ground hole spacing) according to different PCB stack-up parameters (board thickness, Dk, Df), rather than providing a single fixed package drawing. Specifically for high-frequency network connectors and Gen-Z connectors, it focuses on solving the balance between internal coupling maintenance and external crosstalk suppression (NEXT / FEXT).

[0017] To achieve the above objectives, the present invention provides the following solution: An optimized signal path design method for high-frequency signal transmission includes: A 3D model for high-frequency electromagnetic field simulation is constructed, with key geometric dimensions as variables. TDR simulation analysis was performed on the 3D model to obtain the capacitive impedance drop results. Based on the capacitive impedance drop results, an anti-pad structure was set and non-functional pads were removed. The anti-pads in the anti-pad structure are fused using differential methods. S-parameter simulation is performed on the fused model. The optimal return loss in the target frequency band is used as the objective function for initial optimization. The key geometric dimensions are adjusted using an optimizer until the simulated S-parameter curve meets the standard template requirements, thereby obtaining the optimal PCB package.

[0018] Optionally, constructing the 3D model under the high-frequency electromagnetic field simulation includes: Import the 3D component model of the connector model, which includes signal pins, ground shielding sheet and insulator material properties; Obtain the PCB manufacturing process, and based on the PCB manufacturing process, determine the number of PCB layers, the thickness of the copper foil dielectric material, and the roughness model, and set the key geometric dimensions as variables.

[0019] Optionally, the key geometric dimensions include: signal pad diameter, surface antipad diameter, antipad diameter on the inner reference ground plane, center distance between return ground via and signal via, fanout trace width, and stub length.

[0020] Optionally, performing TDR simulation analysis on the 3D model includes: TDR simulation analysis is performed on the 3D model. When the TDR curve is concave downward, it indicates that the region is capacitive. When the TDR curve is convex upward, it indicates that the region is inductive. The physical location of the impedance change point is determined by the time axis of the TDR curve. The physical location includes: the pad, the intermediate layer of the via, and the residual pile.

[0021] Optionally, setting the anti-pad structure includes: Replace the cylindrical antipad with a funnel-shaped or drum-shaped antipad structure, expand the antipad in the antipad structure on each reference ground plane through which the via passes, expand the antipad to a first target range in the intermediate layer where signal coupling is strong, and shrink the antipad to a first target range near the surface layer.

[0022] Optionally, removing the non-functional pads includes: in an inner layer where no electrical connection is made, removing the metal pad ring on the signal via, leaving only the via copper pillar.

[0023] Optionally, fusing the antipads in the antipad structure using differential includes: fusing the two independent antipads of P / N into an elliptical cavity using the differential.

[0024] Optionally, the objective function includes: ; in, The objective function value, The starting frequency of the target frequency band. This is the cutoff frequency for the target frequency band. For frequency variables, For frequency The weighting coefficients at the point, For frequency S-parameter return loss amplitude at the location, This is the preset target threshold for return loss.

[0025] The beneficial effects of this invention are as follows: Improved impedance consistency: This invention reduces the impedance fluctuation range of the connector via area from the traditional ±15% to within ±5%, eliminating the "capacitive pit" on the TDR curve.

[0026] Improved return loss: This invention generally improves return loss by 3-5dB in the DC-25GHz band. For example, at 12.8GHz, S11 is optimized from -10dB to -18dB, significantly reducing signal reflection.

[0027] Crosstalk suppression: This invention reduces near-end crosstalk (NEXT) by approximately 6dB through an optimized "GSSG" ground hole layout, meeting the anti-interference requirements of high-density connectors (such as the I / O series from Zhilun Electronics).

[0028] Bandwidth expansion: Successfully increased the available bandwidth limit of traditional through-hole structures by 30%-50%, enabling low-cost PCB processes to carry higher-speed signals.

[0029] Low cost and high performance: The core advantage of this invention lies in replacing expensive process compensation (such as back drilling or blind / buried vias) with design compensation (changing the pattern). For Zhilun Electronics, this means being able to offer products that meet high-end performance requirements at a more competitive price.

[0030] Design Agility: This invention is not dependent on a specific connector type. Whether it's RJ45, SFP, or Gen-Z, as long as the corresponding 3D model is input, the algorithm can generate the optimal PCB package.

[0031] System-level solution: This invention can provide customers with proven reference designs, enhancing customer stickiness and upgrading from simply "selling components" to "selling interconnect solutions".

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a flowchart of an optimized signal path design method for high-frequency signal transmission according to an embodiment of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] like Figure 1 As shown, this embodiment discloses an optimized signal path design method for high-frequency signal transmission, including: constructing a 3D model under high-frequency electromagnetic field simulation, where the 3D model uses key geometric dimensions as variables; performing TDR simulation analysis on the 3D model to obtain capacitive impedance drop results; setting an anti-pad structure and removing non-functional pads based on the capacitive impedance drop results; fusing the anti-pads in the anti-pad structure using differential methods; performing S-parameter simulation on the fused model; using optimal return loss within the target frequency band as the initial optimization objective function; and further using an optimizer to adjust the key geometric dimensions until the simulated S-parameter curve meets the standard template requirements, thereby obtaining the optimal PCB package. More specifically: Core Design Methodology: The core of this invention lies in modeling the connector and PCB as a unified three-dimensional electromagnetic system, and finding the optimal solution for geometric parameters through algorithms. The specific process is as follows: Step 1: Construct a parametric 3D simulation model: Use high-frequency electromagnetic field simulation software (such as Ansys HFSS or CSTMicrowave Studio) to construct a 3D model containing the following elements.

[0037] Connector Model: Import 3D component models, including signal pins, ground shields, and insulator material properties.

[0038] PCB layer stack-up environment: Based on the actual production process, accurately define the number of PCB layers, dielectric material (such as FR4 or Megtron 6 / 7), copper foil thickness, and roughness model (Huray Model).

[0039] Parameterized variable settings: Set key geometric dimensions as variables instead of fixed values. Dpad: Signal pad diameter, Danti-pad_L1: Surface anti-pad diameter, Danti-pad_Ln: Anti-pad diameter on the inner layer reference ground plane (key innovation: can be changed independently for each layer), Sground: Center distance between return ground via and signal via, Wbreakout: Fanout trace width, Lstub: Estimated stub length.

[0040] Step 2, Initial Time Domain Reflection (TDR) Diagnosis: Perform TDR simulation analysis on the unoptimized initial model.

[0041] Diagnostic logic: Observe the TDR curve. If the curve dips downwards (impedance < system impedance), it indicates that the region is capacitive, usually caused by parasitic capacitance of via pads. If the curve bulges upwards (impedance > system impedance), it indicates that the region is inductive, usually caused by pin inductance or via length.

[0042] Location: Use the time axis of the TDR to accurately correspond to the physical location to determine whether the impedance change point is at the pad, the middle layer of the via, or the residual pile.

[0043] Step 3, Impedance Compensation based on the "coaxial air cavity" principle: For the capacitive impedance drop diagnosed by TDR, this invention adopts a layer-wise voiding strategy.

[0044] Physical principle: The impedance formula for a coaxial transmission line is... To increase Z0 (to compensate for capacitive dips), the outer diameter D (anti-pad diameter) must be increased or the equivalent dielectric constant εr must be decreased.

[0045] Implementation plan: On each reference ground plane through which the vias pass, the size of the anti-pad is flexibly adjusted according to different situations.

[0046] Non-uniform design: Unlike traditional cylindrical anti-pads with uniform top and bottom, this invention designs anti-pad structures in the form of "funnel" or "drum". For example, in the middle layer where signal coupling is strong, the anti-pad size is increased to reduce coupling capacitance; while near the surface layer, a smaller anti-pad size is used compared to the middle layer to maintain mechanical strength.

[0047] Non-functional pad removal (NFP Removal): On inner layers where no electrical connection is made, completely remove the metal pad ring on the signal via, leaving only the via copper pillar. This significantly reduces the metal surface area, thereby reducing parasitic capacitance by 10%-15%.

[0048] Step 4, Differential Pair Coupling Tuning: For Zhilun Electronics' Gen-Z or RJ45 differential pair products: Oval Anti-Pad: Traditional differential via designs typically use two separate, independent circular anti-pads, which leads to discontinuous dielectric distribution between the differential pairs, thus affecting signal quality. This invention addresses the insulation gap regions formed by the positive P and negative N terminals when crossing the reference ground plane in differential signal transmission lines—the independent anti-pads of P and N—by using geometric modeling technology to connect and merge them into a large elliptical (racetrack-shaped) cavity.

[0049] Effect: This integrated antipad structure can significantly improve the dielectric uniformity between differential pairs, ensuring tight coupling between differential pairs (P and N) (maintaining differential impedance) and increasing the distance between differential pairs and the reference ground plane (P / N and GND) (reducing common-mode capacitance and improving common-mode impedance).

[0050] Step 5, Mode Resonance Suppression and Ground Fence: For resonance caused by stubs: Optimize the location of ground vias: Arrange 2-4 ground vias around the signal vias.

[0051] Algorithm optimization: By scanning the distance Sground between the ground via and the signal via. When Sground decreases, the loop inductance decreases and the high-frequency return path is shorter, but this increases capacitance. This method seeks a "sweet spot" that optimizes the return loss (S11) within the target frequency band (e.g., 0-25GHz) while shifting the resonant frequency outside the operating frequency band.

[0052] Step 6, Automatic Iteration and Convergence: Set the optimization objective function (Cost Function): ; The above variables are automatically adjusted using the optimizer built into the simulation software (such as a Genetic Algorithm). Driven by optimizing the return loss within the target frequency band, the geometric dimensions are iterated continuously until the simulated S-parameter curve meets the template requirements of the IEEE 802.3 or PCIe standard.

[0053] In one embodiment, two specific examples are given below in conjunction with the products of Ningbo Zhilun Electronics.

[0054] Example 1: Optimized design applied to Gen-Z high-speed connectors: Application scenario: High-speed memory expansion interface inside a server, with a speed of 56GT / s PAM4 11. PCB parameters: 12-layer board, 2.0mm thickness, material Megtron 6 (Dk=3.7). Specific structure: Signal hole: drilled with a diameter of 0.25mm.

[0055] Anti-pad design: The diameter of the L2 (ground) anti-pad is set to 1.4mm. The diameter of the L3-L10 (signal transmission area) anti-pads is increased to 1.6mm to form an air cavity to reduce capacitance. The L11 (bottom layer) anti-pad is reduced to 1.2mm to match the BGA fanout. All non-functional pads (NFPs) on the inner layers are removed. Return vias: One ground via is placed on each side of the differential pair, with a spacing of 1.0mm, forming a "GSSG" structure. Back-drilling: Back-drilling is only performed from L12 to L10, and the residual stub is controlled within 8mil. Results: Simulation shows that this structure has an S11 better than -15dB at 28GHz, and the impedance is controlled at 85±3Ω.

[0056] Low-cost optimized design for 10G RJ45 connectors: Application scenario: 5G base station or enterprise-level switch network port, speed 10Gbps. PCB parameters: 6-layer board, board thickness 1.6mm, material FR4 (Dk=4.2).

[0057] Specific structure: Strategy: Do not use back drills (to reduce costs), and rely entirely on geometric optimization to compensate for the stub effect.

[0058] Anti-pad gradient: Since the stub exists at the bottom (assuming the signal enters at the Top layer, exits at the L3 layer, and L4-L6 are stubs), this invention significantly increases the size of the anti-pad in the L4, L5, and L6 layers (30% larger than the standard value).

[0059] Principle: By expanding the cavity around the stub, the characteristic impedance of the stub itself is reduced, causing its resonant frequency to shift to higher frequencies, thereby ensuring signal integrity within a 10GHz bandwidth.

[0060] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A method for optimizing signal path design for high-frequency signal transmission, characterized in that, include: A 3D model for high-frequency electromagnetic field simulation is constructed, with key geometric dimensions as variables. TDR simulation analysis was performed on the 3D model to obtain the capacitive impedance drop results. Based on the capacitive impedance drop results, an anti-pad structure was set and non-functional pads were removed. The anti-pads in the anti-pad structure are fused using differential methods. S-parameter simulation is performed on the fused model. The optimal return loss in the target frequency band is used as the objective function for initial optimization. The key geometric dimensions are adjusted using an optimizer until the simulated S-parameter curve meets the standard template requirements, thereby obtaining the optimal PCB package.

2. The optimized signal path design method for high-frequency signal transmission according to claim 1, characterized in that, Constructing the 3D model under the high-frequency electromagnetic field simulation includes: Import the 3D component model of the connector model, which includes signal pins, ground shielding sheet and insulator material properties; Obtain the PCB manufacturing process, and based on the PCB manufacturing process, determine the number of PCB layers, the thickness of the copper foil dielectric material, and the roughness model, and set the key geometric dimensions as variables.

3. The optimized signal path design method for high-frequency signal transmission according to claim 1, characterized in that, The key geometric dimensions include: signal pad diameter, surface antipad diameter, antipad diameter on the inner reference ground plane, center distance between return ground via and signal via, fanout trace width, and residual stud length.

4. The optimized signal path design method for high-frequency signal transmission according to claim 1, characterized in that, The TDR simulation analysis of the 3D model includes: TDR simulation analysis is performed on the 3D model. When the TDR curve is concave downward, it indicates that the region is capacitive. When the TDR curve is convex upward, it indicates that the region is inductive. The physical location of the impedance change point is determined by the time axis of the TDR curve. The physical location includes: the pad, the intermediate layer of the via, and the residual pile.

5. The optimized signal path design method for high-frequency signal transmission according to claim 1, characterized in that, Setting the antipad structure includes: Replace the cylindrical antipad with a funnel-shaped or drum-shaped antipad structure, expand the antipad in the antipad structure on each reference ground plane through which the via passes, expand the antipad to a first target range in the intermediate layer where signal coupling is strong, and shrink the antipad to a first target range near the surface layer.

6. The optimized signal path design method for high-frequency signal transmission according to claim 1, characterized in that, Removing the non-functional pads includes: in the inner layer where no electrical connection is made, removing the metal pad ring on the signal via, leaving only the via copper pillar.

7. The optimized signal path design method for high-frequency signal transmission according to claim 1, characterized in that, The method of fusing the antipads in the antipad structure using differential includes: using the differential to fuse the two independent antipads of P / N into an elliptical cavity.

8. The optimized signal path design method for high-frequency signal transmission according to claim 1, characterized in that, The objective function includes: ； in, The objective function value, The starting frequency of the target frequency band. This is the cutoff frequency for the target frequency band. For frequency variables, For frequency The weighting coefficients at the point, For frequency S-parameter return loss amplitude at the location, This is the preset target threshold for return loss.

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