A second-order adjustable transistor with time-domain programmable characteristics and a preparation method thereof
By introducing a ferroelectric material barrier layer and coupling it with the floating gate charge trapping mechanism in the floating gate transistor, multi-time factor modulation of neuromorphic devices is realized, solving the problem of single time response of existing devices and providing low power consumption and high efficiency for multi-scenario adaptability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHAOXIN LABORATORY
- Filing Date
- 2026-03-23
- Publication Date
- 2026-07-14
AI Technical Summary
Existing neuromorphic devices have a single time response characteristic, making it difficult to achieve multiple stable time factors and a wide adjustment range without external circuitry or under continuous bias conditions. This results in a narrow detection speed range, making it difficult to adapt to the needs of various application scenarios.
By introducing an electrically programmable polarization state ferroelectric material barrier layer into the floating gate transistor structure, and combining it with the floating gate charge trapping mechanism, the height of the Schottky barrier at the floating gate interface can be dynamically controlled by programming the polarization state, thereby achieving dynamic controllability of photogenerated carrier release and forming multiple stable time factors.
It enables the adjustment of multiple stable time factors without the need for continuous external bias voltage or additional control circuitry, reducing system complexity and power consumption, expanding the time-domain response freedom of neuromorphic transistors, and adapting to multi-speed motion detection and multi-scenario applications.
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Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices, specifically to a second-order tunable transistor with time-domain programmable characteristics and its fabrication method, and more particularly to a neuromorphic phototransistor device and its fabrication technology that achieves tunable relaxation time of photogenerated carriers based on ferroelectric polarization effect and floating gate charge trapping coupling mechanism. Background Technology
[0002] With the rapid development of intelligent sensing and artificial intelligence technologies, "in-sensory computing" technology based on neuromorphic devices has gradually become an important development direction for next-generation sensors. These devices integrate information acquisition and processing by introducing synaptic-like dynamic behavior within the sensing unit, offering advantages such as compact structure, fast response speed, and low power consumption. They have broad application prospects, especially in motion detection and dynamic visual perception.
[0003] However, existing neuromorphic devices generally suffer from a lack of diverse time response characteristics. Specifically, most devices possess only a single, fixed time factor (t0), and their photogenerated carrier relaxation time or conductance decay time is either unadjustable or has a limited range of adjustment. In motion velocity detection applications based on "in-sensory computing," different motion speeds correspond to different time scale requirements. When the device's time factor is fixed, it can only effectively identify targets within a specific speed range, resulting in a narrow detectable speed range and difficulty in adapting to the needs of various application scenarios.
[0004] To address the above problems, existing technologies typically employ the following two strategies to adjust the time factor: (1) Switching between different time response modes through an external control circuit. This approach requires the introduction of additional control modules and logic units, which not only increases chip area and manufacturing cost but also increases system complexity, hindering the development of highly integrated sensing chips.
[0005] (2) The device is adjusted as a whole by continuously applying an external bias voltage. This method is a global control strategy, which is difficult to achieve independent adjustment for local or multi-target speed scenarios. At the same time, continuous bias will increase power consumption, which is not conducive to the realization of low power consumption system.
[0006] Therefore, how to introduce new physical degrees of freedom within a single neuromorphic device, enabling it to achieve multiple stable and programmable time factors without additional external circuitry or continuous bias, has become a pressing technical problem in this field.
[0007] In recent years, floating-gate transistors based on two-dimensional materials have been considered a potential technological path for constructing novel neuromorphic devices due to their excellent carrier control capabilities, ultra-thin structure, and strong gate coupling ability. In such devices, the lifetime of photogenerated carriers is a key parameter affecting the motion velocity detection performance. Its magnitude is closely related to the release dynamics of the trapped charge in the floating-gate structure, and this release process is influenced by the band structure and the distribution of the interface barrier.
[0008] However, the band structure of existing two-dimensional material floating gate devices is usually essentially fixed after fabrication, lacking an adjustable mechanism and making it difficult to achieve dynamic responses across multiple time scales. Therefore, it is necessary to introduce functional materials or structural units that can dynamically control the internal electric field and band structure to expand the device's time-domain adjustability.
[0009] Ferroelectric materials, due to their electrically programmable and non-volatile polarization properties, can form stable polarization states under the influence of an applied electric field, inducing internal electric field reconstruction and thus altering the interface barrier distribution and carrier transport characteristics. Therefore, combining the ferroelectric polarization effect with the floating gate charge trapping mechanism holds promise for achieving tunable control of photogenerated carrier relaxation dynamics in a single device structure, thereby overcoming the technical bottlenecks of traditional neuromorphic devices with their single time factor and limited response range.
[0010] In summary, the existing technology still lacks a neuromorphic transistor structure that can achieve multiple stable time factors and a wide adjustment range without the need for additional external circuitry or continuous bias. Summary of the Invention
[0011] To realize a neuromorphic transistor structure with multiple stable time factors and a wide adjustment range, this application provides a second-order tunable transistor with time-domain programmable characteristics and its fabrication method.
[0012] The second-order tunable transistor with time-domain programmable characteristics provided in this application adopts the following technical solution: In a first aspect, a second-order tunable transistor with time-domain programmable characteristics includes: an insulating substrate; Including the gate bottom electrode located on the surface of the insulating substrate; Includes a barrier layer that covers the gate bottom electrode and a portion of the insulating substrate; It includes a floating gate layer, which is disposed on the barrier layer; It includes a tunneling layer that covers the floating grid layer and the barrier layer; It includes a trench layer, which is disposed on the tunnel layer; It includes a source and a drain, which are disposed on the channel layer; The barrier layer is a ferroelectric material layer with an electrically programmable polarization state; The polarization state of the ferroelectric material layer and the charge trapping behavior of the floating gate layer form a coupling mechanism, which is used to control the height of the Schottky barrier at the floating gate interface. The modulation of the Schottky barrier is used to change the release dynamics of photogenerated carriers, thereby enabling time-domain programmable adjustment of multiple different time factors without the need for a continuous external bias voltage.
[0013] By adopting the above technical solution, a ferroelectric material barrier layer with electrically programmable polarization states is introduced into the floating gate transistor structure, so that the ferroelectric polarization effect and the floating gate charge trapping mechanism form a stable physical coupling relationship. From the structural level, a device system with built-in controllable band structure is constructed. Under the action of an external electric pulse, the ferroelectric material generates different non-volatile polarization states, thereby changing the built-in electric field distribution and Schottky barrier height at the floating gate interface, so that the release rate of the trapped photogenerated carriers changes controllably. The carrier release dynamics directly determine the photogenerated current decay process and relaxation time of the device. Since the time factor can be actively adjusted by programming the polarization state, unlike the control method that relies on external control circuits or continuous bias voltage, the non-volatile characteristics of ferroelectric polarization can maintain a predetermined time response state without continuous external voltage. Multiple stable time scales can be switched within a single device structure, expanding the degree of freedom of neuromorphic transistors in the time domain, reducing system complexity and power consumption, and providing a programmable and low-power hardware implementation path for multi-velocity motion detection and multi-scenario "in-sensory computing" applications.
[0014] Optionally, the bottom gate electrode completely covers the area where the floating gate layer is located in the top view direction; The source and drain electrodes partially overlap with the channel layer, and the channel region formed between the source and drain electrodes is completely within the projection range of the floating gate layer.
[0015] By adopting the above technical solution, the bottom electrode of the gate completely covers the floating gate layer region in the top view direction, which enhances the gate's ability to control the electric field of the floating gate and improves the consistency and stability of polarization modulation. At the same time, the channel region is completely located within the projection range of the floating gate layer, ensuring that the behavior of channel carriers is fully controlled by the floating gate charge and ferropolarization, thereby improving the accuracy and reliability of time factor adjustment.
[0016] Optionally, the barrier layer is a ferroelectric hafnium zirconium oxide material layer; The atomic ratio of hafnium to zirconium in the ferroelectric hafnium-zirconium oxide is 1:1.
[0017] By adopting the above technical solution, using ferroelectric hafnium-zirconium oxide as a barrier layer, and controlling the atomic ratio of hafnium to zirconium to be 1:1, it is beneficial to obtain a stable ferroelectric phase structure and good residual polarization performance, thereby enhancing the polarization control capability and non-volatile built-in electric field strength, improving the time factor adjustment range and device operating stability.
[0018] Optionally, the floating gate layer is a platinum metal layer; The tunneling layer is a hafnium oxide layer; The channel layer is a two-dimensional semiconductor material layer; the channel layer is an indium gallium zinc oxide semiconductor layer.
[0019] By adopting the above technical solutions, using platinum metal as a floating gate layer can improve the charge storage stability and interface barrier controllability; using hafnium oxide as a tunneling layer is beneficial to achieving stable charge injection and retention; selecting two-dimensional semiconductors or indium gallium zinc oxide as the channel layer can improve carrier modulation sensitivity and photoresponse characteristics, thereby enhancing the time factor adjustment effect and the applicability of the device.
[0020] Optionally, the two-dimensional semiconductor material is molybdenum sulfide.
[0021] By adopting the above technical solutions, photoelectric response capability is enhanced, and carrier control accuracy and time adjustment sensitivity are improved.
[0022] Optionally, the ferroelectric material layer is rapidly thermally annealed to crystallize and form a ferroelectric phase structure, which is used to generate a non-volatile polarization built-in electric field. By applying electrical pulses of different amplitudes to set the polarization state of the ferroelectric material layer, the relaxation time of photogenerated carriers can be adjusted in the range of milliseconds to seconds.
[0023] By adopting the above technical solution, rapid thermal annealing promotes the formation of a stable ferroelectric phase structure in ferroelectric materials, which can establish a non-volatile polarization built-in electric field. Then, by programming the polarization state through electric pulses of different amplitudes, the potential barrier at the floating gate interface and the carrier release rate can be precisely controlled, thereby realizing the programmable adjustment of the time factor in the range of milliseconds to seconds.
[0024] In a second aspect, a method for fabricating a second-order tunable transistor with time-domain programmable characteristics as described in any one of claims 1-6, characterized in that it comprises the following steps: Step S1: Clean the insulating substrate; Step S2: Form a gate bottom electrode pattern on the insulating substrate; Step S3: Deposit a ferroelectric barrier layer on the bottom gate electrode; Step S4: Perform rapid thermal annealing on the ferroelectric barrier layer to induce its crystallization and form a ferroelectric phase; Step S5: Form a floating gate layer on the barrier layer; Step S6: Deposit the tunneling layer; Step S7: Form the channel layer; Step S8: Form the source and drain electrodes; The polarization state of the ferroelectric barrier layer can be programmed and set by an external electrical pulse to regulate the potential barrier at the floating gate interface, thereby enabling programmable adjustment of the device's time factor.
[0025] By employing the above technical solution, a stable bottom gate structure is formed through substrate cleaning and gate bottom electrode patterning, providing a foundation for subsequent electric field control. Subsequently, a ferroelectric barrier layer is deposited and rapidly thermally annealed to induce crystallization, forming a stable ferroelectric phase. This endows the material with electrically programmable and non-volatile polarization characteristics, establishing an adjustable built-in electric field source at the material level. Based on this, a floating gate layer and a tunneling layer are sequentially constructed, enabling the floating gate to capture and retain charges, and achieving controlled charge injection and release through the tunneling medium. Further, a channel layer and source / drain electrodes are formed, constructing a complete current control path. The synergistic design of layer structure and process sequence enables the ferroelectric polarization state to be programmed and stably maintained through external electrical pulses, thereby regulating the barrier height and charge release rate at the floating gate interface. Ultimately, this achieves precise control over the relaxation dynamics of photogenerated carriers, obtaining multiple stable time factors without the need for a continuous external bias voltage. This method has a clear process path, and the material system is compatible with mainstream semiconductor processes. It has the technical advantages of strong feasibility, good repeatability, and ease of large-scale fabrication, providing a reliable process implementation scheme for building low-power, multi-timescale response neuromorphic devices.
[0026] Optionally, the ferroelectric barrier layer is deposited using an atomic layer deposition method; The rapid thermal annealing was carried out in a nitrogen atmosphere at a temperature range of 450℃-650℃. The channel layer is formed by transferring two-dimensional semiconductor material using a polystyrene-assisted transfer method; The channel layer is formed by depositing an indium gallium zinc oxide thin film using a radio frequency sputtering method; The source and drain electrodes are patterned by electron beam lithography and formed by electron beam evaporation to deposit metallic materials.
[0027] By adopting the above technical solutions, atomic layer deposition forms a ferroelectric barrier layer, which enables precise control of film thickness and composition, improving device consistency. Rapid thermal annealing in a nitrogen atmosphere is beneficial for the stable formation of a ferroelectric phase structure. Using polystyrene-assisted transfer or radio frequency sputtering to form a channel layer, combined with electron beam lithography and electron beam evaporation to prepare source and drain electrodes, can improve device interface quality and fabrication accuracy, thereby improving overall performance and stability.
[0028] Optionally, the ferroelectric polarization effect and the floating gate charge trapping mechanism constitute a dual physical coupling control mechanism, enabling the device to have multiple stable time factors in a single structure.
[0029] By adopting the above technical solution, the ferroelectric polarization effect is combined with the floating gate charge capture mechanism to form a dual physical coupling control mechanism. This mechanism can simultaneously realize polarization electric field modulation and charge storage control in a single device structure, thereby changing the carrier release dynamics and enabling the device to have multiple stable programmable time factors, thus improving the flexibility of time-domain response.
[0030] Optionally, the multiple time factors correspond to the relaxation time of photogenerated carriers under different polarization states, which can be used to adapt to sensing tasks with different motion speeds.
[0031] By adopting the above technical solution and setting multiple polarization states, the device can correspond to different photogenerated carrier relaxation times under different polarization states, thereby forming multiple adjustable time factors. This enables the device to match signal changes at different time scales, improving the sensing ability and recognition accuracy of targets with different moving speeds.
[0032] In summary, this application includes at least one of the following beneficial technical effects: 1. This application introduces a ferroelectric material barrier layer with an electrically programmable polarization state into the floating gate transistor structure, so that the ferroelectric polarization effect and the floating gate charge trapping mechanism form a coupled control relationship, realizing the controllable design of the energy band structure of the floating gate interface from the structural level, thereby modulating the release dynamics of photogenerated carriers, enabling the device to obtain multiple stable time factors in a single structure, breaking through the technical limitation of the single time factor of traditional neuromorphic devices. 2. This application utilizes the non-volatile polarization characteristics of ferroelectric materials to program and set the polarization state through electrical pulses, and maintains the predetermined time response state when the power is off. The switching and maintenance of the time factor can be achieved without continuously applying an external bias voltage or relying on additional control circuits, thereby effectively reducing system power consumption and simplifying the peripheral circuit structure. 3. By rationally designing the spatial structural relationship between the gate bottom electrode, floating gate layer, tunneling layer and channel layer, the channel region is completely within the floating gate control range. Combined with ferroelectric polarization modulation, the ability to control carrier transport behavior is improved, thereby enhancing the stability and repeatability of time factor adjustment. 4. This application adopts ferroelectric hafnium zirconium oxide materials, two-dimensional semiconductor materials or indium gallium zinc oxide channels and combines them with atomic layer deposition, rapid thermal annealing and electron beam lithography to make the device structure compatible with existing semiconductor processes. It has the advantages of strong feasibility, high fabrication precision and easy mass production. 5. This application enables the device to form multiple time factors ranging from milliseconds to seconds by adjusting the relaxation time of photogenerated carriers under different polarization states. This allows it to adapt to the dynamic signal processing requirements of different time scales, improve the sensing capability of targets with different motion speeds, and provide a new hardware implementation path for realizing a low-power, high-efficiency "in-sensory computing" neuromorphic sensing system. Attached Figure Description
[0033] Figure 1 This is a side view of the second-order adjustable transistor with time programmable characteristics according to an embodiment of this application.
[0034] Figure 2 This is a schematic flowchart illustrating the fabrication method of a second-order tunable transistor with time-programmable characteristics according to an embodiment of this application.
[0035] Figure 3 This is a schematic diagram of the electrical characteristic curves of a second-order adjustable transistor with time programmability according to an embodiment of this application.
[0036] Figure 4 This is a schematic diagram of the photoelectric characteristic curves of a second-order tunable transistor with time programmability in an embodiment of this application.
[0037] Explanation of reference numerals in the attached figures: 1. Insulating substrate; 2. Gate bottom electrode; 3. Barrier layer; 4. Floating gate layer; 5. Tunneling layer; 6. Two-dimensional material channel layer; 7. Source and drain. Detailed Implementation
[0038] The following is in conjunction with the appendix Figure 1-4 This application will be described in further detail.
[0039] This application discloses a second-order tunable transistor with time-domain programmable characteristics, referring to... Figure 1 The system includes: an insulating substrate 1, a gate bottom electrode 2 located on the upper surface of the insulating substrate, a barrier layer 3 covering the gate electrode 2 and the insulating substrate 1, a floating gate layer 4 made of metal covering the barrier layer 3, a tunneling layer 5 covering the floating gate layer 4 and the barrier layer 3, a two-dimensional channel layer 6 covering the surface of the tunneling layer 5, and source and drain electrodes 7 located on the channel layer 6. For the barrier layer 3, a ferroelectric layer with polarization effect is introduced to improve the control of carrier relaxation time. The Schottky barrier at the floating gate interface is adjusted by adjusting the polarization state, thereby regulating the dynamics of photocarrier release. The gate bottom electrode 2 is made of cadmium and platinum, with thicknesses of 5 nanometers and 7 nanometers, respectively. Barrier layer 3 covers the gate bottom electrode 2 and part of the insulating substrate. Barrier layer 3 is a ferroelectric hafnium zirconium oxide material layer with a thickness of 10 nanometers. The atomic ratio of hafnium to zirconium in the ferroelectric hafnium zirconium oxide is 1:1. A floating gate layer 4 is disposed on a barrier layer 3; a tunneling layer 5 covers the floating gate layer 4 and the barrier layer 3; the floating gate layer 4 is a platinum layer with a thickness of 5 nanometers, and the tunneling layer 5 is a hafnium oxide layer with a thickness of 4 nanometers. The channel layer 6 is disposed on the tunneling layer 5, and the channel layer 6 is a two-dimensional semiconductor material layer; the channel layer 6 is an indium gallium zinc oxide semiconductor layer, and the two-dimensional semiconductor material is molybdenum sulfide. The source and drain 7 are disposed on the channel layer 6. The channel layer 6 is made of molybdenum sulfide, a two-dimensional semiconductor material. The source and drain 7 partially overlap with the channel layer 6, and the channel region formed between the source and drain is completely within the projection range of the floating gate layer 4. The source and drain 7 are made of cadmium and gold, respectively, with thicknesses of 5 nanometers and 40 nanometers. Among them, the barrier layer 3 is a ferroelectric material layer with an electrically programmable polarization state. The ferroelectric material layer is crystallized by rapid thermal annealing to form a ferroelectric phase structure, which is used to generate a non-volatile polarization built-in electric field. By applying electrical pulses of different amplitudes, the polarization state of the ferroelectric material layer is set, thereby realizing the adjustable relaxation time of photogenerated carriers in the range of milliseconds to seconds. The polarization state of the ferroelectric material layer and the charge trapping behavior of the floating gate layer 4 form a coupling mechanism to control the height of the Schottky barrier at the floating gate interface. The modulation of the Schottky barrier is used to change the release dynamics of photogenerated carriers, thereby realizing time-domain programmable adjustment of multiple different time factors without the need for a continuous external bias voltage.
[0040] Reference Figure 2 As shown, the bottom gate electrode 2 must completely contain the floating gate layer 4; the source and drain electrodes 7 need to partially overlap with the two-dimensional channel layer 6; the device channel region between the source and drain electrodes must be completely contained within the floating gate layer 4. The insulating substrate 1 is a rigid substrate such as a silicon wafer, on which a 100-nanometer or 300-nanometer thermally oxidized silicon dioxide layer is grown.
[0041] Reference Figure 2 As shown, the fabrication method of a second-order tunable transistor with time-domain programmability can modulate the lifetime of photogenerated carriers through appropriate storage stack structure design and ferroelectric-trapping coupling mechanism, thereby achieving adaptive time response; rapid thermal annealing crystallizes the ferroelectric layer, generating ferroelectric polarization; the method includes the following steps: Step S1: Clean the insulating substrate; Step S2: Form a gate bottom electrode pattern on the insulating substrate; Step S3: Deposit a ferroelectric barrier layer on the bottom gate electrode; Step S4: Perform rapid thermal annealing on the ferroelectric barrier layer to induce its crystallization and form a ferroelectric phase; Step S5: Form a floating gate layer on the barrier layer; Step S6: Deposit the tunneling layer; Step S7: Form the channel layer; Step S8: Form the source and drain electrodes; The polarization state of the ferroelectric barrier layer can be programmed and set by an external electrical pulse to regulate the floating gate interface barrier, thereby realizing the programmable adjustment of the device time factor. The ferroelectric barrier layer is deposited by an atomic layer deposition method. In practice, step 1: clean the silicon / silicon dioxide substrate with acetone; Step 2: Define the gate pattern and position of the flash memory device on a silicon / silicon dioxide substrate using photolithography, including but not limited to ultraviolet lithography, electron beam lithography, and laser direct writing. After growing the gate metal material, perform a lift-off process to obtain the patterned gate bottom electrode. Techniques for growing the metal material include but are not limited to electron beam evaporation, physical vapor deposition, and thermal evaporation. Step 3: A hafnium-zirconium oxide (hafnium to zirconium ratio of 1:1) thin film of approximately 10 nanometers was deposited using atomic layer deposition (ALD). The hafnium to zirconium ratio was controlled by alternating deposition of hafnium oxide and zirconium oxide for one cycle. Step 4: Perform rapid thermal annealing at 550 degrees Celsius under a nitrogen atmosphere (heat for 30 seconds, hold for 30 seconds, cool for 30 seconds) to induce crystallinity of the hafnium zirconium oxide film.
[0042] Step 5: Define the floating gate region using electron beam lithography, grow 5-nanometer-thick platinum metal using electron beam evaporation, and obtain a patterned metal floating gate layer using a lift-off process; Step 6: Use techniques such as atomic layer deposition to grow the tunneling layer dielectric of the device, which is hafnium oxide with a thickness of about 4 nanometers; Step 7: The two-dimensional channel material was transferred to the tunneling layer medium using a polystyrene (PS)-assisted transfer method. The PS protective layer was removed in a toluene solution, followed by annealing in a nitrogen atmosphere (200°C, 2 hours). Step 8: Define the trench region using techniques such as photolithography and etching; Step 9: Define the source and drain regions using electron beam lithography, grow the source and drain metals using electron beam evaporation, and obtain the patterned source and drain through a lift-off process.
[0043] This application discloses a novel neuromorphic transistor with multiple time factors, which can promote the development of high-performance motion-sensing neuromorphic device technology. To further illustrate that the transistor obtained by the above-described fabrication method possesses a ferroelectric-trapping coupling mechanism and multiple adjustable time factors, the electrical and optical characteristics of the transistor obtained according to this invention will be described in detail below. Figure 3The schematic diagram shows the electrical characteristic curves of the second-order tunable transistor with time-domain programmable characteristics provided by the present invention, as shown below. Figure 3 As shown, under small-amplitude positive electric pulse stimulation, the trapping effect dominates inside the device, and the channel conductance decreases with the increase of the number of pulses. This clarifies that the transistor obtained by the above preparation method has a trapping effect. When the amplitude of the applied electric pulse increases, the channel conductance first decreases and then increases with the increase of the number of pulses, proving that the device is transformed from being dominated by the trapping effect to being dominated by the ferroelectric effect. This clarifies that there is a ferroelectric-trapping coupling mechanism inside the device.
[0044] Figure 4 The schematic diagram shows the photoelectric characteristic curves of the second-order tunable transistor with time-domain programmable characteristics provided by the present invention, as shown below. Figure 4 As shown, compared to the initial state, the decay rate of the photogenerated current of the device slows down after positive electric pulse stimulation, the carrier lifetime increases, and the relaxation time is 6.88 seconds. The decay rate of the photogenerated current of the device accelerates after negative electric pulse stimulation, the carrier lifetime decreases, and the relaxation time is 7 milliseconds. This clarifies that the transistor obtained by the above preparation method can regulate the dynamic relaxation of photogenerated carriers without relying on external circuits or bias.
[0045] The beneficial technical effects of the technical solution of this application include: 1. The optoelectronic floating gate transistor uses ferroelectric materials as a barrier layer, which can realize intermediate polarization state, and the thin film preparation process is mature and compatible with existing semiconductor manufacturing processes; 2. By utilizing the ferroelectric polarization effect and the floating gate charge trapping mechanism, the lifetime of photogenerated carriers is dynamically adjusted from 7 milliseconds to 6.88 seconds, realizing a novel neuromorphic device with multiple different time factors, thereby adapting to more motion sensing scenarios; 3. Thanks to the polarization effect and the non-volatility of the floating gate charge, the carrier relaxation state can be adjusted without continuously applying an external bias voltage; This application breaks through the bottleneck of the single time factor of neuromorphic devices. By combining ferroelectric polarization with floating gate charge capture, the device can intrinsically regulate the relaxation dynamics of photogenerated carriers without relying on external circuits or bias. It solves the shortcomings of traditional motion sensing neuromorphic devices that are limited by narrow time response range and fixed duration, and provides a new path for the development of multi-speed motion situation perception.
[0046] The greatest advantage of this application is that it can intrinsically regulate the relaxation dynamics of photogenerated carriers without relying on external circuits or bias voltages. By combining ferroelectric polarization with a floating gate charge trapping mechanism, a wide and continuous adjustment of the photogenerated carrier lifetime is achieved, ranging from 7 milliseconds to 6.88 seconds.
[0047] The most crucial part of this application is the use of ferroelectric materials as the barrier layer for floating-gate transistors. Ferroelectric materials offer significant advantages because electrically programmable polarization states can induce non-volatile internal electric fields, thereby reshaping the local energy landscape. By applying electrical pulses to set the polarization state of the ferroelectric layer, the built-in electric field modulates the Schottky barrier at the floating-gate interface, thus controlling the dynamic process of photocarrier release. Alternative solutions to the technical solution of this application: In this patent, the channel material and the source / drain contact electrode metal can be replaced, and the specific replacement scheme is as follows: The insulating substrate 1 is typically a rigid substrate such as a silicon wafer, with a 100-nanometer or 300-nanometer thermally oxidized silicon dioxide layer grown on the surface of the silicon wafer.
[0048] The gate bottom electrode 2 is made of titanium and platinum, with thicknesses of 5 nanometers and 7 nanometers, respectively. The aforementioned barrier layer 3 is a ferroelectric material hafnium zirconium oxide with a thickness of 10 nanometers. The floating gate layer 4 is made of platinum and has a thickness of 5 nanometers. The tunneling layer 5 is hafnium oxide with a thickness of 4 nanometers; The channel layer 6 material can be replaced with indium gallium zinc oxide (IGZO). The source and drain materials 7 can be replaced with titanium and gold, with thicknesses of 5 nanometers and 40 nanometers, respectively. The specific steps for replacing the channel layer and contact electrode material in this application are as follows: Step 1: Clean the silicon / silicon dioxide substrate with acetone; Step 2: Define the gate pattern and position of the flash memory device on a silicon / silicon dioxide substrate using photolithography, including but not limited to ultraviolet lithography, electron beam lithography, and laser direct writing. After growing the gate metal material, perform a lift-off process to obtain the patterned gate bottom electrode. Techniques for growing the metal material include but are not limited to electron beam evaporation, physical vapor deposition, and thermal evaporation. Step 3: A hafnium-zirconium oxide (hafnium to zirconium ratio of 1:1) thin film of about 10 nanometers was deposited by atomic layer deposition. The ratio of hafnium to zirconium was controlled by alternating deposition of hafnium oxide and zirconium oxide for one cycle. Step 4: Perform RTP treatment at 550 degrees Celsius under a nitrogen atmosphere (heat for 30 seconds, hold for 30 seconds, cool for 30 seconds) to induce crystallinity in the HZO film.
[0049] Step 5: Define the floating gate region using electron beam lithography, grow a 5-nanometer-thick Pt metal using electron beam evaporation, and obtain a patterned metal floating gate layer using a lift-off process; Step 6: Use techniques such as atomic layer deposition to grow the tunneling layer dielectric of the device, which is HfO2 with a thickness of about 4 nanometers; Step 7: Using an IGZO ceramic target with an atomic ratio of In:Ga:Zn:O = 1:1:1:4, an indium gallium zinc oxide thin film was deposited by radio frequency sputtering. During the sputtering process, the working pressure and the flow rates of argon and oxygen were fixed at 0.88 Pa and 48 and 2 sccm, respectively. Step 8: Define the trench region using techniques such as photolithography and wet etching; Step 9: Define the source and drain regions using electron beam lithography, grow the source and drain metals using electron beam evaporation, and obtain the patterned source and drain through a lift-off process.
[0050] The implementation principle of the second-order tunable transistor with time-domain programmable characteristics and its fabrication method in this application is as follows: This application introduces a ferroelectric material with electrically programmable polarization state as a barrier layer in the floating gate transistor structure, so that the ferroelectric polarization effect and the floating gate charge trapping mechanism form a synergistic coupling control relationship. After rapid thermal annealing, the ferroelectric hafnium zirconium oxide material forms a stable ferroelectric phase structure, which can generate polarization states with different directions and intensities under the action of external electric pulses, thereby forming a non-volatile polarization built-in electric field inside the barrier layer. The built-in electric field can change the band structure at the interface between the floating gate layer and the tunneling layer, and modulate the Schottky barrier height at the floating gate interface so that the charge trapping and release behavior in the floating gate layer can be controlled to change. Under illumination, the two-dimensional semiconductor material in the channel layer generates photogenerated carriers. These carriers migrate under the influence of the internal electric field of the device and are jointly regulated by the charge trapping effect of the floating gate layer and the ferroelectric polarization field. When the ferroelectric polarization direction and the floating gate trapping charge form a synergistic effect, the floating gate interface barrier increases, the release process of photogenerated carriers is suppressed, and the relaxation time of the carriers is prolonged. When the polarization direction changes, the interface barrier decreases, the photogenerated carriers are released more easily, and the relaxation time of the device is significantly shortened. By adjusting the amplitude and polarity of the externally applied electric pulse, the polarization state of the ferroelectric layer can be programmed, thereby realizing the regulation of the floating gate interface barrier and the carrier release dynamics. Because both ferroelectric materials and floating gate charges are non-volatile, the set polarization state and charge distribution remain stable after power is turned off. This allows the device to maintain a predetermined time response state without continuously applying an external bias voltage. Through this dual-physical control method that combines the ferroelectric polarization effect with the floating gate charge trapping mechanism, the device can form multiple stable time factors in a single structure. This enables the relaxation time of photogenerated carriers to be continuously adjustable in the range of milliseconds to seconds. The device can achieve adaptive time response adjustment according to the sensing requirements of different motion speeds or different dynamic scenes. This provides a new hardware implementation scheme for high-performance neuromorphic visual perception and motion perception systems that can achieve multi-timescale processing capabilities without complex external circuits.
[0051] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.
Claims
1. A second-order tunable transistor with time-domain programmable characteristics, characterized in that, Including an insulating substrate (1); Includes a gate bottom electrode (2) located on the surface of an insulating substrate (1); Includes a barrier layer (3) that covers the gate bottom electrode (2) and a portion of the insulating substrate (1). Includes a floating grid layer (4), which is disposed on the barrier layer (3); It includes a tunneling layer (5) that covers the floating grid layer (4) and the barrier layer (3); and a channel layer (6) disposed on the tunneling layer (5). It includes a source and a drain (7), which are disposed on the channel layer (6); The barrier layer (3) is a ferroelectric material layer with an electrically programmable polarization state; The polarization state of the ferroelectric material layer and the charge trapping behavior of the floating gate layer (4) form a coupling mechanism to regulate the height of the Schottky barrier at the floating gate interface; The modulation of the Schottky barrier is used to change the release dynamics of photogenerated carriers, thereby enabling time-domain programmable adjustment of multiple different time factors without the need for a continuous external bias voltage.
2. The second-order tunable transistor according to claim 1, characterized in that: The gate bottom electrode (2) completely covers the area where the floating gate layer (4) is located in the top view direction; The source and drain (7) partially overlap with the channel layer (6), and the channel region formed between the source and drain is completely within the projection range of the floating gate layer (4).
3. The second-order tunable transistor according to claim 1, characterized in that: The barrier layer (3) is a ferroelectric hafnium zirconium oxide material layer; The atomic ratio of hafnium to zirconium in the ferroelectric hafnium-zirconium oxide is 1:
1.
4. The second-order tunable transistor according to claim 1, characterized in that: The floating gate layer (4) is a platinum metal layer; The tunneling layer (5) is a hafnium oxide layer; The channel layer (6) is a two-dimensional semiconductor material layer; the channel layer (6) is an indium gallium zinc oxide semiconductor layer.
5. The second-order tunable transistor according to claim 4, characterized in that: The two-dimensional semiconductor material is molybdenum sulfide.
6. The second-order tunable transistor according to claim 1, characterized in that: The ferroelectric material layer is rapidly thermally annealed and crystallized to form a ferroelectric phase structure, which is used to generate a non-volatile polarization built-in electric field. By applying electrical pulses of different amplitudes to set the polarization state of the ferroelectric material layer, the relaxation time of photogenerated carriers can be adjusted in the range of milliseconds to seconds.
7. A method for fabricating a second-order tunable transistor with time-domain programmable characteristics as described in any one of claims 1-6, characterized in that, Includes the following steps: Step S1: Clean the insulating substrate; Step S2: Form a gate bottom electrode pattern on the insulating substrate; Step S3: Deposit a ferroelectric barrier layer on the bottom gate electrode; Step S4: Perform rapid thermal annealing on the ferroelectric barrier layer to induce its crystallization and form a ferroelectric phase; Step S5: Form a floating gate layer on the barrier layer; Step S6: Deposit the tunneling layer; Step S7: Form the channel layer; Step S8: Form the source and drain electrodes; The polarization state of the ferroelectric barrier layer can be programmed and set by an external electrical pulse to regulate the potential barrier at the floating gate interface, thereby enabling programmable adjustment of the device's time factor.
8. The preparation method according to claim 7, characterized in that: The ferroelectric barrier layer is deposited using an atomic layer deposition method; The rapid thermal annealing was carried out in a nitrogen atmosphere at a temperature range of 450℃-650℃. The channel layer is formed by transferring two-dimensional semiconductor material using a polystyrene-assisted transfer method; The channel layer is formed by depositing an indium gallium zinc oxide thin film using a radio frequency sputtering method; The source and drain electrodes are patterned by electron beam lithography and formed by electron beam evaporation to deposit metallic materials.
9. The second-order tunable transistor according to claim 1, characterized in that: The ferroelectric polarization effect and the floating gate charge trapping mechanism constitute a dual physical coupling control mechanism, enabling the device to have multiple stable time factors in a single structure.
10. The second-order tunable transistor according to claim 1, characterized in that: The multiple time factors correspond to the relaxation time of photogenerated carriers under different polarization states, which are used to adapt to sensing tasks with different motion speeds.