Data storage device and method for non-uniform mapping of variable read resolution

Abstract

The present disclosure relates to data storage devices and methods for non-balanced mapping for variable read resolution. Data is typically stored using a mapping in a multi-level memory (e.g., quad-level cell (QLC)) that balances the error rates between various pages in the memory. The number of sensing operations required to read each page is also relatively balanced. If a low resolution version of the data is desired to be read later, a data storage device presented herein can decide to store that data using a non-balanced mapping. With the non-balanced mapping, fewer sensing operations are required to read a lower page of data that contains the low resolution version of the data. If a higher resolution version of the data is desired, other pages can be read and techniques can be used to mitigate the higher error rates that can be encountered in those other pages due to the use of the non-balanced mapping.

Description

Background Technology

[0001] Data storage devices can contain memory cells that store more than one data bit per cell. For example, a Quadruple Level Cell (QLC) can store four bits of data. The four data bits in a QLC cell belong to four pages (bottom page, middle page, top page, and top page), and mapping can be used to store data across various logical pages. For example, using a 4-4-3-4 mapping, data can be written into the QLC cell such that the bottom, middle, and top pages can be read by sensing the cell voltage in four steps, while the top page can be read by sensing the cell voltage in three steps. Using this mapping, transitions between multiple adjacent states are divided approximately equally between logical pages. Because the bits representing adjacent states differ from each other by only one bit, this mapping can be used to balance the bit error rate (BER) between pages. Attached Figure Description

[0002] Figure 1A This is a block diagram of the data storage device in the implementation scheme.

[0003] Figure 1B This is a block diagram illustrating the storage module of an example implementation.

[0004] Figure 1C This is a block diagram illustrating a hierarchical storage system for an example implementation.

[0005] Figure 2A This is an example based on the implementation plan. Figure 1A The block diagram of the controller components of the data storage device is shown in the figure.

[0006] Figure 2B This is an example based on the implementation plan. Figure 1A The block diagram of the components of the data storage device is shown in the figure.

[0007] Figure 3 This is a block diagram of the host and data storage devices in the implementation scheme.

[0008] Figure 4 This is an example of the 4-3-4-4 bit error rate (BER) balancing mapping in the implementation scheme.

[0009] Figure 5 This is an example of the 1-2-4-8 unbalanced mapping of the implementation scheme.

[0010] Figure 6 This is a flowchart of a method for implementing a method for writing data received from a host.

[0011] Figure 7 This is a flowchart of a method for remapping previously written data. Detailed Implementation

[0012] The following embodiments generally relate to a data storage device and method for an unbalanced mapping with variable read resolution. In one embodiment, a data storage device is provided, comprising: a memory including multiple levels of memory cells; and one or more processors. The one or more processors are individually or in combination configured to: determine whether a low-resolution version of the data needs to be provided; in response to determining that a low-resolution version of the data does not need to be provided, store the data in the memory using a first mapping; and in response to determining that a low-resolution version of the data needs to be provided, store the data in the memory using a second mapping, wherein only the lower pages of the data are read to provide the low-resolution version of the data, and wherein fewer memory sensing operations are required to read the lower pages when storing the data using the second mapping compared to when storing the data using the first mapping.

[0013] In another embodiment, a method is provided to be performed in a data storage device comprising multiple levels of memory cells. The method includes: determining whether data is designated for reading at a dynamic read resolution; and in response to determining that the data is designated for reading at a dynamic read resolution, storing the data in the memory using a non-BER (bit error rate) balanced mapping, wherein when the data is stored using the non-BER balanced mapping instead of a BER balanced mapping, fewer memory sensing operations are required to read the lower pages of the data.

[0014] In yet another embodiment, a data storage device is provided, comprising: a memory including multiple levels of memory cells; and means for: selecting a mapping from a plurality of mappings based on whether the data is specified for a variable read resolution; and writing the data to the memory using the selected mapping.

[0015] Other embodiments are possible, and each embodiment can be used alone or in combination. Therefore, various embodiments will now be described with reference to the accompanying drawings.

[0016] Implementation Plan

[0017] The implementation schemes described below relate to data storage devices (DSDs). As used herein, a "data storage device" refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid-state drives (SSDs), tape drives, hybrid drives, etc. Detailed information about example DSDs is provided below.

[0018] Figures 1A to 1C Examples of data storage devices suitable for implementing these embodiments are shown below. It should be noted that these are merely examples and other specific implementations may be used. Figure 1A This is a block diagram illustrating a data storage device 100 according to an implementation scheme. (See reference) Figure 1A In this example, the data storage device 100 includes a controller 102 coupled to non-volatile memory, which may consist of one or more non-volatile memory dies 104. As used herein, the term "die" refers to a non-volatile memory cell formed on a single semiconductor substrate and the associated circuitry for managing the physical operation of those non-volatile memory cells. The controller 102 interfaces with a host system and sends a sequence of commands for read, program, and erase operations to the non-volatile memory die 104. Furthermore, as used herein, the phrase "communicating with" or "coupled with" can mean directly communicating / coupling with or indirectly communicating / coupling with through one or more components, which may or may not be shown or described herein. The communication / coupling can be wired or wireless.

[0019] Controller 102 (which may be a non-volatile memory controller (e.g., flash memory, resistive random access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random access memory (MRAM) controller) may include one or more components configured individually or in combination to perform certain functions, including but not limited to those described herein and illustrated in the flowcharts. For example, such as Figure 2A As shown, controller 102 may include one or more processors 138, which are individually or in combination configured to perform these functions, such as, but not limited to, those described herein and illustrated in the flowcharts, by executing computer-readable program code stored within and / or outside controller 102 (e.g., stored in random access memory (RAM) 116 or read-only memory (ROM) 118). Alternatively, the one or more components may include circuitry, such as, but not limited to, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0020] In one example implementation, a nonvolatile memory controller 102 is a device that manages data stored on nonvolatile memory and communicates with a host (such as a computer or electronic device) having any suitable operating system. The nonvolatile memory controller 102 may have various functionalities beyond those specifically described herein. For example, the nonvolatile memory controller may format the nonvolatile memory to ensure proper operation, map out faulty nonvolatile memory cells, and allocate spare cells to replace future failed cells. A portion of the spare cells may be used to maintain firmware (and / or other metadata for housekeeping and tracking) to operate the nonvolatile memory controller and implement other features. In operation, the host may communicate with the nonvolatile memory controller when it needs to read data from or write data to the nonvolatile memory. If the host provides a logical address where data will be read / written, the nonvolatile memory controller may translate the logical address received from the host into a physical address in the nonvolatile memory. The non-volatile memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wear on specific blocks of memory that would otherwise be repeatedly written) and garbage collection (moving only valid data pages to a new block after a block is full, so that the full block can be erased and reused).

[0021] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state (e.g., flash memory) memory cells and may be programmable once, less-programmable, or more-programmable. The memory cells may also be single-level cells (SLC), multi-level cells (MLC) (e.g., two-level cells, three-level cells (TLC), four-level cells (QLC), etc.) or may use other memory cell-level technologies now known or developed hereafter. Furthermore, the memory cells may be fabricated in two or three dimensions.

[0022] The interface between controller 102 and non-volatile memory die 104 can be any suitable flash memory interface, such as switching modes 200, 400, or 800. In one embodiment, data storage device 100 can be a card-based system, such as a Secure Digital (SD) card or a micro-Secure Digital (micro-SD) card. In another embodiment, data storage device 100 can be part of an embedded data storage device.

[0023] Despite Figure 1AIn the illustrated example, data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between controller 102 and non-volatile memory die 104; however, the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as...) Figure 1B and Figure 1C In the architecture shown, depending on the controller's capabilities, there may be two, four, eight, or more memory channels between the controller and the memory device. In any of the embodiments described herein, even if a single channel is shown in the figures, there may be more than one single channel between the controller and the memory die.

[0024] Figure 1B An example is illustrated of a storage module 200 comprising multiple non-volatile data storage devices 100. Thus, the storage module 200 may include a storage controller 202 that interfaces with a host and with data storage devices 204, which include multiple data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA), a Peripheral Component Rapid Interconnect (PCIe) interface, a Double Data Rate (DDR) interface, or a Serial Connected Small Scale Compute Interface (SAS / SCSI). In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), as found in server PCs or portable computing devices such as laptops and tablets.

[0025] Figure 1C This is a block diagram illustrating a tiered storage system. The tiered storage system 250 includes a plurality of storage controllers 202, each of which controls a corresponding data storage device 204. A host system 252 can access the memory within the storage system 250 via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Fast (NVMe) interface or an Ethernet Fibre Channel (FCoE) interface. In one embodiment, Figure 1C The illustrated system may be a rack-mounted mass storage system that can be accessed by multiple host computers, such as those found in data centers or other locations where mass storage is required.

[0026] Refer again Figure 2AThe controller 102 in this example also includes a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules, such as, but not limited to, a buffer manager / bus controller module that manages buffers in RAM 116 and controls the internal bus arbitration of controller 102. Modules may include one or more processors or components, as discussed above. ROM 118 may store system boot code. Although in Figure 2A The RAM 116 is illustrated as being located separately from the controller 102, but in other embodiments, one or both of the RAM 116 and ROM 118 may be located within the controller 102. In yet another embodiment, portions of the RAM 116 and ROM 118 may be located both within and outside the controller 102.

[0027] Front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide electrical interfacing with a host or next-level storage controller. The type of host interface 120 may be chosen depending on the type of memory used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, Serial ATA Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. Host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0028] Backend module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and corrects errors in data bytes read from the non-volatile memory. Command sequencer 126 generates command sequences (such as programming and erasing command sequences) to be sent to the non-volatile memory die 104. RAID (Redundant Array of Independent Disks) module 128 manages the generation of RAID parity and the recovery of faulty data. RAID parity can be used as an additional level of integrity protection for data being written to memory device 104. In some cases, RAID module 128 may be part of ECC engine 124. Memory interface 130 provides command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, memory interface 130 may be a double data rate (DDR) interface, such as a switching mode 200, 400, or 800 interface. The controller 102 in this example also includes a media management layer 137 and a flash control layer 132, which controls the overall operation of the back-end module 110.

[0029] The data storage device 100 also includes other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interface with the controller 102. In an alternative embodiment, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components that are not necessary in the controller 102.

[0030] Figure 2B This is a block diagram illustrating the components of a non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells for storing data. The non-volatile memory cells can be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 also includes a data cache 156 and address decoders 148, 150 for caching data. In this example, the peripheral circuitry 141 includes a state machine 152 that provides status information to the controller 102. The peripheral circuitry 141 may also include one or more components that are individually or in combination configured to perform certain functions, including but not limited to those described herein and illustrated in the flowchart. For example, as... Figure 2B As shown, the memory die 104 may include one or more processors 168, which are individually or in combination configured to execute computer-readable program code stored in one or more non-transitory memories 169, in the memory array 142, or external to the memory die 104. Alternatively, the one or more components may include circuitry, such as, but not limited to, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0031] As a complement or alternative to one or more processors 138 (or more generally, components) in controller 102 and one or more processors 168 (or more generally, components) in memory die 104, data storage device 100 may include another set of one or more processors (or more generally, components). Generally, regardless of the location and number of the one or more processors (or more generally, components) in data storage device 100, these processors may be configured individually or in combination to perform various functions, including but not limited to those described herein and illustrated in the flowcharts. For example, the one or more processors (or components) may be located in controller 102, memory device 104, and / or other locations within data storage device 100. Furthermore, different processors (or components) or combinations of processors (or components) may be used to perform different functions. Additionally, means for performing functions may be implemented using a controller that includes one or more components (e.g., processors or other components described above).

[0032] Return again Figure 2A The flash control layer 132 (which will be referred to herein as the flash translation layer (FTL)) handles flash errors and interfaces with the host. Specifically, the FTL (which may be an algorithm in the firmware) is responsible for the internal operations of memory management and translates writes from the host into writes destined for memory 104. An FTL may be necessary because memory 104 may have limited endurance, may only be written in multi-page format, and / or may not be written to at all (unless it is erased as a block). The FTL understands these potential limitations of memory 104, which may be invisible to the host. Therefore, the FTL attempts to translate writes from the host into writes destined for memory 104.

[0033] The FTL may include a logical-to-physical address (L2P) mapping (sometimes referred to herein as a table structure or data structure) and allocated cache memory. In this way, the FTL translates logical block addresses (“LBA”) from the host into physical addresses in memory 104. The FTL may include other features such as, but not limited to, power-off recovery (enabling the recovery of the FTL’s data structure in the event of a sudden power outage) and wear leveling (ensuring uniform wear across memory blocks to prevent some blocks from becoming excessively worn, which would lead to a greater likelihood of failure).

[0034] Turn to the attached image again. Figure 3This is a block diagram of a host 300 and a data storage device 100 according to an embodiment. The host 300 may take any suitable form, including but not limited to a computer, mobile phone, tablet, wearable device, digital video recorder, surveillance system, etc. The host 300 (hereinafter referred to as a computing device) in this embodiment includes one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in one or more memories 340 configures one or more processors 330 to perform actions described herein as being performed by the host 300. Therefore, actions performed by the host 300 are sometimes referred to herein as being performed by an application (computer-readable program code) running on the host 300. For example, the host 300 may be configured to transfer data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the memory 104 of the data storage device.

[0035] In one embodiment, the memory 104 of the data storage device 100 may include a matrix of storage (memory) cells. Based on the storage technology, each of these cells may be a single-level cell (SLC), which stores a single bit per cell; or a multi-level cell (MLC), which stores more than one bit per cell. When an MLC memory stores three or four bits per cell, the memory may be referred to as a three-level cell (TLC) memory or a four-level cell (QLC) memory, respectively. The following examples will be described with reference to QLC memory; however, it should be understood that any suitable memory technology available now or developed in the future may be used. For example, other bit technologies (e.g., TLC) may be used.

[0036] There are multiple ways to store and retrieve data in a QLC cell, which can be organized by page and block. In this example, write and read operations are performed at the page level, and the page is 16KB. The four bits in the QLC cell belong to four pages: the bottom page, the middle page, the top page, and the top page. For four 16KB pages, each page can hold 4,096 data samples, where each sample (e.g., a single element of a 32-bit vector) is 32 bits (i.e., each sample is stored in 32 cells, and each bit is stored in a separate cell). When a write operation is performed in the QLC cell, all four pages are available. The four-bit content of the QLC cell can be represented as a voltage value in the charge gate of the QLC cell. This voltage representation of the bit value allows for an arrangement in which the individual bits of the stored quantity can be detected in a minimal number of voltage sensing operation steps.

[0037] Logical bit mapping (decoding schemes) can be used to store data across various logical pages in a multi-bit memory cell. For example, bit error rate (BER) balancing mapping can be used to balance both the reliability of logical pages (i.e., the vulnerability of different logical pages to bit flipping errors) and the latency of reading from different logical pages. For example, the 4-4-3-4 decoding mechanism is a standard bit mapping used for QLC cells (e.g., in a BiCS5 memory array). In the 4-4-3-4 decoding mechanism (see...), Figure 4 In this architecture, data is written to QLC cells in such a way that the bottom, middle, and top pages can be read by sensing the cell voltage in four steps, while the top page can be read by sensing the cell voltage in three steps. This standard mapping can be a Gray mapping, in which bits representing adjacent states differ from each other by only one bit. This characteristic of the Gray mapping also improves memory reliability because transitions between multiple adjacent states are divided approximately equally between logical pages. Although this mapping is sometimes called a balanced mapping, it should be noted that this "balanced" mapping is not actually balanced, as the middle page has three transitions while other pages have four. Furthermore, although a 4-3-4-4 mapping is used in this example, this problem can also occur in other fairly balanced mappings. U.S. Provisional Patent Application No. 19 / 035,315 (Attorney's File No. 10519 / 4282 (WDA-8004-US)), filed January 23, 2025, entitled "Data Storage Device and Method for Bit Error Rate (BER) Balancing Based on Dynamic Sense Time," describes a method for mitigating the inherent BER differences between logical pages in a "balanced" mapping. While the standard 4-3-4-4 mapping has advantages in terms of reliability, the inventors have recognized that using non-standard mappings (e.g., 1-2-4-8) can be advantageous in certain situations. More specifically, while using non-standard mappings may result in less reliable stored data compared to using standard mappings, the use of non-standard mappings can provide significantly reduced latency and power consumption, which may be desirable in several applications. In one implementation, the data storage device 100 is configured to select which mapping (e.g., a standard 4-3-4-4 mapping or a non-standard 1-2-4-8 mapping) to use to write data to memory 104 when data is received from host 300 or when previously stored data is rewritten to memory 104 using a different mapping. This provides the data storage device 100 with variable read resolution capability.

[0038] There are several use cases where the data storage device 100, capable of multi-resolution reads from memory 104, can benefit from its flexibility. For example, using different resolutions / quantizations can be useful for machine learning models (e.g., using dynamic / lower resolution to represent model parameters with different bit depths). Another example use case is reading images from memory 104 at a lower resolution for initial visualization purposes (e.g., image downsampling, such as when a small-sized image (“thumbnail”) is used to represent a full-size image stored in memory 104).

[0039] There can be challenges in allowing for faster reading of lower-resolution data from memory. For example, in a machine learning / artificial intelligence context, if 1 / 2 / 4 / 8 / 32 / 64 bits are used for each model parameter value, more bits are needed to represent each model parameter. While the computation may be more accurate, it can be memory-intensive and computationally more expensive. Similarly, in an image / video data context, 1 to 32 bits can be used to represent each image pixel. Below is a list of some common color depths and their corresponding bits per pixel:

[0040] 1st position: Black and white (two colors)

[0041] 8-bit: 256 colors (grayscale)

[0042] 16-bit: 65,536 colors (high color gamut)

[0043] 24-bit: 16,700,000 colors (true color)

[0044] 32-bit: 4,300,000,000 colors (with an alpha channel for transparency)

[0045] In one implementation, an improved method is provided that uses a non-standard mapping (e.g., an unbalanced Gray mapping of 1-2-4-8) to store data, resulting in significantly lower latency (e.g., about 3 times) and lower power consumption when reading low-resolution versions of data compared to reading data stored using a standard mapping (e.g., a 4-2-4-4 mapping). It should be noted that while the following examples are described in relation to standard mapping versus non-standard mapping or 4-2-4-4 mapping versus 1-2-4-8 mapping, any suitable mapping can be used. Therefore, the phrases "first mapping" and "second mapping" may be used herein, and any particular type of mapping (e.g., 4-2-4-4 or 1-2-4-8) should not be construed as a claim unless expressly stated in the claims. Furthermore, while the following examples are described in relation to QLC memory, these implementations can be used with any suitable type of memory.

[0046] In one example implementation, data storage device 100 may use a non-standard, unbalanced Gray mapping to allow for faster and lower-power reads of frequently used low-resolution data. By providing several resolution / quantization “levels” / options for reading data from memory 104, these implementations offer flexible trade-offs in manipulating read latency / power with the resolution of the read data. In one example implementation, using a special bit mapping that allows for efficient manipulation between read latency / power and the resolution / quantization of the read content can provide ultra-fast reads (up to 15 times faster) of low-resolution data.

[0047] In one implementation, data storage device 100 may use a non-BER balanced mapping for scenarios involving dynamic read resolution. In one example implementation, a 1-2-4-8 non-balanced bit mapping is used to support partitioning that allows for flexible trade-offs between read latency / power and read resolution. In some scenarios, non-balanced mapping may not be desirable due to unequal latency of logical pages. However, in these cases, non-balanced mapping can be used to provide an efficient solution for faster reading of low-resolution content. As described below, several measures can be used to mitigate the unbalanced BER caused by using such unconventional mapping.

[0048] Turning back to the attached image, Figure 5 This is an example of a 1-2-4-8 unbalanced mapping implementation. With this mapping, the lower page has only one transition between adjacent states, the middle page has two transitions, the upper page has four transitions, and the top page has eight transitions. This 1-2-4-8 mapping includes one sensing operation associated with the lower page, two sensing operations for the middle page, four sensing operations for the upper page, and eight sensing operations for the top page. Such a mapping can lead to unequal properties in logical pages. Because a logical page can have a high number of transitions between zero and one, it can be more vulnerable to bit errors and have higher read latency (due to the higher number of associated sensing operations required to read its data).

[0049] For standard applications, a preferred configuration is used to balance latency and reliability across different logical pages, and therefore, a bitmap with balanced BER may be desirable. However, for use cases where faster reads at lower resolution are desired, an unbalanced bitmap (e.g., a 1-2-4-8 map) may be useful.

[0050] In one example, controller 102 places the most significant bit of each model parameter or pixel of the image in the lower page. This type of data placement allows for modular resolution readings, which optimize latency and power consumption for frequently used scenarios. For example, assuming a high-resolution representation of the parameters of a deep neural network model comprises 32 bits, these bits can be stored using a full-resolution model where each parameter is placed in four bits across eight units. In total, this provides 32 bits per parameter. To apply fast, low-resolution readings of the model, controller 102 can cause memory 104 to apply only a single sensing operation to read only the lower page. For this type of read, the parameter has eight bits. In cases where a slightly higher resolution read is desired, controller 102 can cause three sensing operations to be applied to read the lower and middle pages to obtain a 16-bit value for the same parameter. Data storage device 100 can be read in a similar manner at 24-bit or 32-bit resolution.

[0051] Reading the lower page involves only one sensing operation, while reading from full resolution from a QLC device involves applying 15 sensing operations. Therefore, the low-resolution fast read (of the lower page only) significantly accelerates the read operation and reduces its power consumption. Assuming that low-resolution information is likely sufficient most of the time and high-resolution information is rarely needed, these implementations can significantly improve the overall performance of the data storage device 100 and reduce its power consumption.

[0052] While the varying read latencies of different logical pages in an unbalanced Gray map are useful in many use cases, various approaches can be taken to address the potential BER increase encountered when using an unbalanced 1-2-4-8 map. One approach is to apply the same amount of error-correcting code (ECC) parity protection to all logical pages, which will typically have a higher BER value based on the decoding capability claimed by the higher page limit. Another approach is to apply the same amount of ECC parity protection to all logical pages. This way, in cases where decoding fails at a higher logical page (e.g., due to increased vulnerability to bit flips), decoding can return the read data as is. Assuming such reads occur frequently enough, this approach may be acceptable for relevant use cases such as applications for thumbnail previews and even applications using low-resolution machine learning models for inference (especially if users are frequently aware of the predictive performance degradation of low-resolution models).

[0053] Another approach uses a different parity allocation per logical page to balance ECC protection across pages. This solution can be more complex than the methods discussed above because it needs to support different codeword sizes. Yet another approach uses non-uniform voltage distribution of states, making the states near the active read threshold of the top page more independent than the "active states" of lower pages, and so on. The active states of logical pages with a large number of transitions (and more active states) between internal logical states can be placed in a larger voltage window space, while the active states of lower pages can be placed closer together, for example, to make the overall BER level of these pages more balanced.

[0054] In another approach, adapted sensing accuracy is applied to a specific page BER level. For example, readings of lower pages with lower BER levels can use more relaxed sensing timing (making it even faster based on sensing with a single threshold), while readings of top pages with eight read thresholds and therefore higher sensing BER can be accomplished using longer sensing timing, resulting in more accurate sensing that reduces and balances BER. The sensing timing can be controlled by longer / shorter settling times for the bit line voltage (VBL) and control gate voltage (Vcg), and by longer / shorter integration times for the sense amplifier, which allows control over the BER of the sensed page. In this way, the BER of different pages can be balanced to some extent.

[0055] In one embodiment, the controller 102 of the data storage device 100 may determine which of the first and second mappings (e.g., a standard 4-3-4-4 mapping or a non-standard 1-2-4-8 mapping) to use when storing data received from the host 300. Figure 6 The flowchart in Figure 600 illustrates this implementation scheme. Figure 6 As shown, when data for storage in memory 104 of data storage device 100 is received from host 300, controller 102 of data storage device 100 determines whether to read the data at dynamic read resolution (610). This determination can be made in any suitable manner. For example, host 300 can explicitly (e.g., using flags, vendor-specific codes, etc.) Explicit instructions from host 300 regarding the required mapping type (i.e., whether...) (Data should be read faster at a lower resolution) Instructions are provided to the data storage device 100 either explicitly (e.g., by requesting that data be stored in a logical partition designated for low-resolution reading, or by identifying an application that is sending data on host 300) or implicitly (e.g., by requesting that data be stored in a logical partition designated for low-resolution reading, or by identifying an application that is sending data on host 300).

[0056] If controller 102 determines that it does not intend to read data at dynamic read resolution, controller 102 communicates with memory 104 and enables data to be written in a standard mapping (e.g., 4-3-4-4 mapping) (620). However, if controller 102 determines that it intends to read data at dynamic read resolution, controller 102 communicates with memory 104 and enables data to be written in a non-standard mapping (e.g., 1-2-4-8 mapping) (630).

[0057] Additionally or alternatively, the controller 102 of the data storage device 100 can remap previously written data. This implementation... Figure 7 The flowchart 700 illustrates this. Figure 7 As shown, after data has been programmed into memory 104 (710) using a standard mapping (e.g., a 4-3-4-4 mapping) and an ongoing operation (720) exists, controller 102 determines whether dynamic read resolution support is required (730). Controller 102 can make this determination in any suitable manner. For example, controller 102 can, based on... Internal observations regarding shared use or in response to explicit instructions from host 300. This determination is made. If controller 102 determines that there is no such need, the method loops back to 720, and no data remapping occurs. However, if controller 102 determines that dynamic read resolution needs to be supported, controller 102 generates another copy of the data (740) and stores this copy in another location in memory 104 (750) using a non-standard mapping (e.g., a 1-2-4-8 mapping). The original copy of the data may be retained or discarded.

[0058] Several advantages exist associated with these implementations. For example, these implementations provide an efficient way to store data within the memory of a data storage device, allowing data to be read at several granularities / resolutions / quantization levels and at several speeds. In one example implementation, the data storage device can provide up to 16 times faster read rates for lower-resolution versions of the stored data compared to conventional QLC memory. Moreover, dynamic / lower resolution using machine learning model weights offers advantages over other possible solutions to the problems mentioned above. One such possible solution is to store several copies of the model parameters in memory, each copy contained at a different resolution. This solution reduces the overall throughput of loading model parameters at the cost of (i.e., the storage capacity required to maintain the model). However, dynamic / lower resolution using machine learning model weights provides latency reductions that this solution cannot offer.

[0059] Another possible solution to the aforementioned problem is to arrange the data across different logical pages and allow only partial reading of those pages. Therefore, if low-resolution reading is required, only a single logical page can be sensed and transferred, containing low-resolution data (e.g., the most significant bits of weights in a machine learning model or low-resolution pixel data of an image). This is described in more detail in U.S. Patent Application 18 / 945,932, which is incorporated herein by reference. However, in some contexts, the above-described embodiments may offer advantages over the methods described in that patent document.

[0060] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) devices or static random access memory (“SRAM”) devices; non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which is considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0061] Memory devices can be formed from passive and / or active components in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements such as antifuses, phase-change materials, and optionally manipulation elements such as diodes. As yet another non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0062] Multiple memory elements can be configured such that they are connected in series or that each element is individually accessible. As a non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically comprises memory elements connected in series. A NAND memory array can be configured such that the array consists of multiple memory strings, where a string consists of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured such that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0063] Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional memory structures or three-dimensional memory structures.

[0064] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single planar level or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane that extends substantially parallel to the main surface of the substrate supporting the memory element (e.g., in the xz plane). The substrate may be a wafer on which the memory element layer is formed, or the substrate may be a carrier substrate attached to the memory element after the memory element is formed. As a non-limiting example, the substrate may include a semiconductor (such as silicon).

[0065] Memory elements can be arranged in an ordered array (such as by multiple rows and / or columns) within a single memory device level. However, memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0066] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., along the x, y and z directions, where the y direction is generally perpendicular to the main surface of the substrate, and the x and z directions are generally parallel to the main surface of the substrate).

[0067] As a non-limiting example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate (i.e., along the y-direction), each column containing multiple memory elements. The columns can be arranged in a two-dimensional configuration (e.g., in the xz plane) to produce a three-dimensional arrangement of memory elements having multiple vertically stacked elements on memory planes. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0068] As a non-limiting example, in a three-dimensional NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0069] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers that are at least partially located within the single substrate. As a non-limiting example, the substrate may include a semiconductor (such as silicon). In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the lower memory device class of the array. However, the layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or there may be intermediate layers between memory device classes.

[0070] Furthermore, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on individual substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on individual substrates, the resulting memory array is not a monolithic three-dimensional memory array. Alternatively, multiple (monolithic or non-monolithic) two-dimensional or three-dimensional memory arrays can be formed on individual chips and then packaged together to form a stacked chip memory device.

[0071] The operation and communication with memory elements typically require associated circuitry. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0072] Those skilled in the art will recognize that the present invention is not limited to the described two-dimensional and three-dimensional structures, but covers all relevant memory structures as described herein and as understood by those skilled in the art within the spirit and scope of the invention.

[0073] The above detailed description is intended to be understood as an illustration of selected forms of the invention, and not a definition of the invention. Only the following claims (including all equivalents) are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of any embodiment described herein may be used alone or in combination with each other.

Claims

1. A data storage device, the data storage device comprising: The memory includes multiple levels of memory units; and One or more processors, wherein the one or more processors are configured individually or in combination to: Determine whether a lower-resolution version of the data is required; In response to determining that a low-resolution version of the data is not required, the data is stored in the memory using a first mapping; as well as In response to determining that a low-resolution version of the data needs to be provided, the data is stored in the memory using a second mapping, wherein only the lower pages of the data are read to provide the low-resolution version of the data, and wherein fewer memory sensing operations are required to read the lower pages when the data is stored using the second mapping compared to when the data is stored using the first mapping.

2. The data storage device according to claim 1, wherein the first mapping includes a 4-4-3-4 mapping, and the second mapping includes a 1-2-4-8 mapping.

3. The data storage device of claim 1, wherein the first mapping includes a bit error rate (BER) balanced mapping, and the second mapping includes a non-BER balanced mapping.

4. The data storage device of claim 1, wherein the determination is performed in response to receiving data from the host.

5. The data storage device of claim 1, wherein the determination is performed in response to remapping the data previously stored in the memory using a different mapping.

6. The data storage device according to claim 1, wherein the most significant bit of the data is stored in the lower page.

7. The data storage device of claim 1, wherein the low-resolution version of the data includes parameters of a low-resolution version of a machine learning model.

8. The data storage device of claim 1, wherein the low-resolution version of the data includes a low-resolution version of an image.

9. The data storage device according to claim 1, wherein the memory includes a three-dimensional memory.

10. A method in a data storage device comprising multiple levels of memory cells, the method comprising: Determine whether the data is specified for reading at dynamic read resolution; as well as In response to determining that the data is designated for reading at a dynamic read resolution, the data is stored in the memory using a non-BER (Bit Error Rate) balanced mapping, wherein when the data is stored using the non-BER balanced mapping instead of the BER balanced mapping, fewer memory sensing operations are required to read the pages of the data to achieve low-resolution reading.

11. The method according to claim 10, further comprising: Perform operations to mitigate the unbalanced BER caused by the use of the non-BER balanced mapping.

12. The method according to claim 11, further comprising: Higher resolution data is read by reading more pages of the data from the memory.

13. The method of claim 10, wherein the data includes images.

14. The method of claim 10, wherein the data includes parameters of a machine learning model.

15. The method of claim 10, wherein the determination is performed in response to receiving the data from the host.

16. The method of claim 10, wherein the determination is performed in response to remapping the data previously stored in the memory using a different mapping.

17. The method of claim 10, wherein the data is explicitly specified for reading by the host at a dynamic read resolution.

18. The method of claim 10, wherein the data is implicitly specified for reading by the host at a dynamic read resolution.

19. The method of claim 10, wherein the BER balancing mapping comprises a 4-4-3-4 mapping, and the non-BER balancing mapping comprises a 1-2-4-8 mapping.

20. A data storage device, the data storage device comprising: The memory includes multiple levels of memory units; and For use in the following devices: Based on whether the data is specified for variable read resolution, a mapping is selected from multiple mappings; as well as The data is written to the memory using the selected mapping.

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