Integrated circuit and phase-locked loop circuit comprising an integrated circuit

Abstract

An integrated circuit and a PLL circuit including the same are provided. An integrated circuit receiving a control voltage and converting the control voltage into an oscillator control current includes a PAR circuit outputting a compensation current compensating for at least one of process variation, power voltage variation, and temperature variation of the integrated circuit, an amplifier including a first power terminal receiving a power voltage, a second power terminal outputting an amplifier current determining a gain of the amplifier, an inverting input terminal receiving the control voltage, and a non-inverting input terminal receiving an amplifier voltage formed based on the gain of the amplifier, and an IDAC circuit converting a reference current generated based on the amplifier voltage into the oscillator control current according to an IDAC code. The PAR circuit outputs the compensation current.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0011318, filed on January 24, 2025, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This invention relates to integrated circuits and phase-locked loop circuits including integrated circuits. Background Technology

[0003] A System-on-a-Chip (SoC) can use different frequency bands for each embedded component. An SoC includes multiple phase-locked loop (PLL) circuits to support various frequency bands. The PLL circuit uses an internal clock signal that is "synchronously locked to an external clock signal input from an external device" to perform data transmission with the external device in a synchronous semiconductor device. In other words, time synchronization between the reference clock signal and the data is important for stable data transmission between the synchronous semiconductor device and the external device.

[0004] To achieve low-noise and low-power PLL circuits, ring voltage-controlled oscillators are used; however, ring oscillators have the disadvantage of being affected by process variations, temperature variations, and power supply voltage variations. Summary of the Invention

[0005] This invention provides an integrated circuit capable of improving the bandwidth and stability of a PLL circuit.

[0006] The present invention also provides a PLL circuit including an integrated circuit capable of improving the bandwidth and stability of the PLL circuit.

[0007] However, the aspects of the invention are not limited to those set forth herein. The above and other aspects of the invention will become more apparent to those skilled in the art from the specific embodiments of the invention given below.

[0008] According to some embodiments of this disclosure, an integrated circuit is provided, configured to receive a control voltage and convert the control voltage into an oscillator control current. The integrated circuit includes: a process-aware reference (PAR) circuit configured to output a compensation current to compensate for at least one of process variations, power supply voltage variations, or temperature variations of the integrated circuit; an amplifier including: a first power supply terminal, a second power supply terminal, an inverting input terminal, and a non-inverting input terminal, the first power supply terminal being configured to receive a power supply voltage, the second power supply terminal being configured to output an amplifier current determining the amplifier gain, the inverting input terminal being configured to receive the control voltage, and the non-inverting input terminal being configured to receive an amplifier voltage based on the amplifier gain; and a current-to-analog converter (IDAC) circuit configured to convert a reference current generated based on the amplifier voltage into an oscillator control current according to an IDAC code, wherein the PAR circuit is configured to output the compensation current to adjust the amplifier current.

[0009] According to some embodiments of this disclosure, an integrated circuit is provided, configured to receive a control voltage and convert the control voltage into an oscillator control current. The integrated circuit includes: a process-aware reference (PAR) circuit configured to output a compensation current to compensate for at least one of process variations, power supply voltage variations, or temperature variations of the integrated circuit; an amplifier including an inverting input terminal and a non-inverting input terminal, the inverting input terminal being configured to receive the control voltage and the non-inverting input terminal being short-circuited to a first node; a first transistor configured to receive the amplifier's output voltage as a gate voltage and having a first terminal electrically connected to a power supply terminal and a second terminal electrically connected to the first node; a resistor connected in series between the first node and a power supply ground terminal; a second transistor connected in series between the amplifier's power supply terminal and the power supply ground terminal; a third transistor connected in series between the PAR circuit and the power supply ground terminal, and together with the second transistor, serving as a current mirror; and a current digital-to-analog converter (IDAC) circuit that converts the reference current through the resistor into an oscillator control current according to an IDAC code.

[0010] According to some embodiments of this disclosure, a phase-locked loop circuit is provided, comprising: a loop filter configured to output a control voltage based on the amount of charge stored in a capacitor; a voltage-to-current converter configured to receive the control voltage, configured to convert the control voltage into an oscillator control current, and output the oscillator control current; and an oscillator configured to output an output frequency signal based on the oscillator control current, wherein the voltage-to-current converter includes: a process-aware reference (PAR) circuit configured to output a compensation current to compensate for at least one of process variations, power supply voltage variations, or temperature variations of the voltage-to-current converter; an amplifier including a power supply terminal, an inverting input terminal, and a non-inverting input terminal, the power supply terminal configured to output an amplifier current determining the amplifier gain, the inverting input terminal configured to receive the control voltage, and the non-inverting input terminal configured to receive an amplifier voltage based on the amplifier gain; and a current digital-to-analog converter (IDAC) circuit that converts a reference current generated based on the amplifier voltage into an oscillator control current according to an IDAC code, wherein the PAR circuit is configured to output the compensation current to adjust the amplifier current.

[0011] Specific details of other embodiments are included in the detailed description and the accompanying drawings. Attached Figure Description

[0012] The above and other aspects and features of the present invention will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

[0013] Figure 1 This is a block diagram used to illustrate a phase-locked loop circuit.

[0014] Figure 2 This is a circuit diagram used to illustrate an oscillator.

[0015] Figure 3 It is used for explanation Figure 2 The circuit diagram of the delay unit.

[0016] Figure 4 This is a circuit diagram used to illustrate a voltage-to-current converter.

[0017] Figure 5 It is a graph showing the change in the output frequency signal of the oscillator due to the change in control voltage.

[0018] Figure 6 This is a graph showing the change in phase noise caused by changes in the output frequency signal.

[0019] Figure 7 This is a circuit diagram used to illustrate a voltage-to-current converter according to some embodiments.

[0020] Figure 8This is a circuit diagram used to illustrate the structure of a PAR circuit according to some embodiments.

[0021] Figure 9 This is a circuit diagram used to illustrate the structure of a PAR circuit according to some embodiments.

[0022] Figure 10 This is a circuit diagram used to illustrate the structure of a PAR circuit according to some embodiments.

[0023] Figure 11 It is used for explanation Figure 10 The circuit diagram of the three-input amplifier. Detailed Implementation

[0024] In the following description, embodiments of the technical concept according to the present invention will be described with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram used to illustrate a phase-locked loop circuit.

[0026] Reference Figure 1 The phase-locked loop (PLL) circuit (hereinafter, “PLL circuit”) 1 may include a voltage-to-current converter 10, a phase-frequency detector (PFD) 20, an oscillator (VCO) 30, a charge pump 40, a loop filter 50, and a distributor 60.

[0027] The phase frequency detector 20 can receive a reference frequency signal fREF and a feedback frequency signal fFB. The phase frequency detector 20 compares the phase of the reference frequency signal fREF with the phase of the feedback frequency signal fFB and outputs a detection signal DET corresponding to the comparison result. The detection signal DET can be provided to the charge pump 40.

[0028] For example, the phase frequency detector 20 can compare the phase of the reference frequency signal fREF with the phase of the feedback frequency signal fFB, and output a detection signal DET with a magnitude of 0 when there is no phase difference. If there is a phase difference between the reference frequency signal fREF and the feedback frequency signal fFB, the phase frequency detector 20 can output a detection signal DET with a pulse width corresponding to the interval where the phase difference exists (i.e., the interval corresponding to the phase difference). The sign of the detection signal DET can be determined by comparing the magnitude of the reference frequency signal fREF with the magnitude of the feedback frequency signal fFB.

[0029] The charge pump 40 receives a detection signal DET from the phase frequency detector 20. The charge pump 40 supplies charge Q to the loop filter 50 according to the detection signal DET. For example, the loop filter 50 may include a capacitor capable of storing charge. The charge pump 40 can charge the capacitor of the loop filter 50 when the detection signal DET has a positive sign and can discharge the capacitor of the loop filter 50 when the detection signal DET has a negative sign. The charge pump 40 can determine the magnitude of the current supplied to the loop filter 50 based on the pulse width of the detection signal DET.

[0030] The loop filter 50 may include a capacitor. The capacitor may store charge supplied from the charge pump 40. The loop filter 50 may supply a control voltage VCTRL to the voltage-to-current converter 10 based on the amount of charge stored in the capacitor. The loop filter 50 may also include a low-pass filter (LPF). The loop filter 50 may use the LPF to remove noise signals generated in the phase frequency detector 20.

[0031] The voltage-to-current converter 10 can receive a control voltage VCTRL, convert the control voltage VCTRL into an oscillator control current IVCO, and provide it to the oscillator 30.

[0032] Oscillator 30 can output an output frequency signal fVCO based on the oscillator control current IVCO. Oscillator 30 can be, for example, a ring oscillator.

[0033] Divider 60 can receive an output frequency signal fVCO from oscillator 30. Divider 60 can allocate the frequency of the output frequency signal fVCO based on a defined allocation ratio (e.g., N). For example, the allocation ratio can be adjusted by a signal received from an external source. Divider 60 can allocate the frequency of the output frequency signal fVCO to output a feedback frequency signal fFB. The feedback frequency signal fFB can be provided to phase frequency detector 20.

[0034] Figure 2 This is a circuit diagram used to illustrate an oscillator. Figure 3 It is used for explanation Figure 2 The circuit diagram of the delay unit.

[0035] Reference Figure 2 and Figure 3 The oscillator 30 is a ring oscillator consisting of three stages, and may include a first delay unit 31, a second delay unit 32, and a third delay unit 33. The oscillator 30 can be used with... Figure 1 The oscillator 30 corresponds to this. To more effectively remove common-mode noise, the signal path between delay units can be implemented as a differential path.

[0036] Each delay unit may include NMOS transistors and PMOS transistors. For example, the second delay unit 32 may include a pair of PMOS transistors MP11 and MP12 that receive an input voltage and output an output voltage, a pair of NMOS transistors MN11 and MN14, and a pair of NMOS transistors MN12 and MN13 connected by cross-coupling. The PMOS transistors MP11 and MP12 and the NMOS transistors MN11 and MN14 may receive differential input voltages (IN+, IN-) at their gates and output differential output voltages (OUT-, OUT+) at the common drain node (MP11-MN11, MP12-MN14) of the PMOS and NMOS transistors. Each of the NMOS transistors MN12 and MN13 connected by cross-coupling has a source-drain connection to the same source-drain as the NMOS transistors MN11 and MN14, and the differential output voltage may be provided to the gate.

[0037] The differential output signals (OUT+, OUT-) can be generated as a pair of periodic sine waves, with the output signal OUT+ having a 180-degree phase difference with the output signal OUT-. Subsequently, when the differential output signals are later converted to single-ended signals, any common-mode noise injected into the input or power terminals can be eliminated.

[0038] The second delay unit 32 can adjust its frequency based on the transconductance gm of the PMOS transistor pairs MP11 and MP12 and the NMOS transistor pairs MN11 and MN14 and the load capacitance. In this case, the transconductance of the PMOS transistor pairs MP11 and MP12 and the NMOS transistor pairs MN11 and MN14 can be adjusted by a reference current and can have a wide frequency adjustment band based on the transconductance to be adjusted. The transconductance gm can be the change in current divided by the change in gate-source voltage.

[0039] Figure 4 This is a circuit diagram used to illustrate a voltage-to-current converter.

[0040] In the following description of the circuit diagrams and specific embodiments of the present invention, the NMOS transistors and PMOS transistors are examples and are not limited thereto. According to some embodiments of the present invention, an NMOS transistor may be implemented as a PMOS transistor (instead of an NMOS transistor), and a PMOS transistor may be implemented as an NMOS transistor (instead of a PMOS transistor). Figure 4 The voltage-to-current converter 10a can be used with Figure 1 The voltage-to-current converter 10 corresponds to this. (Refer to...) Figure 4The voltage-to-current converter 10a may include a current digital-to-analog converter (IDAC) circuit 11 (hereinafter, “IDAC circuit”) and an amplifier 12.

[0041] The IDAC circuit 11 may include a plurality of PMOS transistors. The IDAC circuit 11 may convert a reference current IUNIT into an oscillator control current IVCO based on a digital code (e.g., the IDAC code IDAC_CODE). For example, the IDAC circuit 11 may turn each of the plurality of PMOS transistors on or off according to the digital code IDAC_CODE. The IDAC circuit 11 may provide an oscillator control current IVCO to the oscillator 30, the oscillator control current IVCO having a magnitude that sums the reference currents IUNIT of the number of PMOS transistors that are turned on. Although the IDAC circuit 11 in… Figure 4 The IDAC circuit 11 is implemented as a plurality of PMOS transistors, but according to some embodiments of the present invention, the IDAC circuit 11 may be implemented as a plurality of NMOS transistors.

[0042] Amplifier 12 may include an inverting input terminal, a non-inverting input terminal, a first power supply terminal, a second power supply terminal, and an output terminal. The inverting input terminal may be externally accessible (e.g., Figure 1 The loop filter 50 receives the control voltage VCTRL. A first power supply terminal can be connected to the power supply terminal VDD. The output terminal of amplifier 12 is connected to PMOS transistor MP21, and the output voltage of amplifier 12 can be provided to PMOS transistor MP21 as the gate voltage. PMOS transistor MP21 may have one end connected to the power supply terminal VDD and the other end connected to the first node. The amplifier voltage VAMP can be formed at the first node by the output voltage of amplifier 12. The non-inverting input terminal of amplifier 12 can be connected to the first node and is supplied with the amplifier voltage VAMP. In one example, the non-inverting input terminal of amplifier 12 can be short-circuited to the first node. Resistor R1 can be connected in series between the first node and the power supply ground terminal VSS. Due to the voltage difference between the first node and the power supply ground terminal VSS, a reference current IUNIT can flow through resistor R1. NMOS transistor MN21 can be connected in series between the second power supply terminal of amplifier 12 and the power supply ground terminal VSS. The bias voltage VBIAS determines the magnitude of the amplifier current IAMP flowing through NMOS transistor MN21.

[0043] The voltage-to-current converter 10a can be affected by process variations, supply voltage variations, and / or temperature variations (PVT variations). For example, the bias voltage VBIAS can be affected by PVT variations and can unintentionally fluctuate at the voltage level. In response to changes in the bias voltage VBIAS, the amplifier current IAMP can also fluctuate at the current level. Changes in the magnitude of the amplifier current IAMP can alter the gain of amplifier 12. When the gain of amplifier 12 changes, the output voltage of amplifier 12 can also change, which can alter the magnitude of the amplifier voltage VAMP.

[0044] Ideally (when the bias voltage VBIAS is not affected by changes in PVT), the amplifier voltage VAMP can be equal to the control voltage VCTRL.

[0045] [Formula 1]

[0046]

[0047] However, due to the variation in PVT, a voltage difference Voffset can occur between the amplifier voltage VAMP and the control voltage VCTRL.

[0048] [Formula 2]

[0049] Referring to Formula 2, the voltage difference Voffset between the amplifier voltage VAMP and the control voltage VCTRL can reduce the amount of change in the magnitude of the reference current IUNIT caused by the change in the magnitude of the control voltage VCTRL, and can also reduce the magnitude of the change in the output frequency signal fVCO of the oscillator 30 caused by the change in the magnitude of the control voltage VCTRL.

[0050] [Formula 3]

[0051]

[0052] Referring to Formula 3, the transfer function LL(s) of the PLL circuit, which determines its bandwidth and stability, can be determined by three parameters: charge pump gain (ICP), loop filter gain (KLF(s)), and oscillator gain KVCO. The voltage difference Voffset between the amplifier voltage VAMP and the control voltage VCTRL can change the oscillator gain KVCO, which can suppress the bandwidth and stability of the PLL circuit.

[0053] Figure 5 It is a graph showing the change in the output frequency signal of the oscillator due to the change in control voltage. Figure 6This is a graph showing the change in phase noise caused by changes in the output frequency signal.

[0054] The difference in oscillator gain KVCO, based on a comparison of the amplifier voltage VAMP and the control voltage VCTRL, will be referenced. Figure 5 To illustrate, the x-axis of the graph represents the magnitude of the control voltage VCTRL, and the y-axis represents the frequency of the output frequency signal fVCO. Figure 1 This represents the change in the oscillator output frequency signal caused by the change in the control voltage VCTRL when the amplifier voltage VAMP is less than the control voltage VCTRL. (Curve) Figure 2 This represents the change in the oscillator output frequency signal caused by the change in the control voltage VCTRL when the amplifier voltage VAMP equals the control voltage VCTRL. (Curve) Figure 3 This represents the change in the oscillator output frequency signal caused by the change in the control voltage VCTRL when the amplifier voltage VAMP is greater than the control voltage VCTRL. According to Formula 3, the slope of each curve represents the oscillator gain KVCO. The oscillator gain KVCO on the curve... Figure 1 The value is minimum in the middle, and the oscillator gain KVCO is on the curve. Figure 3 The middle one is the largest.

[0055] Next, the difference in phase noise based on the comparison between the magnitude of amplifier voltage VAMP and the magnitude of control voltage VCTRL will be referenced. Figure 6 To illustrate, the x-axis of the graph represents the frequency of the output frequency signal fVCO, and the y-axis represents the phase noise. Figure 1 This represents the change in phase noise caused by variations in the output frequency signal when the amplifier voltage VAMP is less than the control voltage VCTRL. (Curve) Figure 2 This represents the change in phase noise caused by variations in the output frequency signal when the amplifier voltage VAMP equals the control voltage VCTRL. (Curve) Figure 3 This represents the change in phase noise caused by the variation in the output frequency signal when the amplifier voltage VAMP is greater than the control voltage VCTRL. Additional noise (shaded area) can be generated when a voltage difference Voffset exists due to the difference between the amplifier voltage VAMP and the control voltage VCTRL.

[0056] Figure 7 This is a circuit diagram used to illustrate a voltage-to-current converter according to some embodiments. Figure 4 The detailed description of the repeated parts is in Figure 7 The lieutenant general was not provided.

[0057] Reference Figure 7 ,and Figure 4 Unlike the voltage-to-current converter 10a, the voltage-to-current converter 10b may also include a PAR (Process Aware Reference) circuit 13. The PAR circuit 13 outputs a compensation current IPAR to compensate for at least one of process variations, power supply voltage variations, and temperature variations (PVT variations). An NMOS transistor MN32 may be connected in series between the PAR circuit 13 and the power supply ground terminal VSS. In this case, the NMOS transistor MN31 between the amplifier 12 and the power supply ground terminal VSS, and the NMOS transistor MN32 between the PAR circuit 13 and the power supply ground terminal VSS, form a current mirror 14. The current mirror 14 allows the same current as the compensation current IPAR to flow through the NMOS transistor MN31 between the amplifier 12 and the power supply ground terminal VSS, and the compensation current IPAR to flow through the NMOS transistor MN32 between the PAR circuit 13 and the power supply ground terminal VSS. That is, the amplifier current IAMP may be substantially equal to the compensation current IPAR. Here, "substantially the same" means not only to include things that are completely identical, but also to include things that are sufficiently similar to be considered identical, including permissible errors caused by various factors. The PAR circuit 13 can output a compensation current IPAR to adjust the magnitude of the amplifier current IAMP.

[0058] The amplifier current IAMP is equal to the compensation current IPAR that compensates for at least one of the PVT variations, and is therefore resistant to PVT variations. The voltage difference Voffset between the amplifier voltage VAMP and the control voltage VCTRL reduces the "amplifier current IAMP that resists PVT variations".

[0059] According to some embodiments, since the voltage-to-current converter 10b also includes a PAR circuit 13, it is feasible to reduce the voltage difference Voffset between the amplifier voltage VAMP and the control voltage VCTRL. Therefore, it is feasible to provide a voltage-to-current converter 10b that can improve the bandwidth and stability of the PLL circuit.

[0060] Figure 8 This is a circuit diagram used to illustrate the structure of a PAR circuit according to some embodiments.

[0061] The structure of a PAR circuit will be described below, but the PAR circuit is not limited to the structure described in this disclosure, and the PAR circuit may have various structures other than those described in this disclosure.

[0062] Reference Figure 8The PAR circuit 13a may include an amplifier 101, NMOS transistor pairs MN41 and MN42, PMOS transistors MP41, MP42, and MP43, and resistors R3 and R4. NMOS transistor pairs MN41 and MN42 may be connected between the power supply ground terminal VSS and node N41, and between the power supply ground terminal VSS and node N42, respectively. NMOS transistor pairs MN41 and MN42 may have a source terminal connected to the power supply ground terminal VSS and a drain terminal connected to the gate terminal, thereby forming a diode connection. A gate-source voltage may be applied to the gate of NMOS transistor MN41, and a gate-source voltage may be applied to the gate of NMOS transistor MN42.

[0063] NMOS transistor MN42 can be connected between the power supply ground terminal VSS and the first terminal (+) of amplifier 101, and NMOS transistor MN41 can be connected between the power supply ground terminal VSS and the second terminal (-) of amplifier 101. Resistor R4 is connected between NMOS transistor MN42 and node N42, and resistor R3 can be connected in parallel with NMOS transistor MN42 (i.e., between power supply ground terminal VSS and node N42).

[0064] PMOS transistors MP41 and MP42 can be connected between node N41 and the power supply terminal VDD, and between node N42 and the power supply terminal VDD, respectively. The gate terminals of PMOS transistors MP41, MP42, and MP43 can be connected to the output node N43 of the amplifier.

[0065] When the NMOS transistor MN41 of PAR circuit 13a operates in the sub-threshold region, the current I flowing through the NMOS transistor MN41 is... DS It can be calculated as shown in Formula 4.

[0066] [Formula 4]

[0067] In the above formula, This represents the gate oxide capacitance per unit area. V represents the carrier mobility. GS1 V represents the gate-source voltage of the NMOS transistor MN41. th Let represent the threshold voltage of NMOS transistor MN41, η represent the subthreshold slope factor of transistor MN41, T represent the absolute temperature, and V T This represents the thermal voltage, which is proportional to absolute temperature.

[0068] The NMOS transistor MN41 connected in a diode configuration can have a voltage V with a negative coefficient in the temperature-voltage relationship. GS1 Furthermore, the current proportional to the voltage can be absolute temperature complementary (CTAT) with a negative coefficient relative to the absolute temperature. Additionally, because the threshold voltage V of the NMOS transistor MN41... th This can change due to variations in manufacturing processes, so information about variations in the manufacturing process of NMOS transistors can be obtained through voltage V. GS1 To obtain. Based on the voltage V due to the parallel connection. GS1 CTAT current ICTAT=V GS1 / R3 can flow through resistor R3.

[0069] Furthermore, NMOS transistor MN41 can have different dimensions than NMOS transistor MN42. NMOS transistor MN41 can have a size difference of n times compared to NMOS transistor MN42. Since the temperature characteristics can vary when the dimensions of NMOS transistor MN41 and NMOS transistor MN42 differ, the PTAT (proportional to absolute temperature) characteristic can be created based on the voltage difference between the two transistors. As shown in Equation 5, the PTAT current based on the size difference between transistors MN41 and MN42 is proportional to the absolute temperature T.

[0070] [Formula 5]

[0071] In Formula 5, V GS2 It is the gate-source voltage of the NMOS transistor MN42, V GS1 It is the gate-source voltage of the NMOS transistor MN41, I O1 and I O2 It is a constant determined by the process and device characteristics, I DS1 It is the drain-source current of the NMOS transistor MP41, and I DS2 This is the drain-source current of the PMOS transistor MN42. Here, n is the size ratio of the NMOS transistor MN42 to the NMOS transistor MN41, and T is the absolute temperature.

[0072] PTAT current PTAT V GS It is proportional to the absolute temperature T. Transistors MN41 and MN42 can be based on resistor R4 and... V GS Generating PTAT current (IPTAT= V GS / R4), and the PTAT current PTAT is proportional to the absolute temperature T.

[0073] As shown in Formula 6, the compensation current Iz of PAR circuit 13a can be generated by adding the PTAT current and the CTAT current.

[0074] [Formula 6]

[0075] According to Equation 6, PAR circuit 13a can achieve a constant current flow by adjusting the ratio of resistors R3 and R4, regardless of temperature changes.

[0076] In addition, the V of the NMOS transistor MN41 GS1 It is feasible to change the process according to the NMOS transistor process, and therefore obtain information about the process changes through the changing current and compensate for the process changes. However, in a typical VCO, since both NMOS and PMOS transistors are affected by process changes, in order to compensate for the VCO, it is necessary not only to configure the PAR circuit 13a designed as an NMOS transistor, but also other circuits designed as PMOS transistors.

[0077] Figure 9 This is a circuit diagram used to illustrate the structure of a PAR circuit according to some embodiments.

[0078] Reference Figure 9 The PAR circuit 13b may include bandgap reference circuit pairs 110 and 120, and a weighted current mirror 130.

[0079] The bandgap reference circuit pairs 110 and 120 may include a first type bandgap reference circuit 110 and a second type bandgap reference circuit 120, each of which is connected to both ends of the weighted current mirror 130.

[0080] According to some embodiments, the first type bandgap reference circuit 110 and the second type bandgap reference circuit 120 may have a twin structure. That is, the first type bandgap reference circuit 110 and the second type bandgap reference circuit 120 can be implemented with the same circuit connection structure, the only difference being whether they are implemented as PMOS transistor circuits or NMOS transistor circuits.

[0081] For example, the first type of bandgap reference circuit 110 may include an amplifier, a pair of PMOS transistors MP51 and MP52, a pair of NMOS transistors MN51 and MN52, and resistors R5 and R6.

[0082] PMOS transistors MP51 and MP52 can be connected between the power supply terminal VDD and node N51, and between the power supply terminal VDD and node N52, respectively. PMOS transistors MP51 and MP52 can have a source terminal connected to the power supply terminal VDD and a drain terminal connected to the gate terminal, thus forming a diode connection. A gate-source voltage can be applied to the gate of PMOS transistor MP51, and a gate-source voltage can be applied to the gate of PMOS transistor MP52.

[0083] PMOS transistor MP51 can be connected between the power supply terminal VDD and the first terminal (+) of the amplifier, and PMOS transistor MP52 can be connected between the power supply terminal VDD and the second terminal (-) of the amplifier. Resistor R6 can be connected between PMOS transistor MP51 and node N51, and resistor R5 can be connected in parallel with PMOS transistor MP51 (that is, between the power supply terminal VDD and node N51).

[0084] NMOS transistors MN51 and MN52 can be connected between node N51 and power supply ground terminal VSS, and between node N52 and power supply ground terminal VSS, respectively. The gate terminals of NMOS transistors MN51 and MN52 can be connected to the output node N58 of the amplifier.

[0085] When the PMOS transistor MP52 of the first type bandgap reference circuit 110 operates in the subthreshold region, the current I flowing through the PMOS transistor MP52 is... DS As shown in formula (7).

[0086] [Formula 7]

[0087] In the above formula, V GSP1 This represents the gate-source voltage of transistor MP52, V. th Let represent the threshold voltage of transistor MP52, η represent the subthreshold slope factor of transistor MP52, T represent the absolute temperature, and V T This represents the thermal voltage, which is proportional to the absolute temperature T.

[0088] The PMOS transistor MP52, connected in a diode configuration, can have a voltage V with a negative coefficient in the temperature-voltage relationship. GSP1 Furthermore, the current proportional to the voltage can be an absolute temperature complementary (CTAT) current with a negative coefficient relative to temperature. That is, the CTAT current flowing through resistor R5 can be ICTAT = V. GSP1 / R5.

[0089] PMOS transistor MP51 can have different dimensions than PMOS transistor MP52. PMOS transistor MP51 can have a size difference of n times compared to PMOS transistor MP52. Since the temperature characteristics change when the dimensions of PMOS transistor MP51 and PMOS transistor MP52 differ, the PTAT (proportional to absolute temperature) characteristic can be created based on the voltage difference between the two transistors. As shown in Equation 8, the PTAT current based on the size difference between the two transistors MP51 and MP52 is proportional to the absolute temperature T.

[0090] [Formula 8]

[0091] In Formula 8, V GSP2 It is the gate-source voltage of the PMOS transistor MP51, V GSP1 It is the gate-source voltage of the PMOS transistor MP52, I DS2 It is the drain-source current of the PMOS transistor MP51, and I DS1 is the drain-source current of PMOS transistor MP2. n is the size ratio of PMOS transistor MP51 to PMOS transistor MP52, and T is the absolute temperature.

[0092] In the example shown, the PMOS transistor MP51 will be described as having a size eight times that of the PMOS transistor MP52. That is, as a non-limiting example, V GSP2 With V GSP1 The gate-source voltage is eight times larger. However, embodiments of the invention are not limited thereto, and the size difference between the two transistors can be set in various ways according to various embodiments.

[0093] In other words, according to Formula 8, since the body-effect between the two transistors MP51 and MP52 is slight, it is assumed that the threshold voltage V th They are roughly the same. V GSP Proportional to absolute temperature T. Transistors MP51 and MP52 are based on resistor R6 and... V GSP Generating PTAT current (IPTAT= V GSP / R6), and the PTAT current IPTAT is proportional to the absolute temperature T.

[0094] The first-type bandgap reference circuit 110 can generate a first-type compensation current IP based on these characteristics. The first-type compensation current IP is calculated as shown in Equation 9.

[0095] [Formula 9]

[0096] In other words, the first type of compensation current IP is obtained by adding the CTAT current ICTAT, which is inversely proportional to the absolute temperature, and the PTAT current IPTAT, which is proportional to the absolute temperature, and the constant current independent of temperature can be output by adjusting the ratio of the two resistors R5 and R6.

[0097] The second type of bandgap reference circuit 120 may include an amplifier, NMOS transistor pairs MN54 and MN55, PMOS transistor pairs MP56 and MP57, and resistors R7 and R8.

[0098] NMOS transistor pairs MN54 and MN55 can be connected between the power supply ground terminal VSS and node N55, and between the power supply ground terminal VSS and node N56, respectively. NMOS transistor pairs MN54 and MN55 can have a source terminal connected to the power supply ground terminal VSS and a drain terminal connected to the gate terminal, thus forming a diode connection. A gate-source voltage can be applied to the gate of NMOS transistor MN54, and a gate-source voltage can be applied to the gate of NMOS transistor MN55.

[0099] NMOS transistor MN55 can be connected between the power supply ground terminal VSS and the first terminal (+) of the amplifier, and NMOS transistor MN54 can be connected between the power supply ground terminal VSS and the second terminal (-) of the amplifier. Resistor R8 can be connected between NMOS transistor MN55 and node N56, and resistor R7 can be connected in parallel with NMOS transistor MN55 (that is, between the power supply ground terminal VSS and node N56).

[0100] PMOS transistors MP56 and MP57 can be connected between node N55 and the power supply terminal VDD, and between node N56 and the power supply terminal VDD, respectively. The gate terminals of PMOS transistors MP56 and MP57 can be connected to the output node N57 of the amplifier.

[0101] like Figure 8 The second type of compensation current IN of the second type bandgap reference circuit 120 described herein is as follows in Formula 10.

[0102] [Formula 10]

[0103] The weighted current mirror 130 may include a PMOS transistor MP53 and an NMOS transistor MN53 connected in a diode configuration for converting the first type compensation current IP generated by the first type bandgap reference circuit 110 at node N52.

[0104] The first bandgap reference circuit 110 generates a first type of compensation current IP flowing from the NMOS transistor MN52 to the PMOS transistor MP52, but the weighted current mirror 130 can reverse the current direction by including auxiliary current mirror circuits MP53 and MN53, which are used to perform a weighted average with the second type of compensation current IN.

[0105] The weighted current mirror 130 can generate a total compensation current obtained by weighting the first type of compensation current IP and the second type of compensation current IN. The weighted current mirror 130 can generate and output the total compensation current IPAR as shown in Equation 11.

[0106] [Formula 11]

[0107] PLL circuits (e.g., Figure 1 The PLL circuit 1) includes at least one PMOS transistor and at least one NMOS transistor, and can be affected by both the PMOS transistor process and the NMOS transistor process. Even if the PLL circuit is affected by the above two processes, the PAR circuit 13b can use the weighted value a of the first type compensation current IP generated by the first type bandgap reference circuit 110 to adjust the influence of the PMOS transistor process, and can use the weighted value (1-a) of the second type compensation current IN generated by the second type bandgap reference circuit 120 to adjust the influence of the NMOS transistor process, thereby adjusting the frequency deviation according to the process.

[0108] According to some embodiments, the weighted current mirror 130 may further include a plurality of first-type weighting circuits 131 and second-type weighting circuits 132 that output a weighted average of a first-type compensation current IP and a second-type compensation current IN. The first-type weighting circuits 131 and 132 may include a plurality of PMOS transistors. The first-type weighting circuit 131 may be connected between the power supply terminal VDD and the total output node N54, and its gate may be connected to the first-type bandgap reference circuit 110. The second-type weighting circuit 132 may be connected between the power supply terminal VDD and the total output node N54, and its gate may be connected to the second-type bandgap reference circuit 120. The first-type weighting circuits 131 and 132 may output the weighted and averaged total compensation current IPAR via the total output node N54.

[0109] To reflect the weighting value, each of the first type of weighting circuit 131 and the second type of weighting circuit 132 may include PMOS transistors of the same size. The weighting current mirror 130 can adjust the weighting value a:(1-a) by changing the number of transistors that are turned on or off in the first type of weighting circuit 131 and the second type of weighting circuit 132.

[0110] In addition, with Figure 9 As shown, each of the first type of weighting circuit and the second type of weighting circuit may include multiple NMOS transistors. The first type of weighting circuit and the second type of weighting circuit may be connected between the power supply ground terminal VSS and the total output node N54, and their gates may be connected to the first bandgap reference circuit 110 and the second bandgap reference circuit 120, respectively.

[0111] The PAR circuit 13b can generate a total compensation current IPAR that is less affected by PVT variations by adjusting the weighting value according to the magnitude changes of the first type of compensation current IP and the second type of compensation current IN based on the PVT variation.

[0112] Figure 10 This is a circuit diagram used to illustrate the structure of a PAR circuit according to some embodiments. Figure 11 It is used for explanation Figure 10 The circuit diagram of the three-input amplifier.

[0113] Reference Figure 10 and Figure 11 PAR circuit 13c can be Figure 4The PAR circuit 13c may include a three-input amplifier 102, NMOS transistor pairs MN61 and MN62, PMOS transistor pairs MP61 and MP62, PMOS transistors MP63, MP64, MP65, and MP66, and resistors R9, R10, and R11. NMOS transistor pairs MN61 and MN62 may be connected between the power supply ground terminal VSS and node N62, and between the power supply ground terminal VSS and node N63, respectively. NMOS transistor pairs MN61 and MN62 may have a source terminal connected to the power supply ground terminal VSS and a drain terminal connected to the gate terminal, thereby forming a diode connection. A gate-source voltage can be applied to the gate of NMOS transistor MN61, and a gate-source voltage can be applied to the gate of NMOS transistor MN62. PMOS transistor pairs MP61 and MP62 may be connected between the power supply ground terminal VSS and node N61, and between the power supply ground terminal VSS and node N63, respectively. PMOS transistors MP61 and MP62 have a drain terminal connected to the power supply ground terminal VSS, and the drain terminal can be connected to the gate terminal to form a diode connection. In one example, PMOS transistor MP62 may have a larger size than PMOS transistor MP61 (e.g., the size ratio of PMOS transistor MP62 to PMOS transistor MP61 may be n).

[0114] NMOS transistor MN62 can be connected between the power supply ground terminal VSS and the first terminal (+) of the three-input amplifier 102, and NMOS transistor MN61 can be connected between the power supply ground terminal VSS and the third terminal (2-) of the three-input amplifier 102. PMOS transistor MP62 can be connected between the power supply ground terminal VSS and the first terminal (+) of the three-input amplifier 102, and PMOS transistor MP61 can be connected between the power supply ground terminal VSS and the second terminal (1-) of the three-input amplifier 102. Resistor R10 can be connected between PMOS transistor MP62 and node N63, resistor R11 can be connected between NMOS transistor MN62 and node N63, and resistor R9 can be connected between the power supply ground terminal VSS and node N63.

[0115] The three-input amplifier 102 has a first terminal (+), a second terminal (1-), and a third terminal (2-) as input terminals, and may include current mirrors 126, 127, and 128. The first terminal (+) can be connected to the gate terminals of NMOS transistors MN72 and MN73, and the second terminal (1-) and the third terminal (2-) can be connected to the gate terminals of NMOS transistors MN71 and MN74, respectively. The first total current flowing through NMOS transistors MN71 and MN72 can be Ix1 = a × Ix, where Ix represents the total tail current of the three-input amplifier. The second total current flowing through NMOS transistors MN73 and MN74 can be Ix2 = (1-a) × Ix. Therefore, the voltage applied to the first terminal (+) of the three-input amplifier 102 can be V. GSA =aV GSP1 +(1-a)V GSN1 In this specification, the NMOS transistors MN71 to MN74 included in the three-input amplifier 102 may also be referred to as amplifier transistors.

[0116] PMOS transistors MP63, MP64, and MP65 can be connected between node N61 and power supply terminal VDD, between node N62 and power supply terminal VDD, and between node N63 and power supply terminal VDD, respectively. The gate terminals of PMOS transistors MP63, MP64, MP65, and MP66 can be connected to the output node N64 of the three-input amplifier 102.

[0117] Referring to the above, due to the source voltage V of the PMOS transistor MP61 GSP1 and the gate-drain voltage V of NMOS transistor MN61 GSN1 Having a negative coefficient in the temperature-voltage relationship, the current IPN_C flowing through resistor R9 is as shown in Equation 12 below, and can also be based on the CTAT (absolute temperature complementary) current of NMOS and PMOS transistors, which have a negative coefficient relative to temperature.

[0118] [Formula 12]

[0119] Similarly, referring to the above, a PTAT characteristic proportional to absolute temperature T can be created by utilizing the temperature characteristics resulting from the dimensional differences between PMOS transistor MP61, NMOS transistor MN61, and PMOS transistor MP62. Furthermore, a PTAT characteristic proportional to absolute temperature T can also be created by utilizing the temperature characteristics resulting from the dimensional differences between PMOS transistor MP61, NMOS transistor MN61, and NMOS transistor MN62. Therefore, the current IP_P flowing through resistor R10 can be a PTAT current based on the PMOS transistor, proportional to absolute temperature T, as shown in Formula 13 below. Furthermore, the current IN_P flowing through resistor R11 can be a PTAT current based on the NMOS transistor, proportional to absolute temperature T, as shown in Formula 14 below.

[0120] [Formula 13]

[0121] [Formula 14]

[0122] Finally, as shown in Equation 15 below, the IPAR current flowing through the PMOS transistor MP66 can be equal to the sum of the CTAT currents of the NMOS and PMOS, the PTAT current of the PMOS, and the PTAT current of the NMOS.

[0123] [Formula 15]

[0124] PLL circuits (e.g., Figure 1 The PLL circuit 1) can be affected by both PMOS and NMOS transistor processes due to including at least one PMOS transistor and at least one NMOS transistor. According to some embodiments, even if the PLL circuit is affected by both PMOS and NMOS transistor processes, the PAR circuit 13c can adjust the effects of the PMOS and NMOS transistor processes to a weighted value 'a', thereby compensating for both process variations in the NMOS and PMOS processes. In this case, the PLL circuit can adjust the transconductance of the three-input amplifier 102 to adjust the weighted value 'a'. For example, the weighted value 'a' can be adjusted by... Figure 11 The transconductance of the NMOS transistors MN71, MN72, MN73, and MN74 can be adjusted. Furthermore, the PLL circuit can output a temperature-independent current by adjusting the ratio of resistors R9, R10, and R11.

[0125] According to some embodiments, the compensation current IPAR generated by the PAR circuit 13c can change with variations in PVT. That is, the compensation current IPAR can reflect variations in the PMOS transistor process, variations due to NMOS transistor process variations or temperature, variations in the power supply voltage, or variations due to power supply voltage noise. The compensation current IPAR can change in response to variations in PVT under the same environmental conditions as transistors included in other components included in the PLL circuit.

[0126] According to some embodiments, the PAR circuit 13c can generate a compensation current IPAR that is less affected by process variations, temperature variations, and power supply voltage variations by adjusting the weighting value a and the resistance ratio to take into account PVT variations.

[0127] Throughout this document, terms such as first, second, etc., indicating order, are used to distinguish elements having the same / similar functions, and ordinal numbers may be interchanged depending on the order in which the terms are mentioned. For the sake of clarity in this disclosure, portions irrelevant to the description will be omitted, and throughout the specification, the same elements or equivalents are indicated by the same reference numerals.

[0128] As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the described features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The terms “and / or” include any and all combinations of one or more of the associated listed items. The term “connection” may be used herein to mean a physical connection and / or an electrical connection, and may mean a direct or indirect physical connection and / or electrical connection.

[0129] Although some embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to these embodiments and can be implemented in various different forms. Those skilled in the art to which this disclosure pertains will understand that the present disclosure can be implemented in other specific forms without altering the technical concept or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are not limiting, but are exemplary in all respects.

Claims

1. An integrated circuit configured to receive a control voltage and convert the control voltage into an oscillator control current, the integrated circuit comprising: A process-aware reference circuit is configured to output a compensation current to compensate for at least one of process variations, power supply voltage variations, and temperature variations of the integrated circuit. Amplifier, including: A first power supply terminal is configured to receive a power supply voltage; a second power supply terminal is configured to output an amplifier current that determines the amplifier gain; an inverting input terminal is configured to receive a control voltage; and a non-inverting input terminal is configured to receive an amplifier voltage based on the amplifier gain; and A current-to-analog converter circuit is configured to convert a reference current generated based on the amplifier voltage into an oscillator control current according to a current-to-analog converter code. The process-aware reference circuit is configured to output the compensation current to adjust the amplifier current.

2. The integrated circuit as described in claim 1, in, The magnitude of the amplifier current is equal to the magnitude of the compensation current.

3. The integrated circuit as described in claim 1, further comprising: A resistor, connected in series between the first node and the ground power supply terminal, supplies the amplifier voltage to the non-inverting input terminal. The reference current is the current through the resistor.

4. The integrated circuit as described in any one of claims 1 to 3, in, The process-aware reference circuit includes a first type of bandgap reference circuit and a second type of bandgap reference circuit. The first type of bandgap reference circuit is configured to generate a first type of compensation current, and the second type of bandgap reference circuit is configured to generate a second type of compensation current. The compensation current is based on the weighted average of the first type of compensation current and the second type of compensation current.

5. The integrated circuit as claimed in claim 4, wherein, The first type of bandgap reference circuit includes: First amplifier; A first pair of PMOS transistors, connected in a diode configuration, is electrically connected between the power supply terminal and the input terminal of the first amplifier; and The first NMOS transistor pair has a gate electrically connected to the output terminal of the first amplifier and electrically connected between the input terminal of the first amplifier and the power supply ground terminal.

6. The integrated circuit as claimed in claim 5, wherein, The first type of bandgap reference circuit also includes: The first resistor is electrically connected between the power supply terminal and the first input terminal of the first amplifier. A first PMOS transistor connected in a diode manner and a second resistor are connected in series between the power supply terminal and the first input terminal of the first amplifier. The second PMOS transistor, which is connected in a diode manner, is electrically connected between the power supply terminal and the second input terminal of the first amplifier. A first NMOS transistor is electrically connected between a first input terminal of a first amplifier and a power supply ground terminal, and has a gate terminal electrically connected to the output terminal of the first amplifier; and The second NMOS transistor is electrically connected between the second input terminal of the first amplifier and the power supply ground terminal, and has a gate terminal electrically connected to the output terminal of the first amplifier.

7. The integrated circuit as claimed in claim 4, wherein, The process-aware reference circuit includes: a weighted current mirror configured to receive a first type of compensation current and weight the first type of compensation current using a first gain to generate a weighted first type of compensation current, configured to receive a second type of compensation current and weight the second type of compensation current using a second gain to generate a weighted second type of compensation current, and configured to output the compensation current by summing the weighted first type of compensation current and the weighted second type of compensation current.

8. The integrated circuit according to any one of claims 1 to 3, wherein, The process-aware reference circuit includes: A three-input amplifier, including a first input terminal, a second input terminal, and a third input terminal; The first PMOS transistor, which is connected in a diode manner, is electrically connected between the first input terminal of the three-input amplifier and the power supply ground terminal. The first NMOS transistor, connected in a diode configuration, is electrically connected between the second input terminal of the three-input amplifier and the power supply ground terminal; and The first resistor is electrically connected between the third input terminal of the three-input amplifier and the power supply ground terminal.

9. The integrated circuit as described in claim 8, in, A three-input amplifier includes a first amplifier transistor, a second amplifier transistor, a third amplifier transistor, and a fourth amplifier transistor. In this configuration, the first input terminal of the three-input amplifier is electrically connected to the gate terminal of the first amplifier transistor. In this configuration, the second input terminal of the three-input amplifier is electrically connected to the gate terminal of the fourth amplifier transistor, and The third input terminal of the three-input amplifier is electrically connected to the gate terminal of the second amplifier transistor and the gate terminal of the third amplifier transistor.

10. The integrated circuit as claimed in claim 8, wherein, The process-aware reference circuit also includes: The second PMOS transistor, connected in a diode configuration, is electrically connected between the third input terminal of the three-input amplifier and the power supply ground terminal, and has a larger size than the first PMOS transistor connected in a diode configuration; and The second resistor is electrically connected between the third input terminal of the three-input amplifier and the second PMOS transistor, which is connected in a diode manner.

11. The integrated circuit as claimed in claim 8, wherein, The process-aware reference circuit also includes: The second NMOS transistor, connected in a diode configuration, is electrically connected between the third input terminal of the three-input amplifier and the power supply ground terminal, and has a larger size than the first NMOS transistor connected in a diode configuration; and The second resistor is electrically connected between the third input terminal of the three-input amplifier and the second NMOS transistor, which is connected in a diode manner.

12. An integrated circuit configured to receive a control voltage and convert the control voltage into an oscillator control current, the integrated circuit comprising: A process-aware reference circuit is configured to output a compensation current to compensate for at least one of process variations, power supply voltage variations, and temperature variations of the integrated circuit. An amplifier includes an inverting input terminal and a non-inverting input terminal, the inverting input terminal being configured to receive a control voltage, and the non-inverting input terminal being short-circuited to a first node; The first transistor is configured to receive the output voltage of the amplifier as the gate voltage and has a first terminal electrically connected to a power supply terminal and a second terminal electrically connected to a first node. A resistor is connected in series between the first node and the power supply ground terminal; The second transistor is connected in series between the power supply terminal and the power ground terminal of the amplifier. The third transistor is connected in series between the process-aware reference circuit and the power supply ground terminal, and together with the second transistor, it serves as a current mirror. as well as The current-to-analog converter circuit is configured to convert a reference current through a resistor into an oscillator control current according to a current-to-analog converter code.

13. The integrated circuit as described in claim 12, in, The process-aware reference circuit includes a first type of bandgap reference circuit and a second type of bandgap reference circuit. The first type of bandgap reference circuit is configured to generate a first type of compensation current, and the second type of bandgap reference circuit is configured to generate a second type of compensation current. The compensation current is the weighted average of the first type of compensation current and the second type of compensation current.

14. The integrated circuit of claim 13, wherein, The first type of bandgap reference circuit includes: First amplifier; A first pair of PMOS transistors, connected in a diode configuration, is electrically connected between the power supply terminal and the input terminal of the first amplifier; and The first NMOS transistor pair has a gate electrically connected to the output terminal of the first amplifier and electrically connected between the input terminal of the first amplifier and the power supply ground terminal.

15. The integrated circuit of claim 14, wherein, The first type of bandgap reference circuit also includes: The first resistor is electrically connected between the power supply terminal and the first input terminal of the first amplifier; A first PMOS transistor connected in a diode manner and a second resistor are connected in series between the power supply terminal and the first input terminal of the first amplifier. The second PMOS transistor, which is connected in a diode manner, is electrically connected between the power supply terminal and the second input terminal of the first amplifier. A first NMOS transistor is electrically connected between a first input terminal of a first amplifier and a power supply ground terminal, and has a gate terminal electrically connected to the output terminal of the first amplifier; and The second NMOS transistor is electrically connected between the second input terminal of the first amplifier and the power supply ground terminal, and has a gate terminal electrically connected to the output terminal of the first amplifier.

16. The integrated circuit of claim 13, wherein, The process-aware reference circuit includes: a weighted current mirror configured to receive a first type of compensation current and weight the received first type of compensation current using a first gain to generate a weighted first type of compensation current, configured to receive a second type of compensation current and weight the second type of compensation current using a second gain to generate a weighted second type of compensation current, and configured to output the compensation current by summing the weighted first type of compensation current and the weighted second type of compensation current.

17. The integrated circuit according to any one of claims 12 to 16, wherein, The process-aware reference circuit includes: A three-input amplifier, including a first input terminal, a second input terminal, and a third input terminal; The first PMOS transistor, connected in a diode configuration, is electrically connected between the first input terminal of the three-input amplifier and the power supply ground terminal. The first NMOS transistor, connected in a diode configuration, is electrically connected between the second input terminal of the three-input amplifier and the power supply ground terminal; and The first resistor is electrically connected between the third input terminal of the three-input amplifier and the power supply ground terminal.

18. The integrated circuit of claim 17, wherein, A three-input amplifier includes a first amplifier transistor, a second amplifier transistor, a third amplifier transistor, and a fourth amplifier transistor. In this configuration, the first input terminal of the three-input amplifier is electrically connected to the gate terminal of the first amplifier transistor. In this configuration, the second input terminal of the three-input amplifier is electrically connected to the gate terminal of the fourth amplifier transistor, and The third input terminal of the three-input amplifier is electrically connected to the gate terminal of the second amplifier transistor and the gate terminal of the third amplifier transistor.

19. The integrated circuit of claim 17, wherein, The process-aware reference circuit also includes: The second PMOS transistor, connected in a diode configuration, is electrically connected between the third input terminal of the three-input amplifier and the power supply ground terminal, and has a larger size than the first PMOS transistor connected in a diode configuration; and The second resistor is electrically connected between the third input terminal of the three-input amplifier and the second PMOS transistor, which is connected in a diode manner.

20. A phase-locked loop circuit, comprising: The loop filter is configured to output a control voltage based on the amount of charge stored in the capacitor; A voltage-to-current converter is configured to receive a control voltage, to convert the control voltage into an oscillator control current, and to output an oscillator control current. as well as The oscillator is configured to output a frequency signal based on the oscillator control current. The voltage-to-current converter includes: A process-aware reference circuit is configured to output a compensation current for at least one of process variations, power supply voltage variations, and temperature variations in a voltage-to-current converter. An amplifier, including a power supply terminal, an inverting input terminal, and a non-inverting input terminal, wherein the power supply terminal is configured to output an amplifier current that determines the amplifier gain, the inverting input terminal is configured to receive a control voltage, and the non-inverting input terminal is configured to receive an amplifier voltage based on the amplifier gain; and A current-to-analog converter circuit is configured to convert a reference current generated based on the amplifier voltage into an oscillator control current according to a current-to-analog converter code. The process-aware reference circuit is configured to output the compensation current to adjust the amplifier current.

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