Low-complexity sequence estimator for General Packet Radio Service (GPRS) system

Abstract

Device (100) comprising the following: a processor (120); and a receiver that is configured to: to receive a phase-shift keying (PSK) modulated signal from a transceiver (113), to unwind the PSK-modulated signal, to feed the PSK-modulated signal to a maximum probability sequence estimation (MLSE) equalizer, wherein the MLSE equalizer has a first main tap gain lookup table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even time samples, and a second MTG LUT and a second ISI LUT corresponding to odd time samples.

Description

AREA

[0001] The present disclosure relates generally to a method and an apparatus, and more specifically to a method and an apparatus for a low-complexity sequence estimator for a General Packet Radio Service (GPRS) system or, more generally, a packet-oriented radio service system and improved data rates for a Global System for Mobile Communication (GSM) Evolution (EDGE) system. BACKGROUND

[0002] In a general packet radio service system (GPRS) network, system capacity is limited by co-channel interference (CCI) due to frequency reuse. Since the majority of users in a second-generation (2G) communication system use a voice service, users of a packet data service are often limited by Gaussian minimum shift keying (GMSK) interference.

[0003] Users of electronic devices require increasing functionality and performance in applications, services, and the communication networks used by these devices. 2G and 2.5G networks, such as GPRS and EDGE, provide high network service coverage and moderate bandwidth for many users of electronic devices. In a GPRS network, system capacity is limited by frequency reuse due to common-mode interference (CCI). To further increase spectral efficiency, high-order modulation, such as 8-phase-shift keying (8PSK), has been implemented in 2G and 2.5G systems, where three bits are transmitted in each phase shift.The introduction of high-order modulation increases the complexity of receivers that utilize maximum likelihood sequence estimation (MLSE). Methods and devices that reduce the complexity of MLSE-based receivers for 8 PSK modulation systems can lower the cost and power consumption of electronic devices while increasing their network performance.

[0004] US 2006 / 0203943A1 describes a novel and useful device and method for single-antenna interference suppression (SAIC) in a wireless communication system. It describes a class of algorithms for downlink Advanced Receiver Performance (DARP) receivers, based on a novel metric calculation used during equalization and optionally in other parts of the receiver, such as soft-value generation. A DARP receiver for 8PSK edge modulation is presented, where the interfering signals include GMSK-modulated signals. According to the invention, the modified metric is adapted to account for the rotation remaining in the noise component of the received signal after derotation of the 8PSK signal. Assuming the interfering signal is a GMSK signal, the I / Q elements of the noise are correlated.This fact is used to modify the decision rule for the received signal, thereby improving the equalizer's performance. The model is further extended to account for the temporal error correlation.

[0005] US 2008 / 0279270A1 provides an equalizer processing module designed to suppress interference associated with received radio frequency (RF) bursts. This equalizer processing module comprises a first equalizer processing branch and an optional second equalizer processing branch. The first equalizer processing branch can be trained using a recursive DMI process, such as a Levison algorithm, based on known training sequences, and equalizes the received RF burst. This results in soft samples, or decisions, which can then be converted into data bits. The soft samples are processed by a deinterleaver and a channel decoder, the combination of which is capable of generating a decoded frame of data bits from the soft samples. This allows for the suppression of interference and more accurate processing of the received RF bursts. SUMMARY

[0006] One aspect of the present disclosure provides for a phase-rotated modification of a conventional MLSE receiver for 8 PSK modulation with single antenna interference cancellation (SAIC) processing and a method for reducing the complexity of an MLSE receiver, such as reduced branch sequence estimation (RBSE) and reduced state sequence estimation (RSSE).

[0007] According to one aspect of the present disclosure, a method is provided which involves receiving, by user equipment, a phase-shift keying (PSK)-modulated signal from a transceiver, unwinding the PSK-modulated signal, and matching the PSK-modulated signal using a maximum likelihood sequence estimator (MLSE) based on a first main tap gain (MTG) lookup table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even-numbered time samples, and a second MTG LUT and a second ISI LUT corresponding to odd-numbered time samples.

[0008] According to another aspect of the present disclosure, a device is provided which has a processor and a receiver, configured to receive a phase-shift keying (PSK) modulated signal from a transceiver, to untwist the PSK-modulated signal, to feed the PSK-modulated signal to a maximum likelihood sequence estimation (MLSE) equalizer, wherein the MLSE equalizer has a first main tap gain (MTG) lookup table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even-numbered time samples, and a second MTG LUT and a second ISI LUT corresponding to odd-numbered time samples.

[0009] According to another aspect of the present disclosure, a method for manufacturing a processor is provided, which includes forming the processor as part of a wafer or package which includes at least one other processor, wherein the processor is configured to receive a phase-shift keying (PSK) modulated signal from the transceiver by means of user equipment (UE), to de-encode the PSK modulated signal in order to form a virtual inter-symbol interference channel by means of mono interference cancellation (MIC) and branch combining (BRC) processing.to feed the PSK-modulated signal to a phase-shifted maximum likelihood sequence estimation (MLSE) equalizer, wherein the MLSE equalizer has a first main tap gain (MTG) lookup table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even-numbered time samples, and a second MTG LUT and a second ISI LUT corresponding to odd-numbered time samples, to reduce one branching sequence estimation and one state sequence estimation in the MLSE equalizer, and to determine a soft symbol based on one of the branching-reduced sequence estimations and one of the state-reduced sequence estimations in the MLSE equalizer.

[0010] According to another aspect of the present disclosure, a method for constructing an integrated circuit is provided, which includes generating a mask layout for a set of features for a layer of the integrated circuit, wherein the mask layout includes standard cell library macros for one or more circuit features, which include a processor configured to receive a phase-shift keying (PSK) modulated signal from the transceiver via user equipment (UE), to de-encode the PSK modulated signal, and to form a virtual inter-symbol interference channel by means of mono interference cancellation (MIC) and branch combining (BRC) processing.to feed the PSK-modulated signal to a phase-shifted maximum likelihood sequence estimation (MLSE) equalizer, wherein the MLSE equalizer has a first main tap gain (MTG) lookup table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even-numbered time samples, and a second MTG LUT and a second ISI LUT corresponding to odd-numbered time samples, to reduce one branching sequence estimation and one state sequence estimation in the MLSE equalizer, and to determine a soft symbol based on one of the branching-reduced sequence estimations and one of the state-reduced sequence estimations in the MLSE equalizer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will become clearer from the following detailed description when taken together with the accompanying drawings, in which: Fig. 1 a block diagram of an electronic device in a communication network according to an embodiment of the present disclosure; Fig. 2 is a block diagram of a wireless receiver which implements a maximum probability sequence estimation (MLSE) for an 8 PSK modulation with SAIC processing according to an embodiment of the present disclosure; Fig. 3 a block diagram of a soft-output MLSE equalizer according to an embodiment of the present disclosure is illustrated; Fig. 4 illustrates a detailed block diagram of an 8 PSK soft-output MLSE equalizer according to an embodiment of the present disclosure; Fig. 5 a trellis diagram for a branch-reduced sequence estimation (RBSE) of a signal with 8 PSK modulation and a channel length Q d = 2 illustrated according to one embodiment of the present disclosure. Fig. 6 illustrates a trellis diagram of symbol partitions of an 8 PSK signal according to an embodiment of the present disclosure; Fig. 7 A diagram of a modified trellis using a state-reduced sequence estimation (RSSE) for 8 PSK and a channel length Q d = 2 illustrated according to one embodiment of the present disclosure; Fig. 8 a flowchart of a method for determining a soft symbol based on an RBSE or RSSE in an MLSE equalizer according to an embodiment of the present disclosure; Fig. 9 a flowchart of a method for testing a processor configured to determine a soft symbol based on an RBSE or an RSSE in an MLSE equalizer according to an embodiment of the present disclosure; and Fig. 10 a flowchart of a method for manufacturing a processor which is configured to determine a soft symbol based on an RBSE or an RSSE in an MLSE equalizer according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The present disclosure will now be described in more full below with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. However, this disclosure can be implemented in many different forms and should not be considered limited to the embodiments described herein. Rather, these embodiments are intended so that this disclosure will be conscientious and complete and will fully convey the scope of the device and the method to those skilled in the art. Similar reference numerals refer throughout to similar elements.

[0013] It will be understood that when an element is referred to as "connected" or "coupled" with another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" with another element, no intermediate elements are present. As used herein, the term includes "and / or" but is not limited to any and all combinations of one or more of the associated listed items.

[0014] It will be understood that, although the terms “first,” “second,” and other terms may be used herein to describe different elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first signal may be referred to as a second signal, and similarly, a second signal may be referred to as a first signal, without deviating from the teachings of Revelation.

[0015] The terminology used herein is solely for the purpose of describing specific embodiments and is not intended to limit the present device and method. When used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, it shall be understood that the terms "has" and / or "includes, but is not limited to" and / or "including, but not limited to," when used in this description, specify the presence of said features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or groups thereof.

[0016] Unless otherwise defined, all terms (including, but not limited to, technical and scientific terms) used herein have the same meanings as generally understood by a person skilled in the art to whose field the present apparatus and method belong. Furthermore, it shall be understood that terms such as those defined in conventionally used dictionaries are to be interpreted as having meanings consistent with their meaning in the context of the relevant field and / or the present description, and not in an idealized or overly formal sense, unless expressly defined so herein.

[0017] Fig. Figure 1 is a block diagram of an electronic device in a network environment according to an embodiment of the present disclosure.

[0018] Referring to Fig. 1 comprises an electronic device 100, but is not limited to a communication block 110, a processor 120, a memory 130, a display 150, an input / output block 160, an audio block 170 and a GPRS / EDGE transceiver 180. The GPRS / EDGE transceiver 180 may be included in a mobile phone base station and comprises, but is not limited to, a wireless transmitter and receiver.

[0019] The electronic device 100 has a communication block 110 for connecting the device 100 to another electronic device or network for communication of voice and data.Communication block 110 provides for GPRS, EDGE, mobile phone, wide-area, short-area, personal area, near-field, device-to-device (D2D), machine-to-machine (M2M), satellite, enhanced mobile broadband (eMBB), massive machine type communication (MMTC), ultra-reliable low latency communication (URLLC), narrowband Internet of Things (NB-IoT), and short-range communications. The functions of the communication block 110 or part thereof, including a transceiver 113, may be implemented by a chipset.In particular, mobile communication block 112 provides for a wide area network connection via terrestrial base transceiver stations or directly to other electronic devices using technologies such as second generation (2G), GPRS, EDGE, D2D, M2M, Long Term Evolution (LTE), fifth generation (5G), Long Term Evolution Advanced (LTEA), code division multiple access (CDMA), wideband code division multiple access (WCDMA), Universal Mobile Telecommunications System (UMTS), Wireless Broadband (WiBro), and Global System for Mobile Communication (GSM). Mobile communication block 112 includes, but is not limited to, a chipset and transceiver 113. Transceiver 113 includes, but is not limited to, a transmitter and a receiver.Wireless Fidelity (WiFi) communication block 114 provides a local area network connection through network access points using technologies such as IEEE 802.11. Bluetooth communication block 116 provides personal-area direct and network communications using technologies such as IEEE 802.15. Near-field communication (NFC) block 118 provides short-range point-to-point communications using standards such as ISO / IEC 14443. Communication block 110 also includes a GNSS receiver 119. The GNSS receiver 119 can support receiving signals from a satellite transmitter.

[0020] The electronic device 100 can receive electrical power to operate the functional blocks from a power supply comprising, but not limited to, a battery. The GPRS / EDGE transceiver 180 can be part of a terrestrial base transceiver station (BTS) (such as a mobile phone base station) and comprise a radio frequency transmitter and receiver that complies with Third Generation Partnership Project (3GPP) standards. The GPRS / EDGE transceiver 180 can provide data and voice communication services for users of a mobile user equipment (UE). In this disclosure, the term "UE" can be used interchangeably with the term "electronic device".

[0021] The processor 120 provides application-layer processing functions required by the user of the electronic device 100. The processor 120 also provides instruction and control functionality for the various blocks within the electronic device 100. The processor 120 provides update control functions required by the functional blocks. The processor 120 can coordinate resources required by the transceiver 113, including, but not limited to, communication control between the functional blocks. The processor 120 can also update the firmware, databases, lookup tables, calibration procedures, and libraries associated with the mobile communication block 112.The mobile communication block 112 may also have a local processor or chipset which dedicates computing resources to the mobile communication block 112 and other functional blocks, such as MLSE receivers for mobile communication.

[0022] Memory 130 provides storage for device control program code, user data, application code, and data. Memory 130 can also include data storage for the firmware, libraries, databases, lookup tables, algorithms, procedures, MLSE parameters, and calibration data required by the mobile communication block 112. The program code and databases required by the mobile communication block 112 can be loaded from memory 130 into local memory within the mobile communication block 112 during device boot. The mobile communication block 112 can also have local, volatile, and non-volatile memory for storing program code, libraries, databases, calibration data, and lookup table data.

[0023] The display 150 can be a touch panel and can be implemented as a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, an active matrix OLED (AMOLED) display, and the like. The input / output block 160 controls the interface to the user of the electronic device 100. The audio block 170 provides audio input and output to / from the electronic device 100.

[0024] The GPRS / EDGE transceiver 180 can be contained in a base station, which is used to receive, transmit, or forward wireless signals. The GPRS / EDGE transceiver 180 can facilitate communication with the electronic device 100 by sending, receiving, and forwarding data communication signals to and from the electronic device 100. The electronic device 100 can be connected to a network via the GPRS / EDGE transceiver 180. For example, the GPRS / EDGE transceiver 180 can be a cell tower, a wireless router, an antenna, multiple antennas, or a combination thereof, which is used to send signals to or receive signals from the electronic device 100, such as a smartphone.The GPRS / EDGE transceiver 180 can relay wireless signals across the network to enable communication with other electronic devices, such as user equipment (UE), servers, or combinations thereof. The GPRS / EDGE transceiver 180 can be used to transmit communication signals such as voice or data.

[0025] According to one embodiment of the present disclosure, a method and an apparatus for a phase-shifted MLSE modification of an 8-phase-shift keying (PSK) modulation receiver with single-antenna interference cancellation (SAIC) processing are provided. In particular, the method and the apparatus provide a low-complexity implementation of a phase-shifted MLSE that uses a branch-reduced state-reduced MLSE with a soft-output metric / soft decision and a log-likelihood ratio (LLR) process.

[0026] Fig. Figure 2 is a block diagram of a wireless receiver which implements a maximum probability sequence estimate (MLSE) for 8 PSK modulation with SAIC processing according to an embodiment of the present disclosure.

[0027] According to one embodiment of the present disclosure, the present system and method provide an MLSE implementation for 8 PSK modulation with SAIC processing, as described in Fig. 2 is shown. Referring to Fig. 2. The front-end receiver module 200 can include a surface acoustic wave (SAW) filter, which provides a narrow-pass filter for incoming RF signals, a low-noise amplifier (LNA) to amplify the incoming low-power RF signal without significantly degrading its signal-to-noise ratio, a duplexer, a switch, and an impedance matching component. The Gaussian minimum shift keying (GMSK) de-rotation module 202 operates on an incoming GMSK signal from the front-end receiver module 200 to perform a de-rotation of pi / 2 per symbol in the GMSK signal.The MIC BRC module 204 provides mono interference cancellation (MIC = mono interference cancellation) and branch combinations (BRC). The 8 PSK soft-output MLSE equalizer module 206 provides a low-complexity implementation of a phase-inverted MLSE equalizer using a branch-reduced or state-reduced MLSE with soft output / soft decision and a log-probability ratio (LLR) saturation process. The burst combiner / denesetter module 208 combines the soft bits received from the 8 PSK soft-output / MLSE equalizer module 206 and denes the combined soft bits.The Viterbi decoder and CRC module 210 uses a Viterbi algorithm to process the bits received from the burst combiner / deboxer module 208. The cyclic redundancy check (CRC) provides error checking by calculating a cyclic code on the decoded bits and comparing the resulting check value with the transmitted check value to determine errors in the data transmission.

[0028] A signal model of an 8 PSK-modulated signal with GMSK interference and channel length L+1 can be represented by equation (1) as follows: r˜[t]=∑l=0Lh˜[l]a[t−l]ejϕ(t−l)+∑m=0Lg˜[m]b[t−m]ejθ(t−m)+w˜[t]︸n˜[t] where a[t] is an 8 PSK-modulated signal with a phase shift of ϕ=3π8 is, and b[t]a GMSK-modulated signal with a phase shift of θ=π2 h̃[l] is the channel which is perceived or experienced by the 8 PSK-modulated signal, g̃[m] is the channel which is experienced by the GMSK interference signal, and w̃[t] is the additive white Gaussian noise (AWGN=Additive White Gaussian Noise=Additives weißes Gausssche Lärm).

[0029] A signal model of an 8 PSK-modulated signal with GMSK interference in a receiver that uses single-antenna interference cancellation (SAIC) with a phase unrotation of θ=−π2 The process can be represented by equation (2) as follows: r[t]=r˜[t]e−jθt=∑l=0Lh˜[l]e−jθla[t−l]ej(ϕ−θ)(t−l)+∑m=0Lg˜[m]e−jθ mb[t−m]+w˜[t]e−jθtr[t]=∑l=0Lh[l]a˜[t−l]+∑m=0Lg[m]b[t−m]+w[t]︸n[t] where ã[t] = a[t]e j(ϕ-θ)t , h[l] = h̃[l]e -jθl , g[m] = g̃[m]e -jθm , b[t] a GMSK-modulated signal with a phase shift of θ=π2 is and w[t] = w̃[t]e -jθt

[0030] Based on an algebraic manipulation, equation (2) can be rewritten for both in-phase and quadrature (I and Q) signals and represented by equation (3) as follows: [rI[t]rQ[t]]=Re{ej(ϕ−θ)t∑l=0Lh˜c[l]a[t−1]}+[nI[t]nQ[t]]where h˜c[l]=[(hI[l]hQ[l])+j(hQ[l]−hI[l])]e−j(ϕ−θ)(l).

[0031] A similar expression to equation (3) above can be obtained using SAIC processing and represented by equation (4) as follows: yT[t]=Pr[t]=∑l=0QdHres[l][a˜I[t−l]a˜Q[t−l]]+eT[t]=Re{ej(ϕ−θ)t∑l=0Qdh˜res,c[l]a[t−l]}+eT[t]

[0032] The balancing procedure, which uses a maximum probability sequence estimation (MLSE) method, determines the sequence of symbols most likely transmitted by GPRS / EDGE transceiver 180. The goal of the sequence estimation is to find the sequence that minimizes the function defined in equation (5) below, or an MLSE estimate of the function defined in equation (5) below: a^[t]=argmina∑t‖y[t]−Re{ej(ϕ−θ)t∑l=0Qdh˜c[l]a[t−l]}‖2where ϕ=3π8,θ=π2.

[0033] Equation (5) can be rewritten by expanding y[t] = [y1[t], ..., y B [t]] T and h̃ c [l] = [h̃ c,1 [l], ..., h̃ c,B [l]] T , where B is the number of virtual inter-symbol interference (ISI) channels, and b is the virtual channel index (b=1, ... B), and can be represented by equation (6) as follows: a^[t]=argmina∑t∑b=1B|yb[t]−Re{ej(ϕ−θ)t∑l=0Qdh˜c,b[l]a[t−l]}|2

[0034] The equation (6) above requires a time-varying trellis state due to e j(ϕ-θ)t In an MLSE implementation, a channel estimate is performed first. After performing the channel estimate, the estimated channel is assumed to be fixed for the entire burst, and a Viterbi algorithm finds the sequence a[t] that minimizes the following: argmina∑t|r[t]−∑l=0Lh[l]a[t−l]|2 where r[l] is the received signal, h[l] is the estimated channel, and a[tl] is the transmitted sequence. Equation (6) is equivalent to a^[t]=argmina∑t∑b=1B|yb[t]−Re{∑l=0Qdh˜c,b[l]a'[t−l]}|2, where a'[t- l] = e j(ϕ-θ)t a[tl], h̃ c,b [l] is obtained from the channel estimation and is assumed to be fixed throughout the entire burst. The effect of e j(ϕ-θ)tApplying the transmitted signal is equivalent to solving the time-varying trellis state, since a'[tl] represents the state of the trellis and is time-varying according to a'[t- l] = e j(ϕ-θ)t a[tl] is.

[0035] Fig. Figure 3 illustrates a block diagram of an 8 PSK soft-output MLSE equalizer according to an embodiment of the present disclosure.

[0036] Referring to Fig. 3 is the input Yb(t) 302, a branch of the received signal generated by a combination of mono interference cancellation and branching. In SAIC processing, B branches of parallel or independent channels are formed by whitening the received signal. The number of branches is a design parameter that trades computational complexity for receiver performance. In one embodiment of the present disclosure, it is assumed that MIC-BRC has been performed and y1[t], ..., y B [t] 302 were calculated from the MIC-BRC processing, the input t 304 provides a time selection control signal for the 8 PSK soft output MLSE equalizer 300, the input {h˜c,b[l]}l=02d 306 is obtained from the MIC-BRC processing. The output a(t)308 represents an 8-PSK configuration, which represents the symbols of highest probability, and the output L(a(t))310 measures the reliability of the captured bits a(t)308. The larger the amplitude of L(a(t))310, the more reliable the decision a(t)308. An L(a(t))310 that is close to zero indicates poor reliability of the decision a(t)308.

[0037] Fig. Figure 4 illustrates a detailed block diagram of an 8 PSK soft-output MLSE equalizer according to an embodiment of the present disclosure.

[0038] According to one embodiment of the present disclosure, the present system provides a lookup table (LUT)-based implementation of a modified MLSE for 8 PSK modulation with SAIC processing. Referring to Fig. Input t304 is a control signal used to select between even-numbered Main Tap Gain (MTG) LUT 402 values, even-numbered Inter-Symbol Interference (ISI) LUT 404 values, odd-numbered MTG LUT 406 values, and odd-numbered ISI LUT 408 values. The control signal t304 also determines the correct state indices as calculated in the State Calculation Module 400 and provides a timing signal for the Soft Viterbi Algorithm (VA) Module 414. The State Calculation Module 400 calculates the time-varying state by untwisting the input state by a multiple of π4. The multiplicity of π4 Unrotation is time-dependent. The Soft-VA module 414 executes a Soft-Viterbi algorithm. The Viterbi algorithm finds the most probable sequence of symbols (the Viterbi path) that leads to a sequence of symbols. Since ϕ−θ=−π8 and a[t] an 8 PSK constellation in the form of ejπ4I[t] In this case, no time-varying complex multiplication actually needs to be performed, since the state calculation module 400 will calculate the correct untwisting accordingly. The present system can generate two sets of LUTs, the first set corresponding to even-numbered time sampling and the second set corresponding to odd-numbered time sampling. The even-numbered Main Tap Gain (MTG) lookup table (LUT) 402 determines the gain allocated to the MTG multiplexor (MUX) 410 for the even-numbered time samples, and the odd-numbered Main Tap Gain (MTG) lookup table (MTG) 406 determines the gain allocated to the MTG multiplexor (MUX) 410 for the odd-numbered time samples.The even-numbered Inter-Symbol Interference (ISI) lookup table (LUT) 404 determines the stored values ​​allocated to the ISI MUX 412 for the even-numbered time samples, and the odd-numbered ISI LUT 408 determines the stored values ​​allocated to the ISI MUX 412 for the odd-numbered time samples. The MTG values ​​for the even-numbered time samples can be represented by equation (7) below, and the MTG values ​​for the odd-numbered time samples can be represented by equation (8) below. The ISI values ​​for the even-numbered time samples can be represented by equation (9) below, and the ISI values ​​for the odd-numbered time samples can be represented by equation (10) below, as follows: MTGe(b,I[t])=Re{h˜c,b[0]ej(π4)I[t]} MTGo(b,I[t])=Re{e−π8h˜c,b[0]ej(π4)I[t]} ISIe(b,(I[t−1],…,I[t−Qd]))=Re{∑l=1Qdh˜c,b[l]ej(π4)I[t−l]} ISIo(b,(I[t−1],…,I[t−Qd]))=Re{e−jπ8∑l=1Qdh˜c,b[l]ej(π4)I[t−l]}

[0039] The odd-numbered tables are, compared to the even-numbered tables, by π8 Untwisted.

[0040] Inter-symbol interference can also be represented by equation (11) below, taking into account that e−jπ4nej(π4)I[t] Another 8 PSK symbol is: Re{e−jπBt∑l=0Qdh˜c,b[l]ej(π4)I[t−l]}={Re{∑l=1Qdh˜c,b[l](e−jπ4nej(π4)I[t−l])}t is evenRe{e−jπB∑l=1Qdh˜c,b[l](e−jπ4nej(π4)I[t−l])}t is odd (t is even = t is even, t is odd = t is odd) where n=⌊t2⌋.

[0041] An example of the equivalence path metric (PM) update for an even / odd time-sampling process in the tuple of state forms for Q d = 2, can be represented by equation (12) as follows: PM(I[t],I[t−1])={minJ[t−2]=[0,…7]{PM(I[t−1],I[t−2])+∑b=1B|yb[t]−MTGo(b,m(I[t],n))−ISIo(b,(m(I[t−1],n),m(I[t−2],n)))|2}t is evenminJ[t−2]=[0,…7]{PM(I[t−1],I[t−2])+∑b=1B|yb[t]−MTGo(b,m(I[t],n))−ISIo(b,(m(I[t−1],n),m(I[t−2],n)))|2}t is odd (t is even = t is even, t is odd = t is odd) where m(a,Δ−Δ,8).

[0042] A tuple of states is a concatenation of a series of states. For example, a tuple of the current state and of preceding states for Q is given by d = 2 is represented as (I[t], I[t - 1]). Similarly, for Q d = 3 represents the tuple of states as (I[t], I[t - 1], I[t - 2]). The tuple representation can also be represented by a linear index as in equation (13).

[0043] Similarly, the path metric (PM) update for even / odd time sampling processing can be represented in a linear index by equation (13) as follows: PM(J[t])={minJ[t−1]{PM(J[t−1])+∑b=1B|yb[t]−MTGe(b,I[t])−ISIe(b,J[t−1])|2} t is evenminJ[t−1]{PM(J[t−1])+∑b=1B|yb[t]−MTGo(b,I[t])−ISIo(b,J[t−1])|2} t is odd (t is even = t is even, t is odd = t is odd)

[0044] The relationship between J[t], I[t], and J[t - 1] can be represented by equations (14) and (15) as follows: I[t]=m(⌊J[t]8⌋,n) J[t−1]={8×m(m(J[t],0),n)+m(k,n),k=0,...7}

[0045] By using odd-numbered and even-numbered time-sampling processing, the present system only requires a correct mapping of the indices of the MTG / ISI LUTs, as shown in equations (14) and (15) above, without recalculating the phase-shifted versions of the LUTs for each example.

[0046] The LUTs only need to be updated with new values ​​whenever the channel estimation is performed and the channel state information is updated.

[0047] According to one embodiment of the present disclosure, the present system RBSE provides to reduce the number of branch metric calculations in the soft VA module 414, thereby reducing the add-compare-select (ACS) operations by dynamically selecting 2 out of the 8 branches that go to each state.

[0048] Fig. Figure 5 illustrates a trellis diagram for RBSE of a signal with 8 PSK modulation and a multipath channel length Q. u = 2 according to one embodiment of the present disclosure.

[0049] Referring to Fig. 5 dynamically selects 2 branches from the 8 available, as illustrated in Trellis Diagram 500. Only two branches can lead to the next state from the preceding state. The branches leading to each next state are determined as follows: - Step 1: Select two candidate states to be evaluated (chosen from previous states). Initially, the candidates can be selected as Ĩ[t - 2] ∈ {0,4}; for the next iteration, candidates are selected according to equation (19) below. - Step 2: For each state, the system determines two branching metrics based on the two candidate states. - Step 3: An implementation with reduced complexity of the LUTs (tuple-of-state representation) in accordance with an embodiment of the present disclosure can be represented by equation (17) as follows: PM(I[t],I[t−1])={minI[t−2]∈{0,4}{PM(I[t−1],I[t−2])+∑b=1B|yb[t]−MTGe(b,m(I[t],n))−ISIe(b,(m(I[t−1],n),m(I[t−2],n)))|2} t is evenminJ[t−2]∈{0,4} {PM(I[t−1],I[t−2])+∑b=1B|yb[t]−MTGo(b,m(I[t],n))−ISIo(b,(m(I[t−1],n),m(I[t−2],n)))|2} t is odd (t is even = t is even, t is odd = t is odd) - Step 4: From the current path metric PM ((0,0), ... PM ((7,7)), the present system selects the following two candidate states from each state to be evaluated, based on equation (18) as follows: I˜[t−1](I[t])={argminI[t−1]∈{0,2,4,6}PM(I[t],I[t−1]),argminI[t−1]∈{1,3,5,7}PM(I[t],I[t−1])} - Step 5: Based on the evaluation of equation (18) above, the current system determines two candidates for a fixed I[t] (which has a cardinality of eight). This set of two candidates (16 total candidates) is replicated to all states based on equation (19) as follows: I˜{t−1}((I[t+1]=0,I[t]))=I˜[t−1](([t−1])=1,I[t]))=⋯=I˜[t−1]((I[t+1]=7,I[t])) - Step 6: The current system increments t = t + 1 as t increases; Ĩ[t - 1] becomes Ĩ[t - 2]. Repeat STEP 2 through STEP 6 until there are no more bits to process.

[0050] The soft VA module 414, which produces a soft output indicating the reliability of the generation, takes into account the preceding probabilities of the input symbols. The soft decision made in the RBSE of each bit corresponds to the symbol and is calculated based on equation (20) as follows: Li(bi[t−Δ])=minI[t],I[t−1]|bi[t−Δ]=0(PM(I[t],I[t−1]))−minI[t],I[t−1]|bi[t−Δ]=0(PM(I[t],I[t−1]))

[0051] In the RBSE, the decision delay is selected to ensure that Δ = 1. Additionally, the RBSE performs LLR saturation based on an average absolute value of the soft decision T, which improves the overall performance as implemented by equation (21) as follows: L˜i(bi[t])=max{Li(bi[t]),1.5T}

[0052] The average absolute value of the soft decision is calculated based on equation (22) as follows: T=E[|Li(bi[t])|]

[0053] According to one embodiment of the present disclosure, the present system provides RSSE with both naive and low-complexity LUT implementations. The partitioning of the symbol is based on Ungerboeck's set partitioning method, which is used in Trellis-coded modulation (TCM). In partition P = [P1, P2], the present system divides the current symbols and the preceding symbols into P1 and P2 partitions, respectively. In other words, I[t] is divided into eight sets (which are the same as the original 8 PSK signal), and I[t - 1] is divided into two sets, namely {[0,2,4,6], [1,3,5,7]}.

[0054] Fig. Figure 6 illustrates a trellis diagram of symbol partitions of an 8 PSK signal according to an embodiment of the present disclosure.

[0055] Referring to Fig. Figure 6 shows the trellis diagram, illustrating how the eight symbols of an 8 PSK signal are partitioned into disjoint residue classes or cosets such that the shortest Euclidean distances increase on each level of the trellis. There are four partitioned levels, which contain the first unpartitioned set. On the first level, 600, which has eight points, the Euclidean distance can be represented by equation (23) as follows: d0=√(2−2)Es

[0056] At the next level down from the first level 600, the second level 602 has four points in each of the two cosets and the Euclidean distance between the points has increased and can be represented by equation (24) as follows: d1=√2Es

[0057] On the next level down from the second level 602, the last level 604 has two points in each of the four cosets and the Euclidean distance between the points has increased and can be represented by equation (25) as follows: d2=2√Es

[0058] Due to the partitioning of the symbols, there is no longer a full trellis. According to one embodiment of the present disclosure, a modified trellis (sub-trellis) is formed in Fig. 7 for a partition of P=[8,2], and where the multipath channel length Q_d=2.

[0059] Fig. Figure 7 illustrates a diagram of a modified trellis (sub-trellis) using RSSE for 8 PSK according to an embodiment of the present disclosure.

[0060] Referring to Fig. Figure 7 illustrates the modified trellis diagram 700, which defines the branching metric (BM), a measure of the Euclidean distance between the transmitted symbol and the received symbol, for each arc in the trellis, modified for partition P = [8,2] using tuples of states and which can be represented by equation (26) as follows: PM(I[t],I[t−1])=minI[t−1]∈{0,2,4,6},I[t−2]∈{[0,2,4,6],[1,3,5,7]}{PM(I[t−1],I[t−2]∑b=1B|yb[t]−MTGt(mod 16)(b,I[t])−ISIt(mod 16)(b,(I[t−1],I^[t−2]))|2} where I[t]∈{0,…7},I[t−1]∈{0,…7},I[t−2]∈{[0,2,4,6],[1,3,5,7]}.

[0061] Similarly, equation (26) above can be implemented with LUT's reduced complexity and can be represented by equation (27) as follows: PM(I[t],I[t−1])={mini[t−1]∈{0,2,4,6},I[t−2]∈{[0,2,4,6],[1,3,5,7]}{PM(I[t−1],I[t−2])+∑b=1B|yb[t]−MTGe(b,m(I[t],n))−ISIe(b,(m(I[t−1],n),m(I^[t−2],n)))|2}t is evenmini[t−1]∈{0,2,4,6},I[t−2]∈{[0,2,4,6],[1,3,5,7]}{PM(I[t−1],I[t−2])+∑b=1B|yb[t]−MTGo(b,m(I[t],n))−ISIo(b,(m(I[t−1],n),m(I^[t−2],n)))|2}t is odd (t is even = t ist geradzahlig, t is odd = t ist ungeradzahlig)

[0062] Die Soft-Output-Ergebnisse des Soft-VA-Moduls 414 können unter Verwendung von Gleichung (28) wie folgt berechnet werden: Li(bi[t−Δ])=minst,st−1|bi[t−Δ]=0(STM(st,st−1))−minst,st−1|bi[t−Δ]=1(STM(st,st−1)) Li(bi[t−Δ])=minI[t],I[t−2],I[t−1]|bi[t−Δ]=0(STM(I[t],I[t−1],I[t−2]))−minI[t],I[t−2],I[t−1]|bi[t−Δ]=1(STM(I[t],I[t−1],I[t−2])) wobei die folgende Notation vereinfacht ist: STM(st,st−1)=STM((I[t],I[t−1]),(I[t−1],I[t−2]))=STM(I[t],I[t−1],I[t−2]).

[0063] Intermediate variables, called a state transition metric (STM) and branching metric (BM), are defined. The STM and BM are updated with each forward recursion.

[0064] The case where P = [P1, P2] = [8,2] and I[t] = {0, ... 7} corresponds to the symbol for the time instance t, I[t - 1] = {0, ...,7}, and I[t - 2] ∈ {[0,2,4,6], [1,3,5,7]}. If P = [P1, P2], P1 = 8 is always selected, there is no ambiguity in determining L. i (b i [t - Δ]). In RSSE with different partitions, the current system uses Δ = 1. Additionally, LLR saturation based on the average absolute value of the soft decision, T, can also be performed according to equation (29) as follows: L˜i(bi[t])=max{Li(bi[t]),1.5T}

[0065] The average principal value of the soft decision can be calculated according to equation (30) as follows: T=E[|Li(bi[t])|]

[0066] Fig. Figure 8 is a flowchart of a method for determining a soft symbol based on a branch sequence estimation and a state sequence estimation in an MLSE equalizer according to an embodiment of the present disclosure.

[0067] Referring to the flowchart of the Fig. In section 801, the present system features a user equipment (UE) receiving a modulated phase-shift keying (PSK) signal from a transceiver. In section 802, the method features a GMSK unrotation process. In section 803, the method features the formation of B virtual symbol interference (ISI) channels through MIC-BRC processing. In section 804, the method features a phase-shifted MLSE process.

[0068] In 805, the procedure involves determining a soft symbol based on the branch sequence estimation and the state sequence estimation in the MLSE equalizer.

[0069] Fig. Figure 9 is a flowchart of a method for testing a processor configured to determine soft symbols according to an embodiment of the present disclosure, wherein the processor is either implemented in hardware or implemented in hardware programmed with software.

[0070] Referring to Fig. In section 901, the method forms the processor as part of a wafer or a package which includes at least one other processor. The processor is configured to receive a phase-shift keying (PSK) modulated signal from a transceiver via a user equipment (UE), to de-rotate the PSK modulated signal, to form a virtual inter-symbol interference channel using mono-interference cancellation (MIC) and branching combination (BRC) processing, and to feed the PSK modulated signal to a phase-inverted maximum probability sequence estimation (MLSE) equalizer, wherein the MLSE equalizer has a first main tap gain (MTG) lookup table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even time samples and a second MTG LUT and a second ISI LUT corresponding to odd time samples, to reduce the branching sequence estimation and state sequence estimation in the MLSE equalizer.and to determine a soft symbol based on one of the reduced branch sequence estimates and the reduced state sequence estimate in the MLSE equalizer. At 903, the procedure tests the processor. Testing the processor involves testing the processor and at least one other processor using one or more electrical-to-optical converters, one or more optical splitters which split or divide an optical signal into two or more optical signals, and one or more opto-electrical converters.

[0071] Fig. Figure 10 is a flowchart of a method for manufacturing a processor configured to determine soft symbols according to an embodiment of the present disclosure.

[0072] Referring to Fig.In section 10, the procedure at 1001 features an initial data layout in which the procedure generates a mask layout for a first set of features for a layer of an integrated circuit. The mask layout includes standard cell library macros for one or more circuit features that include a processor. The processor is configured to receive a phase-shift keying (PSK) modulated signal from a transceiver via a user equipment (UE), to de-rotate the PSK modulated signal, to form a virtual inter-symbol interference (IPI) channel using mono interference cancellation (MIC) and branch combining (BRC) processing, to feed the PSK modulated signal to a phase-shifted maximum probability sequence estimate (MLSE) equalizer, the MLSE equalizer providing a first main tap gain (MTG) lookup table (LUT) and a first inter-symbol interference (ISI) LUT.which correspond to even-numbered time samples, and has a second MTG LUT and a second ISI LUT, which correspond to odd-numbered time samples, to reduce a branch sequence estimate and a state sequence estimate in the MLSE equalizer, and to determine a soft symbol based on one of the branch-reduced sequence estimates and the state-reduced sequence estimate in the MLSE equalizer.

[0073] In version 1003, there is a design rule check in which the procedure rejects relative positions of macros for a match with layout design rules during the generation of the mask layout.

[0074] At 1005, there is an adjustment of the layout in which the procedure checks the relative positions of the macros for compliance with the layout design rules after the mask layout has been generated.

[0075] At 1007, a new layout design is created in which, upon detection of a non-conformity with the layout design rules by any of the macros, the process modifies the mask layout by modifying each of the non-conforming macros to conform to the layout design rules, creates a mask according to the modified mask layout with the set of features for the integrated circuit layer, and manufactures the integrated circuit layer according to the mask.

[0076] While the present disclosure has been shown and described in particular with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in the form and details therein may be made without departing from the idea and scope of the present disclosure as defined by the attached claims and their equivalents.

Claims

[1] Device (100) comprising the following: a processor (120); and a receiver that is configured to: to receive a phase-shift keying (PSK) modulated signal from a transceiver (113), to unwind the PSK-modulated signal, to feed the PSK-modulated signal to a maximum probability sequence estimation (MLSE) equalizer, wherein the MLSE equalizer has a first main tap gain lookup table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even time samples, and a second MTG LUT and a second ISI LUT corresponding to odd time samples. [2] Device (100) according to claim 1, wherein the receiver is further configured to: to reduce branching sequence estimation in the MLSE equalizer, or to reduce state sequence estimation in the MLSE equalizer, and to determine a soft symbol based on the branching sequence estimation or the state sequence estimation in the MLSE equalizer, wherein the MLSE reduces the state sequence estimation by partitioning candidate symbols according to a Euclidean distance between the symbols. [3] Device (100) according to claim 1, wherein the MLSE uses a log probability ratio saturation process. [4] Device (100) according to claim 1, wherein the MLSE modulates the PSK-modulated signal by an integer multiple of π4 = untwisted. [5] Device (100) according to claim 1, wherein the receiver has a single-antenna interference cancellation processing. [6] Device (100) according to claim 2, wherein the branching sequence estimation is reduced to two branches. [7] Device (100) according to claim 1, wherein the first MTG LUT, the first ISI LUT, the second MTG LUT and the second ISI LUT are updated with new values ​​when a channel estimation is performed and a channel state information is updated. [8] Device (100) according to claim 1, wherein the MLSE executes a soft Viterbi algorithm. [9] Device (100) according to claim 8, wherein the Soft-Viterbi algorithm receives Inter-Symbol Interference (ISI) time samples and Main Tap Gain (MTG) time samples through a multiplexer. [10] Method comprising the following: a receiving, by a user equipment (UE), of a phase-shift keying (PSK) modulated signal from a transceiver (113); an unwinding of the PSK-modulated signal; and a matching of the PSK-modulated signal using a Maximum Probability Sequence Estimator (MLSE) based on a first Main Tap Gain (MTG) lookup table (LUT) and a first Inter-Symbol Interference (ISI) LUT corresponding to even time samples, and a second MTG LUT and a second ISI LUT corresponding to odd time samples.

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