Optical power splitter with a multi-level arrangement and method for forming an optical power splitter
The optical power splitter design with a multimode interference region and vertically stacked waveguide cores addresses the issues of large footprint and high insertion loss, providing a compact and efficient optical power splitting solution.
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- GLOBALFOUNDRIES US INC
- Filing Date
- 2021-09-23
- Publication Date
- 2026-06-11
AI Technical Summary
Conventional optical power splitters and combiners have a large footprint and exhibit higher than desired insertion loss.
A structure for an optical power splitter is designed with a multimode interference region and multiple waveguide cores in different vertical levels, surrounded by dielectric layers, allowing for a compact footprint and reduced insertion loss.
The solution achieves a more compact form factor with lower insertion loss and reflection, enabling efficient optical power splitting and combining.
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Abstract
Description
BACKGROUND
[0001] The present invention relates to photonic chips and in particular structures for an optical power splitter and methods for forming a structure for an optical power splitter.
[0002] Photonic chips are used in many applications and systems, such as data communication and computing systems. A photonic chip integrates optical components, such as waveguides, optical switches, optical power splitters, and directional couplers, and electronic components, such as field-effect transistors, into a single platform. Integrating both types of components onto the same chip reduces layout space, costs, and operational overhead, among other factors.
[0003] An optical power splitter is an optical component used in photonic chips to divide optical power between multiple waveguides with a desired coupling ratio. The same structure can be used as an optical power combiner, which combines optical power received from multiple waveguides. Conventional optical power splitters / combiners tend to have a footprint that is larger than desired and may also exhibit higher than desired insertion loss.
[0004] From US 2015 / 0 260 918 A1 a monolithically formed multimode interference coupler is known, with a coupler plate and with a rib structure directly connected to the coupler plate.
[0005] Furthermore, US patent 10 429 581 B1 discloses a structure that has a multimode interference region comprising a first waveguide and a second waveguide stacked over the first waveguide.
[0006] Furthermore, a structure is known from US 2003 / 0 063 836 A1 in which photonic optical waveguide circuits are stacked vertically on top of each other.
[0007] Improved structures for an optical power splitter and methods for forming a structure for an optical power splitter are needed. BRIEF SUMMARY
[0008] In one embodiment of the invention, a structure for an optical power splitter is provided. The structure comprises a multimode interference region, a first dielectric layer over the multimode interference region, a first waveguide core on the first dielectric layer, wherein the first waveguide core includes a section positioned over the multimode interference region, a second waveguide core on the first dielectric layer, wherein the second waveguide core includes a section positioned over the multimode interference region, and a third waveguide core on the first dielectric layer, wherein the third waveguide core includes a section positioned over the multimode interference region.The first waveguide core provides an input connection to the optical power splitter, the second waveguide core provides a first output connection from the optical power splitter, and the third waveguide core provides a second output connection from the optical power splitter, wherein the multimode interference region is located in a first level, the first waveguide core, the second waveguide core, and the third waveguide core are located in a second level, the second level is positioned in a vertical direction within a different plane than the first level, and the first dielectric layer is positioned as a solid layer between the multimode interference region in the first level and the first waveguide core, the second waveguide core, and the third waveguide core in the second level.
[0009] In one embodiment of the invention, a method for forming a structure for an optical power splitter is provided. The method comprises forming a multimode interference region, forming a dielectric layer over the multimode interference region, forming a first waveguide core on the dielectric layer, wherein the first waveguide core comprises a section positioned over the multimode interference region, forming a second waveguide core on the dielectric layer, wherein the second waveguide core comprises a section positioned over the multimode interference region, and forming a third waveguide core on the dielectric layer, wherein the third waveguide core comprises a section positioned over the multimode interference region.The first waveguide core provides an input connection to the optical power splitter, the second waveguide core provides a first output connection from the optical power splitter, and the third waveguide core provides a second output connection from the optical power splitter, wherein the multimode interference region is located in a first level, the first waveguide core, the second waveguide core, and the third waveguide core are located in a second level, the second level is positioned in a vertical direction within a different plane than the first level, and the first dielectric layer is positioned as a solid layer between the multimode interference region in the first level and the first waveguide core, the second waveguide core, and the third waveguide core in the second level. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The accompanying drawings, which are incorporated into and form part of this description, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain these embodiments. In the drawings, the same reference numerals refer to the same features in the different views. Fig. Figure 1 is a top view of a structure in an initial manufacturing stage of a processing method according to embodiments of the invention. Fig. 2 is a cross-sectional view overall seen along line 2-2 in Fig. 1. Fig. Figure 3 is a top view of the structure at a manufacturing stage of the processing procedure following Fig. 1. Fig. Figure 4 is a cross-sectional view as seen along line 4-4 in Fig. 3. Fig. 4A is a cross-sectional view as seen along line 4A-4A in Fig. 3. Fig. 5, Fig. 5A are cross-sectional views of the structure at a manufacturing stage of the processing procedure following Fig. 4, Fig. 4A. Fig. Figures 6-10 are top views of structures according to alternative embodiments of the invention. DETAILED DESCRIPTION
[0011] With reference to Fig. 1, Fig. 2 and according to embodiments of the invention, a structure 10 for an optical multimode power splitter comprises a body or slab 12 positioned on an upper surface 11 of a dielectric layer 14. The slab 12 can define a multimode interference region of the structure 10 that enables optical power splitting. The slab 12 can be provided by a body having an outer perimeter that encloses a closed geometric shape. In one embodiment, the slab 12 can have a rectangular or substantially rectangular geometric shape. The slab 12 comprises opposing side surfaces 15, 17, and opposing side surfaces 16 connecting side surface 15 to side surface 17. The slab 12 can have a width dimension, W1, between the side surfaces 16.
[0012] The slab 12 can consist of a single-crystal semiconductor material, such as single-crystal silicon. In alternative embodiments, the slab 12 can consist of a different material. In one embodiment, the single-crystal semiconductor material can be formed from a fixture layer of a silicon-on-insulator (SOI) substrate, which further comprises a buried oxide layer providing the dielectric layer 14, and a handle substrate 13 consisting of a single-crystal semiconductor material, such as single-crystal silicon. The slab 12 can be patterned from the fixture layer by lithography and etching processes.The device layer can be fully etched to form the slab 12, or alternatively, only partially etched to define a thinned residual layer on the dielectric layer 14, and coupled to a lower section of the slab 12 only at the side surfaces 16. The slab 12 can have a lower surface that is coextensive with the upper surface 11 of the dielectric layer 14 and an opposing upper surface that is spaced vertically away from the lower surface.
[0013] With reference to Fig. 3, Fig. 4, Fig. 4A, in which the same reference sign refers to the same features in Fig. 1, Fig. 2 and in a subsequent manufacturing stage, a dielectric layer 18 is formed over the slab 12 and the dielectric layer 14. The dielectric layer 18 can consist of a dielectric material, such as silicon dioxide, deposited by chemical vapor deposition and planarized, for example, by chemical-mechanical polishing to remove topography. The slab 12 is surrounded by the dielectric material of the dielectric layer 18, which provides a cladding with a low refractive index. Additional dielectric layers 19, 20, 21 can be deposited in a layer stack over the dielectric layer 18. The dielectric layer 20 can consist of silicon nitride, and the dielectric layers 19, 21 can consist of silicon dioxide. In an alternative embodiment, the silicon nitride-containing dielectric layer 20 can be omitted from the layer stack.In one embodiment, the layer stack comprising the dielectric layers 19, 20, 21 can have a thickness that is less than or equal to 100 nanometers.
[0014] A waveguide core 22 and several waveguide cores 24 are formed on the dielectric layer 21. The waveguide cores 22, 24 can be formed by depositing a layer of the material of which they are composed on the dielectric layer 18 and structuring the deposited layer using lithography and etching processes. The deposited layer can be fully etched to define the waveguide cores 22, 24, as shown, or alternatively, only partially etched to define a thin residual layer on the dielectric layer 18 that is coupled to a lower section of the waveguide core 22, and another thin residual layer on the dielectric layer 18 that is coupled to a lower section of the waveguide cores 24.In one embodiment, the waveguide cores 22, 24 can be made of a material with a different composition than the material contained in the slab 12. In one embodiment, the waveguide cores 22, 24 can be made of silicon nitride. In alternative embodiments, the waveguide cores 22, 24 can be made of a different material. In one embodiment, the waveguide cores 22, 24 can have a thickness ranging from 50 nanometers to 500 nanometers.
[0015] The waveguide cores 22, 24 and the slab 12 are positioned in different layers or levels. Specifically, the waveguide cores 22, 24 are located in a level or layer that is positioned vertically within a plane different from the level or layer of the slab 12. The dielectric layers 19, 20, 21 are positioned as solid layers between the waveguide cores 22, 24 and the slab 12.
[0016] The waveguide core 22 can include a tapered section 40 extending over the underlying side surface 15 of the slab 12 and comprising a section 23 that overlaps with a portion of the multimode interference region defined by the slab 12. The tapered section 40 of the waveguide core 22 terminates at an end 26 that can be positioned above and over the slab 12. The section 23 of the tapered section 40 therefore overlaps with a portion of the multimode interference region defined by the slab 12. The overlap distance, d1, of the section 23 of the tapered section 40 with the slab 12 can be greater than or equal to the operating wavelength of the structure 10.
[0017] Each waveguide core 24 can include a tapered section 42 extending over the underlying side surface 17 of the slab 12 and comprising a section 25 that partially overlaps the slab 12. The tapered section 42 of each waveguide core 24 terminates at an end 28 that can be positioned above and over the slab 12. The section 25 of each tapered section 42 therefore overlaps with a portion of the multimode interference region defined by the slab 12. In each case, the overlap distance, d2, of the section 25 of the tapered section 42 with the slab 12 can also be greater than or equal to the operating wavelength of the structure 10.
[0018] The waveguide core 22 can provide an input connection to the multimode interference region of the structure 10. The waveguide cores 24, which can provide multiple output connections for the optical power split by the multimode interference region, are positioned adjacent to one another in a side-by-side, spaced-apart arrangement. In alternative embodiments, additional waveguide cores, similar to or identical with the waveguide core 22, can be provided as additional input connections. In alternative embodiments, additional waveguide cores, similar to or identical with the waveguide cores 24, can be provided as additional output connections.
[0019] The tapered section 40 of the waveguide core 22 tapers along a longitudinal axis 30 with a width dimension, W2, which decreases along its length with increasing distance from its termination end 26. The width dimension, W2, can have a maximum width at the end 26. The waveguide core 22 has opposite side walls 34, 35, which are spaced apart by the width dimension, W2, and which terminate at the end 26. The tapered section 42 of each waveguide core 24 tapers along a longitudinal axis 31 with a width dimension, W3, which decreases along its length with increasing distance from its respective termination end 28. The width dimension, W3, can have a maximum width at the end 28 of each section 25. Each waveguide core 24 has opposite side walls 36, 37, which are spaced apart by the width dimension, W3, and which terminate at the end 28.The width dimension, W1, of the slab 12 is larger than either the width dimension, W2, or the width dimension, W3.
[0020] In one embodiment, the longitudinal axes 31 can be aligned parallel or substantially parallel to each other, and the longitudinal axis 30 can be parallel or substantially parallel to the longitudinal axes 31. In one embodiment, the longitudinal axes 31 can be positioned symmetrically relative to the longitudinal axis 30. In one embodiment, the waveguide cores 24 can be positioned symmetrically relative to the waveguide core 22. In one embodiment, the waveguide cores 24 can be positioned symmetrically relative to the waveguide core 22, and the waveguide cores 22, 24 can be positioned symmetrically relative to the slab 12.
[0021] In one embodiment, the width dimension, W2, of the tapered section 40 and the width dimension, W3, of the tapered section 42 can vary based on a linear function. In an alternative embodiment, the width dimension, W2, of the tapered section 40 and / or the width dimension, W3, of the tapered section 42 can vary based on a non-linear function, such as a quadratic, parabolic, or exponential function.
[0022] Due to the heterogeneous layered configuration of structure 10, the optical power splitter can exhibit a more compact footprint compared to conventional optical power splitters. The multiple materials and / or multiple levels of structure 10 can promote a reduction in the optical power splitter's form factor. Multiple functions, namely coupling and interference, occur simultaneously within structure 10 during operation. The optical power splitter can be characterized by relatively low insertion loss and relatively low reflection, combined with its smaller form factor.
[0023] With reference to Fig. 5, Fig. 5A, in which the same reference sign refers to the same features in Fig. 4, Fig. 4A, and in a subsequent manufacturing stage, a dielectric layer 32 of a contact level is formed by middle-of-line processing over the waveguide cores 22, 24 and the dielectric layer 21. The dielectric layer 32 can consist of a dielectric material, such as silicon dioxide, deposited by chemical vapor deposition using ozone and tetraethyl orthosilicate (TEOS) as reactants.
[0024] A back-end-of-line stack 33 can be formed by back-end-of-line processing over the dielectric layer 32. The back-end-of-line stack 33 can comprise one or more interlayer dielectric layers consisting of one or more dielectric materials, such as silicon dioxide.
[0025] The structure 10, in any of its embodiments described herein, can be integrated into a photonic chip, which may include electronic components and additional optical components in addition to the slab 12 and the waveguide cores 22, 24. The electronic components may, for example, include field-effect transistors fabricated by CMOS processing using the device layer of the SOI substrate.
[0026] When used, laser light on the photonic chip can be guided through the waveguide core 22 from, for example, a fiber coupler or a laser coupler to the structure 10. The laser light is transferred in a distributed manner to the waveguide cores 24 through the multimode interference region defined by the slab 12. In particular, the optical power of the laser light is divided or split by the structure 10 into different fractions or percentages, which are transferred from the waveguide core 22 to the different waveguide cores 24. The optical power of the laser light can be split uniformly or substantially uniformly if the waveguide cores 24 are arranged symmetrically with respect to the waveguide core 22.Alternatively, the coupling ratio can be individually adjusted to differ from an equal or substantially equal split by asymmetrically arranging the waveguide cores 24 with respect to the waveguide core 22. The waveguide core 24 guides the split laser light separately away from the structure 10. The spacing between the waveguide cores 24 can increase downstream of the structure 10 to eliminate interaction and crosstalk. Alternatively, the structure 10 can be used to combine the optical power of laser light received by the waveguide core 24 for output through the waveguide core 22 to, for example, a photodetector or an optical modulator.
[0027] With reference to Fig. 6. According to alternative embodiments of the invention, the structure 10 can be modified such that the waveguide core 22 further comprises a straight section 38, which is positioned above and overlaps the slab 12 and is enclosed in section 23. The straight section 38 can be directly connected to the tapered section 40, and the straight section 38 can be aligned with the tapered section 40 along the longitudinal axis 30. In one embodiment, the straight section 38 can completely overlap the slab 12, and the tapered section 40 can only partially overlap the slab 12. The end 26, which terminates the waveguide core 22, is repositioned at the added straight section 38.
[0028] The structure 10 can further be modified such that each waveguide core 24 additionally comprises a straight section 44, which is positioned above and overlaps the slab 12 and is enclosed within the section 25. The straight section 44 can be directly connected to the tapered section 42, and the straight section 44 can be aligned with the tapered section 42 along the longitudinal axis 31. In one embodiment, the straight section 44 can completely overlap the slab 12, and the tapered section 42 can only partially overlap the slab 12. The end 28 that terminates each waveguide core 24 is repositioned at the added straight section 44.
[0029] With reference to Fig. 7 and according to alternative embodiments of the invention, the slab 12 can be modified to add a tapered section 46 projecting laterally from the side surface 15, and also to add tapered sections 48 projecting laterally from the side surface 17. The tapered section 46 can be positioned below the tapered section 40 of the waveguide core 22, and one of the tapered sections 48 can be positioned below the tapered section 42 of each waveguide core 24. The addition of the tapered section 46 to the slab 12 can serve to increase the overlap between the slab 12 and the tapered section 40 of the waveguide core 22, and therefore to increase the extent of the section 23.Similarly, the addition of the tapered sections 48 to the slab 12 can serve to increase the overlap between the slab 12 and the tapered section 42 of each waveguide core 24, and thus increase the extent of the section 25. The tapered sections 46, 48 can be tapered in the opposite direction to the tapering of the tapered sections 40, 42 and can have a narrower width than the tapered sections 40, 42.
[0030] With reference to Fig. 8 and according to alternative embodiments of the invention, the structure 10 can be modified to add the tapered sections 46, 48 to the slab 12, and the waveguide cores 22, 24 can be modified to include tapered sections 50, 52. The tapered sections 50, 52, which replace the tapered sections 40, 42, have a reverse taper relative to the tapered sections 40, 42. The slab 12 and tapered sections 46, 48 are shown diagrammatically in dashed lines in Fig. Figure 8 shows that the tapered section 46 can be positioned below and overlap the tapered section 50 of the waveguide core 22 to provide the overlapping section 23, and the tapered section 50 of the waveguide core 22 can terminate at or near the side surface 15 of the slab 12. Similarly, one of the tapered sections 48 can be positioned below and overlap the tapered section 52 of each waveguide core 24 to provide the overlapping section 25, and the reverse-tapered tapered section 52 of each waveguide core 24 can terminate at or near the side surface 17 of the slab 12.
[0031] With reference to Fig. 9 and according to alternative embodiments of the invention, the slab 12 can be modified to add a tapered section 54 projecting from the side surface 15 and a tapered section 56 projecting from the side surface 17. The tapered section 40 of the waveguide core 22 partially overlaps the tapered section 54 and is significantly narrower than the tapered section 54 to provide section 23. The tapered section 42 of one or more of the waveguide cores 24 partially overlaps the tapered section 56 to provide respective overlapping sections 25. In one embodiment, the tapered section 42 of more than one waveguide core 24 partially overlaps the tapered section 56.
[0032] With reference to Fig.10 and according to alternative embodiments of the invention, the structure 10 can be modified to add waveguide cores 58, 60, which provide additional input connections to the multimode interference region provided by the slab 12. Each of the added waveguide cores 58, 60 can be constructed substantially similarly to or identically with the waveguide core 22. The waveguide cores 22, 58, 60 can be positioned symmetrically on the side surface 15 and can also be positioned symmetrically relative to the waveguide cores 24.
[0033] The processes described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (that is, as a single wafer containing multiple unpackaged chips), as bare die chips, or in a packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either an intermediate or a final product. The final product can be any product that incorporates integrated circuit chips, such as computer products with a central processing unit or smartphones.
[0034] References herein to expressions modified by approximation language, such as "about," "approximately," and "essentially," are not to be limited to the specified precise value. The approximation language may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may be + / - 10% of the specified value(s).
[0035] References herein to terms such as "vertical," "horizontal," etc., are made for illustrative purposes only and not to limit or establish a frame of reference. The term "horizontal," as used herein, is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal, as just defined. The term "lateral" refers to a direction within the horizontal plane.
[0036] A feature "connected" or "coupled" to another feature can be directly connected or coupled to the other feature, or one or more intervening features can be present. A feature can be "directly connected" or "directly coupled" to another feature if no intervening features are present. A feature can be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. A feature "at" or "contacting" another feature can be directly at or in direct contact with the other feature, or one or more intervening features can be present. A feature can be "directly at" or in "direct contact" with another feature if no intervening features are present.A feature can be “indirectly related” or “indirect contact” with another feature if at least one intervening feature is present.
[0037] The descriptions of the various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations are obvious to those skilled in the art without deviating from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements over commercially available technologies, or to enable other persons skilled in the art to understand the embodiments disclosed herein.
Claims
[1] Structure for an optical power splitter, wherein the structure comprises: a multimode interference region; a first dielectric layer (19, 21) over the multimode interference region; a first waveguide core (22) on the first dielectric layer (19, 21), wherein the first waveguide core (22) comprises a section (23) positioned above the multimode interference region, and the first waveguide core (22) provides a first input terminal to the optical power splitter; a second waveguide core (24) on the first dielectric layer (19, 21), wherein the second waveguide core (24) comprises a section (25) positioned above the multimode interference region, and the second waveguide core (24) provides a first output terminal from the optical power splitter; and a third waveguide core (24) on the first dielectric layer (19, 21), wherein the third waveguide core (24) comprises a section (25) positioned above the multimode interference region, and the third waveguide core (24) provides a second output terminal from the optical power splitter, wherein the multimode interference region is located in a first level, the first waveguide core (22), the second waveguide core (24), and the third waveguide core (24) are located in a second level, the second level being positioned in a vertical direction within a different plane than the first level, and the first dielectric layer (19, 21) being positioned as a solid layer between the multimode interference region in the first level and the first waveguide core (24), the second waveguide core (24), and the third waveguide core (24) in the second level. [2] Structure according to claim 1, wherein the multimode interference region is a slab (12) having a first side surface (15) and a second side surface (17) opposite the first side surface (15), wherein the first waveguide core (22) is positioned to extend over the first side surface (15), and the second waveguide core (24) and the third waveguide core (24) are positioned to extend over the second side surface (17). [3] Structure according to claim 2, wherein the slab (12) comprises a tapered section (46, 54) extending from the first side surface (15) and the section (23) of the first waveguide core (22) is partially positioned over the tapered section (46, 54). [4] Structure according to claim 2, wherein the section (23) of the first waveguide core (22) is a tapered section having a termination end (26) positioned above the slab (12). [5] Structure according to claim 2, wherein the slab (12) comprises a first tapered section (48) and a second tapered section (48) extending from the second side surface (17), the section (25) of the second waveguide core (24) is partially positioned over the first tapered section (48), and the section (25) of the third waveguide core (24) is partially positioned over the second tapered section (48). [6] Structure according to claim 2, wherein the section (25) of the second waveguide core (24) is a tapered section having a termination end (28) positioned above the slab (12), and the section (25) of the third waveguide core (24) is a tapered section having a termination end (28) positioned above the slab (12). [7] Structure according to claim 2, wherein the slab (12) comprises a tapered section (56) extending from the second side surface (17), the section (25) of the second waveguide core (24) and the section (25) of the third waveguide core (24) are partially positioned over the tapered section (56). [8] Structure according to any one of claims 2 to 7, further comprising: a second dielectric layer (20) positioned as a solid layer between the slab (12) and the first waveguide core (22), between the slab (12) and the second waveguide core (24), and between the slab (12) and the third waveguide core (24), wherein the first dielectric layer (19, 21) and the second dielectric layer (20) comprise different dielectric materials. [9] Structure according to any one of claims 1 to 8, wherein the second waveguide core (24) is positioned adjacent to the third waveguide core (24), and the section (23) of the first waveguide core (22) is positioned symmetrically relative to the section (25) of the second waveguide core (24) and the section (25) of the third waveguide core (24). [10] Structure according to any one of claims 1 to 9, wherein the multimode interference region consists of a first material, and the first waveguide core (22), the second waveguide core (24), and the third waveguide core (24) consist of a second material which differs in composition from the first material. [11] Structure according to claim 10, wherein the first material comprises single-crystal silicon, and the second material comprises silicon nitride. [12] Structure according to any one of claims 1 to 11, further comprising: a fourth waveguide core (58, 60) on the first dielectric layer (19, 21), wherein the fourth waveguide core (58, 60) includes a section positioned above the multimode interference region, and the fourth waveguide core (58, 60) provides a second input terminal to the optical power splitter. [13] Structure according to claim 12, wherein the multimode interference region is a slab (12) having a side surface (15), the first waveguide core (22) and the fourth waveguide core (58, 60) being positioned to extend over the side surface (15), and the section of the fourth waveguide core (58, 60) being positioned adjacent to the section of the first waveguide core (22). [14] Structure according to any one of claims 1 to 13, wherein the section (23) of the first waveguide core (22) is a tapered section (40) having a termination end (26) positioned above the multimode interference region. [15] Structure according to any one of claims 1 to 14, wherein the section (25) of the second waveguide core (24) is a tapered section (42) having a termination end (28) positioned above the multimode interference region, and the section (25) of the third waveguide core (24) is a tapered section (42) having a termination end (28) positioned above the multimode interference region. [16] Structure according to any one of claims 1 to 15, further comprising: a substrate (13) comprising a dielectric layer (14), wherein the multimode interference region is positioned on the dielectric layer (14) between the dielectric layer (14) and the first waveguide core (22), between the dielectric layer (14) and the second waveguide core (24), and between the dielectric layer (14) and the third waveguide core (24). [17] Method for forming an optical power splitter, the method comprising: Formation of a multimode interference region; Formation of a dielectric layer (19, 21) over the multimode interference region; Forming a first waveguide core (22) on the dielectric layer (19, 21), wherein the first waveguide core (22) comprises a section (23) positioned above the multimode interference region, and the first waveguide core (22) provides an input connection to the optical power splitter; Forming a second waveguide core (24) on the dielectric layer (19, 21), wherein the second waveguide core (24) comprises a section positioned above the multimode interference region, and the second waveguide core (24) provides a first output terminal from the optical power splitter; and Forming a third waveguide core (24) on the dielectric layer (19, 21), wherein the third waveguide core (24) comprises a section (25) positioned above the multimode interference region, and the third waveguide core provides a second output terminal from the optical power splitter, wherein the multimode interference region is located in a first level, the first waveguide core (22), the second waveguide core (24), and the third waveguide core (24) are located in a second level, the second level being positioned in a vertical direction within a different plane than the first level, and the first dielectric layer (19, 21) being positioned as a solid layer between the multimode interference region in the first level and the first waveguide core (24), the second waveguide core (24), and the third waveguide core (24) in the second level. [18] Method according to claim 17, wherein the multimode interference region is a slab (12) having a first side surface (15) and a second side surface (17) opposite the first side surface (15), the first waveguide core (22) being positioned to extend over the first side surface (15), the second waveguide core (24) being positioned adjacent to the third waveguide core (24), and the second waveguide core (24) and the third waveguide core (24) being positioned to extend over the second side surface (17). [19] Method according to claim 17 or 18, wherein the multimode interference region consists of a first material, and the first waveguide core (22), the second waveguide core (24), and the third waveguide core (24) consist of a second material which differs in composition from the first material. [20] Method according to any one of claims 17 to 19, wherein the section (23) of the first waveguide core (22) is a tapered section having a termination end positioned above the multimode interference region, the section (25) of the second waveguide core (24) is a tapered section having a termination end positioned above the multimode interference region, and the section (25) of the third waveguide core (24) is a tapered section having a termination end positioned above the multimode interference region.