Circuit arrangement for a binarized neural network using silicon gate diodes

Abstract

Circuit arrangement (400) for a binarized neural network, comprising: a plurality of silicon gate diodes in which a diode structure is arranged as a channel region (132) between an anode terminal (131) and a cathode terminal (133), a gate terminal (134) is arranged on the diode structure to perform unidirectional switching by means of a potential barrier control in the channel region (132) based on different voltages applied to each of the anode terminal (131) and the gate terminal (134), and storage properties are realized as holes or electrons that accumulate in the potential well due to a positive feedback loop, wherein the silicon gate diodes operate as synaptic elements (401) in a memory arrangement connected in parallel, and output results of a multiply-accumulate (MAC) operation based on an input signal applied by an input line processor (402) connected to the memory arrangement and a weight update signal applied by a synaptic line processor (403) connected to the memory arrangement, wherein the silicon gate diode receives an anode voltage of the anode terminal (131) as the input signal, generates a latch-up phenomenon due to the positive feedback loop when the applied input signal increases in a positive direction, has any one of two memory states for the channel area (132), receives a gate voltage of the gate terminal (134) as the weight update signal to control the input signal that causes the latch-up phenomenon, updates a synaptic state associated with the memory state according to the application of the input signal and the weight update signal, and performs the MAC calculation function according to the synaptic weight, where, when the synaptic weight is in a “1” state, the silicon gate diode outputs a cathode current of the cathode terminal (133) in a form similar to a graph form of a function of a rectified linear unit (ReLU), regardless of the gate voltage.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority over Korean patent application No. 10-2023-0114457, which was filed with the Korean Intellectual Property Office on August 30, 2023. BACKGROUND OF REVELATION Area of ​​Revelation

[0002] The present disclosure relates to a circuit arrangement for a binarized neural network using silicon gate diodes and, in particular, to a technology for implementing a self-activating circuit arrangement for a binarized neural network that performs a self-activating function using a silicon gate diode that performs storage and switching functions in a single element based on a positive feedback loop. Description of the state of the art

[0003] In a conventional von Neumann-based computer system, a processor and a memory are separate, and data signals are transmitted via a bus line.

[0004] As computing power improves, a bottleneck phenomenon occurs due to a difference in data processing speed between a processor and a memory, and there are limits to processing large amounts of data.

[0005] This means that the von Neumann-based system, which is a product of revolutionary development in the semiconductor industry, has improved the integration density and performance of modern computers, but has the disadvantage of consuming a lot of energy and having long data transmission and standby times due to the physical separation between a processor and a memory hierarchy.

[0006] In view of the increase in data-intensive applications such as 5G communication standards, the Internet of Things (IoT) and artificial intelligence (AI) following the fourth industrial revolution, a new computing paradigm is an essential requirement for large-scale data processing.

[0007] To solve the problems mentioned above, research is actively being conducted on memory technology with internal logic (Logic-in-Memory, LIM), which combines computing and storage functions.

[0008] According to storage technology with internal logic, since the computational function of a processor and the storage function of a memory are performed in the same space, the time and power required during data transmission can be reduced, and the integration of the system can be greatly improved.

[0009] Traditional memory technology with internal logic has been actively explored based on static random-access memory (SRAM) and dynamic RAM (DRAM), which are volatile memory elements, and resistive RAM (ReRAM), magnetoresistive RAM (MRAM), and phase-change RAM (PCRAM), which are non-volatile memory elements.

[0010] To overcome limitations in processing large amounts of data, package-on-package (PoP) and through-silicon-via (TSV) technologies are being explored, integrating logic memory onto a single chip. However, since logic and memory functions cannot be performed simultaneously on a single transistor, problems remain regarding bottlenecks, power consumption, computational efficiency, and integration.

[0011] Furthermore, the memory technology with internal logic based on a non-volatile memory element requires a complex manufacturing process due to the use of non-silicon materials. In addition, this technology exhibits low element uniformity and stability, which complicates its practical application.

[0012] Furthermore, previously explored internal logic memory technologies cannot implement all basic complementary metal oxide semiconductor (CMOS) logic operations in a single cell and exhibit low integration, as individual circuitry and wiring are required for each logic operation.

[0013] Accordingly, the development of a binarized neural network technology using silicon gate diodes that can be applied to the CMOS process and can perform both switching and storage functions simultaneously, and a self-activated neural network technology that performs the activation function of a neuron circuit in a neural network is required.

[0014] WANG, Yin et al.: “An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations”, Nature Communications Vol. 12 (2021), No. 1, p. 3347 and WANG, Yin et al.: “An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations, Supplementary Information”, Nature Communications Vol. 12 (2021), No. 1, p. 3347 describe a MAC circuit arrangement with a 2T-1C configuration comprising two MoS2 FETs and a metal-insulator-metal capacitor.

[0015] JEON, Juhee; CHO, Kyoungah; KIM, Sangsig, “Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors”, Micromachines Vol. 14 (2023), No. 6, p. 1138, describes a 1T DRAM consisting of an FBFET with a p + -npn + silicon nanowire, and investigates memory operation and disturbances in a 3 × 3 array structure through mixed-mode simulations.

[0016] US 2020 / 0 075 094 A1 describes an electronic field-effect device with transposable feedback and an array circuit using the device. [Previous state documents][Patent documents] (Patent document 1) Korean patent application KR 10 2023 0 053 195 A, “STATE-Dependent Memory with Internal Logic with Silicon Diodes” (Patent document 2) Korean patent application KR 10 2022 0 110 774 A , “PERFORMANCE AND AREA EFFICIENT STRUCTURE OF THE SYNAPTIC STORAGE CELL” (Patent document 3) Korean patent application KR 10 2023 0 020 840 A, “VARIABLE STORAGE ELEMENT WITH INTERNAL LOGIC WITH SILICON TRANSISTORS” (Patent document 4) Korean patent application KR 10 2022 0 107 808 A, “CIRCUIT DEVICE OF A BINARY NEURAL NETWORK WITH MIXED SIGNALS” SUMMARY OF THE REVELATION

[0017] Therefore, the present disclosure was made in view of the above problems, and it is an objective of the present disclosure to implement a self-activating circuit arrangement for a binarized neural network that performs a self-activating function using a silicon gate diode that performs storage and switching functions in a single element based on a positive feedback loop.

[0018] It is a further objective of the present disclosure to implement a self-activating circuit arrangement for a binarized neural network, which exhibits unidirectional switching properties by controlling a potential barrier; and which is capable of increasing the area and computational efficiency of an artificial neural network by exhibiting excellent memory properties of a silicon gate diode, which also exhibits memory properties as holes or electrons that accumulate in a potential well due to a positive feedback loop and a self-activating function through the linearity of an output signal according to an input signal.

[0019] Another objective of the present disclosure is to increase the computational accuracy of an artificial neural network by enabling the use of the CMOS process, enabling the fabrication of large-scale arrangements, and virtually eliminating the discrepancy between the properties of a silicon gate diode and the properties of a synaptic device.

[0020] Another objective of the present disclosure is to implement a circuit arrangement for a binarized neural network, comprising a memory arrangement consisting of silicon gate diodes based on a positive feedback loop and performing the activation function of a neuron circuit; and exhibiting excellent uniformity and stability.

[0021] Another objective of the present disclosure is to implement a circuit arrangement for a binarized neural network capable of reducing standby power by utilizing the excellent memory properties of silicon gate diodes; and capable of being used in next-generation artificial intelligence computing technology by increasing computing efficiency with low power consumption through excellent switching properties.

[0022] According to one aspect of the present disclosure, a circuit arrangement for a binarized neural network is provided, comprising a plurality of silicon gate diodes in which a diode structure is arranged as a channel region between an anode terminal and a cathode terminal, a gate terminal is arranged on the diode structure to perform unidirectional switching by means of a potential barrier control in the channel region based on different voltages applied to each of the anode terminal and the gate terminal, and memory properties are realized as holes or electrons that accumulate in the potential well due to a positive feedback loop, wherein the silicon gate diodes operate as synaptic elements in a memory arrangement connected in parallel, and the results of a multiply-accumulate (MAC) operation based on an input signal arewhich is applied by an input line processor connected to the memory arrangement, and outputs a weight update signal applied by a synapse line processor connected to the memory arrangement.

[0023] The silicon gate diode can receive an anode voltage from the anode terminal as the input signal, generate a latch-up phenomenon due to the positive feedback loop when the applied input signal increases in a positive direction, have any one of two memory states for the channel area, receive a gate voltage from the gate terminal as the weight update signal to control the input signal that causes the latch-up phenomenon, update a synaptic state associated with the memory state according to the application of the input signal and the weight update signal, and perform the MAC calculation function according to the synaptic weight.

[0024] The silicon gate diode can output a current signal corresponding to a range of "0" to "1" as an operational result by performing a multiplication operation between a continuous input ranging from "0" to "1" as the applied input signal increases in a positive direction, and a synaptic weight of any "0" state and a "1" state corresponding to the two memory states.

[0025] In the silicon gate diode, in a case of a potentiation operation where the synaptic weight is updated to the "1" state, an operation result can be output as a current signal proportional to the applied input signal, and in a case of a depression operation where the synaptic weight is updated to the "0" state, a current signal at 0 mA can be output regardless of the applied input signal.

[0026] When the synaptic weight is in a "1" state, the silicon gate diode can output a cathode terminal current in a form similar to a graph of a rectified linear unit (ReLU) function, regardless of the gate voltage.

[0027] The memory arrangement can connect the anode, gate, and cathode terminals in parallel within the silicon gate diodes to form an input line, a weight line, and an output line, respectively. The input line can be arranged perpendicular to the weight and output lines, and the weight and output lines can be arranged in parallel.

[0028] The input line can receive the input signal, the weight line can receive the weight update signal, and the output line can output the MAC operation result based on the input signal and the weight update signal to a next artificial neural network.

[0029] In the memory arrangement, the silicon gate diodes can be connected in an N x M configuration, and by a multiplication operation of a synaptic weight, updated based on an input signal applied to the input line and a weight update signal applied to the weight line, each current through the output line can be added, and a summation operation can be performed to output the MAC operation results as a synaptic weight matrix.

[0030] If N and M are “2” in the memory arrangement, the input signal can consist of a first input signal and a second input signal, the synaptic weight can consist of a first synaptic weight up to a fourth synaptic weight, a first current and a second current can be output to the output line, and the synaptic weight matrix, consisting of the first current and the second current, can be calculated as a result of a vector matrix multiplication operation of the synaptic weight and the input signal.

[0031] If both the first and second input signals are applied to the memory arrangement while the weight update signal is set to 1 V, a value of the first current can be twice a value of the second current, and afterwards, if only the first input signal is applied, a value of the first current can be equal to a value of the second current.

[0032] If only the second input signal is applied to the memory arrangement, only the first current can have a value proportional to the second input signal, and if the first and second input signals are not applied, the first and second currents can be measured close to 0 mA.

[0033] The silicon gate diode can comprise a single silicon gate diode, a double silicon gate diode, or a triple silicon gate diode. BRIEF DESCRIPTION OF THE FIGURES

[0034] The above and other tasks, features and other advantages of the present disclosure will become more clearly understandable from the following detailed description in conjunction with the accompanying drawings, of which: Fig. Diagrams 1A to 2B illustrate the structures and circuit symbols of a silicon gate diode that forms a circuit arrangement for a binarized neural network according to an embodiment of the present disclosure; Fig. Figures 3A to 3C are diagrams illustrating the electrical properties of a silicon gate diode forming a circuit arrangement for a binarized neural network according to an embodiment of the present disclosure; Fig. Figure 4 is a diagram illustrating a circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure; Fig. Figures 5A to 6B are diagrams illustrating a multiplication operation in a method for operating a circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure; Fig. Figures 7A to 9F are diagrams illustrating a multiplication-accumulation (MAC) operation in a method for operating a circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure; Fig. 10 comprises the optical images of a silicon gate diode according to an embodiment of the present disclosure; and Fig. Figures 11A to 11C are diagrams illustrating the arithmetic operations of a circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE REVELATION

[0035] The embodiments of the present disclosure are described in detail below with reference to the figures.

[0036] It is understood, however, that the present disclosure is not limited to the embodiments according to the concept of the present disclosure, but includes modifications, equivalents or alternatives that fall within the nature and scope of the present disclosure.

[0037] In the following description of the present disclosure, a detailed description of the known functions and configurations included herein is omitted if it could obscure the subject matter of the present disclosure.

[0038] Furthermore, the terms used in this description are defined taking into account the functions used in this disclosure and may be modified according to the intent or customary practices of clients, operators, and users. Accordingly, definitions of terms should be understood based on the entirety of this description.

[0039] In the description of the figures, the same reference symbols can be used for similar elements.

[0040] The singular expressions in the present description may include plural expressions unless the context clearly indicates otherwise.

[0041] In this description, expressions such as "A or B" and "at least one of A and / or B" can include all possible combinations of the elements listed together.

[0042] Expressions such as "first" and "second" can be used to qualify the elements regardless of order or meaning, and are used to distinguish one element from another without restricting the elements.

[0043] It is understood that when an element (e.g., first) is described as being “connected” or “coupled” with another element (e.g., second), the first element may be directly connected to the second element or connected to the second element via an intermediate element (e.g., third).

[0044] As used herein, “trained to” can be used interchangeably with, for example, “suitable for”, “capable of”, “modified to”, “made for”, “able to” or “designed for” in relation to hardware or software.

[0045] In some situations, the expression "device designed to" may mean that the device can "~ do" with other devices or components.

[0046] For example, in the phrase "processor trained to perform A, B and C", the processor may refer to a general-purpose processor (e.g., CPU or application processor) that is capable of performing a corresponding operation by executing an associated processor (e.g., embedded processor) to perform the corresponding operation, or by executing one or more software programs stored in a storage device.

[0047] Furthermore, the expression “or” means “inclusive or” instead of “exclusive or”.

[0048] That is to say, unless otherwise stated or clearly evident from the context, the expression "x uses a or b" means any of the natural inclusive permutations.

[0049] Terms such as "unit" or "module", etc., should be understood as a unit that performs at least one function or operation and that may be implemented in a hardware manner, a software manner, or a combination of both.

[0050] Fig. Figures 1A to 2B are diagrams that illustrate the structures and circuit symbols of a silicon gate diode that forms a circuit arrangement for a binarized neural network according to an embodiment of the present disclosure.

[0051] Fig. 1A and Fig. Figure 1B illustrates the structures and circuit symbols of the silicon gate diode that forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure.

[0052] With reference to Fig. 1A consists in a silicon gate diode 100, which forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, a channel area between an anode terminal 101 and a cathode terminal 104 comprising a first channel area 102 and a second channel area 103.

[0053] A gate insulating film 105 is located on the second channel area 103 and a gate connector 106 is located on the gate insulating film 105.

[0054] In a circuit symbol 110 of the silicon gate diode, which forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, a channel area 112 is located between an anode terminal 111 and a cathode terminal 113 and a gate terminal 114 is connected thereto.

[0055] With reference to Fig. 1B consists in a silicon gate diode 120, which forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, a channel area between an anode terminal 121 and a cathode terminal 124 comprising a first channel area 122 and a second channel area 123.

[0056] A gate insulating film 125 is located on the first channel area 122 and a gate connector 126 is located on the gate insulating film 125.

[0057] In a circuit symbol 130 of the silicon gate diode, which forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, a channel area 132 is located between an anode terminal 131 and a cathode terminal 133 and a gate terminal 134 is connected thereto.

[0058] According to one embodiment of the present disclosure, an input line is connected to the anode terminal 111 or the anode terminal 131, an output line is connected to the cathode terminal 113 or the cathode terminal 133, and the memory state of the channel area is determined according to the update of a synaptic weight.

[0059] Fig. Figure 2A illustrates the structure and circuit symbol of a double silicon gate diode, which forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure.

[0060] With reference to Fig. 2A is located in a silicon gate diode 200, which forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, an intrinsic region 202 between an anode terminal 201 and a cathode terminal 203, a gate insulating film 204 is located on the intrinsic region 202 and a first gate terminal 205 and a second gate terminal 206 are located on the gate insulating film 204.

[0061] The intrinsic region 202 operates as a channel region based on a gate voltage input from the first gate terminal 205 or the second gate terminal 206.

[0062] In a circuit symbol 210 of the silicon gate diode, which forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, there is an intrinsic region 212 between an anode terminal 211 and a cathode terminal 213 and a first gate terminal 214 and a second gate terminal 215 are connected to it.

[0063] Fig. Figure 2B illustrates the structure and circuit symbol of a triple silicon gate diode, which forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure.

[0064] With reference to Fig. 2B is located in a silicon gate diode 220, which forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, an intrinsic region 222 between an anode terminal 221 and a cathode terminal 223, a gate insulating film 224 is located on the intrinsic region 222 and a programming gate terminal 225 and a control gate terminal 226 are located on the gate insulating film 224.

[0065] The intrinsic area 222 operates as a channel area based on a gate voltage input from the programming gate terminal 225.

[0066] More precisely, if the level of the programming voltage (VPG) input from the intrinsic region 222 into the programming gate port 225 is high, the intrinsic region 222 operates as an n-channel, corresponding to a first-channel operation. If the level of the programming voltage (VPG) is low, the intrinsic region 222 operates as a p-channel, corresponding to a second-channel operation.

[0067] When the first channel operation is performed, if the magnitude of a control voltage (VCG) applied through control gate terminal 226 is high, the silicon gate diode 220 is determined to be in the ON state. If the magnitude of a control voltage (VCG) applied through control gate terminal 226 is low, the silicon gate diode 220 is determined to be in the OFF state.

[0068] In a circuit symbol 230 of the silicon gate diode, which forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, an intrinsic region 232 is located between an anode terminal 231 and a cathode terminal 233, and a programming gate terminal 234 and a control gate terminal 235 are connected thereto.

[0069] For example, the anode terminal, the gate terminal and the cathode terminal can be referred to as an anode electrode, a gate electrode and a cathode electrode respectively.

[0070] That is, the silicon gate diode, which forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, can have a structure in which a single gate electrode terminal is deposited on an n- or p-doped channel region on a silicon channel, or multiple gate electrode terminals are deposited on an intrinsically doped region.

[0071] Furthermore, the silicon gate diode operates by inducing a positive feedback loop through a potential barrier and exhibits switching and storage properties, so that the silicon gate diode can be designed as a synaptic element of the binarized neural network.

[0072] This means that the silicon gate diode has switching and storage properties that make it possible to implement a circuit arrangement for a self-activating binarized neural network, in which the activation function of a neuronal circuit is performed by a neural network.

[0073] Accordingly, the present disclosure can implement a circuit arrangement for a self-activating binarized neural network that performs a self-activating function using a silicon gate diode, which performs storage and switching functions in a single element based on a positive feedback loop.

[0074] Fig. Figures 3A to 3C are diagrams illustrating the electrical properties of a silicon gate diode that forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure.

[0075] Fig. Figures 3A to 3C show the electrical properties of the silicon gate diode that forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure.

[0076] With reference to Fig. Figure 3A shows a diagram 300 relating to the electrical properties of the silicon gate diode that forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, a change in the cathode current (I Diode ), which is output to a cathode terminal, according to an anode voltage (V IN ), which is applied to an anode connection.

[0077] Diagram 300 shows that when the silicon gate diode, which forms the circuit arrangement for a binarized neural network, has an anode voltage (V IN) in the positive direction, a latch-up phenomenon occurs due to a positive feedback loop, and two states are shown.

[0078] Furthermore, the anode voltage at which latch-up occurs varies depending on the gate voltage (VG). W ) the silicon gate diode.

[0079] The circuit arrangement for a binarized neural network can perform synaptic weight update and multiply-accumulate (MAC) computational functions by applying an anode voltage and a gate voltage based on the properties of the single element.

[0080] Regardless of the gate voltage, the cathode current (I) Diode ) of an element in the “1” state of the diagram form of the function of a rectified linear unit (ReLU).

[0081] The ReLU function can be the activation function of a neuronal circuit, which is used in most artificial neural network architectures.

[0082] That is, in the silicon gate diode that forms the binarized neural network of the present disclosure, the output current has the form of the ReLU function in the synaptic weight state of “1” regardless of the gate voltage, so that a circuit arrangement for a self-activating binarized neural network that self-activates a neuron circuit can be implemented.

[0083] Due to the unidirectional switching or self-rectification properties and the high linearity of a single silicon gate diode, a self-activating binarized neural network can be implemented that performs a self-activating function.

[0084] With reference to Fig. Figure 3B shows a diagram 310 relating to the electrical properties of the silicon gate diode that forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, the case in which the gate voltage (V W ) of the silicon gate diode is 0 V, with respect to a change in the cathode current (I Diode ), which is output to a cathode terminal, according to an anode voltage (V IN ), which is applied to an anode connection.

[0085] With reference to Fig. Figure 3C shows a diagram 320 relating to the electrical properties of the silicon gate diode that forms the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure, the case in which the gate voltage (V W ) of the silicon gate diode is 1 V, with respect to a change in the cathode current (I Diode), which is output to a cathode terminal, according to an anode voltage (V IN ), which is applied to an anode connection.

[0086] If the anode voltage (VIN) is 0 V, it may be in a standby state.

[0087] Diagram 320 shows the operating conditions of the Bayesian neural network (BNN), in which the cathode current (I Diode ) at a gate voltage (V W ) from 1 V increases rapidly, at about 2.5 V, when the anode voltage (V IN ) increases.

[0088] Diagram 320 shows that a positive feedback loop is eliminated at approximately 1 V when the anode voltage (V) IN ) decreases.

[0089] The bistable nature is expressed as cathode current (I Diode ) to anode voltage (V IN ) expressed, and the high ratio of the current quantities of states 1 and 0 can be approximately 10 8 be.

[0090] If a gate voltage (V W ) 1 V for an anode voltage (V IN If the voltage is 2 V, the electrical properties of a pn diode with unipolar switching characteristics are adopted.

[0091] Regardless of the gate voltage (V W ) is the shape of the curve for the cathode current (I Diode ) compared to the anode voltage (V IN ) in state 1 of the form of the function of a rectified linear unit used in the activation function of a neural network, similarly.

[0092] The difference in cathode current (I Diode ) depending on the change between state 1 and state 0 can be used in MAC operation.

[0093] Fig. Figure 4 is a diagram illustrating a circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0094] Fig. Figure 4 illustrates the circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0095] With reference to Fig. In a circuit arrangement 400 for a binarized neural network using silicon gate diodes, according to one embodiment of the present disclosure, a diode structure is configured as a channel region between an anode terminal and a cathode terminal, and a gate terminal is located on the diode structure. With this configuration, unidirectional switching is implemented by means of potential barrier control in the channel region based on different voltages applied to the anode terminal and the gate terminal, respectively. Furthermore, multiple silicon gate diodes can be included to implement storage properties such as holes or electrons that accumulate in the potential well due to a positive feedback loop.

[0096] For example, the circuit arrangement 400 for a binarized neural network using silicon gate diodes can be an artificial neural network that reduces computation time and energy consumption by binarizing synaptic weights.

[0097] Accordingly, the present disclosure can implement a self-activating circuit arrangement for a binarized neural network, which has unidirectional switching properties by controlling a potential barrier; and which is able to increase the area and computational efficiency of an artificial neural network by exhibiting excellent memory properties of a silicon gate diode, which also has memory properties as holes or electrons that accumulate in a potential well due to a positive feedback loop and a self-activating function through the linearity of an output signal according to an input signal.

[0098] A plurality of silicon gate diodes can operate as synaptic elements 401 in a memory arrangement, connected in parallel, and can output multiply-accumulate (MAC) operation results based on an input signal applied by an input line processor 402 connected to the memory arrangement and a weight update signal applied by a synaptic line processor 403 connected to the memory arrangement.

[0099] In the memory arrangement, as circuit arrangement 400 for a binarized neural network, an anode terminal, a gate terminal, and a cathode terminal of a plurality of silicon gate diodes can be connected in parallel to form an input line (IL), a weight line (WL), and an output line (OL), respectively. The input line (IL) can be arranged perpendicular to the weight line (WL) and the output line (OL), and the weight line (WL) and the output line (OL) can be arranged parallel to each other.

[0100] The anode terminal is connected to the input line (IL), the gate terminal is connected to the weight line (WL), and the cathode terminal is connected to the output line (OL).

[0101] The gate terminal and the cathode terminal can form the weight line (WL) and the output line (OL), respectively.

[0102] For example, in the memory arrangement, depending on M, which is the number of rows formed by a plurality of silicon gate diodes, the first weight line (WL0) to the M-th weight line (WL) can be m ) be trained and the first output line (OL0) up to the M-th output line (OL m ) can be trained.

[0103] The number of input lines (IL) corresponding to the columns and the number of output lines (OL) corresponding to the rows can be the same or different.

[0104] However, the weight line (WL) and the output line (OL) must have the same number (M).

[0105] Since, for example, the number of elements that form rows and columns can be as much as the number of inputs and outputs, N and M can be the same number or different numbers.

[0106] For example, in the memory arrangement, depending on N, which is the number of columns formed by a plurality of silicon gate diodes, the first input line (IL0) can be extended to the Nth input line (IL). n ) be trained.

[0107] The silicon gate diode receives the anode voltage of the anode terminal as an input signal and generates a latch-up phenomenon due to a positive feedback loop when the applied input signal increases in the positive direction.

[0108] The silicon gate diode has one of two memory states for the channel region. The silicon gate diode receives the gate voltage of the gate terminal as a weight update signal, so that the input signal at which the latch-up phenomenon occurs can be controlled.

[0109] Furthermore, the silicon gate diode can update a synaptic state with respect to any memory state by applying an input signal and a weight update signal, and can perform a MAC calculation function according to a synaptic weighting.

[0110] For example, the silicon gate diode can output a current signal corresponding to one from "0" to "1" as an operational result by performing a multiplication operation between a continuous input from "0" to "1" as the applied input signal increases in the positive direction, and a synaptic weight of one of two memory states "0" and "1".

[0111] Fig. Figures 5A to 6B are diagrams illustrating a multiplication operation in a method for operating a circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0112] Fig. Figure 5A illustrates a multiplication operation in the method for operating the circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0113] With reference to Fig. In the method for operating the circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure, cases are divided into a first case 500 and a second case 501, and a MAC operation is performed between an input signal and a synaptic weight.

[0114] Accordingly, the circuit arrangement for a binarized neural network can implement artificial intelligence functions such as image recognition through a continuous multilayer neural network.

[0115] The synaptic weight can be updated by the input voltage of an input line and a weight line.

[0116] The input signal applied through the input line (V IN ) can have continuous values, which can mean a continuous input A from 0 to 1 in the binarized neural network.

[0117] The current signal (I OUT ), which corresponds to an output, can be read by OL, and at this point the input A can take the form of a ReLU function for the input signal (V) due to the self-activation properties of the silicon gate diode. IN exhibit.

[0118] The operations corresponding to the first case 500 and the second case 501 are summarized in Table 1 below. [Table 1] Anodenspannung (A) synaptischesGewicht (W) Ausgang (OUT) erster Fall 0 ~ 1 0 0 zweiter Fall 1 0 ~ 1

[0119] The silicon gate diode has two storage states, a "1" state and a "0" state, which can each represent a binarized synaptic weight W (0) and a binarized synaptic weight W (1).

[0120] In the first case, 500, when the synaptic weight W is 0, since this case means that the silicon gate diode is switched off (“0” state), the output current (I) flows. OUT ) regardless of the applied input signal (V IN ) at a very low value.

[0121] Regarding the anode voltage (A) of 0 ~ 1, a voltage below the reference voltage corresponds to 0, and a voltage greater than the reference voltage corresponds to 1.

[0122] For example, if the reference voltage is 1 V, a voltage greater than 1 V can correspond to 1.

[0123] Furthermore, at the output, a current greater than the reference current from 0 to 1 is output as 1, and a current less than the reference current is output as 0.

[0124] This can mean that the multiplication operation result of an anode voltage and a synaptic weight in the MAC operation of the binarized neural network is always 0, regardless of an input signal.

[0125] In the second case 501, when the synaptic weight W is 1, since this case means that the silicon gate diode is switched on (“1” state), the output current (I) can be OUT ) linearly proportional to the applied input signal (V IN ) change.

[0126] This means that in the MAC operation of the binarized neural network, the multiplication operation result of an anode voltage and a synaptic weight can be proportional to an input.

[0127] According to one embodiment of the present disclosure, the silicon gate diode can output a current signal corresponding to one from “0” to “1” as an operational result by performing a multiplication operation between a continuous input from “0” to “1” when an applied input signal increases in the positive direction, and the synaptic weight of one of two memory states of “0” and “1”.

[0128] In terms of inputs from "0" to "1", if the input signals increase or decrease in the positive direction, a voltage below the reference voltage corresponds to "0", and a voltage greater than the reference voltage corresponds to "1".

[0129] For example, if the reference voltage is 1 V, a voltage greater than 1 V can correspond to “1”.

[0130] Fig. Figure 5B shows energy band diagrams according to a change of state of a silicon gate diode in the method for operating the circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0131] With reference to Fig. 5B can specify a first energy band diagram 510 that the state of the silicon gate diode is “0”, and a second energy band diagram 511 can specify that the state of the silicon gate diode is “1”.

[0132] In state “0” according to the first energy band diagram 510, excess charge carriers are missing in the potential wells of the n and p doping regions of the energy band diagram, thus preventing diode current (I) from flowing. Diode ) flows into a diode.

[0133] In contrast, in state “1” according to the second energy band diagram 511, excess charge carriers accumulate in the potential wells of the n and p doping regions of the energy band diagram, causing diode current to flow into a diode.

[0134] Modulating a potential barrier allows the diode to exhibit bistable properties.

[0135] A weight voltage of 0 V is applied when exponentiation and depression operations are performed, and a weight voltage of 1 V is applied when standby and multiplication operations are performed.

[0136] The conductivity of state “0” and state “1” can be the conductivity of an element that varies depending on the presence or absence of charge in a potential well, depending on a rise or depression operation.

[0137] Fig. Figure 6A shows the timing diagram of a multiplication operation in the method for operating the circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0138] With reference to Fig. 6A a time diagram 600 can have a corresponding rise section 601 after the update of the weight “1”, can have a corresponding decrease section 602 after the update of the weight “0”, while an output current (I OUT ) proportional to a continuous input signal (V IN )-pulse is measured, and independently of an input signal (V IN ) can result in a low output current (I OUT ) of 0 mA.

[0139] According to one embodiment of the present disclosure, in the silicon gate diode, in the case of a potentiation operation in which a synaptic weight is updated to the state "1", the result of the operation is output as a current signal proportional to an applied input signal. In the case of a depression operation in which a synaptic weight is updated to the state "0", a current signal of 0 mA can be output regardless of an applied input signal.

[0140] When a synaptic weight is in the state “1”, the silicon gate diode can output the cathode current of a cathode terminal in a form similar to the graph form of a rectified linear unit (ReLU) function, regardless of a gate voltage.

[0141] To update the synaptic weight W to 1 according to the operating procedure in the timing diagram 600, the voltage pulses of an input voltage (V) applied to an anode terminal are IN ) of 2 V and a voltage of the synaptic weight applied to a gate terminal (V W ) applied from 0 V.

[0142] After that, a continuous I can OUT from 0 mA to 7.4 mA proportional to a continuous V IN measured from 1.1 to 2.0 V.

[0143] To update the synaptic weight (W) to 0, the voltage pulses of V can IN of 2 V and V W applied from 0 V.

[0144] This can be done regardless of the same input voltage (V) A ) a very low output current close to 0 mA is measured.

[0145] This shows that a single synaptic element performs a multiplication operation based on excellent linearity.

[0146] With reference to Fig. 6B shows the silicon gate diode in diagram 610 an excellent linear relationship between input and output and can perform multiplication operations.

[0147] Diagram 610 shows a test result 611 and a straight fit 612.

[0148] Accordingly, the present disclosure can increase the computational accuracy of an artificial neural network by enabling the use of the CMOS process, enabling the fabrication of large-scale arrangements, and virtually eliminating the discrepancy between the properties of a silicon gate diode and the properties of a synaptic device.

[0149] Technologies that use conventional next-generation memory, such as ReRAM and MRAM, have the disadvantages of not being able to apply the CMOS process, exhibiting poor element uniformity and stability, and being difficult to put into practical use due to complex processing.

[0150] In conventional artificial neural network technology, multiple neural network layers are connected through an activation function, but to implement this requires a complex additional neural circuit, which can worsen the area and energy efficiency of an artificial neural network.

[0151] However, the present disclosure can implement a circuit arrangement for a binarized neural network that is able to reduce standby energy by utilizing the excellent memory properties of silicon gate diodes; and that can be used in next-generation artificial intelligence computing technology by increasing computing efficiency at low energy consumption through excellent switching properties.

[0152] Fig. Figures 7A to 8B are diagrams illustrating a multiplication-accumulation (MAC) operation in the method for operating the circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0153] Fig. 7A and Fig. Figure 7B illustrates a case in which a memory arrangement consisting of silicon gate diodes connected in a 4 × 1 pattern is used with respect to a MAC operation in the method for operating the circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0154] With reference to Fig. 7A is converted into an output current in a storage arrangement 700, which corresponds to the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure. OUT ) through a common output line (OL) and a summation operation is performed.

[0155] With reference to Fig. 7B increases the input voltage (V) in a timing diagram 710, which corresponds to the circuit arrangement for a binarized neural network according to an embodiment of the present disclosure. IN1 to V IN4 ) the input line from 1.1 V to 2 V by 0.1 V per step.

[0156] The timing diagram 710 shows the results of a summation operation in which an output current from each diode is added to the output current (I). OUT ) is added through the common output line (OL).

[0157] Fig. 8A and Fig. Figure 8B shows a matrix MAC operation in relation to a MAC operation in the method for operating the circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0158] Fig. Figure 8A shows a circuit arrangement 800 for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure and a synaptic weight matrix 801 according to the operation of the circuit arrangement for a binarized neural network.

[0159] Fig. Figure 8B shows the circuit arrangement 800 for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure and a timing diagram 810 relating to the operation of the circuit arrangement for a binarized neural network.

[0160] The MAC operation of the binarized neural network uses a silicon gate diode array connected in a 2×2 form, as the circuit arrangement 800 for a binarized neural network.

[0161] In the memory arrangement of the circuit arrangement 800 for a binarized neural network, a plurality of silicon gate diodes are connected in an N×N configuration. Through the multiplication operation of a synaptic weight, which is updated based on an input signal applied to an input line and a weight update signal applied to a weight line, each current through the output line is added, a summation operation is performed, and the MAC operation result can be output to a synaptic weight matrix.

[0162] Furthermore, in the memory arrangement, if N is "2", the input signal consists of a first input signal and a second input signal, the synaptic weight consists of a first synaptic weight up to a fourth synaptic weight and a first current and a second current that are output to the output line, and the synaptic weight matrix, consisting of the first current and the second current, can be calculated as the result of a vector matrix multiplication operation of the synaptic weight and the input signal.

[0163] The silicon gate diode can perform multiplication operations on any input signal (V). IN1 , V IN2 ) and synaptic weights (W 11 , W 12 , W 21 , W 22 ) and can perform a summation operation where each output current (I) OUT1 , I OUT2 ) through the common first output line (O L1) and the second output line (O L2 ) is added.

[0164] Mathematically, this means that the 2×2 array can perform a vector matrix multiplication operation. ([W11W12W21W22][IN1IN2]=[OUT1OUT2]), and the synaptic weight matrix 801 is exemplary

[1110] .

[0165] In the circuit arrangement 800 for a binarized neural network, after updating the synaptic weight of each element, when both V IN1 as well as V IN2 be created while V W is set to 1 V, I OUT1 exactly twice the value of I OUT2 on. Subsequently, if only V IN1 is created OUT1 and I OUT2 the same value.

[0166] Conversely, if only V IN2 is created only I OUT1 exhibit a value proportional to the input signal.

[0167] Finally, if not all input signals are applied, both I OUT1 as well as I OUT2 measured at low levels.

[0168] These results are consistent with the multiplication operation between the input vector and the synaptic weight matrix.

[0169] A silicon gate diode array connected in a 2×2 form by the circuit arrangement 800 for a binarized neural network can implement the MAC operation of a self-activating binarized neural network.

[0170] The circuit arrangement 800 for a binarized neural network is described in a 2×2 form, but can be extended to an N×M form.

[0171] The time diagram 810 shows that in a first area 811, when both V IN1 as well as V IN2 with V W , which is set to 1 V, will be applied, I OUT1 exactly twice the value of IOUT2 exhibits.

[0172] A second area 812 shows that I OUT1 and I OUT2 can have the same value if only V IN1 is created.

[0173] A third area, 813, shows that if only V IN2 is created only I OUT1 can have a value proportional to the input signal.

[0174] A fourth area, 814, shows that both I OUT1 as well as I OUT2 can be measured at low levels when no input signal is applied.

[0175] This means that in the memory arrangement, with respect to the circuit arrangement 800 for a binarized neural network, when both the first and second input signals are applied while the weight update signal is set to 1 V, the value of the first current is twice the value of the second current. Subsequently, when only the first input signal is applied, the first current and the second current can have the same value.

[0176] Furthermore, in the memory arrangement, when only the second input signal is applied, only the first current has a value proportional to the second input signal. When neither the first nor the second input signal is applied, the first and second currents can be measured at approximately 0 mA.

[0177] Accordingly, the present disclosure can implement a circuit arrangement for a binarized neural network comprising a memory arrangement consisting of silicon gate diodes based on a positive feedback loop and performing the activation function of a neuron circuit; and exhibiting excellent uniformity and stability.

[0178] Fig. Figures 9A to 9F are timing diagrams showing the MAC matrix operation results according to the weight update of the circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0179] The matrix operation of the in Fig. The time diagrams shown in 9A to 9F refer to the matrix equation on each time diagram.

[0180] During all matrix operations, the weight voltage is set to 1 V and the input voltage can be 0 V or a value between 1 V and 2 V.

[0181] All matrix equations usually contain , which shows that the V IN pulse in Fig. 7B for V IN1 and V IN2 is applied.

[0182] That is, if the weights of the 2×2 array elements change while both inputs “1” and “2” are set to “1”, the result of the operation satisfies the matrix equation.

[0183] Fig. 9A shows a 900-degree time diagram corresponding to a case where the first output current (I) OUT1 ) is measured as "0" under MAC matrix operations and the second output current (I OUT2 ) is measured as "0".

[0184] The matrix operation according to the time diagram 900 can be the same as the matrix operation on the time diagram 900.

[0185] During the matrix operation, the weight voltage is 1 V and the input voltage can be 0 V or a value between 1 V and 2 V.

[0186] Fig. Figure 11C illustrates a case of performing a matrix operation.

[0187] Fig. 9B shows a timing diagram 910, which corresponds to a case in which the value according to the first output current (I OUT1 ) is measured as "1" under MAC matrix operations and the value according to the second output current (I OUT2 ) is measured as "0".

[0188] The matrix operation according to time diagram 910 can be the same as the matrix operation on time diagram 910.

[0189] Fig. 9C shows a 920 time diagram corresponding to a case where the value is determined according to the first output current (I). OUT1 ) is measured as "1" under MAC matrix operations and the value according to the second output current (I OUT2 ) is measured as “1”.

[0190] The matrix operation according to time diagram 920 can be the same as the matrix operation on time diagram 920.

[0191] Fig. 9D shows a time diagram 930, which corresponds to a case where the value is determined according to the first output current (I). OUT1 ) is measured as "2" under MAC matrix operations and the value according to the second output current (I OUT2 ) is measured as "0".

[0192] The matrix operation according to time diagram 930 can be the same as the matrix operation on time diagram 930.

[0193] Fig. 9E shows a time diagram 940, which corresponds to a case in which the value according to the first output current (I OUT1 ) is measured as "2" under MAC matrix operations and the value according to the second output current (I OUT2 ) is measured as “1”.

[0194] The matrix operation according to time diagram 940 can be the same as the matrix operation on time diagram 940.

[0195] Fig. 9F shows a time diagram 950, which corresponds to a case where the value is determined according to the first output current (I). OUT1 ) is measured as "2" under MAC matrix operations and the value according to the second output current (I OUT2 ) is measured as "2".

[0196] The matrix operation according to time diagram 950 can be the same as the matrix operation on time diagram 950.

[0197] The matrix operations described above can be summarized as shown in Equation 1 below. [W11W12W21W22][IN1IN2]=[OUT1OUT2]

[0198] In equation 1, W can represent a binarized weight (conductivity), IN can represent an input signal (voltage), and OUT can represent an output signal (current) according to a matrix operation.

[0199] According to the timing diagrams 900 to 950, it is "1" when the output current is according to the first output current (I). OUT1 ) and the second output current (I OUT2 ) 7.5 mA. If the output current is 15 mA, it is "2". If the output current is less than 7.5 mA, it is "0".

[0200] However, as in the example above, 7.5 mA is not limited to meaning an output of "1". Regardless of the input voltage, if the output current is 0 mA, it means the output is "0". Conversely, if the output current is measured at a specific value according to the input voltage, it can mean "1".

[0201] This proportional relationship can be expressed by Fig. 6B is confirmed. Output "1" corresponds to one element. In the timing diagram 950, the output current is twice the current of one element compared to the input voltage, so it can mean output "2".

[0202] The circuit arrangement for a binarized neural network using silicon gate diodes can perform a matrix operation for each weight; in this case, the output of the matrix MAC operation exhibits high consistency with a simplified vector matrix multiplication (VMM) equation due to the high uniformity of the silicon gate diode.

[0203] Fig. 10 comprises the optical images of a silicon gate diode according to an embodiment of the present disclosure.

[0204] Fig. Figure 10 shows the optical images of the silicon gate diode according to an embodiment of the present disclosure.

[0205] In Fig. Image 10 shows an image; image 1010 shows an enlarged section of image 1000.

[0206] For example, image 1000 and image 1010 could be optical images of a silicon gate diode for performing a matrix MAC operation between the binarized weight of the BNN and an analog input.

[0207] Fig. Figures 11A to 11C are diagrams illustrating the arithmetic operations of a circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0208] Fig. Figure 11A shows a weight update in the arithmetic operation of the circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0209] With reference to Fig. In a weight update operation 1100, 11A is the binarized weight (W) matrix V. IN (2.0 or -2.0 V) and the silicon gate diode, which consists of the arrangement with VW If V is selected as 0.0, it increases (or decreases) at V IN of 2.0 V (-2.0 V).

[0210] Fig. Figure 11B shows a standby state during the arithmetic operation of the circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0211] With reference to Fig. During a standby operation, 11B applies 1 V to all weight lines and 0 V occurs in all input lines.

[0212] The silicon gate diode maintains a memory state with a very low output current (I Diode ) upright.

[0213] Fig. Figure 11C shows a multiplication operation in the arithmetic operation of the circuit arrangement for a binarized neural network using silicon gate diodes according to an embodiment of the present disclosure.

[0214] With reference to Fig. 11C can, in a multiplication operation 1120, select the diode from the arrangement, V W = 1.0 V and V IN = 0.0 V or V IN = 1.1-2.0 V.

[0215] I OUT , the product of an input voltage and a binarized weight, can be derived from the sum of the output current (I Diode ) will be received.

[0216] The present disclosure can implement a self-activating circuit arrangement for a binarized neural network that performs a self-activating function using a silicon gate diode, which performs storage and switching functions in a single element based on a positive feedback loop.

[0217] The present disclosure can implement a self-activating circuit arrangement for a binarized neural network, which has unidirectional switching properties by controlling a potential barrier; and which is able to increase the area and computational efficiency of an artificial neural network by exhibiting excellent memory properties of a silicon gate diode, which also has memory properties as holes or electrons that accumulate in a potential well due to a positive feedback loop and a self-activating function through the linearity of an output signal according to an input signal.

[0218] The present disclosure can increase the computational accuracy of an artificial neural network by enabling the use of the CMOS process, enabling the fabrication of large-scale arrangements, and virtually eliminating the discrepancy between the properties of a silicon gate diode and the properties of a synaptic device.

[0219] The present disclosure can implement a circuit arrangement for a binarized neural network comprising a memory arrangement consisting of silicon gate diodes based on a positive feedback loop and performing the activation function of a neuron circuit; and exhibiting excellent uniformity and stability.

[0220] The present disclosure can implement a circuit arrangement for a binarized neural network that is capable of reducing standby power by utilizing the excellent memory properties of silicon gate diodes; and that can be used in next-generation artificial intelligence computing technology by increasing computing efficiency at low power consumption through excellent switching properties.

[0221] In the specific embodiments described above, elements contained in the disclosure are expressed in the singular or plural according to the specific embodiments shown.

[0222] It is understood, however, that the singular or plural representations are to be chosen as appropriate for the situation depicted for the purpose of description, and that the embodiments described above are not limited to either the singular or the plural components. Components expressed in the plural may consist of a single number, and components expressed in singular form may consist of multiple elements.

[0223] Furthermore, the present disclosure has been described with reference to exemplary embodiments; however, it is understood that various modifications can be made without deviating from the scope of the present disclosure.

[0224] Therefore, the scope of the present disclosure should not be limited by the embodiments, but should be determined by the following claims and equivalents to the following claims.

Claims

[1] Circuit arrangement (400) for a binarized neural network, comprising: a plurality of silicon gate diodes in which a diode structure is arranged as a channel region (132) between an anode terminal (131) and a cathode terminal (133), a gate terminal (134) is arranged on the diode structure to perform unidirectional switching by means of a potential barrier control in the channel region (132) based on different voltages applied to each of the anode terminal (131) and the gate terminal (134), and storage properties are realized as holes or electrons that accumulate in the potential well due to a positive feedback loop, wherein the silicon gate diodes operate as synaptic elements (401) in a memory arrangement connected in parallel, and output results of a multiply-accumulate (MAC) operation based on an input signal applied by an input line processor (402) connected to the memory arrangement and a weight update signal applied by a synaptic line processor (403) connected to the memory arrangement, wherein the silicon gate diode receives an anode voltage of the anode terminal (131) as the input signal, generates a latch-up phenomenon due to the positive feedback loop when the applied input signal increases in a positive direction, has any one of two memory states for the channel area (132), receives a gate voltage of the gate terminal (134) as the weight update signal to control the input signal that causes the latch-up phenomenon, updates a synaptic state associated with the memory state according to the application of the input signal and the weight update signal, and performs the MAC calculation function according to the synaptic weight, where, when the synaptic weight is in a “1” state, the silicon gate diode outputs a cathode current of the cathode terminal (133) in a form similar to a graph form of a function of a rectified linear unit (ReLU), regardless of the gate voltage. [2] Circuit arrangement (400) for a binarized neural network according to claim 1, wherein the silicon gate diode outputs a current signal corresponding to a range from “0” to “1” as an operational result by performing a multiplication operation between a continuous input from “0” to “1” when the applied input signal increases in a positive direction, and a synaptic weight of any one of a “0” state and a “1” state corresponding to the two memory states. [3] Circuit arrangement (400) for a binarized neural network according to claim 2, wherein in the silicon gate diode, in a case of a potentiation operation in which the synaptic weight is updated to the “1” state, an operation result is output as a current signal proportional to the applied input signal, and in a case of a depression operation in which the synaptic weight is updated to the “0” state, a current signal is output at 0 mA regardless of the applied input signal. [4] Circuit arrangement (400) for a binarized neural network according to claim 1, wherein the memory arrangement connects the anode terminal (131), the gate terminal (134) and the cathode terminal (133) in parallel in the silicon gate diodes to form an input line, a weight line and an output line, wherein the input line is arranged perpendicular to the weight line and the output line and the weight line and the output line are arranged in parallel. [5] Circuit arrangement (400) for a binarized neural network according to claim 4, wherein the input line receives the input signal, the weight line receives the weight update signal and the output line outputs the MAC operation result based on the input signal and the weight update signal to a next artificial neural network. [6] Circuit arrangement (400) for a binarized neural network according to claim 5, wherein in the memory arrangement the silicon gate diodes are connected in a form of N x M and each current through the output line is added by a multiplication operation of a synaptic weight which is updated based on an input signal applied to the input line and a weight update signal applied to the weight line, and a summation operation is performed to output the MAC operation results as a synaptic weight matrix. [7] Circuit arrangement (400) for a binarized neural network according to claim 6, wherein in the memory arrangement, when N and M are “2”, the input signal consists of a first input signal and a second input signal, the synaptic weight consists of a first synaptic weight to a fourth synaptic weight, a first current and a second current are output to the output line, and the synaptic weight matrix, consisting of the first current and the second current, is calculated as a result of a vector matrix multiplication operation of the synaptic weight and the input signal. [8] Circuit arrangement (400) for a binarized neural network according to claim 7, wherein in the memory arrangement, when both the first and the second input signal are applied while the weight update signal is set to 1 V, a value of the first current is twice a value of the second current, and thereafter, when only the first input signal is applied, a value of the first current is equal to a value of the second current. [9] Circuit arrangement (400) for a binarized neural network according to claim 8, wherein in the memory arrangement, when only the second input signal is applied, only the first current has a value proportional to the second input signal, and when the first input signal and the second input signal are not applied, the first current and the second current are measured close to 0 mA. [10] Circuit arrangement (400) for a binarized neural network according to claim 1, wherein the silicon gate diode comprises a single silicon gate diode, a double silicon gate diode or a triple silicon gate diode.

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