Semiconductor equipment

Abstract

To provide a novel semiconductor device that can write and read multilevel data.SOLUTION: A memory cell includes a bit line, a power supply line, first and second nodes, first to fourth transistors, and first and second capacitors. One of two divided multilevel data is written to the first node through the first transistor. The other of the divided multilevel data is written to the second node through the second transistor. A gate of the third transistor is connected to the first node, and a gate of the fourth transistor is connected to the second node. The third and fourth transistors control a conduction state between the bit line and the power supply line. The first and second transistors preferably include an oxide semiconductor in a semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a product, method, or method of manufacture. Alternatively, the present invention relates to a process, machine, or manufacture. This invention relates to a substance or composition of matter. One embodiment relates to a semiconductor device, a display device, a light-emitting device, an energy storage device, a memory device, and a method for driving them. This relates to a semiconductor device, display device, or light-emitting device containing an oxide semiconductor. In particular, one aspect of the present invention relates to a semiconductor device, display device, or light-emitting device containing an oxide semiconductor. Regarding the device.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to the general category. Display devices, electro-optical devices, semiconductor circuits, and electronic devices include semiconductor devices. There are cases where this occurs. [Background technology]

[0003] A transistor using silicon (Si) as the semiconductor layer and an oxide semiconductor (Oxide Se A transistor using semiconductor (OS) as the semiconductor layer, combined with Semiconductor devices that enable data retention are attracting attention (see Patent Document 1).

[0004] In recent years, with the increasing volume of data being handled, there has been a growing demand for semiconductor devices with large storage capacities. In this context, the semiconductor device described in Patent Document 1 mentioned above records multi-level data. The documentation discloses a configuration for reading said data. Unless otherwise specified in this specification, Unless otherwise specified, multi-valued data refers to data of j bits (where j is a natural number greater than or equal to 2). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2012-256400 [Overview of the project] [Problems that the invention aims to solve]

[0006] For example, in the semiconductor device described in Patent Document 1, a single transistor is used to process multi-level data Although writing is being performed, as the number of bits in multi-level data increases, each data corresponds The difference between the potential and the current potential becomes small, making it difficult to determine the potential when reading the data, and errors occur. It is possible to read out the value.

[0007] One aspect of the present invention relates to a semiconductor device capable of writing and reading multi-level data. To provide, or a semiconductor device capable of writing and reading multi-level data. One objective of this invention is to provide a method for driving a device. Another aspect of this invention relates to a novel semiconductor One of the objectives is to provide a device.

[0008] Furthermore, the description of multiple problems does not preclude the existence of each other. The embodiment does not need to solve all of these problems. Furthermore, if there are problems other than those listed, the specification These issues will become clear from the drawings, claims, etc., and these issues will also be addressed in this invention. This could become a challenge for one aspect of the Ming Dynasty. [Means for solving the problem]

[0009] One aspect of the present invention comprises a bit line, a power line, first and second word lines, and first to fourth A semiconductor having a transistor, first and second capacitive elements, and first and second holding nodes. It is a conductive device. The first holding node receives first data via the first transistor. The second holding node is given the second data via the second transistor. The gate of the third transistor is electrically connected to the first holding node. The source and drain of the transistor are electrically connected to the bit line. The source and drain of the zista are connected to one of the source and drain of the fourth transistor. It is electrically connected to the power line. The source and drain of the fourth transistor are connected to the power line. They are electrically connected. The gate of the fourth transistor is electrically connected to the second holding node. The first terminal of the first capacitive element is electrically connected to the first holding node. The second terminal of the capacitive element is electrically connected to the first word line. The terminals of the first element are electrically connected to the second holding node. The second terminal of the second capacitive element is the second It is electrically connected to two word lines. The first and second data can be binary or multi-valued data. The first and second transistors have an oxide semiconductor in their semiconductor layer.

[0010] In the above embodiment, the third and fourth transistors are p-channel transistors.

[0011] In the above embodiment, the third and fourth transistors are n-channel transistors.

[0012] One aspect of the present invention is a semiconductor device described in the above aspect, and a display device, a microphone, a speaker It is an electronic device having a cart, operating keys, or a housing.

[0013] In this specification, a transistor is defined as having a gate (gate terminal or gate electrode) and a drain. It is an element having at least three terminals, including an input and a source. And the drain ( Drain terminal, drain region or drain electrode) and source (source terminal, source region or The source electrode has a channel region between it and the drain, channel region and source. It is capable of conducting electric current.

[0014] Here, the source and drain vary depending on the transistor's structure or operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. The part that functions as a source and the part that functions as a drain are not called source or drain. Let's refer to one of the source and drain as the first electrode, and the other of the source and drain as the second electrode. It may be written as such.

[0015] The ordinal numbers "first," "second," and "third" used herein are intended to avoid confusion of constituent elements. It should be noted that this is added for the purpose of indicating, and is not intended to limit the number.

[0016] In this specification, "A and B are connected" means that A and B are not directly connected. This also includes things that are electrically connected. Here, A and B are electrically connected "Continued" means that there is an object between A and B that has some kind of electrical effect. This refers to a device that enables the exchange of electrical signals between A and B.

[0017] For example, the source (or first terminal, etc.) of the transistor is connected via (or without) Z1. , electrically connected to X, the transistor's drain (or second terminal, etc.) is connected via Z2. If Y is electrically connected (or not connected) to the transistor source (or One terminal (such as the first terminal) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The transistor's drain (or second terminal, etc.) is directly connected to a portion of Z2. Furthermore, if another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible.

[0018] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal) of the transistor." The terminals (such as the X terminal) are electrically connected to each other, and X is the source (or the X terminal) of the transistor. The electrical connections are in the following order: terminal 1, the drain of the transistor (or terminal 2, etc.), and Y. It can be expressed as "It is connected." Or, "The source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X via the drain (or second terminal, etc.) and X, the transistor The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) ), Y is provided in this connection order. By using a specific method of expression to define the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and drain (or second terminal, etc.) of the zista. This allows us to determine the technical scope. Note that these expressions are just examples, and The method of representation is not limited to these. Here, X, Y, Z1, and Z2 are the object (e.g., the device). (This refers to elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.)

[0019] In this specification, words indicating arrangements such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes variably according to the direction in which each component is depicted. Therefore, it is not limited to the words described in the specification and can be appropriately rephrased according to the situation.

[0020] In this specification, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state. The off state, unless otherwise specified, in an n-channel transistor means that the potential difference (V ) between the gate and the source is lower than the threshold voltage (Vth), and in a p-channel transistor, it means that V GS is higher than Vth. For example, the off-current of an n-channel transistor may refer to the drain GS current when V is lower than Vth. The off-current of a transistor may depend on V GS . Therefore, when it is stated that the off-current of a transistor is 10 A or less, it may mean that there exists a value of V GS for which the off-current of the transistor becomes 10 A or less. -21 -21 GS

[0021] Also, the off-current of a transistor may depend on the potential difference (V DS ) between the drain and the source. In this specification, unless otherwise stated, the off-current represents the off-current at V when the absolute value of V DS is 0 .1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 1 2V, 16V, or 20V. Alternatively, the off-current of the transistor V is used in the reliability requirements for semiconductor devices and other equipment that contain stas. DS , or, V used in semiconductor devices, etc., that include the transistor DS Off-current in, It may sometimes be expressed in this way. [Effects of the Invention]

[0022] According to one aspect of the present invention, a semiconductor device capable of writing and reading multi-level data To provide a semiconductor that can write and read multi-level data. This makes it possible to provide a method for driving a body device. Furthermore, according to one aspect of the present invention, a novel semiconductor This makes it possible to provide a conductive device.

[0023] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not need to have all of these effects. Other effects are described in the specification. This will become clear from the descriptions in the drawings and claims, and the specification, drawings, and claims will be clear from the description, drawings, and claims. It is possible to extract other effects from any of these descriptions. [Brief explanation of the drawing]

[0024] [Figure 1] A circuit diagram showing an example of a memory cell. [Figure 2] A timing chart illustrating an example of memory cell operation. [Figure 3] A timing chart illustrating an example of memory cell operation. [Figure 4] A circuit diagram showing an example of a memory cell. [Figure 5] A timing chart illustrating an example of memory cell operation. [Figure 6] A timing chart illustrating an example of memory cell operation. [Figure 7] A circuit block diagram showing an example of a semiconductor device. [Figure 8] A circuit block diagram showing an example of a semiconductor device. [Figure 9] A circuit block diagram showing an example of a row selection driver. [Figure 10] A circuit block diagram showing an example of a column selection driver. [Figure 11] A circuit block diagram showing an example of an A / D converter. [Figure 12] A cross-sectional view showing an example of a semiconductor device. [Figure 13] A top view and cross-sectional view showing an example of a transistor. [Figure 14] A cross-sectional view and band diagram showing an example of a transistor. [Figure 15] High-resolution TEM images and local Fourier transform images of a cross-section of an oxide semiconductor. [Figure 16] A diagram showing the nanobeam electron diffraction pattern of an oxide semiconductor film, and a diagram showing an example of a transmission electron diffraction measurement device. [Figure 17] A diagram showing the changes in the crystal structure due to electron irradiation. [Figure 18] A figure illustrating an example of structural analysis by transmission electron diffraction measurement, and a high-resolution TEM image in a planar view. [Figure 19] A diagram showing an example of an electronic device. [Figure 20] A diagram showing an example of an RF tag. [Figure 21] A circuit diagram showing an example of a memory cell. [Figure 22] A circuit diagram showing an example of a memory cell. [Figure 23] A circuit diagram showing an example of a memory cell. [Figure 24] A circuit block diagram showing an example of a semiconductor device. [Figure 25] A circuit block diagram showing an example of a semiconductor device. [Modes for carrying out the invention]

[0025] The embodiments will be described below with reference to the drawings. However, the embodiments may differ in many ways. It is possible to implement it in any manner, and without deviating from its purpose and scope, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is The following descriptions of embodiments are not to be interpreted as being limited to the following.

[0026] Furthermore, in drawings, the size, layer thickness, or area may be exaggerated for clarity. There is a possibility of compatibility. Therefore, it is not necessarily limited to that scale. Note that the drawing is modeled after an ideal example. This is expressed formulaically and is not limited to the shapes or values ​​shown in the drawings. For example, noise Variations in signals, voltages, or currents, or signals, voltages, due to timing differences. Alternatively, it may include variations in current, etc. Furthermore, the embodiments described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. We will use it and omit the explanation of its repetition.

[0027] (Embodiment 1) In this embodiment, the circuit configuration of the memory cell in the semiconductor device according to one aspect of the present invention The operation of this method will be explained with reference to Figures 1 to 3.

[0028] <Example of memory cell configuration> Figure 1 is a circuit diagram of a memory cell 100 according to one embodiment of the present invention.

[0029] In the memory cell 100 shown in Figure 1, transistor 101, transistor 102, and Transistor 103, capacitive element 104, transistor 105, capacitive element 106, and It has node FN1 and node FN2. Furthermore, the memory cell 100 has bit line BL Power line SL, word line WLC1, word line WLOS1, word line WLC2 and word line It is electrically connected to WLOS2.

[0030] The gate of transistor 101 is electrically connected to the word line WLOS1, One of the sources and drains of 101 is electrically connected to the bit line BL, and the transistor The source and drain of terminal 101 are electrically connected to node FN1, and the transient The second gate of sta101 is electrically connected to the wiring to which signal BG1 is supplied.

[0031] The gate of transistor 102 is electrically connected to node FN1, and transistor 102 One of the source and drain of the transistor 10 is electrically connected to the bit line BL. The other end of the source and drain of transistor 2 is connected to one end of the source and drain of transistor 103. They are electrically connected.

[0032] The gate of transistor 103 is electrically connected to node FN2, and transistor 103 The source and drain of the other are electrically connected to the power line SL.

[0033] One terminal of the capacitive element 104 is electrically connected to the word line WLC1, and the capacitive element 104 The other terminal is electrically connected to node FN1.

[0034] The gate of transistor 105 is electrically connected to the word line WLOS2, One of the sources and drains of the 105 is electrically connected to the bit line BL, and the transistor The source and drain of TA105 are electrically connected to node FN2, and the transient The second gate of ST105 is electrically connected to the wiring to which signal BG2 is supplied.

[0035] One terminal of the capacitive element 106 is electrically connected to the word line WLC2. The other terminal is electrically connected to node FN2.

[0036] Node FN1 has the function of holding binary or multi-valued data. FN1 is M bit (2 M It has the function of storing data (where M is a natural number greater than or equal to 1). Specifically, if the data is 2 bits, it will have 4 values ​​(2 2 This is data from four voltage levels. It is a signal that has a difference of 1.

[0037] Similarly, node FN2 has the ability to hold binary or multi-valued data. Node FN2 is N bits (2 N A function to hold data (where N is a natural number greater than or equal to 1). To possess.

[0038] The above M-bit data and N-bit data are supplied to the bit line. The data from the bit line is supplied to node FN1 via transistor 101. Furthermore, the above N bits of data are transmitted from the bit line to node F via transistor 105. It is given to N2.

[0039] In this specification, the potential of node FN1 or node FN2 corresponds to the voltage of bit line BL. The process of creating a certain potential is called writing data to a memory cell. Also, the bit line BL The potential of the memory cell will be such that it corresponds to the potential of node FN1 or node FN2. It means reading data from there.

[0040] Write signals are applied to the word lines WLOS1 and WLOS2.

[0041] The write signal is used to apply the potential of the bit line BL to node FN1 or FN2, This is a signal that causes either transistor 101 or transistor 105 to conduct.

[0042] Read signals are applied to the word lines WLC1 and WLC2.

[0043] The read signal is used to selectively read data from the memory cell, one of the capacitive elements 104. This is a signal applied to one of the terminals or one of the terminals of the capacitive element 106.

[0044] Transistors 101 and 105 will be described as n-channel type transistors. Furthermore, transistors 102 and 103 will be described as p-channel type transistors. It shall be.

[0045] Transistors 101 and 105 switch between a conductive state and a non-conductive state, thereby transmitting data. It functions as a switch to control writing. Furthermore, by maintaining a non-conductive state... It has the function of maintaining the potential based on the written data.

[0046] Furthermore, transistors 101 and 105 allow current to flow between their source and drain when they are in a non-conductive state. It is preferable to use a transistor with a low off-current. Here, Low current means that at room temperature, with a voltage of 10V between the source and drain, the channel The normalized off-current per 1 μm of width is 10 × 10 -21 This means being less than or equal to A. As an example of a transistor with such a low off-current, a transistor having an oxide semiconductor in its semiconductor layer is a transistor. One example is Njista.

[0047] In the configuration of the memory cell 100 shown in Figure 1, by maintaining a non-conductive state, the written data It maintains a potential based on the t. Therefore, it involves charge transfer at nodes FN1 and FN2. Transistors with low off-currents are used as switches to suppress fluctuations in potential. Particularly preferable.

[0048] Transistors 102 and 103, according to the potential of nodes FN1 and FN2, are connected to the bit line BL. It has the function of conducting current between itself and the power line SL.

[0049] Furthermore, transistors 102 and 103 are transistors with small threshold voltage variations. It is preferable that it be able to stay there. Here, a transistor with small threshold voltage variation is a transistor When transistors are manufactured using the same process, the allowable threshold voltage difference is within 100mV. This refers to a transistor that can be formed. Specifically, the channel is formed from single-crystal silicon. Examples of transistors that are used include:

[0050] Furthermore, the second gates of transistors 101 and 105 are transistors 101 and 10 Function to control the threshold voltage of 5, or to improve the on-current of transistors 101 and 105. It has the function of enabling, but it may be omitted in some cases.

[0051] <Timing Chart> Next, an example of the operation of the memory cell 100 will be explained using the timing charts in Figures 2 and 3. I will reveal it.

[0052] The timing charts shown in Figures 2 and 3 show the bit line BL and power line S of memory cell 100. L, Word line WLOS1, Word line WLC1, Node FN1, Word line WLOS2, Word Figure 2 shows the potential change at node WLC2 and node FN2. Figure 3 shows the timing chart for writing data, and Figure 2 shows the data being written to memory cell 100. This chart shows the timing for reading the data.

[0053] In Figures 2 and 3, the power line SL, and the word lines WLOS1 and WLOS2 are at high power supply potential. and potential V H1 A low power supply potential V is provided. GND The potential V is given. GND The potential can also be ground potential GND. Also, potential V H1 At H level potential, potential V GN D This is sometimes called the L-level potential. Furthermore, the word lines WLOS1 and WLOS2 are potentials. V GND Lower potential -V L1 Potential -V may also be given. L1 is a negative potential ( -V L1 It is preferable that the voltage is <0V.

[0054] In Figures 2 and 3, the word lines WLC1 and WLC2 have a potential V as the high power supply potential. H2 but Given, the low power supply potential is potential V GND The potential V is given. GND is ground The potential can be GND. Also, the potential V H2 At H level potential, potential V GND L-level potential It is sometimes called that. Furthermore, the word lines WLC1 and WLC2 have a potential V GND Lower electricity Place-V L2 Potential -V may also be given. L2 This is a negative potential (-V L2 <0V) It is preferable to do so.

[0055] <Writing operation> The writing operation of memory cell 100 will be explained according to the timing chart in Figure 2. cormorant.

[0056] Figure 2 consists of four periods, p0 through p3, with period p0 being the initial period and period p1 being the first period. Period p2 is the period during which data is written to node FN1, and period p2 is the period during which data is written to node FN2. The interval p3 represents the period for which the written data is retained. Also, as shown in Figure 2 The timestamps T0 through T8 are added to explain the timing of the operation.

[0057] First, in period p0, the bit line BL is V GND Initialized to V GND Maintain, word line WLOS1 is given a potential at L level, and word line WLC1 is given a potential at H level. A potential is applied to the word line WLOS2, and a potential at the L level is applied to the word line WLC. Point 2 is given a potential at the H level.

[0058] Next, at time T0, the potential of the word line WLOS1 changes from L level to H level. The potential of the word line WLC1 changes from a high level to a low level. At this time, the transistor 101 turns on, and the connection between bit line BL and node FN1 becomes conductive, and node F N1 has a potential of V GND It will be initialized.

[0059] Next, at time T1, a potential V1 is applied to the bit line BL, creating a conductive state with the bit line BL. The potential V1 is also written to node FN1 located at [location].

[0060] Note that the parts with hatching patterns in the timing charts of Figures 2 and 3 are hatched. The ching pattern is given a range of potentials, that is, multi-level data is given This indicates that it is possible to obtain it. For example, when writing 4 bits of data to node FN1: The potential V1 is 2 4 It can take on 16 different potential values.

[0061] Next, at time T2, the potential of the word line WLOS1 is set to L level, and transistor 101 After turning it off, at time T3, the potential of bit line BL is set to V GND Initialize it to this. In this state, node FN1 becomes electrically floating and maintains the potential V1.

[0062] Next, at time T4, the potential of the word line WLC1 is set to the H level, and capacitive coupling is performed. The potential of FN1 is V1+V H2 Raise it up to this level. By keeping the potential of node FN1 high, The p-channel transistor 102 remains off, between the bit line BL and the power line SL. This prevents leakage current from flowing. Also, at the same time, the potential of the word line WLOS2 is controlled by L. The voltage is changed from bell to H level, and the potential of the word line WLC2 is changed from H level to L level. At this time, transistor 105 turns on and node FN2 is initialized.

[0063] Furthermore, the potential of the word line WLC1 is transmitted to node FN1 via the capacitive element 104. In this case, the capacitance of the capacitive element 104 is sufficiently larger than the gate capacitance of the transistor 101, and It is preferable that the capacitance of the capacitive element 104 is sufficiently larger than the gate capacitance of the transistor 102. In this embodiment, for the sake of simplicity, the potential applied to the word line WLC1 is, The potential V is then transmitted directly to node FN1 (for example, to word line WLC1). H2 If you give it, The potential of FN1 is from potential V1 to potential V1+V H2 It is explained that it will rise to capacity Capacitance of element 104, gate capacitance of transistor 101, gate capacitance of transistor 102 Depending on the relative magnitudes, the potential applied to the word line WLC1 may be directly transmitted to node FN1. It may not always be the case.

[0064] Next, at time T5, a potential V2 is applied to bit line BL, and a potential V2 is applied to node FN2. This is written. Note that the potential V2 is given as multi-level data. For example, node FN2 When writing 4 bits of data, the potential V2 is 2 4 It can take on a potential of 16 values. Cut.

[0065] Next, at time T6, the potential of the word line WLOS2 is changed from the H level to the L level. Turn off transistor 105, and at time T7, set the potential of bit line BL to V GND Initialize At this time, node FN2 is in an electrically floating state and therefore maintains the potential V2.

[0066] Next, at time T8, the potential of the word line WLC2 is changed from L level to H level, and the capacitance is... The potential of node FN2 is V2+V H2 Raise the potential. Maintain a high potential at node FN2. Therefore, the p-channel transistor 103 remains off, and the power line from the bit line BL to the power line This prevents leakage current from flowing to the SL.

[0067] Furthermore, the potential of the word line WLC2 is transmitted to node FN2 via the capacitive element 106. In this case, the capacitance of the capacitive element 106 is sufficiently larger than the gate capacitance of the transistor 105, It is preferable that the capacitance of the capacitive element 106 is sufficiently larger than the gate capacitance of the transistor 103. In this embodiment, for the sake of simplicity, the potential applied to the word line WLC2 is, This is then transmitted to node FN2 (for example, the potential V is transmitted to word line WLC2). H2 If you give it, The potential of FN2 is V2 + V H2 It is explained that it will rise to capacity Capacitance of element 106, gate capacitance of transistor 105, gate capacitance of transistor 103 Depending on the relative magnitudes, the potential applied to the word line WLC2 may be directly transmitted to node FN2. It may not always be the case.

[0068] During period p3 after time T8, the data written to nodes FN1 and FN2 is: Each is held separately.

[0069] As described above in the timing chart in Figure 2, the write operation was performed on nodes FN1 and FN2 It is possible to write multi-valued data to it.

[0070] Furthermore, during period p1, the potential V applied to the word line WLOS1 H1 The potential V1 is It is preferable that the threshold voltage of the transistor 101 is at a potential higher than the applied potential. If the potential V1 is 3V, and the threshold voltage of transistor 101 is 1V, then the potential V H It is preferable that 1 is 4V (3V + 1V) or higher. This is because the bit line BL is connected to the node When writing a potential of 3V to FN1, if the potential of the word line WLOS1 is less than 4V, Before the potential of the FN1 reaches 3V, the potential between the gate and source of transistor 101 Difference (V GS When the voltage falls below the threshold voltage, transistor 101 turns off, and node FN1 This is because it is not possible to write a potential of 3V.

[0071] Similarly, during period p2, the potential V applied to the word line WLOS2 H1 At potential V2 It is preferable that the threshold voltage of transistor 105 is at a potential higher than the applied potential.

[0072] Note that in this specification, V GS This refers to the electrical current between the gate and the source, relative to the source. This refers to the potential difference. For example, if the source is given a potential of 1V and the gate is given a potential of 3V, then V G S It is 2V. For example, if a potential of 3V is applied to the source and 1V to the gate, V GS The voltage is -2V.

[0073] <Read operation> Data written to memory cell 100 is read according to the timing chart in Figure 3. Let's explain how it works.

[0074] Figure 3 consists of four periods, p3 through p6, and period p3 is the same as period p3 in Figure 2. Period p4 is the period during which the data is retained, and period p is the period during which the data from node FN1 is read. 5 is the period for reading data from node FN2, and period p6 is the period for retaining the data. This is shown. Also, the times T9 to T13 shown in Figure 3 are used to explain the timing of the operation. It was attached to it.

[0075] First, at time T9, the bit line BL is at potential V BL It is pre-charged.

[0076] Next, at time T10, the bit line BL is made electrically floating. That is, the bit Line BL is in a state where its potential fluctuates due to the charging or discharging of electric charge. This state is called a bit line. This is achieved by turning off the switch that supplies potential to BL.

[0077] Also, at time T10, the potential of the word line WLC1 decreases from the H level to the L level, and the capacitance Due to the coupling, the potential of node FN1 also becomes potential V1+V H2 The potential decreases from V1 to node F. When the potential of N1 decreases, the V of the p-channel transistor 102 GS The absolute value of is large As a result, transistor 102 turns on. At the same time, the potential of word line WLC2 reaches the high level. From the potential -V L2 The potential decreases to V2+V due to capacitive coupling, and the potential of node FN2 also decreases to V2+V. H Potential V2-V L2 It decreases. When the potential of node FN2 decreases, the p-channel type V of transistor 103 GS As the absolute value of increases, transistor 103 turns on. When both transistor 102 and transistor 103 are turned on, the bit line BL and the power supply The space between lines SL becomes conductive, current flows, and the bit line BL discharges its charge. The potential decreases.

[0078] When the potential of the bit line BL decreases due to discharge, the V of transistor 102 GS The absolute value of and V of transistor 103 GS The absolute values ​​of both decrease. V GS However, when it reaches the threshold voltage of that transistor, the discharge is complete and the bit The potential of line BL converges to a constant potential. During period p4, node FN2 is closer to node FN1. Because a lower potential is given to transistor 103 than to transistor 102, transistor 103 is more likely to be at a lower potential than transistor 102. Rimo, V GSThe absolute value is larger. In other words, transistor 103 is greater than transistor 102. It has lower channel resistance and higher on-current. Therefore, discharge of the bit line BL begins. And the V of transistor 102 GS The first one to reach the threshold voltage, and the second one, transistor 102 It will turn off first.

[0079] When transistor 102 is turned off, the bit line BL converges to a constant potential (potential V1'). This potential V1' is approximately the threshold voltage of transistor 102, derived from the potential of node FN1. It is obtained as a subtracted value. In other words, the potential V1' of bit line BL is the high potential of node FN1. It can be obtained in a form that reflects the low. By using this difference in potential to determine the data, It is possible to read multi-level data written to code FN1.

[0080] At time T10, the potential of the word line WLOS2 is changed from L level to -V. L1 Change to Therefore, a change in the potential of bit line BL or node FN2 causes transistor 1 This prevents 05 from being turned on.

[0081] Next, at time T11, the potential of bit line BL is again set to potential V. BL Restore to Precha Perform the operation. At the same time, the potential of all word lines, and the potential of nodes FN1 and FN2 are measured over a period of p Return to state 3 and turn off transistors 102 and 103.

[0082] Next, at time T12, the bit line BL is made electrically floating. This state is bit This is achieved by turning off the switch that applies potential to line BL.

[0083] Also, at time T12, the potential of the word line WLC1 changes from H level to potential -V. L2 It changed to Then, the potential of the word line WLC2 changes from the H level to the L level. At this time, due to capacitive coupling The potential of node FN1 is potential V1+V H2 From potential V1-V L2 It decreases to node F The potential of N2 is potential V2 + V H2 The potential drops from to V2. As a result, transistor 10 2, 103 turns on, and conduction occurs between bit line BL and power line SL, bit line B L discharges its charge, and the potential of the bit line BL decreases.

[0084] During period p5, node FN1 is given a lower potential than node FN2, Transistor 102 has a higher V than transistor 103. GS The absolute value is large. Transistor 102 has a lower channel resistance than transistor 103, and the on-current is It is large. Therefore, when the discharge of the bit line BL begins, the V of transistor 103 GS The The threshold voltage is reached first, and transistor 103 turns off first.

[0085] When transistor 103 is turned off, the bit line BL converges to a constant potential (potential V2'). This potential V2' is approximately the threshold voltage of transistor 103, derived from the potential of node FN2. It is obtained as a subtracted value. In other words, the potential V2' of bit line BL is the high potential of node FN2. It can be obtained in a form that reflects the low. By using this difference in potential to determine the data, It is possible to read multi-level data written to code FN2.

[0086] At time T12, the potential of the word line WLOS1 is changed from L level to -V. L1Change to Therefore, a change in the potential of bit line BL or node FN2 causes transistor 1 This prevents 05 from being turned on.

[0087] Next, at time T13, the bit line BL is V GND Initialize to, all word lines, no The potentials of FN1 and FN2 are returned to the state of period p3, and transistors 102 and 103 are turned off. Then, the potentials of nodes FN1 and FN2 are maintained.

[0088] As described above in the timing chart in Figure 3, the read operation for nodes FN1 and FN2 It is possible to read multi-valued data written to it.

[0089] For example, 8-bit data, i.e., 256 (=2 8 Write the potential value of ) to one node. Let's consider the case where it gets crowded. In that case, if the potential range of one value is 0.17V, the data will be retained. The potential range applied to the node is 0.17V × 256 = 43.52V. In other words, To store 8 bits of data in one node, a power supply potential of approximately 45V is required for the memory cell. It is necessary to provide this voltage, but this power supply potential is impractical as it will cause transistor destruction. It is not a valid value.

[0090] On the other hand, when writing 8 bits of data to the memory cell 100 shown in this embodiment, 8 The bit data is split into two parts: two 4-bit data pieces and one 4-bit data piece, and one of them is used as a node. FN1 can store the other in node FN2. Therefore, 16 (=2 4 )value One node will be responsible for the potential. If the range of the single potential is 0.17V, then one The potential range applied to each node is 0.17V × 16 = 2.72V. This is a realistic value for driving the Morissel.

[0091] As described above, by using the memory cell 100 according to one aspect of the present invention, 8-bit data can be stored. This makes it possible to provide a semiconductor device that can store data.

[0092] Furthermore, the number of bits of data that the memory cell 100 can store is not limited to 8 bits, but can be various. It can store data of a certain number of bits. For example, node FN1 can store M bits (2 M Store the data of the value, and set node FN2 to N bits (2 N If the value is stored, Cell 100 is M+N bits (2 M+N It becomes possible to store data of a value.

[0093] The memory cell 100 in Figure 1 is connected to transistor 101, as shown in the circuit diagram in Figure 21(A). A common signal BG may be applied to the second gate of 105.

[0094] The memory cell 100 in Figure 1 may be configured according to the circuit diagram shown in Figure 22(A). Figure 22(A) The circuit diagram shown has two bit lines BL1 and BL2, and transistor 1 The point where 01 and transistor 105 are connected to the common word line WLOS is the circuit in Figure 1. The diagram is different. Also, the second gate and transistor of transistor 101 shown in Figure 22(A) A common signal may be applied to the second gate of sta 105, similar to Figure 21(A). Also, In some cases, these second gates may be omitted.

[0095] The memory cell 100 in Figure 1 may be configured according to the circuit diagram shown in Figure 23(A). Figure 23(A) The circuit diagram shown has a transistor 107, a capacitor element 108, a transistor 109, and a node F N3, a word line WLOS3, and a word line WLC3, and is different from the circuit diagram shown in FIG. 1 . Also, a common signal may be applied to the second gates of the transistor 101, the transistor 105, and the transistor 107 shown in FIG. 23(A), similar to FIG. 21(A). Also, in some cases, these second gates may be omitted. Note that the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0096]

[0097] (Embodiment 2) In this embodiment, the circuit configuration and operation of a memory cell included in a semiconductor device according to an aspect of the present invention will be described with reference to FIGS. 4 to 6.

[0098] 〈Configuration Example of Memory Cell〉 FIG. 4 is a circuit diagram of a memory cell 110 which is an aspect of the present invention.

[0099] In the memory cell 110 shown in FIG. 4, there are a transistor 101, a transistor 112, a transistor 113, a capacitor element 104, a transistor 105, a capacitor element 106, a node FN1, and a node FN2. Also, the memory cell 110 is electrically connected to a bit line BL, a power supply line SL, a word line WLC1, a word line WLOS1, a word line WLC2, and a word line WLOS2.

[0100] The memory cell 110 replaces the transistors 102 and 103 of the memory cell 100 shown in Embodiment 1 with transistors 112 and 113 which are n-channel type transistors. ​ Yes. Hereinafter, transistors 101, 112, 113, and 105 will be described as n-channel transistors.

[0101] Transistors 112 and 113 have the function of flowing a current between the bit line BL and the power supply line SL according to the potentials of nodes FN1 and FN2.

[0102] Note that it is preferable to use transistors with a small variation in threshold voltage for transistors 112 and 113. Here, a transistor with a small variation in threshold voltage means a transistor in which the allowable difference in threshold voltage is within 100 mV when the transistors are manufactured in the same process. Specifically, a transistor in which the channel is formed of single crystal silicon can be mentioned.

[0103] For details regarding other components of memory cell 110, refer to the description of memory cell 100.

[0104] 〈Timing Chart〉 Next, an example of the operation of memory cell 110 will be described using the timing charts of FIGS. 5 and 6.

[0105] The timing charts shown in FIGS. 5 and 6 show the potential changes of the bit line BL, power supply line SL, word line WLOS1, word line WLC1, node FN1, word line WLOS2, word line WLC2, and node FN2 of memory cell 110. FIG. 5 represents the timing chart when writing data to memory cell 110, and FIG. 6 represents the timing chart when reading the data written to memory cell 110 in FIG. 5.

[0106] ​​​​​​​​​​​​In FIGS. 5 and 6, the power line SL is supplied with a potential V as a high power potential H0 and a potential V as a low power potential. The potential V GND may also be the ground potential GND. GND In addition, the potential V may be called the H-level potential, and the potential V H0 may be called the L-level potential in some cases GND .

[0107] In FIGS. 5 and 6, the word lines WLOS1 and WLOS2 are supplied with a potential V as a high power potential and a potential V as a low power potential. The potential V H1 may also be the ground potential GND. GND In addition, the potential V G ND may be called the H-level potential, and the potential V H1 may be called the L-level potential in some cases. Further, the word lines WLOS1 and WLOS2 GND may be supplied with a potential -V lower than the potential V . The potential -V GND is preferably a negative L1 [[ID=Z41]]potential (-V L1 < 0V). <00W0097>

[0108] In FIGS. 5 and 6, the word lines WLC1 and WLC2 are supplied with a potential V as a high power potential and a potential V as a low power potential. The potential V H2 may also be the ground potential GND. GND In addition, the potential V GND may be called the H-level potential, and the potential V H2 may be called the L-level potential in some cases. Further, the word lines WLC1 and WLC2 are supplied with a potential GND lower than the potential V -V V GND L2may also be provided. Potential -V L2 is a negative potential (- V L2 <0V) and is preferably so.

[0109] 〈〈Writing operation〉〉 An example of the writing operation of the memory cell 110 will be described along the timing chart of FIG. 5. to explain.

[0110] FIG. 5 is composed of four periods from period p0 to p3. Period p0 is the initial period, period p1 is the period for writing data to node FN1, period p2 is the period for writing data to node FN2, and period p3 is the period for holding the written data, respectively. Also, the times T0 to T8 shown in FIG. 5 are added to explain the timing of the operation. and period p3 represents the period for holding the written data, respectively. Also, the times T0 to T8 shown in FIG. 5 are added to explain the timing of the operation. and period p3 represents the period for holding the written data, respectively. Also, the times T0 to T8 shown in FIG. 5 are added to explain the timing of the operation. to explain the timing of the operation.

[0111] First, in period p0, the bit line BL and the power supply line SL are initialized to the potential V GND , and the word line WLOS1 is given the potential -V , the word line WLC1 is given the potential -V L1 , the word line WLOS2 is given the potential -V L2 is given, and the word line WLC2 is given the potential -V , the word line WLOS2 is given the potential -V L1 , and the word line WLC2 is given the potential -V L2 is given. is given.

[0112] Next, at time T0, a high - level potential is given to the word line WLOS1, and a low - level potential is given to the word line W LC1. At this time, the transistor 101 turns on, and the bit line BL and the node FN1 become conductive, and the node FN1 is initialized to the potential V . GND is initialized to ​​​​​​The potential V1 is written to node FN1 located at [location].

[0114] Note that the parts with hatching patterns in the timing charts of Figures 5 and 6 are hatched. The ching pattern is given a range of potentials, that is, multi-level data is given This indicates that it can be obtained. For example, when 4 bits of data are written to node FN1 In total, the potential V1 is 2 4 It can take on 16 different potential values.

[0115] Furthermore, in order to keep transistor 112 off at time T1, the power line SL is connected to A potential of level H is applied. At this time, the potential V applied to the power line SL is given. H0 is, bit It is preferable that the potential V1 applied to line BL and node FN1 is higher than the potential V H0 but By satisfying the aforementioned conditions, the V of transistor 112 GS It can be kept at 0V.

[0116] Next, at time T2, a low-level potential is applied to the word line WLOS1, and the transient The Ta101 will be turned off.

[0117] Next, at time T3, the bit line BL and the power line SL are at potential V GND It will be initialized. At this time, node FN1 is electrically floating and maintains the potential V1.

[0118] Next, at time T4, a high-level potential is applied to the word line WLOS2, and the word line W A low-level potential is applied to LC2. At this time, transistor 105 turns on, and the The wire BL and node FN2 become conductive, and node FN2 is at potential V GND Initialized to ru.

[0119] Furthermore, at time T4, the potential -V is present on the word line WLC1. L2 Given, to node FN1 Potential V1-V L2 This is given. If the potential of node FN1 is kept low, an n-channel type Transistor 112 remains off, and leakage flows between the bit line BL and the power line SL. The current is cut off. At this time, to prevent transistor 101 from turning on, the potential is reduced. V L1 This is given to the word line WLOS1.

[0120] Furthermore, the potential of the word line WLC1 is transmitted to node FN1 via the capacitive element 104. In this case, the capacitance of the capacitive element 104 is sufficiently larger than the gate capacitance of the transistor 101, and It is preferable that the capacitance of the capacitive element 104 is sufficiently larger than the gate capacitance of the transistor 112. In this embodiment, for the sake of simplicity, the potential applied to the word line WLC1 is, This is then transmitted to node FN1 (for example, the potential of word line WLC1 is potential V). GND From Place-V L2 When this changes, the potential of node FN1 changes from potential V1 to potential V1-V L2 It changes to It explains that the capacitance of the capacitive element 104 and the gate capacitance of the transistor 101 are... Depending on the relationship with the gate capacitance of the transistor 112, the word line WLC1 is given In some cases, the electric potential may not be transmitted directly to node FN1.

[0121] Next, at time T5, a potential V2 is applied to bit line BL, and a potential V2 is applied to node FN2. This is written. Note that the potential V2 can take on multi-level data. For example, 4-bit data If it is written to node FN2, the potential V2 is 2 4It can take on a potential of 16 values. can.

[0122] Furthermore, in order to keep transistor 113 off at time T5, the power line SL is connected to A potential at level H is applied. At this time, the potential V applied to the power line SL is given. H0 , It is preferable that the potential V2 applied to the T-wire BL and node FN1 is higher than the potential V H0 When the above conditions are met, the V of transistor 113 GS The voltage is kept at 0V.

[0123] Next, at time T6, a low potential is applied to the word line WLOS2, and the transient The Ta105 will be turned off.

[0124] Next, at time T7, the bit line BL and the power line SL are at potential V GND It will be initialized. At this time, node FN2 maintains potential V2 because it is electrically floating.

[0125] Next, at time T8, the potential -V is applied to the word line WLC2. L2 Given, node FN2 Potential V2-V L2 This is given. If the potential of node FN2 is kept low, an n-channel type Transistor 113 remains off, and leakage flows between the bit line BL and the power line SL. The current is interrupted. Also, a potential of -V is applied to the word line WLOS2. L1 Given, transistor 1 This prevents 05 from being turned on.

[0126] Furthermore, the potential of the word line WLC2 is transmitted to node FN2 via the capacitive element 106. In this case, the capacitance of the capacitive element 106 is sufficiently larger than the gate capacitance of the transistor 105, It is preferable that the capacitance of the capacitive element 106 is sufficiently larger than the gate capacitance of the transistor 113. In this embodiment, for the sake of simplicity, the potential applied to the word line WLC2 is, This is then transmitted to node FN2 (for example, the potential of word line WLC2 is potential V). GND From Place-V L2 When this changes, the potential of node FN2 changes from potential V2 to potential V2-V L2 It changes to It is explained that the capacitance of the capacitive element 106 and the gate capacitance of the transistor 105 are, Depending on the relationship with the gate capacitance of transistor 113, it is supplied to the word line WLC2. In some cases, the resulting potential may not be transmitted directly to node FN2.

[0127] During period p3 after time T8, the data written to nodes FN1 and FN2 The data is held separately.

[0128] As described above in the timing chart in Figure 5, the write operation performed on node FN1 and node FN1 Multi-level data can be written to FN2.

[0129] Furthermore, during period p1, the potential V applied to the word line WLOS1 H1 The potential V1 is It is preferable that the threshold voltage of the transistor 101 is at a potential higher than the applied potential.

[0130] Similarly, during period p2, the potential V applied to the word line WLOS2 H1 At potential V2 It is preferable that the threshold voltage of transistor 105 is at a potential higher than the applied potential.

[0131] <<Read operation>> Read the data written to the memory cell 110 according to the timing chart in Figure 6. Let's explain how it works.

[0132] Figure 6 consists of four periods, p3 through p6, and period p3 is the same as period p3 in Figure 5. Period p4 is the period during which the data is retained, and period p is the period during which the data from node FN1 is read. 5 is the period for reading data from node FN2, and period p6 is the period for retaining the data. This is represented. Also, the times T9 to T15 shown in Figure 6 are used to explain the timing of the operation. It was attached to it.

[0133] First, at time T9, a potential of L level is applied to the word line WLOS1, and the word line W When an L-level potential is applied to LC1, the potential of node FN1 becomes potential V1- due to capacitive coupling. V L2 The potential is raised from to V1. When the potential of node FN1 is raised, n-channel V of Nell-type transistor 112 GS As the value increases, transistor 112 turns on.

[0134] Furthermore, at time T9, a low-level potential is applied to the word line WLOS2, and the word line WLC A high-level potential is applied to node 2, and due to capacitive coupling, the potential at node FN2 becomes potential V2-V L Potential V2+V H2 It is raised to. When the potential of node FN2 is raised, n V of channel-type transistor 113 GS As the size increases, transistor 113 turns on. ru.

[0135] Next, at time T10, bit line BL becomes electrically floating. That is, bit Line BL enters a state where its potential fluctuates due to the charging or discharging of electric charge. This state is called a bit line. This can be achieved by turning off the switch that supplies potential to BL.

[0136] Also, at time T10, a high-level potential is applied to the power line SL. When a potential is applied, a potential difference is created between the bit line BL and the power line SL, and the power line SL Current flows from the terminal to the bit line BL. The bit line BL is charged, and the potential of the bit line BL rises. do.

[0137] When the potential of the bit line BL rises due to charging, the V of transistor 112 GS And, Trans V of Sta113 GS Both decrease. The V of either transistor decreases. GS However, When the voltage equals the transistor's threshold voltage, charging is complete, and the potential of the bit line BL becomes equal to the transistor's threshold voltage. It converges to a constant potential. During period p4, a higher potential is applied to node FN2 than to node FN1. Therefore, transistor 113 has more V than transistor 112. GS Large In other words, transistor 113 has a lower channel resistance than transistor 112. The on-current is large. Therefore, when charging of the bit line BL begins, the V of transistor 112 GS The threshold voltage is reached first, and transistor 112 turns off first.

[0138] When transistor 112 is turned off, the bit line BL converges to a constant potential (potential V1'). This potential V1' is approximately the threshold voltage of transistor 112, derived from the potential of node FN1. It is obtained as a subtracted value. In other words, the potential V1' of bit line BL is the high potential of node FN1. It is obtained in a form that reflects the low. By using this difference in potential to determine the data, the node FN The multi-valued data written to 1 can be read.

[0139] Next, at time T11, the bit line BL and the power line SL are at potential V GND Initialized to .

[0140] Next, at time T12, a high-level potential is applied to the word line WLC1, and capacitive coupling occurs. Therefore, the potential of node FN1 changes from potential V1 to potential V1+V H2 It is raised to the same time. When a low-level potential is applied to the word line WLC2, the potential at node FN2 is potential V2+V H2 The potential is lowered to V2. Transistors 112 and 113 are both turned on. ru.

[0141] Next, at time T13, bit line BL becomes electrically floating.

[0142] Also at the same time, at time T13, a high-level potential is applied to the power line SL. When the potential reaches the H level, a potential difference is created between the bit line BL and the power line SL, and the power line SL Current flows from the terminal to the bit line BL. The bit line BL is charged, and the potential of the bit line BL rises. do.

[0143] When the potential of the bit line BL rises due to charging, the V of transistor 112 GS And, Trans V of Sta113 GS Both decrease. The V of either transistor decreases. GS However, When the voltage equals the transistor's threshold voltage, charging is complete, and the potential of the bit line BL becomes equal to the transistor's threshold voltage. It converges to a constant potential. During period p5, a higher potential is applied to node FN1 than to node FN2. Therefore, transistor 112 has more V than transistor 113. GS It's big. In other words, transistor 112 has a lower channel resistance than transistor 113, and turns on The current is large. Therefore, when charging of the bit line BL begins, the voltage of transistor 113 increases. GS The threshold voltage is reached first, and transistor 113 turns off first.

[0144] When transistor 113 is turned off, the bit line BL converges to a constant potential (potential V2'). This potential V2' is approximately the threshold voltage of transistor 113, derived from the potential of node FN2. It is obtained as a subtracted value. In other words, the potential V2' of bit line BL is the high potential of node FN2. It can be obtained in a form that reflects the low. By using this difference in potential to determine the data, It is possible to read multi-level data written to code FN2.

[0145] Next, at time T14, the bit line BL and the power line SL are at potential V GND Initialized to .

[0146] Next, at time T15, all the wiring and nodes in Figure 6 are given the same potential as during period p3. The potentials of nodes FN1 and FN2 are maintained.

[0147] As described above in the timing chart in Figure 6, the read operation for nodes FN1 and FN2 It is possible to read multi-valued data written to it.

[0148] For example, 8-bit data, i.e., 256 (=2 8 Write the potential value of ) to one node. Let's consider the case where it gets crowded. In that case, if the potential range of one value is 0.17V, the data will be retained. The potential range applied to the node is 0.17V × 256 = 43.52V. In other words, To store 8 bits of data in one node, a power supply potential of approximately 45V is required for the memory cell. It is necessary to provide this voltage, but this power supply potential is impractical as it will cause transistor destruction. It is not a valid value.

[0149] On the other hand, when writing 8 bits of data to the memory cell 110 shown in this embodiment, 8 The bit data is split into two parts: two 4-bit data pieces and one 4-bit data piece, and one of them is used as a node. FN1 can store the other in node FN2. Therefore, 16 (=2 4 )value One node will be responsible for the potential. If the range of the single potential is 0.17V, then one The potential range applied to each node is 0.17V × 16 = 2.72V. This is a realistic value for driving the Morissel.

[0150] As described above, by using the memory cell 110 according to one aspect of the present invention, 8-bit data can be stored. It becomes possible to provide a semiconductor device that can store memories. Also, the memory cell 110 can store memories. The number of bits in the data is not limited to 8 bits; it is possible to store data with various bit counts. This is possible. For example, node FN1 can have M bits (2 M Store the data of the value, node FN 2 with N bits (2 N When a value is stored, the memory cell 110 will have M+N bits (2 M+N It becomes possible to store data of a value.

[0151] The memory cell 110 in Figure 4 is connected to the transistor 101, as shown in the circuit diagram in Figure 21(B). A common signal BG may be applied to the second gate of 105.

[0152] The memory cell 110 in Figure 4 may be configured according to the circuit diagram shown in Figure 22(B). Figure 22(B) The circuit diagram shown has two bit lines BL1 and BL2, and transistor 1 The point where 01 and transistor 105 are connected to the common word line WLOS is the circuit in Figure 4. The diagram is different. Also, the second gate and transistor of transistor 101 shown in Figure 22(B) A common signal may be applied to the second gate of sta 105, similar to Figure 21(B). Also, In some cases, these second gates may be omitted.

[0153] The memory cell 110 in Figure 4 may be configured according to the circuit diagram shown in Figure 23(B). Figure 23(B) The circuit diagram shown includes transistor 107, capacitor 108, transistor 114, and node F. It differs from the circuit diagram shown in Figure 4 in that it has N3, word line WLOS3, and word line WLC3. Also, as shown in Figure 23(B), the second gate of transistor 101, transistor 105 The second gate of and the second gate of transistor 107 have a common connection, similar to Figure 21(B). A signal may be applied. Furthermore, in some cases, these second gates may be omitted.

[0154] In this embodiment, one aspect of the present invention has been described. Or, other embodiments may be described. In this section, one aspect of the present invention will be described. However, this aspect of the present invention is not limited to these. It is not possible. For example, one aspect of the present invention has been shown as an example of its application to a memory cell, but One aspect of the invention is not limited thereto. Depending on the circumstances, the present invention may be used in some cases or situations. One aspect of the present invention does not need to be applied to a memory cell. For example, one aspect of the present invention may apply to another function It may also be applied to circuits that have it.

[0155] Note that the configurations and methods shown in this embodiment may be adapted to the configurations and methods shown in other embodiments. They can be used in any combination.

[0156] (Embodiment 3) In this embodiment, a semiconductor device capable of performing the driving method described in Embodiment 1 is provided. Let's explain an example using a diagram.

[0157] <Example of semiconductor device configuration> Figure 7 shows an example configuration of a semiconductor device having the memory cell 100 described in Embodiment 1. This is a block diagram.

[0158] The semiconductor device 500 shown in Figure 7 is a memory cell with multiple memory cells 100 as described in Figure 4. Recell array 501, row selection driver 502, column selection driver 503, and A / D controller It has a converter 504. The semiconductor device 500 has m rows (where m is a natural number greater than or equal to 2) and n columns (n It has memory cells 100 arranged in a matrix of (2 or more natural numbers). Also, Figure 7 So, the word line connected to memory cell 100 in row (m-1) is the word line WLO S1[m-1], Word line WLC1[m-1], Word line WLOS2[m-1], Word The line WLC2[m-1] is shown, and as a word line connected to the memory cell 100 in the mth row, Word line WLOS1[m], Word line WLC1[m], Word line WLOS2[m], Word line This indicates bit line WLC2[m], and bit line B connected to memory cell 100 in the (n-1)th column. L[n-1] represents the bit line BL[n] connected to the nth column memory cell 100, where (n Power line SL connected to the memory cell 100 in the first row and the memory cell 100 in the nth row. This indicates that.

[0159] The memory cell array 501 shown in Figure 7 is a matrix of memory cells 100 as described in Figure 4. It is arranged in this manner. The explanation of each component of the memory cell 100 is the same as in Figure 4. Therefore, the explanation will be omitted, as it will be based on the explanation in Figure 4.

[0160] In the memory cell array 501 shown in Figure 7, adjacent memory cells share the power line SL. This configuration has been modified. By adopting this configuration, the area previously occupied by the power line SL is now available. The product is reduced. Therefore, in semiconductor devices employing this configuration, the amount per unit area is This allows for an improvement in memory capacity.

[0161] The row selection driver 502 selects the transistors 101 and tra in each row of the memory cell 100. Function to selectively activate the inverter 105, and in each row of the memory cell 100 This circuit has the function of selectively changing the potential of nodes FN1 and FN2. By providing the driver 502, the semiconductor device 500 writes data to the memory cell 100. Insertion and retrieval can be selected and performed row by row.

[0162] The column selection driver 503 selects node FN1 and node FN in each column of the memory cell 100. Function to selectively write data to 2, function to initialize the potential of bit line BL, and bit This circuit has the function of making the bit wire BL electrically floating. Specifically, bit wire B L contains the potentials and potentials V corresponding to the multi-level data. GND In a circuit that provides this via a switch Yes. By providing a column selection driver 503, the semiconductor device 500 can access the memory cell 100. Data can be written to and read from each column individually.

[0163] The A / D converter 504 converts the potential of the bit line BL, which is an analog value, into a digital value. It is a circuit equipped with the function to output to the outside. Specifically, a flash-type A / D converter It is a circuit that has a data. By including the A / D converter 504, the semiconductor device 500 The potential of the bit line BL corresponding to the data read from memory cell 100 is output externally. It is possible.

[0164] Note that the A / D converter 504 will be described as a flash-type A / D converter. Successive approximation, multi-slope, or delta-sigma type A / D converters may also be used.

[0165] Figure 8 shows the memory cell 100 in Figure 7 replaced with the memory cell 110 described in Embodiment 2. This is what was obtained. For details, please refer to the description in Figure 7.

[0166] The semiconductor device 500 shown in Figures 7 and 8 may be configured as shown in the block diagram in Figure 24. The block diagram shown in 24 shows that the second gate of the transistor connected to the same word line is This is the case when connected to a standard wiring. A train connected to word line WLOS1[m-1] The second gate of the inverter is connected to the wiring to which the signal BG1[m-1] is applied. The second gate of the transistor connected to the word line WLOS2[m-1] is the signal BG2 [m-1] is connected to the given wiring. It is connected to word line WLOS1[m]. The second gate of the transistor is connected to the wiring to which the signal BG1[m] is supplied. The second gate of the transistor connected to the word line WLOS2[m] is the signal BG2[m]. It is connected to the wiring to which ] is given. Signal BG1[m-1] and signal BG2[m-1] are It can be a common signal or different signals. Similarly, signal BG1[m] and signal BG2[ m] can be a common signal or a different signal.

[0167] The semiconductor device 500 shown in Figures 7 and 8 may be configured as shown in the block diagram in Figure 25. The block diagram shown in 25 shows that all second gates included in the memory cell array 501 are co It is connected to a common wiring harness and is given a common signal BG.

[0168] <Example configuration for row selection driver> Figure 9 is a block diagram showing an example configuration of the row selection driver 502 described in Figures 7 and 8. .

[0169] The row selection driver 502 shown in Figure 9 includes a decoder 517 and a read / write control circuit. It has 518. The read / write control circuit 518 has word lines WLOS1, WLC1, W It is connected to LOS2 and WLC2, and is provided for each row.

[0170] Decoder 517 has the function of outputting a signal for selecting the row on which the word line is provided. This is a circuit. Specifically, an address signal Address is input, and the address signal A A circuit that selects a read / write control circuit 518 for any row according to the address. Yes. By having a decoder 517, the row selection driver 502 can select any row, It is possible to write or read data.

[0171] The read / write control circuit 518 reads the line having the word line selected by the decoder 517. Features include the ability to output a write word signal and the ability to selectively output a read word signal. The circuit is equipped with a read / write control circuit 518, and a write control circuit. The Write_CONT and Read_CONT control signals are input, and the signal Therefore, it is a circuit that selectively outputs either a write signal or a read signal. By including the control circuit 518, the row selection driver 502 selects the row selected by the decoder 517. The system can select to output either a write word signal or a read word signal for each row.

[0172] <Example configuration for column selection driver> Figure 10 is a block diagram showing an example configuration of the column selection driver 503 described in Figures 7 and 8. ru.

[0173] The column selection driver 503 shown in Figure 10 includes a decoder 521, a latch circuit 522, and a D / A converter. It has a converter 523, a switch circuit 524, and a transistor 526. And transistors are provided for each row. Also, the switch circuit 524 and transistors for each row The ZISTA 526 is connected to the bit line BL.

[0174] Decoder 521 selects a column where a bit line BL is provided and distributes the input data. This is a circuit equipped with the function of outputting an address signal and a data signal. Specifically, it outputs an address signal and a data signal. Data is input, and according to the address signal Address, one of the columns is latched. This is a circuit that outputs data to circuit 522. By including decoder 521, the sequence The selection driver 503 can select any column and write data to it.

[0175] The data input to decoder 521 is k-bit digital data. k-bit digital data is represented by binary data, either '1' or '0' for each bit. It is a number. Specifically, for 2-bit digital data, it is '00', '01', '1 This data is represented by '0' and '11'.

[0176] The latch circuit 522 is a circuit that has the function of temporarily storing the input data Data. Yes. Specifically, when the latch signal W_LAT is input, the stored data Data is... A flip-flop circuit outputs to the D / A converter 523 according to the switch signal W_LAT. Yes. By providing a latch circuit 522, the column selection driver 503 can select at any time. Data can be written to it.

[0177] The D / A converter 523 converts the input digital value data into analog value data. DATA V data This is a circuit equipped with the function of converting to [a specific format]. Specifically, the D / A converter 523 is If the number of bits in the data is 3 bits, then there are 8 levels of potential V0 to V7. This circuit converts the signal to one of the positions and outputs it to the switch circuit 524. D / A converter 5 By including 23, the column selection driver 503 writes the data to the memory cell 110. This can be used to represent the potential corresponding to multi-level data.

[0178] Note that the data V output from the D / A converter 523 is data These are expressed in different voltage values. This is the data. In the case of 2-bit data, it would be 0.5V, 1.0V, 1.5V, 2.0V This results in data with four values, and can be described as data that can be represented by any of these voltage values.

[0179] Switch circuit 524 receives the input data V data The function of providing a bit line BL, and This is a circuit that has the function of making the bit line BL electrically floating. Specifically, analog Equipped with a switch and inverter, and controlled by the switch control signal Write_SW, Data V data By applying this to the bit line BL and then turning off the analog switch, the power This is a circuit that creates a floating state. By including a switch circuit 524, it becomes a column selection driver. 503 is data V data After applying the bit line BL, the bit line BL is electrically suspended. It can be maintained in that state.

[0180] Transistor 526 is initialized to a potential V GND The function of providing a bit line BL, This is a circuit that has the function of making the bit line BL electrically floating. Specifically, the initial The potential V is controlled by the control signal Init_EN. GND The bit line BL is given, and then the bit This is a switch that electrically floats the wire BL. It is equipped with transistor 526. So, the column selection driver 503 is, potential V GND After supplying to bit line BL, the bit line BL It can be electrically suspended.

[0181] <Example of A / D converter configuration> Figure 11 is a block diagram showing an example configuration of the A / D converter 504 described in Figure 8.

[0182] The A / D converter 504 shown in Figure 11 includes a comparator 531, an encoder 532, and a resistor. It has a circuit 533 and a buffer 534. Each of the aforementioned circuits and transistors is arranged in a row. A buffer is provided for each column. Additionally, buffer 534 for each column outputs data Dout.

[0183] Comparator 531 compares the potential of the bit line BL with the reference voltages Vref0 to Vref6. The potentials are compared, and the potential of the bit line BL corresponds to one of the multi-level data. This is a circuit equipped with a function to determine whether or not. Specifically, it is equipped with multiple comparators 531, Each comparator 531 has a potential for the bit line BL and a different reference voltage Vref0 to Given Vref6, determine whether the potential of bit line BL is between any of the potentials. This is a circuit. By including the comparator 531, the A / D converter 504 uses bit lines It is possible to determine whether the potential of BL corresponds to one of the multi-level data points.

[0184] For example, the reference voltages Vref0 to Vref6 shown in Figure 11 have multiple values ​​of data. This is the potential given when the data is bit-based, i.e., 8-value data.

[0185] The encoder 532 determines the potential of the bit line BL output from the comparator 531. This is a circuit that has the function of generating a multi-bit digital signal based on a signal. Specifically, Based on the H-level or L-level signals output from multiple comparators 531, encoding This is a circuit that performs A / D conversion and generates a digital signal. By incorporating encoder 532, it performs A / D conversion. The converter 504 converts the data read from the memory cell 110 into digital value data. It is possible.

[0186] The latch circuit 533 has the function of temporarily storing the data of the input digital value. It is a path. Specifically, a latch signal LAT is input, and the stored data is transmitted to the latch signal This is a flip-flop circuit that outputs to buffer 534 according to LAT. Latch circuit 53 By including 3, the A / D converter 504 can output data at any time. This is possible. Note that the latch circuit 533 can be omitted.

[0187] Buffer 534 amplifies the data output from latch circuit 533 and outputs it as the output signal Dout. This is a circuit equipped with the function of outputting as such. Specifically, it is a circuit equipped with an even number of inverter stages. It is a path. By having buffer 534, the A / D converter 504 converts the digital signal to This can reduce the noise. Note that buffer 534 can be omitted.

[0188] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0189] (Embodiment 4) In this embodiment, the semiconductor device capable of realizing the circuits of memory cell 100 and memory cell 110 is An example of placement will be explained using Figure 12.

[0190] <Example of semiconductor device configuration> The semiconductor device shown in Figure 12 consists of a substrate 2000, a transistor 101, and a transistor 12 2, transistor 123, transistor 105, capacitive element 104, capacitive element 10 6, insulating film 2001, insulating film 2002, insulating film 2003, insulating film 2004, Edge film 2005, insulating film 2006, insulating film 2007, insulating film 2008, and plug 21 01, plug 2102, plug 2103, plug 2104, plug 2105, Plug 2106, Plug 2107, Plug 2108, Wiring 2301, Wiring 230 It has 2, wiring 2501, wiring 2502, conductive film 2701, and conductive film 2702. It is.

[0191] Note that when the memory cell 100 is realized in Figure 12, in the following explanation, transistor 122 Replace transistor 102 with transistor 103. That is all that is needed. Similarly, when realizing the memory cell 110 in Figure 12, in the following explanation, Replace transistor 122 with transistor 112, and transistor 123 with transistor 11 Simply replace it with 3.

[0192] Transistors 122 and 123 consist of a gate electrode 2205, a gate insulating film 2204, and a side wall. An insulating layer 2206 and an impurity region 2203 that functions as a source region or drain region, As LDD (Lightly Doped Drain) area or extension area It has a functional impurity region 2202 and a channel-forming region 2201.

[0193] The capacitive element 104 includes a first electrode 2401, a second electrode 2402, and an insulating film 2403. It holds.

[0194] The capacitive element 106 includes a first electrode 2601, a second electrode 2602, and an insulating film 2603. It holds.

[0195] The conductive film 2701 is the same conductive film as the source electrode or drain electrode of the transistor 101. A conductive film formed through a processing step, and the semiconductor layer of transistor 101, which is the same semiconductor It is composed of a semiconductor layer formed through a process of processing a body layer.

[0196] The conductive film 2702 is the same conductive film as the source electrode or drain electrode of transistor 105. A conductive film formed through a processing step, and the semiconductor layer of transistor 105, which is the same semiconductor It is composed of a semiconductor layer formed through a process of processing a body layer.

[0197] Note that in Figure 12, if multiple plugs exist at the same level, only one representative plug is marked. A code will be assigned, and others will use this code in conjunction. Similarly, if multiple wires exist at the same level... In this case, a code is assigned to only one representative element, and the others use this code in conjunction with it. Similarly, at the same hierarchical level... If multiple conductive films exist, only one representative film is assigned a designation, and the others use this designation in conjunction with it. .

[0198] Figure 12 shows the bit line BL, the power line SL, the word line WLOS1, and the word line WLOS The terminals connected to word line WLC1 and word line WLC2 are shown in the diagram. It is.

[0199] The semiconductor device shown in Figure 12 has transistors 122 and 123 mounted on a substrate 2000. Capacitive elements 104 are provided on transistors 122 and 123, and a transistor is provided on the capacitive element 104. A transistor 101 is provided, and a transistor 105 is provided on top of the transistor 101. A capacitive element 106 is provided on the inverter 105. The relative positions of these elements are as follows: This is not limited to this. For example, a capacitive element 106 is provided on the transistor 101, A transistor 105 may be placed on 106.

[0200] Substrate 2000 can be a single-crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline semiconductor substrate. Body substrate, compound semiconductor substrate made of silicon germanium, and SOI (Silicon A substrate such as an insulator can be used. The transistor is designed for high-speed operation. When using a recon substrate, an impurity element that imparts n-type to a portion of the substrate 2000 is added. By forming n-type wells and then forming p-type transistors in the region where n-type wells are formed, It is also possible to use impurity elements that impart the n-type, such as phosphorus (P) and arsenic (As). It is possible to have it. Boron (B), etc., can be used as an impurity element to impart the p-type. can.

[0201] Furthermore, the substrate 2000 may be an insulating substrate or a metal substrate on which a semiconductor film is provided. The substrates include stainless steel substrates, substrates having stainless steel foil, and Examples include tungsten substrates and substrates having tungsten foil. For example, glass substrates, quartz substrates, plastic substrates, flexible substrates, and bonded fills. Examples include paper containing fibrous materials, or substrate films. An example of a glass substrate is... For example, barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples include polyethylene terephthalate (PET) and poly Plastics such as ethylene naphthalate (PEN) and polyethersulfone (PES) Examples include plastics or flexible synthetic resins such as acrylic. Examples include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Examples include polyester, polyamide, polyimide, and These include laminates, epoxy, inorganic vapor-deposited films, or paper products.

[0202] Furthermore, a semiconductor element is formed using one substrate, and then the semiconductor element is transferred to another substrate. This is also acceptable. Examples of substrates on which semiconductor elements are placed include, in addition to the above-mentioned substrates, paper substrates, and Lophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, Fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester)) (or includes regenerated fibers such as acetate, cupro, rayon, and recycled polyester.) These include leather substrates or rubber substrates. By using these substrates, a good quality can be achieved. Formation of transistors, formation of low-power transistors, manufacturing of durable devices, heat resistance It is possible to add flexibility, reduce weight, or make it thinner.

[0203] It is preferable that transistors 122 and 123 use a first semiconductor material for their channels. Furthermore, it is preferable to use a second semiconductor material for the channel of transistors 101 and 105. It is preferable that the first and second semiconductor materials have different band gaps. For example, if the first semiconductor material is a semiconductor material other than an oxide semiconductor (silicon (strained silicon) (including ions), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum (e.g., gallium arsenide, indium phosphide, gallium nitride, organic semiconductors), and the second The semiconductor material can be an oxide semiconductor. Examples of semiconductor materials include single-crystal silicon. The transistor used is easy to operate at high speed. On the other hand, the transistor using oxide semiconductors The sta has a low off-current.

[0204] Details of transistors 101 and 105 will be described in Embodiment 4.

[0205] Transistors 122 and 123 have silicide (salicide), A transistor without a sidewall insulating layer 2206 may also be used. (Salicide) With a structure having such characteristics, the source region and drain region can be made to have lower resistance, and semiconductor device This enables faster operation. Furthermore, because it can operate at low voltage, it reduces the power consumption of semiconductor devices. It is possible to do so.

[0206] Transistors 122 and 123 are either n-channel or p-channel transistors. Any type of transistor will do; the appropriate transistor should be used depending on the circuit. Furthermore, the impurity concentration in impurity region 2203 is higher than that in impurity region 2202. Electrode gate 2 Using 205 and the sidewall insulating layer 2206 as a mask, the impurity region 2203 and impurities Region 2202 can be formed in a self-consistent manner.

[0207] When silicon-based semiconductor materials are used for transistors 122 and 123, the insulating film 2001 and The insulating film 2002 preferably contains hydrogen. The insulating film containing hydrogen is used in transistor 122. By placing it on 123 and performing a heat treatment, hydrogen in these insulating films causes the semiconductor film to... The ring bond is terminated, improving the reliability of transistors 122 and 123. can.

[0208] Examples of insulating films 2001 and 2002 include silicon oxide, silicon oxide nitride, and silicon nitride. Silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxide Aluminum, aluminum nitride, or the like can be used, and the layers can be stacked or single-layered.

[0209] When an oxide semiconductor is used for transistors 101 and 105, the insulating film 2001 and 2 described above Hydrogen in 002 is one of the factors that generate carriers in oxide semiconductors, therefore, This can sometimes reduce the reliability of ZISTA 101 and 105. Therefore, A mechanism to prevent hydrogen diffusion is placed between transistors 101 and 105 and transistors 122 and 123. Providing insulating films 2003 and 2006 with the properties of insulating film 2003 is particularly effective. According to 2006, by confining hydrogen in the lower layer, transistor 122 and transistor In addition to improved reliability, the diffusion of hydrogen from the lower layers to the upper layers is suppressed. This also improves the reliability of transistors 101 and 105.

[0210] Examples of insulating films 2003 and 2006 include aluminum oxide, aluminum oxide and nitride. Gallium oxide, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, HAF oxide The use of nium, hafnium oxidizrind, yttria-stabilized zirconia (YSZ), etc. Yes, it is possible. In particular, aluminum oxide films are effective against both impurities such as hydrogen and water, as well as oxygen. This provides a high blocking effect that prevents the film from permeating, which is preferable.

[0211] Insulating films 2004 and 2007, like insulating films 2003 and 2006, make it difficult for water and hydrogen to diffuse. It is preferable to use a material that is not permeable to oxygen. It is difficult to cover the oxide semiconductor film with an insulating film that is impermeable to oxygen, so that the oxide semiconductor film is not permeable to oxygen. This can suppress the release of oxygen beyond the insulating film.

[0212] Furthermore, insulating films 2004 and 2007, which are impermeable to water and hydrogen, allow external contact with the oxide semiconductor. This suppresses the inclusion of water and hydrogen, which are impurities for transistors 101 and 10 The fluctuations in the electrical characteristics of step 5 are suppressed, enabling the realization of a highly reliable transistor.

[0213] Insulating film 2005 has the function of protecting transistor 101, and insulating film 2008 has the function of protecting transistor It has the function of protecting STA 105. The insulating films 2005 and 2008 contain silicon oxide and acid Silicon nitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum nitride oxide nium, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, oxide An insulating film containing one or more of lanthanum, neodymium oxide, hafnium oxide, and tantalum oxide is used. It is possible. Also, insulating films 2005 and 2008 may be laminates of the above materials. Furthermore, insulating films 2005 and 2008 may be omitted in some cases.

[0214] Wiring 2301 functions as the second gate electrode of transistor 101. Wiring 23 01 may be supplied with a constant potential, or the first gate electrode of transistor 101 The same potential or the same signal may be supplied. Wiring 2302 is for transistor 105. It functions as a second gate electrode. Wiring 2302 is supplied with a constant potential. Alternatively, the same potential or the same signal may be supplied to the first gate electrode of transistor 105. It is acceptable to leave them there. Note that wiring 2301 and 2302 may be omitted in some cases.

[0215] Plugs 2101 to 2108 are made of copper (Cu), tungsten (W), and molybdenum (Mo). Gold (Au), Aluminum (Al), Manganese (Mn), Titanium (Ti), Tantalum ( Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), corn A low-resistance material consisting of balt (Co), either as a pure element or an alloy, or a material primarily composed of these. It is preferable to have a single layer or a multilayer of conductive films containing the compound. In particular, it is desirable to have both heat resistance and conductivity. It is preferable to use high-melting-point materials such as tungsten or molybdenum. It is preferable to form it with a low-resistance conductive material such as aluminum or copper. Furthermore, Cu-Mn alloy When gold is used, manganese oxide is formed at the interface with the oxygen-containing insulator, and the manganese oxide is Cu It is preferable because it has the function of suppressing the spread of [unclear].

[0216] Wirings 2301, 2302, 2501, 2502, first electrode 2401 of capacitive element 104, The second electrode 2402 of the capacitive element 104, the first electrode 2601 of the capacitive element 106 and the capacitive element The second electrode 2602 of child 106 is made of copper (Cu), tungsten (W), and molybdenum (Mo Gold (Au), Aluminum (Al), Manganese (Mn), Titanium (Ti), Tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), Cobalt (Co) is a low-resistance material consisting of elemental or alloyed materials, or materials with these as the main component. It is preferable to have a single layer or a multilayer of conductive film containing a compound that provides heat resistance and conductivity. It is preferable to use high-melting-point materials such as tungsten or molybdenum that are compatible. It is preferable to form it with a low-resistance conductive material such as luminium or copper. Furthermore, Cu-Mn When an alloy is used, manganese oxide is formed at the interface with the oxygen-containing insulator, and the manganese oxide is C It is preferable because it has the function of suppressing the diffusion of u.

[0217] The insulating film 2403 of the capacitive element 104 and the insulating film 2603 of the capacitive element 106 have high dielectric constants. It is preferable to use an insulating film. For example, these insulating films may include aluminum oxide and ma-oxide. Gnesium, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon oxide Gallium, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, acid An insulating film containing one or more neodymium oxide, hafnium oxide, and tantalum oxide can be used. Furthermore, insulating film 2403 and insulating film 2603 may be laminates of the above materials. Oh, these insulating films contain lanthanum (La), nitrogen, zirconium (Zr), etc., as impurities. It may include it.

[0218] Note that in Figure 12, the areas where no symbols and hatching patterns are given are insulators. This represents the constituent regions. These regions include aluminum oxide and aluminum nitride oxide. Um, magnesium oxide, silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride Licon, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, oxide Contains one or more elements selected from lanthanum, neodymium oxide, hafnium oxide, tantalum oxide, etc. An insulator can be used. In addition, polyimide resin, polyamide resin, By using organic resins such as acrylic resin, siloxane resin, epoxy resin, and phenolic resin. It can also be done this way.

[0219] Note that transistors 122 and 123 are not only planar transistors, but also various types It can be a type of transistor. For example, a FIN type, a TRI-GAT It can be used as a transistor such as an E (tri-gate) type.

[0220] By changing the memory cell 110 shown in Figure 4 to the configuration shown in Figure 12, each memory cell The occupied area can be reduced. Also, the memory cell 110 can store multi-level data. Therefore, by using the configuration shown in Figure 12, a high density of information can be stored in a small area. We can provide semiconductor devices.

[0221] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0222] (Embodiment 5) <Example of oxide semiconductor transistor configuration> In this embodiment, the channel is applicable to the transistors 101 and 105 shown in Figure 12. A transistor using an oxide semiconductor layer (hereinafter referred to as OS (Oxide Semiconductor) An example of a transistor will be explained using Figures 13 to 18.

[0223] Figures 13(A) to 13(C) are top and cross-sectional views of an OS transistor. 3(A) is a top view, and the cross-section in the direction of the dashed line A1-A2 shown in Figure 13(A) is shown in Figure 13( This corresponds to B), and the cross-section in the direction of the dashed line B1-B2 shown in Figure 13(A) corresponds to Figure 13(C). In addition, some elements in Figures 13(A) to 13(C) have been enlarged for clarity. The diagrams are reduced in size or abbreviated. Also, the dashed line A1-A2 indicates the channel length direction. The direction of the dashed line B1-B2 is sometimes referred to as the channel width direction.

[0224] Note that channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. The region where the current flows within the semiconductor when the diode is ON and the gate electrode overlap, Or, in the region where the channel is formed, the source (source region or source electrode) and the drain This refers to the distance between the in (drain region or drain electrode). Note that one transistor In a network, the channel length is not necessarily the same across all regions. That is, in a single network, The channel length of a zista may not be fixed to a single value. Therefore, in this specification, The channel length is any one value, maximum value, minimum value, or This will be the average value.

[0225] Channel width refers to, for example, the current flowing within a semiconductor (or transistor) when it is turned on. In the region where the flow portion and the gate electrode overlap, or in the region where the channel is formed This refers to the length of the part where the source and drain face each other. In this case, the channel width is not necessarily the same value in all regions. That is, one channel The channel width of a zista may not be fixed to a single value. Therefore, in this specification, The channel width is any one value, maximum value, minimum value, or This will be the average value.

[0226] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is shown in the top view of the transistor. The apparent channel width shown in [the relevant section] becomes larger, and its effect can no longer be ignored. In some cases, such as in transistors with a fine and three-dimensional structure, the upper surface of the semiconductor may be The ratio of channel regions formed on the side surface of the semiconductor to the ratio of channel regions formed In some cases, the apparent channel width shown in the top view may become larger. However, the effective channel width actually formed is larger.

[0227] By the way, in transistors with a three-dimensional structure, the effective channel width is measured Estimation can be difficult in some cases. For example, estimating the effective channel width from the design value. In order to do this, it is necessary to assume that the shape of the semiconductor is known. If this information is not precisely known, it is difficult to accurately measure the effective channel width.

[0228] Therefore, in this specification, in the top view of a transistor, the semiconductor and the gate electrode overlap. The apparent channel is the length of the portion in the region where the source and drain face each other. Channel width is defined as "Surrounded Channel Width (SCW)". It is sometimes referred to as "channel width." Also, in this specification, when simply referred to as channel width, This may refer to the enclosed channel width or the apparent channel width. Or, this detail In some documents, when simply referred to as "channel width," it may refer to the effective channel width. Oh, channel length, channel width, effective channel width, apparent channel width, enclosure channel Channel width and other parameters can be determined by acquiring cross-sectional TEM images and analyzing those images. The value can be determined.

[0229] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine this. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The values ​​may differ from those obtained when calculating using the channel width.

[0230] The OS transistor has an insulating film 652 on an insulating film 651, and a first oxide on the insulating film 652. A stack formed in the order of a material semiconductor 661 and a second oxide semiconductor 662, and a part of the stack and an electric Source electrode 671 and drain electrode 672 are connected by gas, and a part of the laminate, source electrode A third oxide semiconductor 663 covers part of electrode 671 and part of drain electrode 672, A portion of the laminate, a portion of the source electrode 671, a portion of the drain electrode 672, and a third oxide semiconductor The gate insulating film 653 and gate electrode 673 overlap with a portion of the body 663, and the source electrode 67 1 and drain electrode 672, and insulating film 654 on gate electrode 673, and insulating film 6 It has an insulating film 655 on 54. Note that the first oxide semiconductor 661 and the second oxide semiconductor The oxide semiconductors 662 and the third oxide semiconductor 663 are collectively referred to as oxide semiconductor 660.

[0231] Furthermore, at least a portion of the source electrode 671 (and / or the drain electrode 672) (or (all of them) are the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least part (or all) of the surface, side, top, and / or bottom of any semiconductor layer It is located at [location].

[0232] Or, at least a portion of the source electrode 671 (and / or drain electrode 672) (or all of) the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least part (or all) of the surface, side, top, and / or bottom of a semiconductor layer such as the above. ) is in contact with the source electrode 671 (and / or the drain electrode 672). At least part (or all) of the second oxide semiconductor 662 (and / or the first It is in contact with at least a portion (or all) of a semiconductor layer, such as an oxide semiconductor (661).

[0233] Or, at least a portion of the source electrode 671 (and / or drain electrode 672) (or all of) the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least part (or all) of the surface, side, top, and / or bottom of a semiconductor layer such as the above. ) is electrically connected to the source electrode 671 (and / or the drain electrode). At least a portion (or all) of pole 672) is a second oxide semiconductor 662 (and / or This is electrically connected to a part (or all) of the semiconductor layer, such as the first oxide semiconductor (661). It is being done.

[0234] Or, at least a portion of the source electrode 671 (and / or drain electrode 672) (or all of) the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least part (or all) of the surface, side, top, and / or bottom of a semiconductor layer such as the above. ) is located in close proximity to the source electrode 671 (and / or the drain electrode). At least a portion (or all) of pole 672) is a second oxide semiconductor 662 (and / or It is disposed in close proximity to a part (or all) of the semiconductor layer, such as the first oxide semiconductor (661). It is being done.

[0235] Or, at least a portion of the source electrode 671 (and / or drain electrode 672) (or all of) the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least part (or all) of the surface, side, top, and / or bottom of a semiconductor layer such as the above. It is located on the side of the source electrode 671 (and / or drain electrode 6 72) At least part (or all) of the second oxide semiconductor 662 (and / or It is located on the side of part (or all) of the semiconductor layer, such as the first oxide semiconductor (661). .

[0236] Or, at least a portion of the source electrode 671 (and / or drain electrode 672) (or all of) the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least part (or all) of the surface, side, top, and / or bottom of a semiconductor layer such as the above. It is positioned diagonally above the source electrode 671 (and / or the drain electrode). At least a portion (or all) of pole 672) is a second oxide semiconductor 662 (and / or It is positioned diagonally above a part (or all) of a semiconductor layer such as the first oxide semiconductor (661). It is being done.

[0237] Or, at least a portion of the source electrode 671 (and / or drain electrode 672) (or all of) the second oxide semiconductor 662 (and / or the first oxide semiconductor 661) At least part (or all) of the surface, side, top, and / or bottom of a semiconductor layer such as the above. It is located above the source electrode 671 (and / or drain electrode 6 72) At least part (or all) of the second oxide semiconductor 662 (and / or It is located on top of part (or all) of the semiconductor layer, such as the first oxide semiconductor (661). .

[0238] Furthermore, the "source" and "drain" functions of a transistor are related to transistors with different polarities. When adopting a circuit, or when the direction of current changes during circuit operation, the configuration may be reversed. Therefore, in this specification, the terms "source" and "drain" are interchangeable. It may be used in this manner.

[0239] A transistor according to one aspect of the present invention preferably has a channel length of 10 nm or more and 1000 nm or less. The channel length is 20 nm to 500 nm, more preferably 30 nm. The above is a top-gate type structure with a wavelength of 300 nm or less.

[0240] The components included in the semiconductor device of this embodiment will be described in detail below.

[0241] <Undercoat insulating film> The insulating film 651 and insulating film 652 serve to prevent the diffusion of impurities from beneath insulating film 651. In addition to having this, it can also play a role in supplying oxygen to the oxide semiconductor 660. Therefore Therefore, insulating film 651 and insulating film 652 are preferably insulating films containing oxygen, and stoichiometric It is more preferable that the insulating film contains more oxygen than the composition. For example, TDS(Ther In mal Desorption Spectroscopy analysis, the oxygen atoms were converted. The amount of oxygen released is 1.0 × 10⁻⁶ 19 atoms / cm 3 The membrane is defined as described above. The surface temperature of the film during the above TDS analysis is between 100°C and 700°C, or 10 A range of 0°C to 500°C is preferred. Also, as shown in Figure 12, beneath the insulating film 651, When the device is formed, the insulating film 651 and insulating film 652 have a flat surface. For example, using the CMP (Chemical Mechanical Polishing) method. It is preferable to perform a planarization treatment.

[0242] Insulating films 651 and 652 are made of aluminum oxide, magnesium oxide, and silicon oxide. silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Oxides such as nium, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Insulators, silicon nitride, silicon oxide nitride, aluminum nitride, aluminum oxide nitride, etc. It can be formed using any nitride insulating film or a mixture thereof.

[0243] <Oxide semiconductor> Oxide semiconductors 660 typically include In-Ga oxide, In-Zn oxide, and In-M- Zn oxides (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) are available. In particular, it is preferable to use In-M-Zn oxide as the oxide semiconductor 660.

[0244] However, oxide semiconductor 660 is not limited to oxides containing indium. 660 is, for example, Zn oxide, Zn-Sn oxide, Ga oxide, Ga-Sn oxide. That's fine.

[0245] In the case of oxide semiconductor 660, which is an In-M-Zn oxide fabricated by sputtering, - The atomic ratio of the metal elements in the target used to deposit M-Zn oxide is In≧M It is preferable that Zn ≥ M is satisfied. The atomic ratio of the metal elements of such a target is , In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3 A ratio of 1:2 is preferred. Note that the atomic ratio of the oxide semiconductor 660 to be deposited is limited to the error. The plus or minus of the atomic ratio of metal elements contained in the above sputtering target. Includes a 40% fluctuation.

[0246] Next, the first oxide semiconductor 661, the second oxide semiconductor 662, and the third oxide semiconductor The function and effects of the oxide semiconductor 660, which is formed by stacking of bodies 663, are shown in Figure This will be explained using the energy band structure diagram shown in 14(B). Figure 14(A) is shown in Figure 13( Figure 14(B) is a magnified view of the channel portion of the OS transistor shown in B), and Figure 14(B) is a magnified view of Figure 14( Figure A shows the energy band structure of the region indicated by the dashed line between C1 and C2. Figure 14(B) shows the energy band structure of the channel formation region of the OS transistor. ru.

[0247] In Figure 14(B), Ec652, Ec661, Ec662, Ec663, and Ec653 are... Each of them is an insulating film 652, a first oxide semiconductor 661, a second oxide semiconductor 662, and a third This shows the energy at the lower end of the conduction band of the oxide semiconductor 663 and the gate insulating film 653.

[0248] Here, the difference between the energy of the vacuum level and the energy of the lower end of the conduction band (also called "electron affinity") is true The difference between the energy of the empty level and the energy of the upper end of the valence band (also called the ionization potential) This is the value after subtracting the energy gap. Note that the energy gap is measured using a spectroscopic ellipsometer. Measurement can be performed using the HORIBA JOBIN YVON UT-300. The energy difference between the vacant level and the upper end of the valence band is determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy) equipment (ULVA) Measurements can be taken using the VersaProbe (PHI Corporation).

[0249] Furthermore, using a sputtering target with an atomic ratio of In:Ga:Zn=1:3:2, the shape The resulting In-Ga-Zn oxide has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4 It is 0.5eV. Also, a sputtering turret with an atomic ratio of In:Ga:Zn=1:3:4 The energy gap of the In-Ga-Zn oxide formed using GET is approximately 3.4 eV. The electron affinity is approximately 4.5 eV. Also, the atomic ratio is In:Ga:Zn = 1:3:6. Energy gap of In-Ga-Zn oxide formed using a puttering target The electron affinity is approximately 3.3 eV, and the electron affinity is approximately 4.5 eV. Furthermore, the atomic ratio is In:Ga:Zn In-Ga-Zn oxide formed using a sputtering target with a ratio of 1:6:2 The energy gap is approximately 3.9 eV, and the electron affinity is approximately 4.3 eV. Also, the atomic ratio is In-Ga formed using a sputtering target with an In:Ga:Zn ratio of 1:6:8 - The energy gap of Zn oxide is approximately 3.5 eV, and its electron affinity is approximately 4.4 eV. Furthermore, using a sputtering target with an atomic ratio of In:Ga:Zn=1:6:10 The energy gap of the formed In-Ga-Zn oxide is approximately 3.5 eV, and the electron affinity is approximately It is 4.5 eV. Also, the sputtering machine has an atomic ratio of In:Ga:Zn=1:1:1. The energy gap of the In-Ga-Zn oxide formed using -get is approximately 3.2 eV. The electron affinity is approximately 4.7 eV. Also, the atomic ratio is In:Ga:Zn = 3:1:2. Energy gap of In-Ga-Zn oxide formed using a sputtering target The voltage is approximately 2.8 eV, and the electron affinity is approximately 5.0 eV.

[0250] Since insulating film 652 and gate insulating film 653 are insulators, Ec653 and Ec652 are equal to E Closer to the vacuum level (lower electron affinity) than c661, Ec662, and Ec663. .

[0251] Furthermore, Ec661 is closer to the vacuum level than Ec662. Specifically, Ec661 is E 0.05eV or more, 0.07eV or more, 0.1eV or more, or 0.15eV or more than c662 Above V, and below 2eV, 1eV, 0.5eV, or 0.4eV in vacuum levels. Closer is preferable.

[0252] Furthermore, Ec663 is closer to the vacuum level than Ec662. Specifically, Ec663 is E 0.05eV or more, 0.07eV or more, 0.1eV or more, or 0.15eV or more than c662 Above V, and below 2eV, 1eV, 0.5eV, or 0.4eV in vacuum levels. Closer is preferable.

[0253] Furthermore, near the interface between the first oxide semiconductor 661 and the second oxide semiconductor 662, and the A mixed region is formed near the interface between the second oxide semiconductor 662 and the third oxide semiconductor 663. Therefore, the energy at the lower end of the conduction band changes continuously. That is, at these interfaces There are either no levels, or very few.

[0254] Therefore, in the laminated structure having the energy band structure, electrons are second oxide semiconductor Body 662 will be the primary component to move. Therefore, the first oxide semiconductor 661 and the insulating film will move. The interface with 652, or the interface between the third oxide semiconductor 663 and the gate insulating film 653. Even if a level exists, that level has little effect on electron movement. Also, the first oxidation The interface between the material semiconductor 661 and the second oxide semiconductor 662, and the third oxide semiconductor 663 Because there are no or very few energy levels at the interface between the first and second oxide semiconductor 662, the region It does not hinder electron movement in the region. Therefore, the above oxide semiconductor stacked structure OS transistors can achieve high field-effect mobility.

[0255] Furthermore, as shown in Figure 6, the interface between the first oxide semiconductor 661 and the insulating film 652, and the third Near the interface between the oxide semiconductor 663 and the gate insulating film 653, impurities and defects are present. Although a lap level Et600 may be formed, the first oxide semiconductor 661 and the third The presence of oxide semiconductor 663 allows the second oxide semiconductor 662 and the trap level to interact. It can keep them away.

[0256] In particular, the OS transistor illustrated in this embodiment has a second acid in the channel width direction. The top and side surfaces of the oxide semiconductor 662 are in contact with the third oxide semiconductor 663, and the second oxide semiconductor The lower surface of 662 is formed in contact with the first oxide semiconductor 661 (see Figure 13(C)). ). In this way, the second oxide semiconductor 662 is connected to the first oxide semiconductor 661 and the third oxide By using a configuration that covers it with semiconductor 663, the influence of the above trap levels can be further reduced. can.

[0257] However, if the energy difference between Ec661 or Ec663 and Ec662 is small, Electrons in oxide semiconductor 662 of 2 may exceed the energy difference and reach the trap level. Electrons are trapped in the trap level, creating a negative fixed charge at the interface of the insulating film. The transistor's threshold voltage shifts in the positive direction.

[0258] Therefore, the energy differences between Ec661 and Ec663 and Ec662 are set to 0. If set to 0.1eV or higher, preferably 0.15eV or higher, the threshold voltage of the transistor changes. This is preferable because it reduces vibration and improves the electrical characteristics of the transistor. .

[0259] Furthermore, the band gaps of the first oxide semiconductor 661 and the third oxide semiconductor 663 are Preferably, the band gap is wider than that of the second oxide semiconductor 662.

[0260] The first oxide semiconductor 661 and the third oxide semiconductor 663 are, for example, Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf are used as the second oxide semiconductor 662. Materials containing a high atomic ratio can be used. Specifically, the atomic ratio can be increased by 1.5 times or more. Preferably, the amount is 2 times or more, and more preferably 3 times or more. The aforementioned elements bond strongly with oxygen. Therefore, it has the function of suppressing the occurrence of oxygen vacancies in oxide semiconductors. The first oxide semiconductor 661 and the third oxide semiconductor 663 are the second oxide semiconductor 66 It can be said that oxygen deficiency is less likely to occur than in method 2.

[0261] Furthermore, if the third oxide semiconductor 663 contains In, the In diffuses into the gate insulating film 653. This can cause gate leakage. Therefore, the third oxide semiconductor 663 is In It is preferable to use materials that do not contain the substance. For example, gallium oxide is preferred.

[0262] Furthermore, the first oxide semiconductor 661, the second oxide semiconductor 662, and the third oxide semiconductor 66 3 contains at least indium, zinc, and M(Al, Ti, Ga, Ge, Y, Zr, Sn When it is an In-M-Zn oxide containing a metal (such as La, Ce or Hf), the first oxidation The first is a crystalline semiconductor 661 with the atomic ratio In:M:Zn=x1:y1:z1, and the second is an oxide semiconductor. 662 is In:M:Zn=x2:y2:z2 [atomic ratio], and the third oxide semiconductor 663 is If we set In:M:Zn=x3:y3:z3 [atomic ratio], then y1 / x1 and y3 / x3 It is preferable that y1 / x1 and y3 / x3 are greater than y2 / x It should be 1.5 times or more than 2, preferably 2 times or more, and even more preferably 3 times or more. In the second oxide semiconductor 662, if y2 is greater than or equal to x2, the electrical characteristics of the transistor The properties can be stabilized. However, if y2 becomes more than 3 times x2, the transistor Because the field-effect mobility decreases, it is preferable that y2 be less than three times x2.

[0263] I excluding Zn and O from the first oxide semiconductor 661 and the third oxide semiconductor 663 The atomic ratio of n and M is preferably less than 50 atomic% for In and 50 atomic% for M. mic% or more, more preferably In is less than 25 atomic%, and M is 75 atomic% The percentage must be % or higher. Also, the second oxide semiconductor 662 must be composed of In and M, excluding Zn and O. The atomic ratio is preferably 25 atomic% or more of In and 75 atomic% or less of M. More preferably, In is 34 atomic% or more and M is less than 66 atomic%. ru.

[0264] The thickness of the first oxide semiconductor 661 and the third oxide semiconductor 663 is 3 nm or more. The wavelength should be less than or equal to nm, preferably between 3 nm and 50 nm. Also, the second oxide semiconductor 662 The thickness is 3 nm to 200 nm, preferably 3 nm to 100 nm, and more preferably The wavelength shall be between 3 nm and 50 nm. In addition, the second oxide semiconductor 662 shall be the same as the first acid It is preferable that the oxide semiconductor 661 and the third oxide semiconductor 663 are thicker.

[0265] Furthermore, in order to impart stable electrical characteristics to an oxide semiconductor channel transistor This reduces the impurity concentration in oxide semiconductors, making the oxide semiconductor intrinsically or substantially intrinsically This is effective. Here, "substantially true" means that the carrier density of the oxide semiconductor is 1 × 10 17 / cm 3 It is less than 1 × 10⁻⁶ 15 / cm 3 Being less than, More preferably 1 × 10 13 / cm 3 This refers to being less than or equal to.

[0266] Furthermore, in oxide semiconductors, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component These elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, and carrier density This increases the amount of impurities. Furthermore, silicon contributes to the formation of impurity levels in oxide semiconductors. These impurity levels can act as traps, potentially degrading the electrical characteristics of the transistor. Therefore, the first oxide semiconductor 661, the second oxide semiconductor 662 and the third oxide semiconductor It is preferable to reduce the impurity concentration in the layers of conductor 663 and at each interface.

[0267] To make oxide semiconductors intrinsically or substantially intrinsically, SIMS (Secondary In ion mass spectrometry analysis, for example, in oxide semiconductors, At a certain depth, or in a certain region of an oxide semiconductor, the silicon concentration is 1 × 1 0 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 less than, further Preferably 1 × 10 18 atoms / cm 3 It shall be less than . Also, the hydrogen concentration shall be, for example, At a certain depth in an oxide semiconductor, or in a certain region of an oxide semiconductor, 2 × 10 20 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 The following are better Mashiku is 1 x 10 19 atoms / cm 3 More preferably 5 × 10 18 Atom s / cm 3 The following applies. Furthermore, the nitrogen concentration is, for example, at a certain depth in the oxide semiconductor. Alternatively, in a region of an oxide semiconductor, 5 × 10 19 atoms / cm 3 Less than preferred Or 5 x 10 18 atoms / cm 3 More preferably 1 × 10 18 atom / cm 3 More preferably 5 × 10 17 atoms / cm 3 The following applies:

[0268] Furthermore, if an oxide semiconductor contains crystals, and if silicon or carbon is present in high concentrations, the oxide semiconductor... This can reduce the crystallinity of conductors. To avoid reducing the crystallinity of oxide semiconductors, For example, at a certain depth in an oxide semiconductor, or in a certain region of an oxide semiconductor, silicon concentration 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 Atom s / cm 3 Less than 1 × 10 18 atoms / cm 3 There is a portion that is less than It is sufficient if it is done. Also, for example, at a certain depth in an oxide semiconductor, or in an oxide semiconductor In a certain region of the body, the carbon concentration is 1 × 10⁻⁶ 19 atoms / cm 3 Less than 5 ×10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It is sufficient to have a portion that is less than [a certain value].

[0269] Furthermore, as mentioned above, a transistor using a highly purified oxide semiconductor in the channel formation region The off-current of the device is extremely small. For example, if the voltage between the source and drain is 0.1V, 5V Alternatively, if the voltage is set to approximately 10V, the off-current normalized by the transistor's channel width is It becomes possible to reduce the level from several yA / μm to several zA / μm.

[0270] The OS transistor illustrated in this embodiment uses an oxide semiconductor 660 with a channel width direction. Because the gate electrode 673 is formed to surround the oxide semiconductor 660, Therefore, in addition to the gate electric field from the vertical direction, a gate electric field from the lateral direction is applied (Figure See 13(C). In other words, the gate field is applied to the entire oxide semiconductor. As a result, the current flows throughout the second oxide semiconductor 662 which acts as a channel, and further... The current can be increased.

[0271] <Gate gate> The gate electrode 673 is made of chromium (Cr), copper (Cu), aluminum (Al), and gold (Au). Silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti) , tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt ( Metal elements selected from Co (Co), ruthenium (Ru), and alloys composed of the aforementioned metal elements. Alternatively, it can be formed using an alloy or the like, combining the aforementioned metal elements. The gate electrode 673 may be a single-layer structure or a stacked structure of two or more layers. For example, silico A single-layer structure of an aluminum film containing , a double-layer structure in which a titanium film is laminated on an aluminum film, A two-layer structure in which a titanium film is laminated on top of a titanium nitride film, and a tungsten film is laminated on top of a titanium nitride film. A two-layer structure, where a tungsten film is laminated on top of a tantalum nitride film or a tungsten nitride film. It has a two-layer structure, with a titanium film and an aluminum film laminated on top of that titanium film, and then another titanium film on top of that. A three-layer structure forming a film, a single-layer structure of a Cu-Mn alloy film, and a Cu film on top of a Cu-Mn alloy film. A stacked two-layer structure, where a Cu film is stacked on top of a Cu-Mn alloy film, and then another Cu-Mn alloy film is placed on top of that. Examples include a three-layer structure with multiple layers of gold film. In particular, Cu-Mn alloy films have low electrical resistance and are acid-resistant. It is preferable because it can form manganese oxide at the interface with the insulating film containing the element, thereby preventing the diffusion of Cu. It seems so.

[0272] Furthermore, the gate electrode 673 contains indium tin oxide and tungsten oxide. Indium zinc oxide containing oxides, tungsten oxide, and indium acid containing titanium oxide Indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply conductive materials with light-transmitting properties, such as indium tin oxide. Alternatively, a laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element can be used.

[0273] <Gate insulating film> The gate insulating film 653 contains aluminum oxide, magnesium oxide, silicon oxide, and nitrogen oxide. Silicon oxide, silicon nitride, silicon nitride, gallium oxide, germanium oxide, oxide Yttrium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and An insulating film containing one or more types of tantalum oxide can be used. Also, the gate insulating film 653 is The above materials may be laminated. Furthermore, the gate insulating film 653 may contain lanthanum (La) and nitrogen. It may also contain impurities such as zirconium (Zr).

[0274] Furthermore, an example of the stacked structure of the gate insulating film 653 will be described. The gate insulating film 653 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide. , and preferably containing silicon oxide or silicon oxide nitride.

[0275] Hafnium oxide has a higher dielectric constant compared to silicon oxide and silicon oxide nitride. Therefore Therefore, the physical film thickness can be made larger than the equivalent oxide film thickness, so the equivalent oxide film thickness can be 10 nm or less. Even when the size is set to below 5nm or less, the leakage current due to tunnel current can be reduced. Yes, it is possible. In other words, it is possible to create a transistor with a small off-current.

[0276] <Source electrode and drain electrode> The source electrode 671 and drain electrode 672 are made of the same material as the gate electrode 673. This is possible. In particular, Cu-Mn alloy films have low electrical resistance and oxide semiconductor 660 This is preferable because it forms manganese oxide at the interface and prevents the diffusion of Cu.

[0277] <Protective insulating film> The insulating film 654 blocks oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. It has the function of preventing oxygen from the oxide semiconductor 660 from entering the outside. This prevents diffusion into the oxide semiconductor 660 and prevents hydrogen, water, etc. from entering from the outside. For example, a nitride insulating film can be used as the insulating film 654. Examples include silicon nitride, silicon oxide nitride, aluminum nitride, and aluminum oxide nitride. These include the blocking effects of oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. Instead of a nitride insulating film having a blocking effect, use an oxide film containing oxygen, hydrogen, water, etc., which have a blocking effect. A material insulating film may be provided. An oxide insulating film having a blocking effect of oxygen, hydrogen, water, etc. For example, aluminum oxide, aluminum oxide nitride, gallium oxide, gallium oxide nitride, Yttrium oxide, yttrium oxidized nitride, hafnium oxide, hafnium oxidized nitride, etc. ru.

[0278] Aluminum oxide films allow both hydrogen, water, and other impurities, as well as oxygen, to pass through the film. Because it has a high barrier effect, it is preferable to apply it to insulating film 654. Therefore, aluminum oxide The aluminum film enhances the electrical properties of the transistor during and after the transistor fabrication process. To prevent the inclusion of impurities such as hydrogen and water, which cause fluctuations in properties, into the oxide semiconductor 660, Prevention of oxygen emission from oxide semiconductors, which are the main component materials of semiconductor 660, insulating film 6 It is suitable for use as a protective film that prevents the unnecessary release of oxygen from 52. Furthermore, it is also possible to diffuse the oxygen contained in the aluminum oxide film into the oxide semiconductor. .

[0279] <Crystal structure of oxide semiconductors> Next, we will explain the crystal structure of oxide semiconductors applicable to OS transistors.

[0280] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. "Straight" refers to a state in which two straight lines are positioned at an angle of 80° to 100°. This includes cases where the angle is between 85° and 95°.

[0281] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0282] Oxide semiconductor films are broadly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. A single-crystal oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystals Polycrystalline oxide semiconductor film This refers to microcrystalline oxide semiconductor films, amorphous oxide semiconductor films, etc.

[0283] First, let's explain the CAAC-OS membrane.

[0284] CAAC-OS film is an oxide semiconductor film having multiple c-axis oriented crystalline regions.

[0285] Transmission Electron Microscope (TEM) A composite analysis image of the CAAC-OS film's bright-field image and diffraction pattern (using a scope) By observing what is also called a high-resolution TEM image, multiple crystalline regions can be identified. On the other hand, high-resolution TEM images also clearly show the boundaries between crystal parts, i.e., grain boundaries. It is not possible to confirm the boundary (also called the boundary). Therefore, the CAAC-OS membrane is This means that a decrease in electron mobility due to grain boundaries is less likely to occur.

[0286] When observing a high-resolution TEM image of the cross-section of the CAAC-OS film from a direction roughly parallel to the sample surface, In the crystalline region, it can be confirmed that the metal atoms are arranged in layers. Each layer of metal atoms is This reflects the unevenness of the surface (also called the surface to be formed) or the upper surface of the CAAC-OS film. It has a specific shape and is arranged parallel to the surface or top surface of the CAAC-OS film to be formed.

[0287] On the other hand, a high-resolution TEM image of the CAAC-OS film plane was observed from a direction roughly perpendicular to the sample surface. Then, it was confirmed that the metal atoms in the crystalline region are arranged in a triangular or hexagonal shape. Yes, it is possible. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions.

[0288] Figure 15(a) is a high-resolution TEM image of a cross-section of the CAAC-OS film. Also, Figure 15(b) Figure 15(a) is a high-resolution TEM image of a cross-section that is further enlarged, making it easier to understand. The atomic arrangement is highlighted for this purpose.

[0289] Figure 15(c) shows the area enclosed by a circle (diameter approximately 4n) between AO and A' in Figure 15(a). This is the local Fourier transform image of m). From Figure 15(c), the c-axis orientation in each region is It can be confirmed. Also, the orientation of the c-axis is different between A and O and between O and A', so different grades This suggests that it is in. Also, between A and O, the angle of the c axis is 14.3° and 16.6°. It can be seen that it changes gradually and continuously, such as ° and 26.4°. Similarly, O-A' In between, the angle of the c-axis changes gradually and continuously from -18.3°, -17.6°, to -15.9°. It can be seen that it has transformed.

[0290] Furthermore, when electron diffraction is performed on the CAAC-OS film, oriented spots (bright spots) can be observed. It is measured. For example, on the upper surface of the CAAC-OS film, an electric field of, for example, between 1 nm and 30 nm is measured. When electron diffraction using a sub-beam (also called nanobeam electron diffraction) is performed, a spot is observed. (See Figure 16(A).)

[0291] High-resolution TEM images of the cross-section and high-resolution TEM images of the planar region of the CAAC-OS film It can be seen that it has orientation.

[0292] Furthermore, most of the crystalline parts contained in the CAAC-OS film are cubes with sides less than 100 nm long. It is small enough to fit inside. Therefore, the crystalline portion contained in the CAAC-OS film has a side length of 10n. This also includes cases that fit within a cube smaller than m, smaller than 5 nm, or smaller than 3 nm. Furthermore, multiple crystalline regions contained in the CAAC-OS film are linked together, forming one large crystalline region. This can sometimes form. For example, in a high-resolution planar TEM image, at 2500 nm 2 That's all. , 5μm 2 or greater than 1000 μm 2 In some cases, crystal regions exceeding the above size may be observed.

[0293] X-ray diffraction (XRD) applied to the CAAC-OS film. When structural analysis is performed using this method, for example, a CAAC-OS film having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is generally aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing in a nearly vertical direction.

[0294] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In analysis using the ANE method, a peak may appear when 2θ is around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. Single crystal oxidation of InGaZnO4 For a solid semiconductor film, fix 2θ to around 56°, and use the normal vector of the sample surface as the axis (φ axis). When the sample is rotated while the analysis (φ scan) is performed, the crystal plane equivalent to the (110) plane is found. Six attributed peaks are observed. In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when fixed at approximately 6° and scanned using the φ scan function, no clear peak appears.

[0295] From the above, it can be concluded that in CAAC-OS films, the orientation of the a-axis and b-axis is inconsistent between different crystalline regions. It is a rule, but it has c-axis orientation and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. It can be seen that it is facing in that direction. Therefore, as confirmed by the high-resolution TEM observation of the cross-section mentioned above, Each layer of metal atoms arranged in layers is a plane parallel to the ab-plane of the crystal.

[0296] The crystalline portion is formed when the CAAC-OS film is deposited, or when crystallization treatment such as heat treatment is performed. It is formed when this occurs. As mentioned above, the c-axis of the crystal is the surface on which the CAAC-OS film is formed or It is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, the shape of the CAAC-OS film When the shape is altered by etching or other means, the c-axis of the crystal becomes the surface on which the CAAC-OS film is formed. Alternatively, it may not be parallel to the normal vector of the top surface.

[0297] Furthermore, the distribution of c-axis oriented crystalline regions within the CAAC-OS film does not need to be uniform. For example, the crystalline portion of the CAAC-OS film is formed by crystal growth from near the top surface of the CAAC-OS film. When formed in this way, the region near the top surface has a more c-axis oriented crystalline structure than the region near the surface being formed. The proportion of impurities can increase. Also, in CAAC-OS films with added impurities, the impurities The added region is altered, and regions with different proportions of partially c-axis-oriented crystals are formed. Sometimes.

[0298] Furthermore, the out-of-plane method for CAAC-OS films containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 36° 2θ indicate c-axis orientation in a portion of the CAAC-OS film. This indicates that it contains crystals that do not have [the specified characteristic]. The CAAC-OS film has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0299] CAAC-OS films are oxide semiconductor films with low impurity concentrations. The impurities include hydrogen, carbon, These are elements other than silicon and transition metal elements, which are the main components of oxide semiconductor films. In particular, silicon Elements such as ions, which have a stronger bonding force with oxygen than the metal elements that make up oxide semiconductor films, By removing oxygen from the material semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a certain atomic radius. Because of its large molecular radius, when it is contained within an oxide semiconductor film, the oxide semiconductor film This disrupts the atomic arrangement and reduces crystallinity. Furthermore, these impurities are present in oxide semiconductor films. Objects can sometimes act as carrier traps or carrier sources.

[0300] Furthermore, CAAC-OS films are oxide semiconductor films with a low defect level density. For example, oxide Oxygen vacancies in semiconductor films can act as carrier traps or capture hydrogen. It can be a source of carrier activity.

[0301] A low impurity concentration and low defect level density (few oxygen vacancies) is referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film Because there are fewer carrier sources, the carrier density can be kept low. Transistors using oxide semiconductor films exhibit electrical characteristics where the threshold voltage is negative (no Also called Marion.) It rarely becomes high-purity genuine or substantially high-purity genuine. Oxide semiconductor films, being of a certain nature, have few carrier traps. Therefore, the oxide semiconductor film Transistors using this technology exhibit less variation in electrical characteristics and are highly reliable. Furthermore, the time required to release the charge trapped in the carrier trap of the oxide semiconductor film is [time]. The interval is long, and it can behave as if it were a fixed charge. Therefore, the impurity concentration is high. Transistors using oxide semiconductor films with a high defect level density exhibit unstable electrical properties. There are cases where this is the case.

[0302] Furthermore, transistors using CAAC-OS films exhibit electrical characteristics under irradiation with visible light and ultraviolet light. The fluctuations are small.

[0303] Next, we will explain microcrystalline oxide semiconductor films.

[0304] Microcrystalline oxide semiconductor films have areas where crystalline regions can be confirmed in high-resolution TEM images. It has regions where a clear crystalline structure cannot be observed, and regions where a clear crystalline structure cannot be identified. Microcrystalline oxide semiconductor film The crystalline portion contained therein is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, the minute particles are between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having nanocrystals (nc) which are crystalline, -OS(nanocrystalline oxide semiconductor) It is called a film. Furthermore, nc-OS films, for example, clearly show grain boundaries in high-resolution TEM images. There may be cases where it cannot be recognized.

[0305] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). The atomic arrangement has periodicity in the region of 3 nm or less. Also, the nc-OS film is different No regularity in crystal orientation is observed between the crystalline regions. Therefore, no orientation is observed throughout the film. In some cases, nc-OS films are indistinguishable from amorphous oxide semiconductor films depending on the analytical method. There are cases where XRD equipment using X-rays with a diameter larger than that of the crystalline region is used on nc-OS films. When structural analysis is performed using this method, the out-of-plane method reveals the crystal planes. No peaks are detected. Also, for nc-OS films, the probe diameter is larger than that of the crystalline region. For example, electron diffraction (also called limited-field electron diffraction) is performed using an electron beam of 50 nm or greater. Then, a diffraction pattern resembling a halo pattern is observed. On the other hand, for the nc-OS film, Nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the crystal region. When this is done, a spot is observed. Furthermore, nanobeam electron diffraction is performed on the nc-OS film. In some cases, a region of high brightness may be observed in a circular (ring-shaped) pattern. - When nanobeam electron diffraction is performed on the OS film, multiple spots are observed within a ring-shaped region. This may occur (see Figure 16(B)).

[0306] nc-OS films are oxide semiconductor films with higher orderliness than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, In nc-OS films, no regularity is observed in the crystal orientation between different crystalline regions. Therefore, nc-O The S film has a higher defect level density compared to the CAAC-OS film.

[0307] Next, we will explain amorphous oxide semiconductor films.

[0308] Amorphous oxide semiconductor films have an irregular atomic arrangement within the film and do not contain crystalline regions. These are physical semiconductor films. One example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0309] In amorphous oxide semiconductor films, crystalline regions cannot be observed in high-resolution TEM images.

[0310] When structural analysis of amorphous oxide semiconductor films is performed using an XRD device, out-of-p Analysis using the Lane method did not detect any peaks indicating crystal planes. Furthermore, amorphous oxide semi-crystalline materials were found. When electron diffraction is performed on a conductive film, a halo pattern is observed. Furthermore, amorphous oxide semiconductors... When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is not seen. It is observed.

[0311] Furthermore, oxide semiconductor films exhibit physical properties between nc-OS films and amorphous oxide semiconductor films. It may have such a structure. Oxide semiconductor films having such a structure are particularly amorphous-like oxide Amorphous-like semiconductor (amorphous-like OS: amorphous-like Ox It is called an IDE Semiconductor film.

[0312] Amorphous-like OS films exhibit porosity (also known as voids) in high-resolution TEM images. In some cases, the following may be observed. Also, the crystalline portion can be clearly identified in high-resolution TEM images. It has regions where this can be done and regions where the crystalline part cannot be observed. Phosphorus-like OS films can be bonded by minute electron irradiation, such as that observed by TEM. Crystallization may occur, and growth of crystalline regions may be observed. On the other hand, if the nc-OS film is of good quality... Crystallization is hardly observed even with minute amounts of electron irradiation, such as that observed by TEM.

[0313] Furthermore, the size of the crystalline portion of the amorphous-like OS film and nc-OS film is measured. Measurement can be performed using high-resolution TEM images. For example, an InGaZnO4 crystal is It has a layered structure, with two Ga-Zn-O layers between the In-O layers. (InGaZnO4) The unit cell of this crystal has 3 In-O layers and 6 Ga-Zn-O layers, for a total of 9 It has a structure in which layers are stacked in a layered manner along the c-axis. Therefore, the spacing between these adjacent layers is It is approximately the same as the lattice plane spacing (also called the d value) of the (009) plane, and from crystal structure analysis, The value has been determined to be 0.29 nm. Therefore, we focused on the lattice fringes in the high-resolution TEM image. Furthermore, in areas where the spacing between the grid lines is between 0.28 nm and 0.30 nm, The lattice fringes were considered to correspond to the ab-plane of the InGaZnO4 crystal. Observation of the lattice fringes The maximum length in the region is defined as the amorphous-like OS film and nc-OS This refers to the size of the crystalline portion of the film. Specifically, crystalline portions larger than 0.8 nm are selected. evaluate.

[0314] Figure 17 shows high-resolution TEM images of an amorphous-like OS film and nc -This is an example of investigating the change in the average size of the crystalline regions (20 to 40 locations) of the OS film. As shown in Figure 17, the amorphous-like OS film crystallizes depending on the cumulative dose of electrons irradiated. It can be seen that the part gets larger. Specifically, in the initial stages of observation using TEM, 1. The crystalline portion, which was about 2 nm in size, changed when the cumulative irradiation dose reached 4.2 × 10⁻¹⁴ 8 e - / nm 2 In It can be seen that it has grown to a size of about 2.6 nm. On the other hand, a good quality nc-OS film is The cumulative dose of electrons from the start of electron irradiation was 4.2 × 10⁻⁶. 8 e - / nm 2 The range until it reaches Therefore, it can be seen that there is no change in the size of the crystal region regardless of the cumulative dose of electrons irradiated.

[0315] Furthermore, the crystals of the amorphous-like OS film and the nc-OS film are shown in Figure 17. The change in the size of the part is linearly approximated, and the cumulative electron irradiation dose is 0e - / nm 2 Extrapolating to this point, It can be seen that the average size of the crystal region takes a positive value. Therefore, amorphous-li The crystalline portions of the ke-OS film and nc-OS film were present before TEM observation. You can understand that.

[0316] Note that oxide semiconductor films include, for example, amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and CA The AC-OS film may be a multilayer film having two or more types.

[0317] When an oxide semiconductor film has multiple structures, its structure can be analyzed using nanobeam electron diffraction. It may be possible.

[0318] Figure 16(C) shows the electron gun chamber 10, the optical system 12 below the electron gun chamber 10, and below the optical system 12. Sample chamber 14, optical system 16 below sample chamber 14, observation chamber 20 below optical system 16, and observation chamber A camera 18 installed in 20 and a film chamber 22 below the observation chamber 20, having a transmission electron The diffraction measuring device is shown. Camera 18 is installed facing the inside of the observation room 20. It is not necessary to have a chamber 22.

[0319] Furthermore, Figure 16(D) shows the internal structure of the transmission electron diffraction measurement device shown in Figure 16(C). Inside the transmission electron diffraction measuring device, electrons emitted from the electron gun installed in the electron gun chamber 10 The light is then irradiated onto the substance 28 placed in the sample chamber 14 via the optical system 12. The electrons are incident on the fluorescent screen 32 installed inside the observation room 20 via the optical system 16. On plate 32, a pattern appears corresponding to the intensity of the incident electrons, forming a transmission electron diffraction pattern. It can be measured.

[0320] Camera 18 is positioned facing the fluorescent screen 32 and captures the patterns that appear on the fluorescent screen 32. It is possible to do so by passing a straight line through the center of the lens of camera 18 and the center of the fluorescent screen 32. The angle between the top surface of the fluorescent board 32 and the top surface of the fluorescent board is, for example, 15° to 80°, or 30° to 7°. The angle should be 5° or less, or between 45° and 70°. The smaller the angle, the more likely it is to be captured by camera 18. The transmission electron diffraction pattern will be highly distorted. However, if the angle is known in advance... If present, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. In some cases, it is acceptable to install camera 18 in film chamber 22. For example, camera 18 is in film chamber 22. The fluorescent panel 3 may be placed in the chamber 22 so as to be opposite to the direction of incidence of the electrons 24. A low-distortion transmission electron diffraction pattern can be captured from the back surface of 2.

[0321] A holder for fixing the sample substance 28 is installed in the sample chamber 14. It has a structure that allows electrons to pass through material 28. The holder is, for example, made of The holder may have a function to move 28 along the X, Y, Z axes, etc. For example, 1nm to 10nm, 5nm to 50nm, 10nm to 100nm Move within ranges such as 50 nm to 500 nm, and 100 nm to 1 μm. It is sufficient to have accuracy. These ranges can be determined by setting the optimal range based on the structure of material 28. good.

[0322] Next, the transmission electron diffraction pattern of the material is measured using the transmission electron diffraction measuring device described above. I will explain the method.

[0323] For example, as shown in Figure 16(D), the irradiation position of electrons 24, which are a nanobeam, in a material By altering (scanning) it, we can observe how the structure of a substance changes. If the substance 28 is a CAAC-OS film, the cycle will be as shown in Figure 16(A). A folding pattern is observed. Alternatively, if material 28 is an nc-OS film, it is shown in Figure 16(B). A diffraction pattern like the one shown is observed.

[0324] By the way, even if substance 28 is a CAAC-OS film, it may be partially an nc-OS film, etc. Similar diffraction patterns may be observed. Therefore, the quality of the CAAC-OS film can be judged as follows: The percentage of the region in which the diffraction pattern of a CAAC-OS film is observed within a certain range (CAAC It can sometimes be expressed as (also called the concentration ratio). For example, in a high-quality CAAC-OS film Therefore, the CAAC conversion rate is 50% or more, preferably 80% or more, and more preferably 90% or more. More preferably, it is 95% or more. Note that the diffraction pattern is different from that of the CAAC-OS film. The proportion of the observed region is denoted as the non-CAAC rate.

[0325] For example, immediately after film deposition (indicated as-sputtered), or in an oxygen-containing atmosphere. The upper surface of each sample having a CAAC-OS film after heat treatment at 450°C was scanned. While doing so, a transmission electron diffraction pattern was acquired. Here, a speed of 5 nm / second was used for 60 seconds. The diffraction pattern is observed while scanning, and the observed diffraction pattern is converted into a still image every 0.5 seconds. The CAAC conversion rate was derived by performing the conversion. The electron beam used had a probe diameter of 1 nm. A nanobeam electron beam was used. Similar measurements were performed on six samples. CAA The average value of six samples was used to calculate the carbonization rate.

[0326] Figure 18(A) shows the CAAC conversion rate for each sample. CAAC-OS film immediately after deposition The AC conversion rate was 75.7% (the non-CAAC conversion rate was 24.3%). Furthermore, the 450°C heating treatment was performed. The CAAC conversion rate of the CAAC-OS film after processing was 85.3% (the non-CAAC conversion rate was 14.7%). Yes, it was found. It can be seen that the CAAC conversion rate is higher after 450°C heat treatment compared to immediately after film deposition. Furthermore, heat treatment at high temperatures (e.g., 400°C or higher) results in a lower non-CAAC conversion rate. It can be seen that this occurs (the CAAC conversion rate increases). Also, in heat treatment below 500°C This shows that a CAAC-OS film with a high CAAC conversion rate can be obtained.

[0327] Here, most of the diffraction patterns that differ from those of the CAAC-OS film are similar to those of the nc-OS film. It was a pattern. Furthermore, the amorphous oxide semiconductor film could be confirmed in the measurement area. It was not possible. Therefore, by heat treatment, regions having a structure similar to that of the nc-OS film were created. This suggests that the structure of adjacent regions influences the rearrangement and subsequent transformation into CAAC (Computer-Aware Algebraic) structures.

[0328] Figures 18(B) and 18(C) show CAAC-O immediately after deposition and after heat treatment at 450°C. This is a high-resolution TEM image of the planar surface of the S film. By comparing Figure 18(B) and Figure 18(C)... This indicates that the CAAC-OS film after heat treatment at 450°C has a more homogeneous film quality. In other words, it was found that the film quality of the CAAC-OS film is improved by heat treatment at high temperatures. Light.

[0329] Using this measurement method, it is possible to analyze the structure of oxide semiconductor films that have multiple structures. It can happen.

[0330] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0331] (Embodiment 6) A semiconductor device according to one aspect of the present invention comprises a display device, a personal computer, and a recording medium. Image playback devices (typically DVDs: Digital Versatile Discs) To be used in a device that has a display capable of playing back recording media such as the above and displaying the images thereof. This is possible. In addition, electronic devices that can use a semiconductor device according to one aspect of the present invention This includes mobile phones, game consoles including portable models, mobile data terminals, e-readers, and video cameras. , cameras such as digital still cameras, goggle-type displays (head-mounted displays) (Ray), navigation systems, sound reproduction devices (car audio, digital audio) Players, photocopiers, fax machines, printers, multifunction printers, ATMs Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 19. vinegar.

[0332] Figure 19(A) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display unit. 904, Microphone 905, Speaker 906, Control Keys 907, Stylus 908 It has the following features. The portable game console shown in Figure 19(A) has two display units 903 and a display unit. Although it has part 904, the number of display units that a portable game console has is not limited to this. .

[0333] Figure 19(B) shows a portable data terminal, comprising a first housing 911, a second housing 912, and a first display unit 9 13. It has a second display unit 914, a connection unit 915, an operation key 916, etc. First display unit 913 The first housing 911 is provided, and the second display unit 914 is provided in the second housing 912. Furthermore, the first housing 911 and the second housing 912 are connected by a connecting part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting part 915. The video in the first display unit 913 is connected to the first housing 911 and the second housing 9 in the connection unit 915. It may also be configured to switch according to the angle between 12 and 12. Also, the first display unit 913 and A display device in which at least one of the second display unit 914 is provided with a function as a position input device. You may also use a touch panel. Note that the function as a position input device is provided by the display device. It can be added by providing a panel. Alternatively, the function as a position input device is It can also be added by installing a photoelectric conversion element, also called a photosensor, in the pixel section of the display device. It is possible.

[0334] Figure 19(C) shows a notebook personal computer, comprising a casing 921, a display unit 922, and a keyboard. It includes a board 923, a pointing device 924, and the like.

[0335] Figure 19(D) shows an electric refrigerator-freezer, consisting of a casing 931, a refrigerator door 932, and a freezer door 93 It has a third-class rating.

[0336] Figure 19(E) shows a video camera, comprising a first housing 941, a second housing 942, a display unit 943, It has an operation key 944, a lens 945, a connecting part 946, etc. Operation key 944 and lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. And the first housing 941 and the second housing 942 are connected by a connecting part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting part 946. The video on the display unit 943 is connected to the first housing 941 and the second housing 94 in the connection unit 946. It could also be configured to switch according to the angle between 2 and 3.

[0337] Figure 19(F) is a regular passenger car, consisting of a body 951, wheels 952, dashboard 953, and It has Ito 954, etc.

[0338] This embodiment can be appropriately combined with other embodiments shown herein. .

[0339] (Embodiment 7) In this embodiment, an example of the use of an RF tag according to one aspect of the present invention will be shown with reference to Figure 20. Let me explain. RF tags have a wide range of applications, such as banknotes, coins, securities, and bearer tags. Bonds, certificates (such as driver's licenses and residence certificates, see Figure 20(A)), recording media (DVDs and videotapes) Tapes, etc. (see Figure 20(B)), packaging containers (wrapping paper, bottles, etc., see Figure 20(C)) ), vehicles (bicycles, etc., see Figure 20(D)), personal belongings (bags, glasses, etc.), food products, plants Objects, animals, human bodies, clothing, household goods, medical products including drugs and pharmaceuticals, or electronic devices (liquids) Items such as crystal display devices, EL display devices, television equipment, or mobile phones, or each It can be used by attaching it to luggage tags (see Figures 20(E) and 20(F)) etc. Cut.

[0340] An RF tag 4000 according to one aspect of the present invention can be attached to or embedded in the surface of an object. It is fixed to the product. For example, in the case of a book, it is embedded in the paper, and in the case of a package made of organic resin. The RF tag is embedded inside the organic resin and fixed to each article. The 4000 is designed to be small, thin, and lightweight, and even after being fixed to an object, it does not affect the design of the object itself. It does not impair the integrity of banknotes, coins, securities, bearer bonds, or certificates. By providing an RF tag 4000 according to one aspect of the present invention to the same type of object, an authentication function can be provided. This allows for counterfeiting to be prevented by utilizing this authentication function. Furthermore, packaging containers... The present invention applies to items such as recording media, personal belongings, food products, clothing, household goods, or electronic devices. By attaching RF tags related to the configuration, the efficiency of systems such as inspection systems can be improved. It is possible to attach an RF tag according to one aspect of the present invention to vehicles as well. This enhances security against theft and other crimes.

[0341] As described above, the RF tag according to one aspect of the present invention can be used for each of the applications listed in this embodiment. This reduces the operating power, including the power required for writing and reading information, thus extending the maximum communication distance. It becomes possible to store information for a long period of time. Furthermore, even when the power is cut off, information can be stored for an extremely long period of time. Because it can retain data for extended periods, it can be suitably used in applications where the frequency of writing and reading is low. Cut.

[0342] This embodiment can be appropriately combined with other embodiments shown herein. . [Explanation of Symbols]

[0343] BG1 signal BG2 signal BL bit line BL1 bit line BL2 bit line FN1 node FN2 node FN3 node p0 period p1 Period p2 Period p3 Period p4 Period p5 Period p6 period T0 time T1 time T2 time T3 time T4 time T5 time T6 time T7 time T8 time T9 time T10 time T11 time T12 time T13 time T14 time T15 time WLC1 Word Line WLC2 Word Line WLC3 Word Line WLOS1 Word Line WLOS2 Word Line WLOS3 Word Line 10 Electronic gun chamber 12 Optical system 14 Sample Room 16 Optical system 18 Cameras 20 Observation Room 22 Film Room 24 electronic 28 Substance 32 Fluorescent board 100 cell cells 101 Transistors 102 transistors 103 Transistors 104 Capacitive element 105 transistors 106 Capacitive elements 107 transistors 10⁸ Capacitive elements 109 transistors 110 memory cells 112 transistors 113 Transistors 114 transistors 122 transistors 123 Transistors 500 Semiconductor Equipment 501 memory cell array 502 Select Driver 503 Column Selection Driver 504 A / D Converter 517 Decoder 518 Control Circuit 521 Decoder 522 Latch Circuit 523 D / A Converter 524 Switch Circuit 526 transistors 531 Comparator 532 encoders 533 Latch Circuit 534 buffers 651 Insulating film 652 Insulating film 653 Gate insulating film 654 Insulating film 655 Insulating film 660 Oxide Semiconductor 661 Oxide Semiconductor 662 Oxide Semiconductor 663 Oxide semiconductor 671 Source electrode 672 Drain electrode 673 Station 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 911 cabinet 912 cabinet 913 Display section 914 Display section 915 Connection part 916 Operation Keys 921 cabinet 922 Display section 923 Keyboard 924 Pointing Devices 931 cabinet 932 Refrigerator door 933 Freezer door 941 cabinet 942 cabinets 943 Display section 944 Operation Keys 945 lens 946 Connection part 951 Body 952 wheels 953 Dashboard 954 Light 2000 circuit boards 2001 Insulating film 2002 Insulating film 2003 Insulating Film 2004 Insulating film 2005 Insulating film 2006 Insulating Film 2007 Insulating Film 2008 Insulating Film 2101 Plug 2102 Plug 2103 Plug 2104 Plug 2105 Plug 2106 Plug 2107 Plug 2108 Plug 2201 Channel formation region 2202 Impurity region 2203 Impurity region 2204 Gate Insulator 2205 Gridgate 2206 Sidewall insulation layer 2301 Wiring 2302 Wiring 2401 Electrode 2402 Electrode 2403 Insulating film 2501 Wiring 2502 Wiring 2601 Electrode 2602 Electrode 2603 Insulating film 2701 Conductive film 2702 Conductive film 4000 RF tags

Claims

1. It comprises first to third transistors, a capacitive element, and a power line. The source and drain of the first transistor are electrically connected to the gate of the second transistor and to one electrode of the capacitive element. The source and drain of the first transistor are electrically connected to one of the source and drain of the second transistor. The source and drain of the second transistor are electrically connected to one of the source and drain of the third transistor. The source and drain of the third transistor are connected electrically to the power line, and the other is a semiconductor device. A semiconductor film having a channel formation region for the second transistor and a channel formation region for the third transistor, A first conductive film having a region located above the semiconductor film and functioning as one electrode of the capacitive element, A first insulating film having nitrogen and silicon and having a region located above the first conductive film, A second conductive film having a region that overlaps with the first conductive film via the first insulating film, and functioning as the other electrode of the capacitive element, A second insulating film having a region located above the second conductive film and comprising oxygen and silicon, An oxide semiconductor film having a region located above the second insulating film and having a channel formation region for the first transistor, A third conductive film having a region located above the oxide semiconductor film and functioning as the gate electrode of the first transistor, A fourth conductive film having a region located above the oxide semiconductor film and functioning as one of the source electrode and drain electrode of the first transistor, A fifth conductive film having the same material as the fourth conductive film, A third insulating film having a region located above the third conductive film, a region located above the fourth conductive film, and a region located above the fifth conductive film, A sixth conductive film having a region located above the third insulating film and functioning as the power line, The sixth conductive film is electrically connected to the semiconductor film via the fifth conductive film. The semiconductor film has silicon, The oxide semiconductor film has In, Ga, and Zn. The first transistor and the second transistor are arranged such that the channel length direction of the first transistor and the channel length direction of the second transistor are aligned along the first direction. Semiconductor equipment.

2. It comprises first to third transistors, a capacitive element, and a power line. The source and drain of the first transistor are electrically connected to the gate of the second transistor and to one electrode of the capacitive element. The source and drain of the first transistor are electrically connected to one of the source and drain of the second transistor. The source and drain of the second transistor are electrically connected to one of the source and drain of the third transistor. The source and drain of the third transistor are connected electrically to the power line, and the other is a semiconductor device. A semiconductor film having a channel formation region for the second transistor and a channel formation region for the third transistor, A first conductive film having a region located above the semiconductor film and functioning as one electrode of the capacitive element, A first insulating film having nitrogen and silicon and having a region located above the first conductive film, A second conductive film having a region that overlaps with the first conductive film via the first insulating film, and functioning as the other electrode of the capacitive element, A second insulating film having a region located above the second conductive film and comprising oxygen and silicon, An oxide semiconductor film having a region located above the second insulating film and having a channel formation region for the first transistor, A third conductive film having a region located above the oxide semiconductor film and functioning as the gate electrode of the first transistor, A fourth conductive film having a region located above the oxide semiconductor film and functioning as one of the source electrode and drain electrode of the first transistor, A fifth conductive film having the same material as the fourth conductive film, A third insulating film having a region in contact with the upper surface of the fourth conductive film and a region in contact with the upper surface of the fifth conductive film, A sixth conductive film having a region located above the third insulating film and functioning as the power line, The sixth conductive film is electrically connected to the semiconductor film via the fifth conductive film. The semiconductor film has silicon, The oxide semiconductor film has In, Ga, and Zn. The first transistor and the second transistor are arranged such that the channel length direction of the first transistor and the channel length direction of the second transistor are aligned along the first direction. Semiconductor equipment.

3. It comprises first to third transistors, a capacitive element, and a power line. The source and drain of the first transistor are electrically connected to the gate of the second transistor and to one electrode of the capacitive element. The source and drain of the first transistor are electrically connected to one of the source and drain of the second transistor. The source and drain of the second transistor are electrically connected to one of the source and drain of the third transistor. The source and drain of the third transistor are connected electrically to the power line, and the other is a semiconductor device. A semiconductor film having a channel formation region for the second transistor and a channel formation region for the third transistor, A first conductive film having a region located above the semiconductor film and functioning as one electrode of the capacitive element, A first insulating film having nitrogen and silicon and having a region located above the first conductive film, A second conductive film having a region that overlaps with the first conductive film via the first insulating film, and functioning as the other electrode of the capacitive element, A second insulating film having a region located above the second conductive film and comprising oxygen and silicon, An oxide semiconductor film having a region located above the second insulating film and having a channel formation region for the first transistor, A third conductive film having a region located above the oxide semiconductor film and functioning as the gate electrode of the first transistor, A fourth conductive film having a region located above the oxide semiconductor film and functioning as one of the source electrode and drain electrode of the first transistor, A fifth conductive film having the same material as the fourth conductive film, A third insulating film having a region in contact with the upper surface of the fourth conductive film and a region in contact with the upper surface of the fifth conductive film, A sixth conductive film having a region located above the third insulating film and functioning as the power line, The sixth conductive film is electrically connected to the semiconductor film via the fifth conductive film. The semiconductor film has silicon, The oxide semiconductor film has In, Ga, and Zn. The first transistor and the second transistor are arranged such that the channel length direction of the first transistor and the channel length direction of the second transistor are aligned along the first direction. In a cross-sectional view in the first direction, the first conductive film does not have a region that overlaps with the channel formation region of the third transistor. Semiconductor equipment.

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