Shift register and driving method thereof, light emitting control circuit, and display device

Abstract

Embodiments of the present application provide a shift register and a driving method thereof, a light emitting control circuit and a display device. The shift register is electrically connected with a first signal line and a second signal line respectively. The first signal line is a trigger signal line or a cascade line between the shift register and other stage shift registers. In a first working mode, the shift register outputs a first driving signal in response to a first signal of the first signal line. In a second working mode, the shift register outputs a second driving signal in response to a second signal of the second signal line. The embodiments of the present application can solve the problem that the working mode of the shift register in the related art is relatively single.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a shift register and its driving method, a light-emitting control circuit and a display device. Background Technology

[0002] In the field of display, a display panel includes sub-pixels, and each sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit can control whether the light-emitting element emits light under the drive of the light-emitting control circuit.

[0003] The light emission control circuit may include multiple shift registers. In related technologies, multiple shift registers are cascaded. Due to the current structure of the light emission control circuit, the working mode of multiple shift registers is relatively simple. Summary of the Invention

[0004] This application provides a shift register and its driving method, a light-emitting control circuit, and a display device, which can solve the problem that the shift register has a relatively simple working mode in related technologies.

[0005] In a first aspect, embodiments of this application provide a shift register, which is electrically connected to a first signal line and a second signal line, wherein the first signal line is a trigger signal line or a cascaded routing line between the shift register and other stage shift registers; in a first operating mode, the shift register responds to a first signal on the first signal line and outputs a first drive signal; in a second operating mode, the shift register responds to a second signal on the second signal line and outputs a second drive signal.

[0006] Secondly, embodiments of this application provide a light-emitting control circuit, including a shift register as described in the first aspect embodiment.

[0007] Thirdly, this application also provides a driving method for a shift register as described in the first aspect of the embodiment above. The shift register includes a first high-level output stage, a first low-level output stage, a second low-level output stage, a third low-level output stage, and a second high-level output stage in a first working mode or a second working mode. The driving methods include: During the first high-level output phase, the first clock signal line provides a cutoff level, while the second clock signal line and the input of the shift register provide a conduction level. The sixth control module, responding to the conduction level of the fifth node, writes the conduction level of the second clock signal line into the fourth node. The fifth control module, responding to the conduction level of the fourth node, writes the conduction level of the second clock signal line into the first node. The first output module, responding to the conduction level of the first node, writes the high level of the first power supply voltage signal line into the output of the shift register. The second node remains at a cutoff level, and the second output module, responding to the cutoff level of the second node, turns off. During the first low-level output phase, the first clock signal line and the input of the shift register are provided with an on level, and the second clock signal line is provided with an off level. The first control module responds to the on level of the first clock signal line by writing the on level of the shift register's input to the third node; the second control module responds to the on level of the third node by writing the off level of the first power supply voltage signal line to the first node; the first output module responds to the off level of the first node by turning off; the third control module responds to the on level of the first clock signal line by writing the on level of the shift register's input to the second node; the fourth control module responds to the on level of the second power supply voltage signal line by writing the on level of the third node to the second node; and the second output module responds to the on level of the second node by writing the low level of the second power supply voltage signal line to the output of the shift register. During the second low-level output phase, the first clock signal line provides a cutoff level, the second clock signal line and the input of the shift register provide a conduction level, the second storage module maintains the first node at a cutoff level, and the first output module turns off in response to the cutoff level of the first node; the second coupling module maintains the second node at a conduction level, and the second output module turns on in response to the conduction level of the second node, writing the low level of the second power supply voltage signal line into the output of the shift register; In the third low-level output phase, the first clock signal line provides an on level, and the second clock signal line and the input of the shift register provide an off level. The first control module, responding to the on level of the first clock signal line, writes the off level of the shift register's input to the third node. The seventh control module, responding to the on level of the first clock signal line, writes the off level of the first power supply voltage signal line to the fifth node. The sixth control module, responding to the on level of the fifth node, writes the off level of the second clock signal line to the fourth node. The fifth control module, responding to the off level of the second clock signal line, turns off. The second control module, responding to the off level of the third node, turns off. The second storage module maintains the first node at the off level, and the first output module, responding to the off level of the first node, turns off. The fourth control module, responding to the on level of the second power supply voltage signal line, writes the off level of the third node to the second node. The second output module, responding to the off level of the second node, turns off, and the output of the shift register remains at the low level of the previous phase. During the second high-level output phase, the first clock signal line provides a cutoff level, the second clock signal line provides a conduction level, the input of the shift register provides a cutoff level, the fifth node remains on, the sixth control module responds to the conduction level of the fifth node and writes the conduction level of the second clock signal line into the fourth node; the fifth control module responds to the conduction level of the second clock signal line and writes the conduction level of the fourth node into the first node; the first output module responds to the conduction level of the first node and writes the high level of the first power supply voltage signal line into the output of the shift register; the second coupling module maintains the second node at a cutoff level, and the second output module responds to the cutoff level of the second node and turns off.

[0008] Fourthly, embodiments of this application also provide a driving method applied to a shift register as described in the first aspect of the embodiment above, wherein the shift register includes a fourth low-level output stage and a fifth low-level output stage in a second operating mode; The driving methods include: In the fourth low-level output phase, the second clock signal line provides an on level, the first sub-signal line provides an on level, the second sub-signal line provides an off level, and the third switch signal line provides an on level. The eighth control module responds to the on level of the third switch signal line by writing the on level of the first sub-signal line into the third node; the second control module responds to the on level of the third node by writing the off level of the first power supply voltage signal line into the first node; the first output module responds to the off level of the first node by turning off; the ninth control module responds to the on level of the third switch signal line by writing the on level of the first sub-signal line into the seventh node; the fourth... The control module responds to the on-level of the second power supply voltage signal line by writing the on-level of the third node into the second node; the second output module responds to the on-level of the second node by writing the low level of the second power supply voltage signal line into the output of the shift register; the fifth node is at the off-level, and the second coupling control unit responds to the off-level of the fifth node by turning off; the first coupling control unit responds to the on-level of the third switch signal line by turning on, and the second clock signal line jumps from high to low, further pulling down the potential of the sixth node through the first coupling module; the second switch module turns on, and the lower potential of the sixth node enters the second node, making the second output module more fully open; During the fifth low-level output phase, the first clock signal line provides a cutoff level, the second clock signal line provides a cutoff level, the first sub-signal line provides a conduction level, the second sub-signal line provides a cutoff level, and the third switch signal line provides a conduction level. The eighth control module responds to the conduction level of the third switch signal line by writing the conduction level of the first sub-signal line into the third node. The second control module responds to the conduction level of the third node by writing the cutoff level of the first power supply voltage signal line into the first node. The first output module responds to the cutoff level of the first node by turning off. The ninth control module responds to the conduction level of the third switch signal line by turning on. The first sub-signal line's conduction level is written to the seventh node; the fourth control module, responding to the conduction level of the second power supply voltage signal line, writes the conduction level of the third node to the second node; the second output module, responding to the conduction level of the second node, writes the low level of the second power supply voltage signal line to the output of the shift register; the fifth node is at the cutoff level, and the second coupling control unit, responding to the cutoff level of the fifth node, turns off; the first coupling control unit, responding to the conduction level of the third switch signal line, turns on, and the second clock signal line jumps from low to high, further pulling up the potential of the sixth node through the first coupling module; the second switch module turns off.

[0009] Fifthly, embodiments of this application also provide a display device, including the light-emitting control circuit as described in the second aspect embodiment.

[0010] In this embodiment, the trigger signal of the shift register is no longer singular, but is triggered by the first signal of the first signal line in the first working mode and by the second signal of the second signal line in the second working mode, so that the working mode of the shift register is no longer singular, but supports multiple working modes. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a shift register connection in related technologies; Figure 2 yes Figure 1 A timing diagram; Figure 3 This is a schematic diagram of a shift register provided in an embodiment of this application; Figure 4 This is a schematic diagram of the connection of multiple shift registers in the light-emitting control circuit provided in the embodiment of this application; Figure 5 yes Figure 4 A timing diagram of the first operating mode; Figure 6 yes Figure 4 A timing diagram of the second working mode; Figure 7 This is another schematic diagram showing the connection of multiple shift registers in the light-emitting control circuit provided in the embodiments of this application; Figure 8 Show Figure 7 A schematic diagram of a switch module; Figure 9 This application provides a schematic diagram of a module structure of a shift register; Figure 10 A schematic diagram of a shift register provided in an embodiment of this application; Figure 11 Another schematic diagram of the shift register structure provided in the embodiments of this application; Figure 12 Another schematic diagram of the module structure of the shift register provided in the embodiments of this application; Figure 13 Another schematic diagram of a shift register structure provided in this application embodiment; Figure 14 This application provides another schematic diagram of a shift register module structure; Figure 15 Another schematic diagram of a shift register structure provided in this application embodiment; Figure 16 This is another schematic diagram showing the connection of multiple shift registers in the light-emitting control circuit provided in the embodiments of this application; Figure 17 This is a flowchart illustrating a driving method for a shift register provided in an embodiment of this application; Figure 18 yes Figure 11 A timing diagram of the first operating mode; Figure 19 yes Figure 11 A timing diagram of the second working mode; Figure 20 This is a flowchart illustrating another driving method for the shift register provided in an embodiment of this application; Figure 21 yes Figure 13 or Figure 14 A timing diagram of the second working mode; Figure 22 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0013] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0014] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0015] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0016] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-state level is high and the off-state level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-state level is low and the off-state level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. In specific implementations, the gate of each transistor is used as its control terminal. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa. No distinction is made here. Additionally, the on-state and off-state levels in the embodiments of this invention are general terms. The on-state level refers to any level that enables the transistor to conduct, and the off-state level refers to any level that enables the transistor to turn off / become off.

[0017] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0018] In the embodiments of this application, the first node, the second node, and the third node are defined only for the convenience of describing the circuit structure, and the first node, the second node, and the third node are not actual circuit units.

[0019] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0020] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies: As mentioned earlier, a limitation of related technologies is that shift registers have a relatively limited operating mode. For example, ... Figure 1 and Figure 2 As shown, in related technologies, multiple shift registers VSR' in the light-emitting control circuit are cascaded sequentially. The enable level output by the shift registers VSR' can only be transmitted one stage at a time through cascading. Thus, multiple shift registers VSR' can only output the conduction level stage by stage. Figure 2 (Illustrated with a low level), the shift register has a relatively simple operating mode. The on-state level of the shift register VSR' can be the level that controls the emission of sub-pixels. For example, a first-level shift register VSR' is used to drive a row of sub-pixels. In related technologies, it can only control multiple rows of sub-pixels to emit light one row at a time, and cannot achieve the function of controlling multiple rows of sub-pixels to emit light simultaneously.

[0021] To address the aforementioned technical problems, this application provides a shift register and its driving method, a light-emitting control circuit, and a display device. The various embodiments of this application will be described below with reference to the accompanying drawings.

[0022] like Figure 3 As shown, this application provides a shift register 10, which is electrically connected to a first signal line 21 and a second signal line 22. The first signal line 21 is a trigger signal line, which is electrically connected to a driver chip; alternatively, the first signal line 211 is a cascaded trace 210 between the current-stage shift register and other-stage shift registers, used to transmit signals output from other-stage shift registers to the current-stage shift register. Additionally, the second signal line 22 is electrically connected to the driver chip.

[0023] For example, such as Figure 4 As shown, the light-emitting control circuit EM includes an m-stage shift register 10, where m is an integer greater than 1. For the first-stage shift register 10(1), the first signal line 21 electrically connected to the first-stage shift register 10(1) is the trigger signal line STV. For the second-stage shift register 10(2), the first signal line 21 electrically connected to it is the cascaded trace 210 between the first-stage shift register 10(1) and the second-stage shift register 10(2). For the third-stage shift register 10(3), the first signal line 21 electrically connected to it is the cascaded trace between the second-stage shift register 10(2) and the third-stage shift register 10(3). Similarly, for the m-th stage shift register 10(2), the first signal line 21 electrically connected to it is the cascaded trace between the (m-1)-th stage shift register 10(m-1) and the m-th stage shift register 10(m). In addition, each shift register is electrically connected to the same second signal line 22. For example, the first-stage shift register 10(1) to the m-th-stage shift register 10(m) are electrically connected to the same second signal line 22.

[0024] The shift register 10 supports multiple operating modes. In the first operating mode, the shift register 10 responds to the first signal on the first signal line 21 and outputs the first drive signal. In the second operating mode, the shift register 10 responds to the second signal on the second signal line 22 and outputs the second drive signal.

[0025] Both the first signal and the second signal can be signals that trigger the shift register 10 to work. In this embodiment, the trigger signal of the shift register 10 is no longer single. Instead, in the first working mode, it is triggered by the first signal of the first signal line 21; in the second working mode, it is triggered by the second signal of the second signal line 22, so that the working mode of the shift register is no longer single, but supports multiple working modes.

[0026] In some embodiments, in a first operating mode, shift register 10 outputs the first drive signal in a time-sharing manner with other shift register stages.

[0027] For example, the first or second signal output by shift register 10 can be used to control whether a sub-pixel emits light. One shift register 10 is used to drive one row of sub-pixels, while multiple rows of sub-pixels are driven by multiple shift registers.

[0028] Shift register 10 connects to sub-pixels in different rows with other shift registers. In the first operating mode, shift register 10 and other shift registers drive sub-pixels in different rows to emit light in a time-division manner, where time-division means different start times.

[0029] In the first operating mode, the shift register is triggered by the first signal of the first signal line 21. The first signal line 21 electrically connected to the first-stage shift register 10(1) is the trigger signal line STV. The first signal lines 21 electrically connected to other stage shift registers besides the first-stage shift register 10(1) are cascaded traces 210. Figure 5 As shown, in the first working mode mode1, the first-level shift register 10(1) to the m-th level shift register 10(m) are triggered step by step, and the first-level shift register 10(1) to the m-th level shift register 10(m) output the first signal step by step, thereby driving the multi-row sub-pixels to emit light line by line.

[0030] In some embodiments, in the second operating mode, shift register 10 outputs the second drive signal simultaneously with other shift register stages.

[0031] Shift register 10 connects to sub-pixels in different rows with other shift registers. In the second working mode, shift register 10 and other shift registers drive sub-pixels in different rows to emit light simultaneously. Here, "simultaneously" includes the same start time.

[0032] In the second operating mode, the shift register is triggered by the second signal of the second signal line 22. The first-stage shift register 10(1) to the m-th-stage shift register 10(m) can be connected to the same second signal line 22, such as... Figure 6 As shown, in the second working mode mode2, the first-level shift register 10(1) to the m-th level shift register 10(m) are triggered simultaneously, and the first-level shift register 10(1) to the m-th level shift register 10(m) simultaneously output the second signal, thereby driving multiple rows of sub-pixels to emit light simultaneously.

[0033] According to the shift register provided in the embodiments of this application, the shift register can support multiple working modes. In the first working mode (e.g., progressive scan mode), the shift register can respond to the first signal of the first signal line (trigger signal line STV or cascaded wiring) and output a first driving signal. In the second working mode, the shift register can respond to the second signal of the second signal line and output a second driving signal. When the shift register outputs the second driving signal, it can output the second driving signal simultaneously with other shift registers, thereby supporting multi-line simultaneous scan mode.

[0034] In some embodiments, such as Figure 7 As shown, the input terminal IN of the shift register 10 is electrically connected to the first signal line 21 through the first switch module 31, and the input terminal IN of the shift register 10 is electrically connected to the second signal line 22 through the second switch module 32. In the first working mode, the first switch module 31 is turned on and the second switch module 32 is turned off. In the second working mode, the second switch module 32 is turned on and the first switch module 31 is turned off.

[0035] Specifically, the first terminal of the first switch module 31 is electrically connected to the first signal line 21, and the second terminal of the first switch module 31 is electrically connected to the input terminal IN of the shift register 10; the first terminal of the second switch module 32 is electrically connected to the second signal line 22, and the second terminal of the second switch module 32 is electrically connected to the input terminal IN of the shift register 10. The first switch module 31 and the second switch module 32 are not simultaneously turned on; therefore, the signals from the first signal line 21 and the second signal line 22 are not simultaneously transmitted to the input terminal IN of the shift register 10.

[0036] In the first working mode, the first switch module 31 is turned on, the first signal of the first signal line 21 triggers the operation of the shift register, and the signal output by the output terminal OUT of the previous shift register 10 serves as the trigger signal for the input terminal IN of the next shift register 10, which can drive multiple rows of sub-pixels to emit light row by row.

[0037] In the second working mode, the second switch module 32 is turned on, and the second signal of the second signal line 22 triggers each shift register to work simultaneously, which can drive multiple rows of sub-pixels to emit light simultaneously.

[0038] In some embodiments, such as Figure 8 As shown, the first switch module 31 includes a first transistor M1, the gate of the first transistor M1 is electrically connected to the first switch signal line SW1, the first terminal of the first transistor M1 is electrically connected to the first signal line 21, and the second terminal of the first transistor M1 is electrically connected to the input terminal IN of the shift register 10; the second switch module 32 includes a second transistor M2, the gate of the second transistor M2 is electrically connected to the second switch signal line SW2, the first terminal of the second transistor M2 is electrically connected to the second signal line 22, and the second terminal of the second transistor M2 is electrically connected to the input terminal IN of the shift register 10.

[0039] The control signal on the first switch signal line SW1 is used to control whether the first transistor M1 is turned on or off, and the control signal on the second switch signal line SW2 is used to control whether the second transistor M2 is turned on or off. The first switch signal line SW1 and the second switch signal line SW2 are electrically connected to the driver chip, which provides them with control signals.

[0040] In the first operating mode, the control signal on the first switch signal line SW1 is at the on level, the control signal on the second switch signal line SW2 is at the off level, the first transistor M1 is turned on, and the second transistor M2 is turned off.

[0041] In the second operating mode, the control signal on the first switch signal line SW1 is at the cutoff level, the control signal on the second switch signal line SW2 is at the on level, the first transistor M1 is turned off, and the second transistor M2 is turned on.

[0042] In some embodiments, such as Figure 9 As shown, the shift register 10 includes a first output module 101, a second output module 102, a first control module 103, a second control module 104, a third control module 105, and a fourth control module 106.

[0043] The control terminal of the first output module 101 is electrically connected to the first node Q1, the first terminal of the first output module 101 is electrically connected to the first power supply voltage signal line VGH, and the second terminal of the first output module 101 is electrically connected to the output terminal OUT of the shift register 10.

[0044] The control terminal of the second output module 102 is electrically connected to the second node Q2, the first terminal of the second output module 102 is electrically connected to the second power supply voltage signal line VGL, and the second terminal of the second output module 102 is electrically connected to the output terminal OUT of the shift register 10.

[0045] For example, the first power supply voltage signal line VGH provides a high level, and the second power supply voltage signal line VGL provides a low level.

[0046] The control terminal of the first control module 103 is electrically connected to the first clock signal line CK. The first terminal of the first control module 103 is electrically connected to the input terminal IN of the shift register 10. The second terminal of the first control module 103 is electrically connected to the third node Q3. The first control module 103 is used to transmit the first signal or the second signal of the input terminal IN of the shift register 10 to the third node Q3 under the control of the first clock signal line CK.

[0047] The control terminal of the second control module 104 is electrically connected to the third node Q3. The first terminal of the second control module 104 is electrically connected to the first power supply voltage signal line VGH. The second terminal of the second control module 104 is electrically connected to the first node Q1. The second control module 104 is used to write the cutoff level of the first power supply voltage signal line VGH into the first node Q1 under the control of the third node Q3.

[0048] The control terminal of the third control module 105 is electrically connected to the first clock signal line CK. The first terminal of the third control module 105 is electrically connected to the input terminal IN of the shift register 10. The second terminal of the third control module 105 is electrically connected to the second node Q2. The third control module 105 is used to write the first signal or the second signal of the input terminal IN of the shift register 10 into the second node Q2 under the control of the first clock signal line CK.

[0049] The control terminal of the fourth control module 106 is electrically connected to the second power supply voltage signal line VGL. The first terminal of the fourth control module 106 is electrically connected to the third node Q3. The second terminal of the fourth control module 106 is electrically connected to the second node Q2. The fourth control module 106 is used to write the on or off level of the third node Q3 into the second node Q2 under the control of the second power supply voltage signal line VGL.

[0050] In this embodiment, the first control module 103 is used to control the potential of the third node Q3, the second control module 104 is used to control the potential of the first node Q1, and the third control module 105 and the fourth control module 106 are used to control the potential of the second node Q2. The first node Q1 is used to control the state of the first output module 101, and the second node Q2 is used to control the state of the second output module 102. When the first node Q1 is at the on level, the first output module 101 is turned on, and the high level of the first power supply voltage signal line VGH is transmitted to the output terminal OUT. When the second node Q2 is at the on level, the low level of the second power supply voltage signal line VGL is transmitted to the output terminal OUT.

[0051] The signals at the input terminals IN connected to the first control module 103 and the third control module 105 come from the first signal line 21 or the second signal line 22.

[0052] For example, such as Figure 10 As shown, the first output module 101 includes a third transistor M3, the second output module 102 includes a fourth transistor M4, the first control module 103 includes a fifth transistor M5, the second control module 104 includes a sixth transistor M6, the third control module 105 includes a seventh transistor M7, and the fourth control module 106 includes an eighth transistor M8. The gate of the third transistor M3 is electrically connected to the first node Q1, the first terminal of the third transistor M3 is electrically connected to the first power supply voltage signal line VGH, and the second terminal of the third transistor M3 is electrically connected to the output terminal OUT of the shift register 10.

[0053] The gate of the fourth transistor M4 is electrically connected to the second node Q2, the first terminal of the fourth transistor M4 is electrically connected to the second power supply voltage signal line VGL, and the second terminal of the fourth transistor M4 is electrically connected to the output terminal OUT of the shift register 10.

[0054] The gate of the fifth transistor M5 is electrically connected to the first clock signal line CK, the first terminal of the fifth transistor M5 is electrically connected to the input terminal IN of the shift register 10, and the second terminal of the fifth transistor M5 is electrically connected to the third node Q3.

[0055] The gate of the sixth transistor M6 is electrically connected to the third node Q3, the first terminal of the sixth transistor M6 is electrically connected to the first power supply voltage signal line VGH, and the second terminal of the sixth transistor M6 is electrically connected to the first node Q1.

[0056] The gate of the seventh transistor M7 is electrically connected to the first clock signal line CK, the first terminal of the seventh transistor M7 is electrically connected to the input terminal IN of the shift register 10, and the second terminal of the seventh transistor M7 is electrically connected to the second node Q2.

[0057] The gate of the eighth transistor M8 is electrically connected to the second power supply voltage signal line VGL, the first terminal of the eighth transistor M8 is electrically connected to the third node Q3, and the second terminal of the eighth transistor M8 is electrically connected to the second node Q2.

[0058] In some embodiments, such as Figure 9 As shown, the shift register also includes a fifth control module 107, a first storage module 108, a sixth control module 109, and a seventh control module 110; The control terminal of the fifth control module 107 is electrically connected to the second clock signal line CKB, the first terminal of the fifth control module 107 is electrically connected to the fourth node Q4, and the second terminal of the fifth control module 107 is electrically connected to the first node Q1. The first end of the first storage module 108 is electrically connected to the fifth node Q5, and the second end of the first storage module 108 is electrically connected to the fourth node Q4. The control terminal of the sixth control module 109 is electrically connected to the fifth node Q5, the first terminal of the sixth control module 109 is electrically connected to the second clock signal line CKB, and the second terminal of the sixth control module 109 is electrically connected to the fourth node Q4. The sixth control module 109 is used to write the second clock signal of the second clock signal line CKB into the fourth node Q4 under the control of the fifth node Q5. The control terminal of the seventh control module 110 is electrically connected to the first clock signal line CK, the first terminal of the seventh control module 110 is electrically connected to the second power supply voltage signal line VGL, and the second terminal of the seventh control module 110 is electrically connected to the fifth node Q5. The seventh control module 110 is used to write the conduction level of the second power supply voltage signal line VGL into the fifth node Q5 under the control of the first clock signal line CK.

[0059] In this embodiment, the fifth control module 107 is used to control the potential of the first node Q1, the sixth control module 109 is used to control the potential of the fourth node Q4, the first storage module 108 is used to stabilize the potential of the fourth node Q4, and the seventh control module 110 is used to control the potential of the fifth node Q5. Through the cooperation of the first control module 103, the second control module 104, the fifth control module 107, the first storage module 108, the sixth control module 109, and the seventh control module 110, the stability and reliability of the potential control of the first node Q1 can be improved.

[0060] For example, such as Figure 10 As shown, the fifth control module 107 includes a ninth transistor M9, the first storage module 108 includes a first capacitor C1, the sixth control module 109 includes a tenth transistor M10, and the seventh control module 110 includes an eleventh transistor M11.

[0061] The gate of the ninth transistor M9 is electrically connected to the second clock signal line CKB, the first terminal of the ninth transistor M9 is electrically connected to the fourth node Q4, and the second terminal of the ninth transistor M9 is electrically connected to the first node Q1.

[0062] The first terminal of the first capacitor C1 is electrically connected to the fifth node Q5, and the second terminal of the first capacitor C1 is electrically connected to the fourth node Q4.

[0063] The gate of the tenth transistor M10 is electrically connected to the fifth node Q5, the first terminal of the tenth transistor M10 is electrically connected to the second clock signal line CKB, and the second terminal of the tenth transistor M10 is electrically connected to the fourth node Q4.

[0064] The gate of the eleventh transistor M11 is electrically connected to the first clock signal line CK, the first terminal of the eleventh transistor M11 is electrically connected to the second power supply voltage signal line VGL, and the second terminal of the eleventh transistor M11 is electrically connected to the fifth node Q5.

[0065] In some embodiments, such as Figure 9 As shown, the shift register also includes a first coupling module 111 and a coupling control module 112; The first end of the first coupling module 111 is electrically connected to the second node Q2; The coupling control module 112 is electrically connected to the second node Q2, the fifth node Q5, the second clock signal line CKB, the first power supply voltage signal line VGH, and the second terminal of the first coupling module 111. Under the control of the fifth node Q5, the coupling control module 112 is used to write the cutoff level of the first power supply voltage signal line VGH into the second terminal of the first coupling module 111, and under the control of the second node Q2, write the second clock signal of the second clock signal line CKB into the second terminal of the first coupling module 111.

[0066] For example, when the second node Q2 is on, the coupling control module 112 transmits the low level of the second clock signal line CKB to the second terminal of the first coupling module 111. Through the coupling effect of the first coupling module 111, the potential of the second node Q2 is further pulled down, making the second output module 102 more fully turned on, thereby making the output terminal OUT output a lower and more stable low level. When the fifth node Q5 is on, the coupling control module 112 writes the cutoff level of the first power supply voltage signal line VGH to the second terminal of the first coupling module 111, making the second node Q2 cutoff, preventing the first output module 101 and the second output module 102 from being turned on simultaneously and causing timing errors.

[0067] For example, such as Figure 10 As shown, the first coupling module 111 includes a second capacitor C2, and the coupling control module 112 includes a twelfth transistor M12 and a thirteenth transistor M13; The first terminal of the second capacitor C2 is electrically connected to the second node Q2; The gate of the twelfth transistor M12 is electrically connected to the fifth node Q5, the first terminal of the twelfth transistor M12 is electrically connected to the first power supply voltage signal line VGH, and the second terminal of the twelfth transistor M12 is electrically connected to the second terminal of the second capacitor C2. The gate of the thirteenth transistor M13 is electrically connected to the second node Q2, the first terminal of the thirteenth transistor M13 is electrically connected to the second clock signal line CKB, and the second terminal of the thirteenth transistor M13 is electrically connected to the second terminal of the second capacitor C2.

[0068] In some embodiments, such as Figure 9As shown, the shift register also includes a third switch module 113; the control terminal and the first terminal of the third switch module 113 are electrically connected to the sixth node Q6, and the second terminal of the third switch module 113 is electrically connected to the second node Q2; the second terminal of the third control module 113 and the first terminal of the first coupling module 111 are both electrically connected to the sixth node Q6.

[0069] For example, such as Figure 10 As shown, the third switch module 113 includes a fourteenth transistor M14. The gate and first terminal of the fourteenth transistor M14 are electrically connected to the sixth node Q6, and the second terminal of the fourteenth transistor M14 is electrically connected to the second node Q2. The fourteenth transistor M14 forms a diode, which can allow a lower level on the sixth node Q6 to be written to the second node Q2, and can prevent a higher level from being written to the second node Q2 when the sixth node Q6 is pulled high.

[0070] In some embodiments, such as Figure 10 As shown, the coupling control module includes a first coupling control unit 1121 and a second coupling control unit 1122; The control terminal of the first coupling control unit 1121 is electrically connected to the sixth node Q6. The first terminal of the first coupling control unit 1121 is electrically connected to the second clock signal line (CKB). The second terminal of the first coupling control unit 1121 is electrically connected to the second terminal of the first coupling module 111. The first coupling control unit 1121 is used to transmit the second clock signal of the second clock signal line (CKB) to the second terminal of the first coupling module 111 under the control of the sixth node Q6. The control terminal of the second coupling control unit 1122 is electrically connected to the fifth node Q5. The first terminal of the second coupling control unit 1122 is electrically connected to the first power supply voltage signal line VGH. The second terminal of the second coupling control unit 1122 is electrically connected to the second terminal of the first coupling module 111. The second coupling control unit 1122 is used to transmit the first power supply voltage signal of the first power supply voltage signal line VGH to the second terminal of the first coupling module 111 under the control of the fifth node Q5.

[0071] In this embodiment, different signals are transmitted to the second end of the first coupling module 111 by two coupling control units, which can ensure the accuracy of signal transmission.

[0072] For example, the second coupling control unit 1122 includes a twelfth transistor M12, and the first coupling control unit 1121 includes a thirteenth transistor M13. The above example illustrates the connection relationship between the twelfth transistor M12 and the thirteenth transistor M13, which will not be repeated here.

[0073] In some embodiments, such as Figure 10As shown, the shift register also includes a fourth switch module 114. The control terminal of the fourth switch module 114 is electrically connected to the second power supply voltage signal line VGL. The first terminal of the fourth switch module 114 is electrically connected to the sixth node Q6. The second terminal of the fourth switch module 114 is electrically connected to the seventh node Q7. The seventh node Q7 is electrically connected to the second terminal of the third control module 105.

[0074] For example, the fourth switch module 114 includes a fourteenth transistor M14, the gate of the fourteenth transistor M14 is electrically connected to the second power supply voltage signal line VGL, the first terminal of the fourteenth transistor M14 is electrically connected to the sixth node Q6, and the second terminal of the fourteenth transistor M14 is electrically connected to the seventh node Q7.

[0075] When the potential of the sixth node Q6 is low, the fourteenth transistor M14 can prevent the low potential from entering the seventh node Q7, thereby protecting the devices of the third control module 105.

[0076] In some embodiments, such as Figure 10 As shown, the shift register also includes a fifth switch module 115. The control terminal of the fifth switch module 115 is electrically connected to the second power supply voltage signal line VGL. The first terminal of the fifth switch module 115 is electrically connected to the fifth node Q5. The second terminal of the fifth switch module 115 is electrically connected to the first terminal of the first storage module 108.

[0077] For example, the fifth switch module 115 includes a fifteenth transistor M15, the gate of the fifteenth transistor M15 is electrically connected to the second power supply voltage signal line VGL, the first terminal of the fifteenth transistor M15 is electrically connected to the fifth node Q5, and the second terminal of the fifteenth transistor M15 is electrically connected to the first terminal of the first storage module 108.

[0078] When the potential of the first terminal of the first storage module 108 is low, the fifteenth transistor M15 can prevent the low potential from entering the fifth node Q5, thereby protecting the device connected to the fifth node Q5.

[0079] In some embodiments, such as Figure 9 and Figure 10 As shown, the shift register 10 also includes a second storage module 116 and a second coupling module 117; The first end of the second storage module 116 is electrically connected to the first node Q1, and the second end of the second storage module 116 is electrically connected to the first power supply voltage signal line VGH. The first end of the second coupling module 117 is electrically connected to the second node Q2, and the second end of the second coupling module 117 is electrically connected to the output terminal OUT of the shift register 10.

[0080] The first power supply voltage signal line VGH is a fixed voltage signal line, and the second storage module 116 can stabilize the potential of the first node Q1. When the output terminal OUT of the shift register 10 changes from high level to low level, the potential of the second node Q2 is further pulled down through the coupling effect of the second coupling module 117, so that the second output module 102 is turned on more fully.

[0081] For example, the second storage module 116 includes a third capacitor C3, and the second coupling module 117 includes a fourth capacitor C4.

[0082] In some embodiments, such as Figure 9 As shown, the shift register 10 also includes a clock signal writing module 118 and a reset module 119; The control terminal of the clock signal writing module 118 is electrically connected to the third node Q3, the first terminal of the clock signal writing module 118 is electrically connected to the first clock signal line CK, and the second terminal of the clock signal writing module 118 is electrically connected to the fifth node Q5. The clock signal writing module 118 is used to write the first clock signal of the first clock signal line CK into the fifth node Q5 under the control of the third node Q3. The control terminal of the reset module 119 is electrically connected to the reset signal line RST. The first terminal of the reset module 119 is electrically connected to the first power supply voltage signal line VGH. The second terminal of the reset module 119 is electrically connected to the third node Q3. The reset module 119 is used to write the first power supply voltage signal of the first power supply voltage signal line VGH into the third node Q3 under the control of the reset signal line RST.

[0083] The clock signal writing module 118 can adjust the potential of the fifth node Q5 based on the signals of the third node Q3 and the first clock signal line CK. The reset module 119 can reset the potential of the third node Q3.

[0084] For example, such as Figure 10 As shown, the reset module 119 includes a seventeenth transistor M17. The gate of the seventeenth transistor M17 is electrically connected to the reset signal line RST. The first terminal of the seventeenth transistor M17 is electrically connected to the first power supply voltage signal line VGH. The second terminal of the seventeenth transistor M17 is electrically connected to the third node Q3.

[0085] In one example, such as Figure 10As shown, the clock signal writing module 118 may include at least one sixteenth transistor M16. The gate of the sixteenth transistor M16 is electrically connected to the third node Q3, the first terminal of the sixteenth transistor M16 is electrically connected to the first clock signal line CK, and the second terminal of the sixteenth transistor M16 is electrically connected to the fifth node Q5. The clock signal writing module 118 may include at least two sixteenth transistors M16 connected in series to reduce the risk of leakage between the first clock signal line CK and the fifth node Q5.

[0086] In some embodiments, such as Figure 11 As shown, the input terminal IN is electrically connected to the first signal line 21 through the first switch module 31, and the input terminal IN is electrically connected to the second signal line 22 through the second switch module 32. In the first working mode, the first switch module 31 is turned on, and the signal of the input terminal IN is the first signal on the first signal line 21. In the second working mode, the second switch module 32 is turned on, and the signal of the input terminal IN is the second signal on the second signal line 22.

[0087] Figure 11 In the illustrated embodiment, the first switch module 31 is connected between the first-stage shift register and the trigger signal line, or the first switch module 31 is connected between two adjacent shift registers, which is equivalent to a non-embedded design scheme. Multiple working modes of the shift register are realized through the non-embedded design scheme.

[0088] In other embodiments, multiple operating modes of the shift register can also be implemented through an embedded design.

[0089] In some embodiments, such as Figure 12 As shown, the second signal line 22 includes the first sub-signal line 221; the shift register also includes the eighth control module 120 and the ninth control module 121; The control terminal of the eighth control module 120 is electrically connected to the third switch signal line sw3, the first terminal of the eighth control module 120 is electrically connected to the first sub-signal line 221, and the second terminal of the eighth control module 120 is electrically connected to the third node Q3. The eighth control module 120 is used to write the first sub-signal of the first sub-signal line 221 into the third node Q3 under the control of the third switch signal line sw3. The control terminal of the ninth control module 121 is electrically connected to the third switch signal line sw3. The first terminal of the ninth control module 121 is electrically connected to the first sub-signal line 221. The second terminal of the ninth control module 121 is electrically connected to the second node Q2. The ninth control module 121 is used to write the first sub-signal of the first sub-signal line 221 into the second node Q2.

[0090] For example, in the first operating mode, the third switch signal line sw3 provides a cutoff level, and the eighth control module 120 and the ninth control module 121 are turned off; the first clock signal line CK provides a normal high and low level alternating first clock signal, so that the first signal on the first signal line is normally written into the third node Q3 and the second node Q2 through the input terminal IN, and multiple shift registers can drive multiple rows of sub-pixels to emit light row by row.

[0091] In the second operating mode, the third switch signal line sw3 provides a conduction level, and the eighth control module 120 and the ninth control module 121 are turned on; the first clock signal line CK provides a cutoff level, so that the first sub-signal on the first sub-signal line 221 can be written to the third node Q3 and the second node Q2 of multiple shift registers at the same time, and multiple shift registers can drive multiple rows of sub-pixels to emit light at the same time.

[0092] The eighth control module 120 and the ninth control module 121 are connected to the internal nodes of the shift register 10, which is equivalent to an embedded scheme. The multiple working modes of the shift register are realized through the embedded scheme.

[0093] For example, such as Figure 13 As shown, the eighth control module 120 includes an eighteenth transistor M18. The gate of the eighteenth transistor M18 is electrically connected to the third switch signal line sw3, the first terminal of the eighteenth transistor M18 is electrically connected to the first sub-signal line 221, and the second terminal of the eighteenth transistor M18 is electrically connected to the third node Q3. The ninth control module 121 includes a nineteenth transistor M19. The gate of the nineteenth transistor M19 is electrically connected to the third switch signal line sw3, the first terminal of the nineteenth transistor M19 is electrically connected to the first sub-signal line 221, and the second terminal of the nineteenth transistor M19 is electrically connected to the second node Q2.

[0094] In some embodiments, such as Figure 12 As shown, the second signal line 22 also includes a second sub-signal line 222; the shift register 10 also includes a fifth control module 107, a first storage module 108, a sixth control module 109, and a tenth control module 122; The control terminal of the fifth control module 107 is electrically connected to the second clock signal line CKB, the first terminal of the fifth control module 107 is electrically connected to the fourth node Q4, and the second terminal of the fifth control module 107 is electrically connected to the first node Q1. The first end of the first storage module 108 is electrically connected to the fifth node Q5, and the second end of the first storage module 108 is electrically connected to the fourth node Q4. The control terminal of the sixth control module 109 is electrically connected to the fifth node Q5, the first terminal of the sixth control module 109 is electrically connected to the second clock signal line CKB, and the second terminal of the sixth control module 109 is electrically connected to the fourth node Q4. The sixth control module 109 is used to write the second clock signal of the second clock signal line CKB into the fourth node Q4 under the control of the fifth node Q5. The control terminal of the tenth control module 122 is electrically connected to the third switch signal line sw3, the first terminal of the tenth control module 122 is electrically connected to the second sub-signal line 222, and the second terminal of the tenth control module 122 is electrically connected to the fifth node Q5. The tenth control module 122 is used to write the second sub-signal of the second sub-signal line 222 into the fifth node Q5 under the control of the third switch signal line sw3.

[0095] For example, in the first operating mode, the third switch signal line sw3 provides a cutoff level, and the eighth control module 120, the ninth control module 121 and the tenth control module 122 are turned off; the first clock signal line CK provides a normal high and low level alternating first clock signal, so that the first signal on the first signal line is normally written into the third node Q3 and the second node Q2 through the input terminal IN, and multiple shift registers can drive multiple rows of sub-pixels to emit light row by row.

[0096] In the second operating mode, the third switch signal line sw3 provides a conduction level, and the eighth control module 120, the ninth control module 121, and the tenth control module 122 are turned on; the first clock signal line CK provides a cutoff level, so that the first sub-signal on the first sub-signal line 221 can be written to the third node Q3 and the second node Q2 of multiple shift registers at the same time, and the second sub-signal on the second sub-signal line 222 can be written to the fifth node Q5. Multiple shift registers can drive multiple rows of sub-pixels to emit light simultaneously.

[0097] For example, the first sub-signal on the first sub-signal line 221 and the second sub-signal on the second sub-signal line 222 are inverted signals.

[0098] For example, such as Figure 13 As shown, the tenth control module 122 includes a twentieth transistor M20. The gate of the twentieth transistor M20 is electrically connected to the third switch signal line sw3. The first terminal of the twentieth transistor M20 is electrically connected to the second sub-signal line 222. The second terminal of the twentieth transistor M20 is electrically connected to the fifth node Q5.

[0099] In some embodiments, such as Figure 14 As shown, the shift register also includes an eleventh control module 123 and a twelfth control module 124; The control terminal and the first terminal of the eleventh control module 123 are both electrically connected to the first clock signal line CK. The second terminal of the eleventh control module 123 is electrically connected to the fifth node Q5. The eleventh control module 123 is used to transmit the first clock signal of the first clock signal line CK to the fifth node Q5 under the control of the first clock signal line CK. The control terminal of the twelfth control module 124 is electrically connected to the third node Q3, the first terminal of the twelfth control module 124 is electrically connected to the first clock signal line CK, and the second terminal of the twelfth control module 124 is electrically connected to the fifth node Q5. The twelfth control module 124 is used to transmit the first clock signal of the first clock signal line CK to the fifth node Q5 under the control of the third node Q3.

[0100] When the first clock signal line CK is at the on level, the eleventh control module 123 is turned on, and the on level of the first clock signal line CK is transmitted to the fifth node Q5 through the eleventh control module 123.

[0101] When the third node Q3 is at the on level, the twelfth control module 124 is turned on, and the first clock signal of the first clock signal line CK is transmitted to the fifth node Q5 through the twelfth control module 124.

[0102] In some embodiments, such as Figure 15 As shown, the eleventh control module 123 includes a first sub-control unit 1231 and a second sub-control unit 1232, and the twelfth control module 124 includes a third sub-control unit 1243 and a fourth sub-control unit 1244. The control terminals of the first sub-control unit 1231 and the second sub-control unit 1232 are both electrically connected to the first clock signal line CK. The first terminal of the first sub-control unit 1231 is electrically connected to the first clock signal line CK. The second terminal of the first sub-control unit 1231 is electrically connected to the first terminal of the second sub-control unit 1232. The second terminal of the second sub-control unit 1232 is electrically connected to the fifth node Q5. The control terminals of the third sub-control unit 1243 and the fourth sub-control unit 1244 are both electrically connected to the third node Q3. The first terminal of the third sub-control unit 1243 is electrically connected to the first clock signal line CK. The second terminal of the third sub-control unit 1243 is electrically connected to the first terminal of the fourth sub-control unit 1244. The second terminal of the fourth sub-control unit 1244 is electrically connected to the fifth node Q5.

[0103] For example, the first sub-control unit 1231 includes a twenty-first transistor M21, the second sub-control unit 1232 includes a twenty-second transistor M22, the third sub-control unit 1243 includes a twenty-third transistor M23, and the fourth sub-control unit 1244 includes a twenty-fourth transistor M24; the twenty-first transistor M21 and the twenty-second transistor M22 are connected in series between the first clock signal line CK and the second node Q5, and the twenty-third transistor M23 and the twenty-fourth transistor M24 are connected in series between the first clock signal line CK and the second node Q5, which can reduce the risk of leakage current.

[0104] For example, in the case of implementing multiple operating modes of a shift register using an embedded scheme, such as Figure 6 As shown, each shift register 10 is electrically connected to the same first sub-signal line 221, each shift register 10 is electrically connected to the same second sub-signal line 222, and each shift register 10 is electrically connected to the same third switch signal line sw3.

[0105] For example, such as Figure 8 or Figure 6 As shown, regardless of whether a non-embedded scheme or an embedded scheme is adopted, the first clock signal line CK may include the first sub-clock signal line clk1 and the third sub-clock signal line clk3, and the second clock signal line CKB may include the second sub-clock signal line clk2 and the fourth sub-clock signal line clk4. In the two adjacent shift registers 10, one shift register 10 is electrically connected to the first sub-clock signal line clk1 and the second sub-clock signal line clk2, and the other shift register 10 is electrically connected to the third sub-clock signal line clk3 and the fourth sub-clock signal line clk4.

[0106] Based on the same technical concept, embodiments of this application also provide a light-emitting control circuit, such as... Figure 8 or Figure 16 As shown, the light-emitting control circuit EM includes the shift register 10 described in any of the above embodiments.

[0107] The light-emitting control circuit provided in this application embodiment has the beneficial effects of the shift register 10 provided in this application embodiment. For details, please refer to the specific description of the shift register 10 in the above embodiments. This embodiment will not repeat the description here.

[0108] In some embodiments, in the second operating mode, the multi-stage shift register 10 of the light-emitting control circuit EM simultaneously outputs the second driving signal, and / or, in the first operating mode, the multi-stage shift register 10 of the light-emitting control circuit EM sequentially outputs the first driving signal.

[0109] According to the shift register provided in the embodiments of this application, the shift register can support multiple working modes. In the first working mode (e.g., progressive scan mode), the shift register can respond to the first signal of the first signal line (trigger signal line STV or cascaded wiring) and output a first driving signal. In the second working mode, the shift register can respond to the second signal of the second signal line and output a second driving signal. When the shift register outputs the second driving signal, it can output the second driving signal simultaneously with other shift registers, thereby supporting multi-line simultaneous scan mode.

[0110] In some embodiments, such as Figure 7 As shown, the light-emitting control circuit EM also includes multiple first switch modules 31 and multiple second switch modules 32; the input terminal IN of the shift register 10 is electrically connected to the first signal line 21 through the first switch module 31, and the input terminal IN of the shift register 10 is electrically connected to the second signal line 22 through the second switch module 32. In the first operating mode, the first switch module 31 is turned on and the second switch module 32 is turned off. In the second operating mode, the second switch module 32 is turned on, and the first switch module 31 is turned off.

[0111] In the first working mode, the first switch module 31 is turned on, the first signal of the first signal line 21 triggers the operation of the shift register, and the signal output by the output terminal OUT of the previous shift register 10 serves as the trigger signal for the input terminal IN of the next shift register 10, which can drive multiple rows of sub-pixels to emit light row by row.

[0112] In the second working mode, the second switch module 32 is turned on, and the second signal of the second signal line 22 triggers each shift register to work simultaneously, which can drive multiple rows of sub-pixels to emit light simultaneously.

[0113] Based on the same technical concept, this application also provides a driving method applied to a shift register as described in any of the above embodiments, such as... Figure 17 As shown, the shift register includes steps S171~S175 in both the first and second operating modes. The following is a combination of... Figure 11 , Figure 18 , Figure 19 The driving method provided in the embodiments of this application will be described. Figure 18 and Figure 19 IN(n), CK(n), and CKB(n) represent the timing of the input of the nth stage shift register, and OUT(n) and OUT(n+1) represent the timing of the output of the nth stage and the (n+1)th stage shift register, respectively. The diagram is illustrated with the cutoff level being high and the on level being low. The driving method below takes the nth stage shift register as an example. In step S171, during the first high-level output phase b1, the first clock signal line CK provides a cutoff level, and the second clock signal line CKB and the input terminal IN of the shift register provide a conduction level. The sixth control module 109 responds to the conduction level of the fifth node Q5 and writes the conduction level of the second clock signal line CKB into the fourth node Q4. The fifth control module 107 responds to the conduction level of the fourth node Q4 and writes the conduction level of the second clock signal line CKB into the first node Q1. The first output module 101 responds to the conduction level of the first node Q1 and writes the high level of the first power supply voltage signal line VGH into the output terminal OUT of the shift register. The second node Q2 remains at a cutoff level, and the second output module 102 responds to the cutoff level of the second node Q2 and turns off. In step S172, during the first low-level output phase b2, the first clock signal line CK and the input terminal IN of the shift register are provided with an on-level, and the second clock signal line CKB is provided with an off-level. The first control module 103 responds to the on-level of the first clock signal line CK by writing the on-level of the input terminal IN of the shift register into the third node Q3. The second control module 104 responds to the on-level of the third node Q3 by writing the off-level of the first power supply voltage signal line VGH into the first node Q1. The first output module 101... In response to the cutoff level of the first node Q1, the third control module 105 turns on in response to the on level of the first clock signal line CK, and writes the on level of the input terminal IN of the shift register into the second node Q2; the fourth control module 106 turns on in response to the on level of the second power supply voltage signal line VGL, and writes the on level of the third node Q3 into the second node Q2; the second output module 102 turns on in response to the on level of the second node Q2, and writes the low level of the second power supply voltage signal line VGL into the output terminal OUT of the shift register. In step S173, during the second low-level output stage b3, the first clock signal line CK provides a cutoff level, the second clock signal line CKB and the input terminal IN of the shift register provide a conduction level, the second storage module 116 maintains the first node Q1 at a cutoff level, and the first output module 101 turns off in response to the cutoff level of the first node Q1; the second coupling module 117 maintains the second node Q2 at a conduction level, and the second output module 102 turns on in response to the conduction level of the second node Q2, writing the low level of the second power supply voltage signal line VGL into the output terminal OUT of the shift register; In step S174, during the third low-level output stage b4, the first clock signal line CK provides an on-level, and the second clock signal line CKB and the input terminal IN of the shift register provide an off-level. The first control module 103 responds to the on-level of the first clock signal line CK by writing the off-level of the input terminal IN of the shift register into the third node Q3. The seventh control module 110 responds to the on-level of the first clock signal line CK by writing the off-level of the first power supply voltage signal line VGH into the fifth node Q5. The sixth control module 109 responds to the on-level of the fifth node Q5 by writing the off-level of the second clock signal line CKB. Write to the fourth node Q4; the fifth control module 107 turns off in response to the cutoff level of the second clock signal line CKB; the second control module 104 turns off in response to the cutoff level of the third node Q3; the second storage module 116 maintains the first node Q1 at the cutoff level, and the first output module 101 turns off in response to the cutoff level of the first node Q1; the fourth control module 106 turns on in response to the conduction level of the second power supply voltage signal line VGL, and writes the cutoff level of the third node Q3 to the second node Q2; the second output module 102 turns off in response to the cutoff level of the second node Q2, and the output terminal OUT of the shift register maintains the low level of the previous stage; In step S175, during the second high-level output stage b5, the first clock signal line CK provides a cutoff level, the second clock signal line CKB provides a conduction level, the input terminal IN of the shift register provides a cutoff level, the fifth node Q5 remains at the conduction level, the sixth control module 109 responds to the conduction level of the fifth node Q5 and writes the conduction level of the second clock signal line CKB into the fourth node Q4; the fifth control module 107 responds to the conduction level of the second clock signal line CKB and writes the conduction level of the fourth node Q4 into the first node Q1; the first output module 101 responds to the conduction level of the first node Q1 and writes the high level of the first power supply voltage signal line VGH into the output terminal OUT of the shift register; the second coupling module 117 maintains the second node Q2 at the cutoff level, and the second output module 102 responds to the cutoff level of the second node Q2 and turns off.

[0114] Figure 18 and Figure 19 The difference is: Figure 18 The signal at the input terminal IN comes from the first signal line 21. Figure 18 It can realize the output of the first drive signal by multiple shift registers in succession, that is, Figure 18 The low level output from the output terminal of the multi-stage shift register is shifted sequentially to the next stage; Figure 19 The signal at the input terminal IN comes from the second signal line 22. Figure 19 It can enable multiple shift registers to simultaneously output the first drive signal, that is, Figure 19The low-level output of the multi-stage shift register is time-aligned.

[0115] Reference Figure 11 and Figure 18 In the first operating mode (mode 1), the first switch module 31 is turned on, and the second switch module 32 is turned off. (Refer to the reference...) Figure 11 and Figure 19 In the second working mode (mode2), the first switch module 31 is turned off, and the second switch module 32 is turned on.

[0116] Figure 13 or Figure 14 The timing sequence under the first working mode (mode1) can also be as follows: Figure 18 As shown, specifically, in the first working mode (mode1), the eighth control module 120, the ninth control module 121, and the tenth control module 122 are turned off.

[0117] Based on the same technical concept, this application also provides a driving method applied to a shift register as described in any of the above embodiments, such as... Figure 20 As shown, the shift register in the second working mode (mode2) includes steps S201~S202, which are described below in conjunction with... Figure 13 , Figure 21 The driving method provided in the embodiments of this application will be described. Figure 21 IN(n), CK(n), and CKB(n) represent the timing of the input of the nth stage shift register, and OUT(n) and OUT(n+1) represent the timing of the output of the nth stage and the (n+1)th stage shift register, respectively. The diagram is illustrated with a high level for the cutoff level and a low level for the on level. In the second working mode (mode2), the first clock signal line CK provides the cutoff level (e.g., a high level Vgh). The following driving method takes the nth stage shift register as an example. In step S201, during the fourth low-level output stage b6, the first clock signal line CK provides a cutoff level, the second clock signal line CKB provides a conduction level, the first sub-signal line 221 provides a conduction level, the second sub-signal line 222 provides a cutoff level, and the third switch signal line sw3 provides a conduction level. The eighth control module 120 responds to the conduction level of the third switch signal line sw3 by writing the conduction level of the first sub-signal line 221 into the third node Q3. The second control module 104 responds to the conduction level of the third node Q3 by writing the cutoff level of the first power supply voltage signal line VGH into the first node Q1. The first output module 101 responds to the cutoff level of the first node Q1 by turning off. The ninth control module 121 responds to the conduction level of the third switch signal line sw3 by writing the conduction level of the first sub-signal line 221 into the third node Q1. The input is to the seventh node Q7; the fourth control module 106 responds to the conduction level of the second power supply voltage signal line VGL and writes the conduction level of the third node Q3 into the second node Q2; the second output module 102 responds to the conduction level of the second node Q2 and writes the low level of the second power supply voltage signal line VGL into the output terminal OUT of the shift register; the fifth node Q5 is at the cutoff level, and the second coupling control unit 1122 responds to the cutoff level of the fifth node Q5 and turns off; the first coupling control unit 1121 responds to the conduction level of the third switch signal line sw3 and turns on, the second clock signal line CKB jumps from high to low, and further pulls down the potential of the sixth node Q6 through the first coupling module 111; the third switch module 113 turns on, the lower potential of the sixth node Q6 enters the second node Q2, and the second output module 102 is turned on more completely; In step S202, during the fifth low-level output stage b7, the first clock signal line CK provides a cutoff level, the second clock signal line CKB provides a cutoff level, the first sub-signal line 221 provides a conduction level, the second sub-signal line 222 provides a cutoff level, and the third switch signal line sw3 provides a conduction level. The eighth control module 120 responds to the conduction level of the third switch signal line sw3 by writing the conduction level of the first sub-signal line 221 into the third node Q3. The second control module 104 responds to the conduction level of the third node Q3 by writing the cutoff level of the first power supply voltage signal line VGH into the first node Q1. The first output module 101 responds to the cutoff level of the first node Q1 by turning off. The ninth control module 121 responds to the conduction level of the third switch signal line sw3 by turning off. When the first sub-signal line 221 is turned on, the conduction level of the first sub-signal line 221 is written to the seventh node Q7; the fourth control module 106 is turned on in response to the conduction level of the second power supply voltage signal line VGL, and writes the conduction level of the third node Q3 to the second node Q2; the second output module 102 is turned on in response to the conduction level of the second node Q2, and writes the low level of the second power supply voltage signal line VGL to the output terminal OUT of the shift register; the fifth node Q5 is at the cutoff level, and the second coupling control unit 1122 is turned off in response to the cutoff level of the fifth node Q5; the first coupling control unit 1121 is turned on in response to the conduction level of the third switch signal line sw3, and the second clock signal line CKB jumps from low to high, further pulling up the potential of the sixth node Q6 through the first coupling module 111; the third switch module 113 is turned off.

[0118] This application also provides a display device, including the light-emitting control circuit provided in this application. Please refer to... Figure 22 , Figure 22 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 22 The provided display device 1000 includes the light-emitting control circuit EM provided in any of the above embodiments of this application. Figure 22 The embodiments use a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and vehicle-mounted display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the light-emitting control circuit EM provided in this application embodiment. For details, please refer to the specific descriptions of the light-emitting control circuit EM in the above embodiments; these will not be repeated here.

[0119] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0120] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude multiple; the terms "first" and "second" are used to identify names and not to indicate any particular order. Any reference numerals in the claims should not be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A shift register, characterized in that, include: The shift register is electrically connected to the first signal line and the second signal line respectively. The first signal line is a trigger signal line or a cascaded routing line between the shift register and other stage shift registers. In the first operating mode, the shift register responds to the first signal on the first signal line and outputs the first drive signal; In the second operating mode, the shift register responds to the second signal on the second signal line and outputs a second drive signal.

2. The shift register according to claim 1, characterized in that, In the second operating mode, the shift register outputs the second drive signal simultaneously with other stage shift registers.

3. The shift register according to claim 1, characterized in that, In the first operating mode, the shift register outputs the first drive signal in a time-sharing manner with other shift register stages.

4. The shift register according to claim 1, characterized in that, The input terminal of the shift register is electrically connected to the first signal line through a first switch module, and the input terminal of the shift register is electrically connected to the second signal line through a second switch module. In the first operating mode, the first switch module is turned on and the second switch module is turned off; In the second operating mode, the second switch module is turned on, and the first switch module is turned off.

5. The shift register according to claim 4, characterized in that, The first switching module includes a first transistor, the gate of the first transistor is electrically connected to a first switching signal line, the first terminal of the first transistor is electrically connected to the first signal line, and the second terminal of the first transistor is electrically connected to the input terminal of the shift register. The second switching module includes a second transistor, the gate of which is electrically connected to a second switching signal line, the first terminal of which is electrically connected to the second signal line, and the second terminal of which is electrically connected to the input terminal of the shift register.

6. The shift register according to claim 1, characterized in that, The shift register includes: The first output module has a control terminal electrically connected to the first node, a first terminal electrically connected to the first power supply voltage signal line, and a second terminal electrically connected to the output terminal of the shift register. The second output module has its control terminal electrically connected to the second node, its first terminal electrically connected to the second power supply voltage signal line, and its second terminal electrically connected to the output terminal of the shift register. A first control module, wherein the control terminal of the first control module is electrically connected to the first clock signal line, the first terminal of the first control module is electrically connected to the input terminal of the shift register, and the second terminal of the first control module is electrically connected to the third node, and the first control module is used to transmit the first signal or the second signal of the input terminal of the shift register to the third node under the control of the first clock signal line; The second control module has its control terminal electrically connected to the third node, its first terminal electrically connected to the first power supply voltage signal line, and its second terminal electrically connected to the first node. The second control module is used to write the cutoff level of the first power supply voltage signal line into the first node under the control of the third node. The third control module has a control terminal electrically connected to the first clock signal line, a first terminal electrically connected to the input terminal of the shift register, and a second terminal electrically connected to the second node. The third control module is used to write the first signal or the second signal of the input terminal of the shift register into the second node under the control of the first clock signal line. The fourth control module has its control terminal electrically connected to the second power supply voltage signal line, its first terminal electrically connected to the third node, and its second terminal electrically connected to the second node. The fourth control module is used to write the on or off level of the third node into the second node under the control of the second power supply voltage signal line.

7. The shift register according to claim 6, characterized in that, The shift register also includes: The fifth control module has its control terminal electrically connected to the second clock signal line, its first terminal electrically connected to the fourth node, and its second terminal electrically connected to the first node. A first storage module, wherein a first end of the first storage module is electrically connected to a fifth node, and a second end of the first storage module is electrically connected to the fourth node; The sixth control module has its control terminal electrically connected to the fifth node, its first terminal electrically connected to the second clock signal line, and its second terminal electrically connected to the fourth node. The sixth control module is used to write the second clock signal of the second clock signal line into the fourth node under the control of the fifth node. The seventh control module has its control terminal electrically connected to the first clock signal line, its first terminal electrically connected to the second power supply voltage signal line, and its second terminal electrically connected to the fifth node. The seventh control module is used to write the conduction level of the second power supply voltage signal line into the fifth node under the control of the first clock signal line.

8. The shift register according to claim 7, characterized in that, The shift register also includes: A first coupling module, wherein a first end of the first coupling module is electrically connected to the second node; A coupling control module is electrically connected to the second node, the fifth node, the second clock signal line, the first power supply voltage signal line, and the second terminal of the first coupling module. The coupling control module is used to write the cutoff level of the first power supply voltage signal line to the second terminal of the first coupling module under the control of the fifth node, and to write the second clock signal of the second clock signal line to the second terminal of the first coupling module under the control of the second node.

9. The shift register according to claim 8, characterized in that, The shift register also includes: The third switch module has its control terminal and first terminal electrically connected to the sixth node, and its second terminal electrically connected to the second node. The second end of the third control module and the first end of the first coupling module are both electrically connected to the sixth node.

10. The shift register according to claim 9, characterized in that, The coupling control module includes: The first coupling control unit is electrically connected to the sixth node, the first end of the first coupling control unit is electrically connected to the second clock signal line, and the second end of the first coupling control unit is electrically connected to the second end of the first coupling module. The first coupling control unit is used to transmit the second clock signal of the second clock signal line to the second end of the first coupling module under the control of the sixth node. The second coupling control unit has its control terminal electrically connected to the fifth node, its first terminal electrically connected to the first power supply voltage signal line, and its second terminal electrically connected to the second terminal of the first coupling module. The second coupling control unit is used to transmit the first power supply voltage signal of the first power supply voltage signal line to the second terminal of the first coupling module under the control of the fifth node.

11. The shift register according to claim 9, characterized in that, The shift register further includes a fourth switch module. The control terminal of the fourth switch module is electrically connected to the second power supply voltage signal line. The first terminal of the fourth switch module is electrically connected to the sixth node. The second terminal of the fourth switch module is electrically connected to the seventh node. The seventh node is electrically connected to the second terminal of the third control module.

12. The shift register according to claim 7, characterized in that, The shift register also includes a fifth switch module. The control terminal of the fifth switch module is electrically connected to the second power supply voltage signal line, the first terminal of the fifth switch module is electrically connected to the fifth node, and the second terminal of the fifth switch module is electrically connected to the first terminal of the first storage module.

13. The shift register according to claim 6, characterized in that, The shift register also includes: The second storage module has a first end electrically connected to the first node and a second end electrically connected to the first power supply voltage signal line. The second coupling module has a first end electrically connected to the second node and a second end electrically connected to the output of the shift register.

14. The shift register according to claim 7, characterized in that, The shift register also includes: A clock signal writing module, wherein the control terminal of the clock signal writing module is electrically connected to the third node, the first terminal of the clock signal writing module is electrically connected to the first clock signal line, and the second terminal of the clock signal writing module is electrically connected to the fifth node, and the clock signal writing module is used to write the first clock signal of the first clock signal line into the fifth node under the control of the third node; A reset module, wherein the control terminal of the reset module is electrically connected to the reset signal line, the first terminal of the reset module is electrically connected to the first power supply voltage signal line, and the second terminal of the reset module is electrically connected to the third node, and the reset module is used to write the first power supply voltage signal of the first power supply voltage signal line into the third node under the control of the reset signal line.

15. The shift register according to claim 6, characterized in that, The second signal line includes the first sub-signal line; The shift register also includes: The eighth control module has its control terminal electrically connected to the third switch signal line, its first terminal electrically connected to the first sub-signal line, and its second terminal electrically connected to the third node. The eighth control module is used to write the first sub-signal of the first sub-signal line into the third node under the control of the third switch signal line. The ninth control module has its control terminal electrically connected to the third switch signal line, its first terminal electrically connected to the first sub-signal line, and its second terminal electrically connected to the second node. The ninth control module is used to write the first sub-signal of the first sub-signal line into the second node.

16. The shift register according to claim 15, characterized in that, The second signal line includes a second sub-signal line; The shift register also includes: The fifth control module has its control terminal electrically connected to the second clock signal line, its first terminal electrically connected to the fourth node, and its second terminal electrically connected to the first node. A first storage module, wherein a first end of the first storage module is electrically connected to a fifth node, and a second end of the first storage module is electrically connected to the fourth node; The sixth control module has its control terminal electrically connected to the fifth node, its first terminal electrically connected to the second clock signal line, and its second terminal electrically connected to the fourth node. The sixth control module is used to write the second clock signal of the second clock signal line into the fourth node under the control of the fifth node. The tenth control module has its control terminal electrically connected to the third switch signal line, its first terminal electrically connected to the second sub-signal line, and its second terminal electrically connected to the fifth node. The tenth control module is used to write the second sub-signal of the second sub-signal line into the fifth node under the control of the third switch signal line.

17. The shift register according to claim 16, characterized in that, The shift register also includes: The eleventh control module has its control terminal and first terminal both electrically connected to the first clock signal line, and its second terminal electrically connected to the fifth node. The eleventh control module is used to transmit the first clock signal of the first clock signal line to the fifth node under the control of the first clock signal line. The twelfth control module has its control terminal electrically connected to the third node, its first terminal electrically connected to the first clock signal line, and its second terminal electrically connected to the fifth node. The twelfth control module is used to transmit the first clock signal of the first clock signal line to the fifth node under the control of the third node.

18. The shift register according to claim 17, characterized in that, The eleventh control module includes a first sub-control unit and a second sub-control unit, and the twelfth control module includes a third sub-control unit and a fourth sub-control unit; The control terminals of the first sub-control unit and the second sub-control unit are both electrically connected to the first clock signal line. The first terminal of the first sub-control unit is electrically connected to the first clock signal line. The second terminal of the first sub-control unit is electrically connected to the first terminal of the second sub-control unit. The second terminal of the second sub-control unit is electrically connected to the fifth node. The control terminals of the third sub-control unit and the fourth sub-control unit are both electrically connected to the third node. The first terminal of the third sub-control unit is electrically connected to the first clock signal line. The second terminal of the third sub-control unit is electrically connected to the first terminal of the fourth sub-control unit. The second terminal of the fourth sub-control unit is electrically connected to the fifth node.

19. A light-emitting control circuit, characterized in that, Includes multiple cascaded shift registers as described in any one of claims 1 to 18.

20. The light-emitting control circuit according to claim 19, characterized in that, In the second operating mode, the multi-stage shift register of the light-emitting control circuit simultaneously outputs the second driving signal, and / or, in the first operating mode, the multi-stage shift register of the light-emitting control circuit sequentially outputs the first driving signal.

21. The light-emitting control circuit according to claim 19, characterized in that, The light-emitting control circuit also includes multiple first switch modules and multiple second switch modules; The input terminal of the shift register is electrically connected to the first signal line through a first switch module, and the input terminal of the shift register is electrically connected to the second signal line through a second switch module. In the first operating mode, the first switch module is turned on and the second switch module is turned off; In the second operating mode, the second switch module is turned on, and the first switch module is turned off.

22. A driving method, characterized in that, The shift register is applied to any one of claims 1 to 18, wherein the shift register includes a first high-level output stage, a first low-level output stage, a second low-level output stage, a third low-level output stage, and a second high-level output stage in the first operating mode or the second operating mode; The driving method includes: During the first high-level output phase, the first clock signal line provides a cutoff level, and the second clock signal line and the input terminal of the shift register provide a conduction level. The sixth control module, responding to the conduction level of the fifth node, writes the conduction level of the second clock signal line into the fourth node. The fifth control module, responding to the conduction level of the fourth node, writes the conduction level of the second clock signal line into the first node. The first output module, responding to the conduction level of the first node, writes the high level of the first power supply voltage signal line into the output terminal of the shift register. The second node remains at a cutoff level, and the second output module, responding to the cutoff level of the second node, turns off. During the first low-level output phase, the first clock signal line and the input terminal of the shift register are provided with an on level, and the second clock signal line is provided with an off level. The first control module, in response to the on level of the first clock signal line, writes the on level of the input terminal of the shift register into the third node; the second control module, in response to the on level of the third node, writes the off level of the first power supply voltage signal line into the first node; the first output module, in response to the off level of the first node, turns off; the third control module, in response to the on level of the first clock signal line, writes the on level of the input terminal of the shift register into the second node; the fourth control module, in response to the on level of the second power supply voltage signal line, writes the on level of the third node into the second node; and the second output module, in response to the on level of the second node, writes the low level of the second power supply voltage signal line into the output terminal of the shift register. During the second low-level output phase, the first clock signal line provides a cutoff level, the second clock signal line and the input of the shift register provide a conduction level, the second storage module maintains the first node at a cutoff level, and the first output module turns off in response to the cutoff level of the first node; the second coupling module maintains the second node at a conduction level, and the second output module turns on in response to the conduction level of the second node, writing the low level of the second power supply voltage signal line into the output of the shift register; During the third low-level output phase, the first clock signal line provides an on level, and the second clock signal line and the input of the shift register provide an off level. The first control module, responding to the on level of the first clock signal line, writes the off level of the input of the shift register into the third node; the seventh control module, responding to the on level of the first clock signal line, writes the off level of the first power supply voltage signal line into the fifth node; the sixth control module, responding to the on level of the fifth node, writes the off level of the second clock signal line into the fourth node; the fifth control module, responding to the off level of the second clock signal line, turns off; the second control module, responding to the off level of the third node, turns off; the second storage module maintains the first node at the off level; the first output module, responding to the off level of the first node, turns off; the fourth control module, responding to the on level of the second power supply voltage signal line, writes the off level of the third node into the second node; the second output module, responding to the off level of the second node, turns off; and the output of the shift register remains at the low level of the previous phase. During the second high-level output phase, the first clock signal line provides a cutoff level, the second clock signal line provides a conduction level, and the input of the shift register provides a cutoff level. The fifth node remains on, and the sixth control module responds to the on level of the fifth node by writing the on level of the second clock signal line into the fourth node; the fifth control module responds to the on level of the second clock signal line by writing the on level of the fourth node into the first node; the first output module responds to the on level of the first node by writing the high level of the first power supply voltage signal line into the output terminal of the shift register; the second coupling module maintains the second node at the off level, and the second output module responds to the off level of the second node by turning off.

23. A driving method, characterized in that, The shift register is applied to any one of claims 1 to 18, wherein the shift register includes a fourth low-level output phase and a fifth low-level output phase in the second operating mode; The driving method includes: During the fourth low-level output phase, the second clock signal line provides an on level, the first sub-signal line provides an on level, the second sub-signal line provides an off level, and the third switch signal line provides an on level. The eighth control module, responding to the on level of the third switch signal line, writes the on level of the first sub-signal line into the third node. The second control module, responding to the on level of the third node, writes the off level of the first power supply voltage signal line into the first node. The first output module, responding to the off level of the first node, turns off. The ninth control module, responding to the on level of the third switch signal line, writes the on level of the first sub-signal line into the seventh node. The fourth control module responds to the conduction level of the second power supply voltage signal line by writing the conduction level of the third node into the second node; the second output module responds to the conduction level of the second node by writing the low level of the second power supply voltage signal line into the output terminal of the shift register; the fifth node is at the cutoff level, and the second coupling control unit responds to the cutoff level of the fifth node by turning off; the first coupling control unit responds to the conduction level of the third switch signal line by turning on, and the second clock signal line jumps from high to low, further pulling down the potential of the sixth node through the first coupling module; the third switch module turns on, and the lower potential of the sixth node enters the second node, making the second output module more fully open; During the fifth low-level output phase, the first clock signal line provides a cutoff level, the second clock signal line provides a cutoff level, the first sub-signal line provides a conduction level, the second sub-signal line provides a cutoff level, and the third switch signal line provides a conduction level. The eighth control module, responding to the conduction level of the third switch signal line, writes the conduction level of the first sub-signal line into the third node. The second control module, responding to the conduction level of the third node, writes the cutoff level of the first power supply voltage signal line into the first node. The first output module, responding to the cutoff level of the first node, turns off. The ninth control module, responding to the conduction level of the third switch signal line, turns on. The first control module writes the conduction level of the first sub-signal line to the seventh node; the fourth control module, in response to the conduction level of the second power supply voltage signal line, writes the conduction level of the third node to the second node; the second output module, in response to the conduction level of the second node, writes the low level of the second power supply voltage signal line to the output terminal of the shift register; the fifth node is at the cutoff level, and the second coupling control unit, in response to the cutoff level of the fifth node, turns off; the first coupling control unit, in response to the conduction level of the third switch signal line, turns on, and the second clock signal line jumps from low to high, further pulling up the potential of the sixth node through the first coupling module; the third switch module turns off.

24. A display device, characterized in that, Includes the light-emitting control circuit as described in any one of claims 19 to 21.

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