DISPLAY DEVICE

Abstract

A display device comprises a substrate, a first planarization layer on the substrate, a second planarization layer on top of the first planarization layer, and a hole through the second planarization layer. A light-emitting element is positioned within the hole, and the second planarization layer has a first inclined surface and a second inclined surface that define the hole. A black bank is located between the first inclined surface and the second inclined surface. The first and second inclined surfaces and the black bank reflect light, causing reflected light to exit the display device and thus enhancing its display characteristics.

Description

This application claims priority over Korean patent application No. 10-2024-0198990, filed on December 27, 2024, with the Korean Intellectual Property Office. BACKGROUND Technical field The present disclosure relates to electronic devices and in particular, but not exclusively, to display devices. Description of the related area In today's information society, display devices for presenting images or visual information are becoming increasingly important for users. The need for such display devices has spurred developments in display device technology, and various types of display devices, such as liquid crystal displays (LCDs), organic light-emitting diode displays (OLEDs), and the like, have been developed and used. Display devices can suffer from a situation in which some of the light emitted by a layer of light-emitting elements cannot escape from a display panel due to total internal reflection between the layer of light-emitting elements and an electrode or an organic layer, thereby reducing the light extraction efficiency. Furthermore, the reflection sensitivity and viewing angle characteristics of display devices can be reduced due to external light entering the display devices. SUMMARY One object of the present disclosure is to provide a display device that can improve reflection sensitivity and / or implement good viewing angle characteristics. At least one of these objects is solved by the features of the independent claims. According to the present disclosure, a display device is provided which has a structure in which light emitted by a light-emitting element can be absorbed by a bank or can cause light trapped in a display board due to total internal reflection to escape from the display board. According to one aspect of the present disclosure, a display device comprises a substrate, a first planarization layer arranged on the substrate, a second planarization layer arranged on the first planarization layer and having a first hole that allows a first light-emitting element to be arranged, and having an inner surface comprising a first inclined surface, a second inclined surface and a second hole different from the first hole, a first pixel electrode arranged on the first planarization layer in the first hole and extending along the first inclined surface and the second inclined surface to an upper surface of the second planarization layer, a first black bank located in the second hole, a second black bank located on the second planarization layer, a third black bank,which is located between the first inclined surface and the second inclined surface, a non-black bank located on the first black bank, the second black bank, the third black bank and the first pixel electrode, a first intermediate layer located on a section of the first pixel electrode and the non-black bank, and a common electrode located on the first intermediate layer. According to one aspect of the present disclosure, a display device comprises a substrate, a first planarization layer arranged on the substrate, a second planarization layer arranged on the first planarization layer and having a first hole that allows a first light-emitting element to be arranged, and having an inner surface comprising a first inclined surface, a second inclined surface and a second hole different from the first hole, a first pixel electrode arranged on the first planarization layer in the first hole and extending along the first inclined surface and the second inclined surface to an upper surface of the second planarization layer, a bank arranged on the first pixel electrode and the second planarization layer, and a first intermediate layer arranged on a section of the first pixel electrode and the bank.and a common electrode located on the first intermediate layer. In one or more aspects, a first angle formed by the first inclined surface and the back surface of the second planarization layer is smaller than a second angle formed by the second inclined surface and the back surface of the second planarization layer. According to one aspect of the present disclosure, a display device comprises the following: a substrate having multiple layers; multiple TFT layers on the substrate; multiple planarization layers arranged on the TFT layers; a subpixel arranged on the multiple planarization layers and containing an anode, the subpixel being connected to the multiple TFT layers and having multiple light-emitting surfaces; and a black bank arranged on the multiple planarization layers and covering at least one section of the anode. According to one aspect of the present disclosure, a display device comprises the following: a substrate having multiple layers; multiple TFT layers on the substrate; multiple planarization layers arranged on the TFT layers; a subpixel arranged on the multiple planarization layers and connected to the multiple TFT layers, the subpixel having a light-emitting major surface, a light-emitting minor surface, and an intermediate surface between the light-emitting major surface and the light-emitting minor surface; and a black bank arranged on the multiple planarization layers. According to one aspect of the present disclosure, a display device comprises the following: a substrate; several thin-film transistors on the substrate; a planarization layer on the thin-film transistors; a subpixel having a light-emitting element arranged on the planarization layer, the light-emitting element comprising an anode connected to one of the several thin-film transistors, and the subpixel having several light-emitting surfaces; and a black bank arranged on the planarization layer covering at least one section of the anode. According to the present disclosure, a display device may be able to improve reflection sensitivity and / or implement viewing angle characteristics by incorporating a structure in which a planarization layer has an inclined surface and a black bank on a pixel electrode is arranged on the planarization layer outside the inclined surface. According to the present disclosure, a display device can include a structure in which an electrode of a light-emitting element has several inclined surfaces and can cause light emitted by the light-emitting element to exit a display panel by altering paths of light that is absorbed by a bank or trapped in the display panel due to total internal reflection. According to the present disclosure, a display device may be able to enable process optimization through an improved light extraction structure without a separate additional process. Aspects, examples, and embodiments of the present disclosure are not limited to the preceding description, and additional aspects, examples, and embodiments of the present disclosure will become apparent to those skilled in the art from the following description. Effects, benefits, or advantages of aspects, examples, and embodiments described herein are not limited thereto, and additional effects or advantages will become apparent to those skilled in the art from the following description. Brief description of the different views of the drawings The accompanying drawings, which are included to provide a better understanding of the disclosure and are incorporated into and form part of the disclosure, illustrate aspects of the disclosure and, together with the description, serve to explain principles of the disclosure. It should therefore be understood that aspects, examples, and embodiments described herein are not limited to the illustrations in the accompanying drawings; they show: Fig. 1 an embodiment of a system configuration of a display device according to aspects of the present disclosure; Fig. 2 a display panel of the display device of Fig. 1; Fig. 3 a cross-sectional view of the display panel of Fig. 2 along line AA in Fig. 2; Fig. 4 a top view of the display panel of Fig. 2; Figs. 5, 6, 7 to 8 cross-sectional views of embodiments of the display panel of Fig. 4 extending along line AB of Fig. 4.4 were taken according to aspects of the present disclosure; Fig. 9 is a cross-sectional view of an embodiment of the display panel of Fig. 4, taken along line AC of Fig. 4, according to aspects of the present disclosure; Fig. 10 is a top view of an embodiment of a light-emitting surface of the display panel of Fig. 2 according to aspects of the present disclosure; and Fig. 11 is a top view of an embodiment of several light-emitting surfaces of the display panel of Fig. 2 according to aspects of the present disclosure. DETAILED DESCRIPTION Reference is now made to exemplary embodiments of the present disclosure, examples or aspects of which are illustrated in the accompanying drawings. In the following description, the structures, implementations, methods, and operations described herein are not limited to the specific examples, aspects, and embodiments presented here and may be modified as is known in the prior art, unless otherwise indicated. Similar reference numerals denote similar elements throughout, unless otherwise indicated. The names of the respective elements used in the following explanations are chosen solely for the convenience of simplifying the writing of the application text and may therefore differ from those used in actual products.The advantages and features of the present disclosure and its implementation methods are illustrated by the following exemplary embodiments, which are described with reference to the accompanying drawings. The present disclosure may, however, be embodied in various forms and should not be interpreted as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to ensure that this disclosure is sufficiently thorough and complete to assist those skilled in the art in fully understanding the scope of the present disclosure. Furthermore, the scope of the claims and their correspondences is not limited by the present disclosure. In the following description, where a precise description of the relevant known function or configuration might unnecessarily obscure aspects of the present disclosure, a precise description of such a known function or configuration has been omitted.The shapes, sizes, ratios, angles, numbers, and the like illustrated in the drawings to describe various exemplary embodiments of the present disclosure are, in some embodiments, merely illustrative. In other embodiments, the shapes, sizes, ratios, angles, numbers, and the like illustrated in the drawings are to scale and intended to represent features of the disclosure. The terms used here, such as "contain," "exhibit," "incorporate," "represent," "form," and "formed," are generally intended to allow for the addition of further components, unless the terms are used with the term "merely." Singular forms used herein are intended to include plural forms unless the context clearly indicates otherwise. Although the terms “first”, “second”, A, B, (a), (b) and the like are used here to describe different elements, these elements should not be interpreted as being limited by these terms, since they are not used to define any particular order or priority. These terms are used merely to distinguish one element from another. For example, a first element could be called a second element and, correspondingly, a second element could be called a first element without departing from the scope of the present disclosure. When it is mentioned that a first element is "connected to or coupled to a second element," "touches it," "overlaps it," or the like, this should be interpreted to mean that the first element can not only be "directly connected to or coupled to the second element," "directly touch it," or "directly overlap it," but also that a third element can be "interposed" between the first and second elements, or that the first and second elements can be "connected or coupled" to each other, "touch" each other, "overlap" each other, or the like, via a fourth element. Here, the second element can be contained within at least one of two or more elements that are "connected or coupled to each other," "touch" each other, "overlap" each other, or the like. Where positional relationships are described, e.g., where the positional relationship between two parts is described using "at," "above," "below," "above," "below," "next to," "next to," or the like, one or more other parts may be positioned between the two parts unless a more restrictive term such as "immediately," "directly," or "near" is used. For example, where an element or layer is positioned "at" another element or layer, a third element or layer may be positioned between them. Furthermore, the expressions "left," "right," "above," "below," "downward," "upward," "upper," "lower," and the like refer to any frame of reference. Additionally, when dimensions, relative sizes, etc., are mentioned, it should be noted that numerical values ​​for elements or characteristics, or corresponding information (e.g., level, range, and the like), include a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, and the like), even if no relevant description is provided. Unless otherwise noted, such a tolerance or error range is plus or minus 5% of the stated value. Thus, for example, a dimension stated as 10 cm is interpreted as being within the range of 9.5 cm to 10.5 cm, unless the context requires otherwise. Furthermore, the term "could" fully encompasses all meanings of the term "may." Fig. 1 illustrates an example system configuration of a display device 100 according to aspects of the present disclosure. With reference to Fig. 1, in one or more exemplary embodiments, the display device 100 comprises a display panel 110 and at least one display control circuit as elements for displaying images. The at least one display control circuit can be one or more circuits for controlling the display panel 110. The at least one display control circuit comprises a data control circuit 120, a gate control circuit 130, a control unit 140, and other circuit components; however, aspects of the present disclosure are not limited thereto. The display panel 110 contains a substrate 111 and several subpixels SP arranged on the substrate 111. Substrate 111 contains a display area DA and a non-display area NDA. The display area DA is an area that allows an image to be displayed, or is configured to display an image, and can also be referred to as an active area. Several subpixels SP for displaying images are arranged within the display area DA. The non-display area NDA is an area where no image is displayed and can be an area outside the display area DA. The non-display area NDA can also be a non-active area, a border area, or a border. The non-display area NDA contains a contact area. The non-display area (NDA) comprises a first non-display area, a second non-display area, a third non-display area, and a fourth non-display area. The first non-display area is located outside the display area (DA) in a row. The second non-display area is located outside the display area (DA) in a row and can be on the opposite side of the first non-display area. The third non-display area is located outside the display area (DA) in a column. The fourth non-display area is located outside the display area (DA) in a column and can be on the opposite side of the third non-display area. In other words, the four non-display areas can surround the display area (DA) with a non-display area on each side of the display area (DA). Among the first to fourth non-display areas, the fourth non-display area contains a contact area in which a control circuit is connected or contacted, and the first to third non-display areas can be very small. However, aspects of the present disclosure are not limited to this. In one or more aspects, a boundary surface is defined between the display surface DA and the non-display surface NDA. In this example, the boundary surface is curved at a specific angle to the display surface DA, and therefore the non-display surface NDA is located below the display surface DA. In this implementation, when the user views the display device 100 from its front, all or most of the non-display area NDA is invisible to the user; however, aspects of the present disclosure are not limited to this. In one or more aspects, the display device 100 is a self-emitting display device in which light is emitted from the display panel 110 itself; however, aspects of the present disclosure are not limited to this. In one example, in which the display device 100 is the self-emitting display device, each of several subpixels SP contained in the display panel 110 includes a light-emitting element. The display device 100 according to aspects of the present disclosure is an organic light-emitting display device in which light-emitting elements are implemented using organic light-emitting diodes (OLEDs). In another example, the display device 100 according to aspects of the present disclosure is an inorganic light-emitting display device in which light-emitting elements are implemented using light-emitting diodes based on inorganic material. In yet another example, the display device 100 according to aspects of the present disclosure is a quantum dot display device in which light-emitting elements are implemented using quantum dots that are self-emitting semiconductor crystals. In yet another example, the display device 100 according to aspects of the present disclosure is a micro-LED display device, a mini-LED display device, or the like. The structure of each of several subpixels SP contained in the display panel 110 can depend on the type of display device 100. In one example, where the display device 100 is a self-emitting display device containing self-emitting subpixels SP, each subpixel SP contains a self-emitting light-emitting element, one or more transistors, and one or more capacitors; however, aspects of the present disclosure are not limited thereto. Several types of signal lines for controlling multiple subpixels SP can be arranged on the substrate 111 of the display panel 110. These multiple types of signal lines include, for example, multiple data lines DL for transmitting data signals (which can be referred to as data voltages or image signals) to the multiple subpixels SP, multiple gate lines GL for transmitting gate signals (which can be referred to as sampling signals) to the multiple subpixels SP, and the like. The multiple data lines DL and the multiple gate lines GL can intersect in one or more aspects. Each of the multiple gate lines GL can run in a first direction (e.g., a row or a column direction). Each of the multiple data lines DL can run in a second direction (e.g., a column or a row direction) that differs from the first direction. The first direction can be the row direction and the second direction can be the column direction. In another example, the first direction can be the column direction and the second direction can be the row direction. Here, the row direction and the column direction can be relative directions, not absolute directions. Depending on the direction in which the display device 100 or the display panel 110 is viewed, the column direction can be the row direction and vice versa. For the sake of simplicity, discussions based on examples may be provided below, where each of several data lines DL is arranged in the column direction and each of several gate lines GL is arranged in the row direction; however, aspects of the present disclosure are limited thereto.Here, the angle between the first direction and the second direction can be vertical (or 90 degrees) or an angle other than vertical. For reference, Fig. 1 illustrates, based on the orientation of the display device 100 in Fig. 1, the "line direction" as a left / right direction and the "column direction" as an up / down direction. The data control circuit 120 is a circuit for controlling multiple data lines DL and can output the data signals to the multiple data lines DL. The data control circuit 120 can receive image data DATA in digital form from the control unit 140, convert the received image data DATA into data signals (or data voltages) in analog form and output the resulting data signals to the multiple data lines DL. The data control circuit 120 can be connected to the display panel 110 by an automatic tape assembly (TAB) technique, or to a conductive contact such as a connecting surface of the display panel 110 by a chip-on-glass (COG) or chip-on-panel (COP) technique, or to the display panel 110 by a chip-on-thin-film (COF) technique. However, aspects of the present disclosure are not limited to these. In one or more aspects, the data control circuit 120 is located in only one side or edge (e.g., an upper section or a lower section) of the display panel 110 and / or is electrically connected to it, but is not limited to this. In one or more aspects, the data control circuit 120 is arranged in accordance with control schemes, panel design schemes, or the like in two sides or two edges (e.g., an upper section and a lower section) of the display panel 110 or at least two of four sides or edges (e.g., the upper section, the lower section, a left section, and a right section) of the display panel 110 and / or is electrically connected to it, but is not limited to this. The data control circuit 120 is connected to an area that is located outside the display area DA of the display board 110, or can be located in the display area DA of the display board 110. The gate drive circuit 130 is a circuit for driving multiple gate lines GL and can supply gate signals to the multiple gate lines GL. The gate drive circuit 130 can receive several types of gate drive control signals GCS and a first gate voltage corresponding to a turn-on voltage (or a turn-on level voltage) and a second gate voltage corresponding to a turn-off voltage (or a turn-off level voltage). This allows the gate drive circuit 130 to generate a gate signal containing a period with the first gate voltage and a period with the second gate voltage during a specific time period (e.g., a period of a frame time or a sub-period of a frame time) and to feed the generated gate signals to the multiple gate lines GL. The turn-on level voltage can be a high voltage, and the turn-off level voltage can be a low voltage. Alternatively, the turn-on level voltage can be a low voltage, and the turn-off level voltage can be a high voltage. In one or more aspects, the gate drive circuit 130, which is contained in the display device 100, is embedded in the display panel 110 by a gate-in-panel (GIP) technique; however, aspects of the present disclosure are not limited to this. In one example where the gate drive circuit 130 is implemented by the gate-in-panel (GIP) technique, the gate drive circuit 130 is placed on the substrate 111 of the display panel 110 during the manufacturing process of the display panel 110 or the display device 100. Here, the gate drive circuit 130, which is embedded in the display panel 110 by the gate-in-panel (GIP) technique, can also be referred to as a "gate-in-panel circuit". The gate drive circuit 130 is located in the non-display area NDA of the display panel 110. In another example, the gate drive circuit 130 is located in the display area DA of the display panel 110. In one or more aspects, the gate drive circuit 130 is located in and / or electrically connected to a first area (e.g., a left section or a right section) in the display area DA of the display panel 110, but is not limited to this. In one or more aspects, the gate drive circuit 130 is located in and / or electrically connected to a first area (e.g., a left section or a right section) in the display area DA and a second area (e.g., the right section or the left section) in the display area DA, but is not limited to this.In one or more aspects, the gate control circuit 130 is arranged in all or one or more of the surfaces of the display surface DA. In an example where the gate drive circuit 130 is located in the display area DA of the display panel 110, the gate drive circuit 130 can vertically overlap with one or more subpixels SP located in the display area DA. The gate drive circuit 130 can vertically overlap with one or more light-emitting elements and one or more transistors contained in one or more subpixels SP located in the display area DA. The gate drive circuit 130 can vertically overlap with multiple light-emitting elements and multiple transistors contained in multiple subpixels SP located in the display area DA. The gate drive circuit 130 contains multiple transistors.Each of the multiple transistors contained in the gate drive circuit 130 contains an active layer comprising a first semiconductor material, and each of the multiple transistors contained in the subpixels SP contains an active layer comprising a second semiconductor material. The first and second semiconductor materials can be essentially the same. In another example, the first and second semiconductor materials can be different. The first semiconductor material can be a silicon-based semiconductor material (e.g., low-temperature polysilicon (LTPS)), and the second semiconductor material can be an oxide semiconductor material. The active layer can be a semiconductor layer, but aspects of the present disclosure are not limited to this. The control unit 140 is a device for controlling the data control circuit 120 and the gate control circuit 130 and can control a control timing sequence for several data lines DL and a control timing sequence for several gate lines GL. The control unit 140 can supply a data control signal DCS to the data control circuit 120 in order to control the data control circuit 120, and supply a gate control signal GCS to the gate control circuit 130 in order to control the gate control circuit 130. The control unit 140 can be implemented in a component separate from the data control circuit 120 or integrated with the data control circuit 120, such that the control unit 140 and the data control circuit 120 can be implemented in a single integrated circuit. The control unit 140 can be a timing control unit used in typical display device technology, or a control device / equipment that can perform additional control functionalities beyond the typical function of the timing control unit. In one or more embodiments, the control unit 140 is one or more additional control circuits different from the timing control unit, or a circuit or component within the control device / equipment. The control unit 140 can be implemented using various circuits or electronic components, such as an integrated circuit (IC), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a processor, and / or the like. However, aspects of the present disclosure are not limited to these. The control unit 140 can be mounted on a printed circuit board, a flexible printed circuit or the like, and is electrically connected to the data control circuit 120 and the gate control circuit 130 via the printed circuit board, the flexible printed circuit and / or the like. The control unit 140 can send signals to and receive signals from the data control circuit 120 via one or more predefined interfaces. For example, such interfaces include a low-voltage differential signaling interface (LVDS interface), an embedded clock point-point (EPI) interface, a serial peripheral interface (SPI), and the like. However, aspects of the present disclosure are not limited to these. In one or more aspects, the display device 100 can provide, in addition to an image display device function, a touch detection function for detecting the presence or absence of touch by an object such as a finger, a pen or the like, or a location of touch. In some aspects, the display device 100 is a mobile device such as a smartphone, tablet, or similar device, or a monitor, television (TV), or similar device. Such devices can be configured in various types, sizes, and shapes.The display device 100 according to aspects of the present disclosure is applied to mobile devices, video phones, smartwatches, watch phones, portable devices, foldable devices, rollable devices, flexible devices, stretchable devices, curved devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia playback devices (PMPs), personal digital assistants (PDAs), MP3 playback devices, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation devices, passenger car navigation devices, vehicle display devices, vehicle devices, theatre devices, theatre display devices, televisions, wallpaper devices, signage devices, gaming devices, notebook computers, monitors, cameras, camcorders, and household appliances and the like. In one or more aspects, the display device 100 may further include an electronic device such as a camera (or image sensor), a sensor capable of detecting an object, ambient light, etc., and the like. The sensor is a sensor capable of detecting an object or a human body by receiving light such as infrared light, ultrasonic light, ultraviolet light, or the like. However, aspects of the present disclosure are not limited to this. Fig. 2 illustrates an exemplary configuration of the display board 110 according to aspects of the present disclosure. Referring to Fig. 2, in one or more exemplary embodiments the display panel 110 comprises a substrate 111 on which several subpixels SP are arranged, an encapsulation layer 200 over the substrate 111 and a color filter layer 210 on the encapsulation layer 200. The encapsulation layer 200 can be referred to as an encapsulation substrate or an encapsulation part. In the example where the display device 100 is a self-emitting display device, each of the multiple subpixels SP arranged on the substrate 111 contains a light-emitting element ED and a subpixel circuit SPC for controlling the light-emitting element ED. The subpixel circuit SPC contains several transistors and at least one capacitor for controlling the light-emitting element ED; however, aspects of the present disclosure are not limited thereto. In one or more aspects, the subpixel circuit SPC can control the light-emitting element ED by supplying a control current to the light-emitting element ED in a predefined time sequence. The light-emitting element ED can emit light by being driven by the control current. The multiple transistors include a drive transistor DT for controlling the light-emitting element ED and a sampling transistor ST, which is configured to be switched on or off by a sampling signal SC. The driver transistor DT can supply a drive current to the light-emitting element ED. The sampling transistor ST is configured to control the electrical state of a corresponding node in the subpixel circuit SPC or to control the state or operation of the driver transistor DT. The at least one capacitor includes a storage capacitor Cst, which is configured to maintain a voltage at a constant level during a display device frame or a specific period of time within the display device frame. To control one or more subpixels SP, at least one data signal VDATA, which is an image signal, and at least one sampling signal SC, which is a gate signal, are applied to the one or more subpixels SP. Furthermore, to control one or more subpixels SP, common control signals, containing a drive voltage VDD and a base voltage VSS, are supplied to the one or more subpixels SP. The light-emitting element ED contains a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL is positioned between the pixel electrode PE and the common electrode CE. The pixel electrode PE is an electrode arranged for each subpixel SP such that there is one pixel electrode PE for each subpixel SP, and the common electrode CE is an electrode arranged in all or some of several subpixels SP. The pixel electrode PE is an anode and the common electrode CE is a cathode. In another example, the pixel electrode PE is a cathode and the common electrode CE is an anode. For the sake of simplicity, the following description refers to embodiments in which the pixel electrode PE is an anode and the common electrode CE is a cathode. In an example where the light-emitting element ED is an organic light-emitting diode, the intermediate layer EL contains an emission layer EML, a first common intermediate layer COM1 between the pixel electrode PE and the emission layer EML, and a second common intermediate layer COM2 between the emission layer EML and the common electrode CE. A layer containing the first common intermediate layer COM1 and the second common intermediate layer COM2 can be referred to as a common intermediate layer EL_COM. The emission layer (EML) is arranged for each subpixel SP or is arranged jointly over all or some of several subpixels SP. The common intermediate layer (EL_COM) is arranged jointly over all or some of several subpixels SP, but aspects of the present disclosure are not limited thereto. The emission layer (EML) can be formed as a single layer or as multiple layers. Where the emission layer (EML) is multi-layered, the emission layers (EML) can have a tandem or stacked structure to increase the light output with an overall lower power consumption for the display device. The emission layer EML is arranged for each light-emitting surface or can be arranged jointly over all or some of several light-emitting surfaces. The common intermediate layer EL_COM is arranged jointly over all or some of several light-emitting surfaces and a non-light-emitting surface; however, aspects of the present disclosure are not limited thereto. The first common intermediate layer COM1 contains a hole injection layer (HIL), an electron barrier layer (EBL), a hole transfer layer (HTL), and the like; however, aspects of the present disclosure are not limited thereto. The second common intermediate layer COM2 contains an electron transfer layer (ETL), a hole barrier layer (HBL), an electron injection layer (EIL), and the like; however, aspects of the present disclosure are not limited thereto. The hole injection layer can inject holes from the pixel electrode PE to the hole transport layer, and the hole transport layer can transport holes to the emission layer EML; the electron injection layer can inject electrons from the common electrode CE to the electron transport layer, and the electron transport layer can transport electrons to the emission layer EML. The common electrode CE is electrically connected to a common voltage line VSSL. A common voltage VSS is applied to the common electrode CE via the common voltage line VSSL. The pixel electrode PE is electrically connected directly or indirectly (via another transistor) to a first node N1 of the corresponding driver transistor DT of each subpixel SP. Here, the common voltage VSS can also be referred to as a first common voltage, a low-power supply voltage, or a low voltage, and the common voltage line VSSL can also be referred to as a first common voltage line, a low-power supply voltage line, or a low voltage line. Each light-emitting element (ED) is configured by stacking a pixel electrode (PE), an emissive layer (EML) within an intermediate layer (EL), and a common electrode (CE). A specific light-emitting surface is formed by each ED. For example, a specific light-emitting surface of each ED contains an area where a pixel electrode (PE), an emissive layer (EML) within an intermediate layer (EL), and a common electrode (CE) overlap. In one or more aspects, all or one or more of the light-emitting elements ED contained in the display panel 110 are an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a light-emitting quantum dot element, a micro-LED, or a mini-LED; however, aspects of the present disclosure are not limited thereto. In the example where each light-emitting element ED is an organic light-emitting diode (OLED), the corresponding intermediate layer EL of each light-emitting element ED is a layer containing an organic material. Referring to Fig. 2, the drive transistor DT is a transistor configured to supply a drive current to the light-emitting element ED. The drive transistor DT is connected between a drive voltage line VDDL and the light-emitting element ED. The driver transistor DT contains a first node Na, a second node Nb, and a third node Nc. The first node Na is electrically connected to the light-emitting element ED. A data signal VDATA is applied to the second node Nb. A drive voltage VDD, which is a type of common voltage transmitted via the drive voltage line VDDL, is applied to the third node Nc. Here, the drive voltage VDD can also be referred to as a second common voltage, a high-power supply voltage, or a high voltage, and the drive voltage line VDDL can also be referred to as a second common voltage line, a high-power supply voltage line, or a high voltage line. In the driver transistor DT, the second node Nb is a gate node, the first node Na is a source or drain node, and the third node Nc is a drain or source node. For the sake of simplicity, the following descriptions will use examples where the first, second, and third nodes (Na, Nb, and Nc) of the driver transistor DT are a source, gate, and drain node, respectively. However, aspects of this disclosure are not limited to this. The sampling transistor ST, which is included in the subpixel circuit SPC illustrated in Fig. 2, is a switching transistor for transmitting a data signal VDATA, which is an image signal, to the second node Nb, which is the gate node of the drive transistor DT. The sampling transistor ST can be switched on or off by a sampling signal SC, which is a type of gate signal transmitted via a sampling line SCL, which is a type of gate line GL, and which controls an electrical connection between the second node Nb of the driver transistor DT and a data line DL. One of the drain electrodes or the source electrode of the sampling transistor ST is electrically connected to the data line DL. The other of the source electrode or the drain electrode of the sampling transistor ST is electrically connected to the second node Nb of the driver transistor DT. The gate electrode of the sampling transistor ST is electrically connected to the sampling line SCL. The storage capacitor Cst can be electrically connected between the first node Na and the second node Nb of the driver transistor DT. The storage capacitor Cst comprises a first capacitor electrode that is electrically connected to, or corresponds to, the first node Na of the driver transistor DT, and a second capacitor electrode that is electrically connected to, or corresponds to, the second node Nb of the driver transistor DT. The storage capacitor Cst is an external capacitor intentionally designed to be located outside the drive transistor DT and is therefore distinct from an internal capacitor such as a parasitic capacitor (e.g., a Cgs, a Cgd) formed between the first node Na and the second node Nb of the drive transistor DT. However, aspects of the present disclosure are not limited to this. Each of the drive transistor DT and the sampler transistor ST is either an n-type or a p-type transistor, however, aspects of the present disclosure are not limited thereto. For example, one of the drive transistor DT and one of the sampler transistor ST is either an n-type or a p-type transistor. The display panel 110 can have a top-emitting or a bottom-emitting structure. In an example where the display panel 110 has the top-emitting structure, at least one section of the subpixel circuit SPC can overlap with at least one section of the light-emitting element ED in the vertical direction. In this configuration, the area or size of a corresponding light-emitting area can increase, and a corresponding aperture ratio can increase. In an example where the display panel 110 has the bottom-emitting structure, the subpixel circuit SPC does not have to overlap with the light-emitting element ED in the vertical direction. As shown in Fig. 2, the SPC subpixel circuit contains two transistors (2T: DT and ST) and one capacitor (1C: Cst) (which may be referred to as a “2T1C structure”) and may, in some implementations, further contain one or more transistors and / or further contain one or more capacitors. However, aspects of the present disclosure are not limited thereto. The subpixel circuit SPC can have a 3T1C structure, containing 3 transistors and 1 capacitor. In another example, the subpixel circuit SPC can have an 8T1C structure, containing 8 transistors and 1 capacitor. In yet another example, the subpixel circuit SPC can have a 6T2C structure, containing 6 transistors and 2 capacitors. In yet another example, the subpixel circuit SPC can have a 7T1C structure, containing 7 transistors and 1 capacitor. However, aspects of the present disclosure are not limited thereto. The types and number of gate signals supplied to a subpixel SP, and / or the types and number of gate lines connected to the subpixel SP, can vary depending on the structure of the corresponding subpixel circuit SPC. Furthermore, the types and number of common drive signals supplied to a subpixel SP can also vary depending on the structure of the corresponding subpixel circuit SPC. With reference to Fig. 2, the encapsulation layer 200 is arranged in or on the display panel 110, since circuit elements (e.g., light-emitting elements ED such as organic light-emitting diodes (OLEDs) containing an organic material) in each subpixel SP are susceptible to external moisture or oxygen. The encapsulation layer 200 can prevent external moisture or oxygen from penetrating the circuit elements (e.g., the light-emitting elements ED). The encapsulation layer 200 is arranged in various shapes or configurations to prevent light-emitting elements ED from coming into contact with moisture or oxygen. The encapsulation layer 200 contains two or more layers in which one or more organic layers and one or more inorganic layers are stacked alternately; however, aspects of the present disclosure are not limited to these. Fig. 3 is an example cross-sectional view of the display board 110 according to aspects of the present disclosure along line AA in Fig. 2 . With reference to Fig. 3, in one or more exemplary embodiments the display panel 110 comprises a substrate 111, a transistor part (which may also be referred to as a transistor or a transistor stack), a part of light-emitting elements (which may also be referred to as a light-emitting element or a light-emitting stack) and an encapsulation part (which may also be referred to as an encapsulation layer or encapsulation layers), however, aspects of the present disclosure are not limited thereto. The substrate 111 can be in the form of a single-layer or a multi-layer stack. In an example where the substrate 111 has a multi-layer structure, it comprises a first substrate 301, an intermediate substrate layer 302, and a second substrate 303. The intermediate substrate layer 302 is located between the first substrate 301 and the second substrate 303. In one or more aspects, each of the first substrate 301 and the second substrate 303 is a polyimide layer (PI layer), but aspects of this disclosure are not limited to this. The intermediate substrate layer 302 is an inorganic insulating layer, but aspects of this disclosure are not limited to this.If electrical charges are stored on the first substrate 301, which is a polyimide layer (PI layer), the intermediate substrate layer 302, via the second substrate 303, which is a polyimide layer (PI layer), can block the charges from affecting transistors arranged on the second substrate 303. Furthermore, the intermediate substrate layer 302 can block moisture from migrating upwards through the first substrate 301. The intermediate substrate layer 302 can be in the form of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or a multiple layer of silicon nitride (SiNx) and / or silicon oxide (SiOx), or it can be in the form of bilayers of silicon dioxide (SiO2) and silicon nitride (SiNx), however, aspects of the present disclosure are not limited to these. The transistor section contains insulating layers (311, 312, 313, 321, 322 and 323), thin-film transistors (TFT1 and TFT2), a storage capacitor Cst and several electrodes or signal lines on the substrate 111. The thin-film transistors (TFT1 and TFT2) contained in the transistor section include a first thin-film transistor TFT1 and a second thin-film transistor TFT2. The first thin-film transistor TFT1 contains a first active layer ACT1, a first electrode E1a, a second electrode E1b and a third electrode E1c. The first electrode E1a is a gate electrode, the second electrode E1b is a source electrode or a drain electrode, and the third electrode E1c is either the drain electrode or the source electrode. For the sake of simplicity, embodiments are described below in which the first, second, and third electrodes (E1a, E1b, and E1c) are a first gate electrode E1a, a first source electrode E1b, and a first drain electrode E1c, respectively. However, aspects of the present disclosure are not limited to these. The first active layer ACT1 contains a first semiconductor material. The first semiconductor material contains an oxide semiconductor, amorphous silicon, polysilicon, low-temperature polysilicon (LTPS), or the like; however, aspects of this disclosure are not limited to these. The first thin-film transistor TFT1 can be a p-channel transistor or an n-channel transistor; however, aspects of this disclosure are not limited to these. The second thin-film transistor TFT2 contains a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b and a sixth electrode E2c. The fourth electrode E2a can be a gate electrode, the fifth electrode E2b can be a source electrode or a drain electrode, and the sixth electrode E2c can be either the drain electrode or the source electrode. For the sake of simplicity, a further description based on examples is provided below, where the fourth, fifth, and sixth electrodes (E2a, E2b, and E2c) are a second gate electrode E2a, a second source electrode E2b, and a second drain electrode E2c, respectively. However, aspects of the present disclosure are not limited to this. The second active layer ACT2 contains a second semiconductor material. This second semiconductor material may be an oxide semiconductor, amorphous silicon, polysilicon, low-temperature polysilicon (LTPS), or the like; however, aspects of this disclosure are not limited to these. The second thin-film transistor TFT2 is a p-channel transistor or an n-channel transistor; however, aspects of this disclosure are not limited to these. The types of respective semiconductor materials of the first active layer ACT1 of the first thin-film transistor TFT1 and the second active layer ACT2 of the second thin-film transistor TFT2 are further described below. For example, each of the first active layer ACT1 of the first thin-film transistor TFT1 and the second active layer ACT2 of the second thin-film transistor TFT2 contains an oxide semiconductor material. For example, each of the first active layer ACT1 of the first thin-film transistor TFT1 and the second active layer ACT2 of the second thin-film transistor TFT2 contains a low-temperature polysilicon semiconductor material. The first active layer ACT1 of the first thin-film transistor TFT1 contains a low-temperature polysilicon semiconductor material, and the second active layer ACT2 of the second thin-film transistor TFT2 contains an oxide semiconductor material. The first active layer ACT1 of the first thin-film transistor TFT1 contains an oxide semiconductor material, and the second active layer ACT2 of the second thin-film transistor TFT2 contains a low-temperature polysilicon semiconductor material. However, aspects of the present disclosure are not limited thereto. Transistors arranged in the DA display area are used as follows. For example, all transistors contained in each subpixel SP are implemented as the first thin-film transistor TFT1. For example, all transistors contained in each subpixel SP are implemented as the second thin-film transistor TFT2. For example, one or more of the transistors contained in each subpixel SP can be implemented as the first thin-film transistor TFT1, and the one or more remaining transistors can be implemented as the second thin-film transistor TFT2. For example, each subpixel SP contains at least one first thin-film transistor TFT1 and at least one second thin-film transistor TFT2. In an example where one or more of the transistors contained in each subpixel SP are implemented as the first thin-film transistor TFT1, and the one or more remaining transistors are implemented as the second thin-film transistor TFT2, various configurations are applied as described below. For example, in each subpixel SP, a drive transistor DT is implemented as the first thin-film transistor TFT1 and the one or more remaining transistors (e.g. a sampling transistor ST, an emission control transistor and / or the like) are implemented as the second thin-film transistor TFT2. For example, in each subpixel SP a drive transistor DT is implemented as the second thin-film transistor TFT2 and the one or more remaining transistors (e.g. a sampling transistor ST, an emission control transistor and / or the like) are implemented as the first thin-film transistor TFT1. In Fig. 3, the second thin-film transistor TFT2, which is connected to a pixel electrode PE of a light-emitting element ED, is, depending on the configuration of a corresponding subpixel circuit SPC, either a driver transistor DT or a transistor different from the driver transistor DT. For example, in Fig. 3, the second thin-film transistor TFT2, which is connected to the pixel electrode PE of the light-emitting element ED, is an emission control transistor connected between the driver transistor DT and the light-emitting element ED. In embodiments where the second thin-film transistor TFT2 is the driver transistor, the second thin-film transistor TFT2 is an oxide transistor and the first thin-film transistor TFT1 is an LPTS transistor, which allows more power to be supplied to the subpixels to increase the light output with an overall lower power consumption for the display device.The active layer ACT2 of the second thin-film transistor TFT2 is an LTPS transistor and is thinner than the active layer ACT1 of the first thin-film transistor TFT1. Transistors arranged in the non-display area (NDA) are used as follows. The active layers of transistors contained in the gate-in-table (GIP) type gate drive circuit contain an oxide semiconductor material. The active layers of transistors contained in the gate-in-table (GIP) type gate drive circuit contain a low-temperature polysilicon semiconductor material. For example, among the active layers of transistors contained in the gate-in-table (GIP) type gate drive circuit, some active layers contain a low-temperature polysilicon semiconductor material, while other active layers, or the one or more remaining active layers, contain an oxide semiconductor material. The second active layer ACT2 of the second thin-film transistor TFT2 is located higher from the substrate 111 than the first active layer ACT1 of the first thin-film transistor TFT1. A first buffer layer 311 is arranged beneath the first active layer ACT1 of the first thin-film transistor TFT1, and a second buffer layer 321 is arranged beneath the second active layer ACT2 of the second thin-film transistor TFT2. The first active layer ACT1 of the first thin-film transistor TFT1 is located on the first buffer layer 311, and the second active layer ACT2 of the second thin-film transistor TFT2 is located on the second buffer layer 321. The second buffer layer 321 is positioned higher than the first buffer layer 311 in the cross-sectional view. The storage capacitor Cst is arranged in several metal layers in the display panel 110. The storage capacitor Cst contains a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. The light-emitting element portion contains several light-emitting elements ED arranged on at least one planarization layer 330. Each of the several light-emitting elements ED contains a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The encapsulation part includes an encapsulation layer 200 on the multiple light-emitting elements ED. The encapsulation layer 200 is in the form of a single-layer or a multi-layer structure, although aspects of the present disclosure are not limited to this. In addition to the encapsulation layer 200, the encapsulation part further includes at least one dam 314 to prevent any material contained in the encapsulation layer 200 from overflowing. For example, if a second encapsulation layer 342 contained in the encapsulation layer 200 is an organic encapsulation layer containing an organic material, the dam 314 prevents the organic encapsulation layer from overflowing. The dam 314 may be formed at least partially by the second planarization layer 332 described below.The second planarization layer 332 is a black bank, or in some embodiments, a black bank is formed instead of the second planarization layer 332. In such embodiments, the black bank 332 is arranged in the contact area PA of the non-display area NDA and covers at least one section or all of a first and a second source drain and any additional layers that may be present over the first and the second source drain. The dam 314 may be formed by several different layers of the display device 100. The dam 314 overlaps with the first connection pattern CP1, which in some embodiments may be an anode. The dam 314 also overlaps with the second connection pattern CP2, which may be one or more source drains, such as a first and a second source drain. The following section describes in more detail a vertical structure or a stacked structure of the display board 110 with reference to Fig. 3. With reference to Fig. 3, the first buffer layer 311 is arranged on the substrate 111. The first buffer layer 311 is in the form of a single-layer or a multi-layer stack, however, aspects of the present disclosure are not limited thereto. In an example, wherein the first buffer layer 311 has a multi-layer structure, the first buffer layer 311 includes a lower buffer layer 311a and an upper buffer layer 311b. The first active layer ACT1 of the first thin-film transistor TFT1 is located on the first buffer layer 311. The first active layer ACT1 contains a channel region in which a channel is formed, a source connection region on one side of the channel region, and a drain connection region on a second, opposite side of the channel region. A first gate isolation layer 312 is arranged on the first active layer ACT1 of the first thin-film transistor TFT1. The first gate electrode E1a of the first thin-film transistor TFT1 is arranged on the first gate isolation layer 312. A first intermediate isolation layer 313 is arranged on the first gate electrode E1a of the first thin-film transistor TFT1. A metal layer in which the first gate electrode E1a of the first thin-film transistor TFT1 is arranged can be referred to as a first gate metal layer. The second buffer layer 321 is arranged on the first insulating layer 313. A second gate insulating layer 322 is arranged on the second active layer ACT2 of the second thin-film transistor TFT2. The second gate electrode E2a of the second thin-film transistor TFT2 is arranged on the second gate insulating layer 322. A second insulating layer 323 is arranged on the second gate electrode E2a of the second thin-film transistor TFT2. The second gate electrode E2a of the second thin-film transistor TFT2 can be referred to as a second gate metal layer. The first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2 are arranged on the second insulating intermediate layer 323. The first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1 are connected to the source junction area and the drain junction area of ​​the first active layer ACT1, respectively, by holes in the second intermediate insulation layer 323, the second gate insulation layer 322, the second buffer layer 321, the first intermediate insulation layer 313 and the first gate insulation layer 312. The second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2 are connected to the source junction area and the drain junction area of ​​the second active layer ACT2, respectively, by holes in the second insulating intermediate layer 323 and the second gate insulating layer 322. The first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2 contain a first source / drain metal and are arranged in a first source / drain metal layer. Referring to Fig. 3, in one or more aspects the storage capacitor Cst contains the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2. In one or more aspects, the storage capacitor Cst contains three or more capacitor electrodes or contains two or more capacitors connected in parallel. Each of the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 is arranged in several metal layers, which are arranged in the display panel 110. In one or more aspects, the first capacitor electrode CAPE1 contains the same first gate metal as the first gate electrode E1a of the first thin-film transistor TFT1 on the first gate insulating layer 312 and is arranged in the first gate metal layer; however, aspects of the present disclosure are not limited thereto. In one or more aspects, the second capacitor electrode CAPE2 is arranged on the first insulating intermediate layer 313. The second source electrode E2b of the second transistor TFT2 is electrically connected to the second capacitor electrode CAPE2 by holes in the second insulating intermediate layer 323, the second gate insulating layer 322 and the second buffer layer 321. In one or more aspects, the transistor part further includes a first shielding pattern BSM1, which is arranged on the substrate 111. The first shielding pattern BSM1 overlaps with the first active layer ACT1 of the first thin-film transistor TFT1. The first shielding pattern BSM1 is arranged below the first active layer ACT1 of the first thin-film transistor TFT1. The first shielding pattern BSM1 is arranged between the substrate 111 and the first buffer layer 311, or is arranged between the lower buffer layer 311a and the upper buffer layer 311b. The transistor portion further includes a second shielding pattern BSM2, which is arranged on substrate 111. The second shielding pattern BSM2 overlaps with the second active layer ACT2 of the second thin-film transistor TFT2. The second shielding pattern BSM2 is arranged beneath the second active layer ACT2 of the second thin-film transistor TFT2. The second shielding pattern BSM2 is arranged in a metal layer between the first insulating intermediate layer 313 and the second buffer layer 321. The second shielding pattern BSM2 is arranged in the same metal layer as the second capacitor CAPE2, although aspects of this disclosure are not limited thereto. The second shielding pattern BSM2 is arranged in the same first gate metal layer as the first gate electrode E1a of the first thin-film transistor TFT1. The planarization layer 330 is arranged on the first thin-film transistor TFT1 and the second thin-film transistor TFT2 and is located beneath the light-emitting element ED. The planarization layer 330 is an organic insulating layer containing an organic insulating material. The planarization layer 330 can be in the form of a single layer. Alternatively, the planarization layer 330 contains two layers. The planarization layer 330 contains a first planarization layer 331 and a second planarization layer 332. The planarization layer 330 contains three or more layers, however, aspects of the present disclosure are not limited to this. The first planarization layer 331 is arranged on the first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1 and on the second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2. The first planarization layer 331 is arranged on the first thin-film transistor TFT1 and the second thin-film transistor TFT2. The first planarization layer 331 is arranged such that it covers both the first thin-film transistor TFT1 and the second thin-film transistor TFT2. A connecting electrode RE is arranged on the first planarization layer 331. The connecting electrode RE electrically connects the second source electrode E2b of the second thin-film transistor TFT2 and the pixel electrode PE. The connecting electrode RE is electrically connected to the second source electrode E2b of the second thin-film transistor TFT2 via a hole in the first planarization layer 331. The second source electrode E2b of the second thin-film transistor TFT2 is electrically connected to the second capacitor electrode CAPE2 of the storage capacitor Cst. The connecting electrode RE is arranged in a second source / drain metal layer on the first planarization layer 331 and contains a second source / drain metal. The second planarization layer 332 is arranged on the connecting electrode RE. The portion of the light-emitting elements is arranged on the second planarization layer 332. The light-emitting element ED is formed on the second planarization layer 332. The light-emitting element ED contains the pixel electrode PE, the intermediate layer EL, and the common electrode CE. A light-emitting area of ​​the light-emitting element ED is formed by an area in which the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap and touch each other. The pixel electrode PE is arranged on the second planarization layer 332. The pixel electrode PE is electrically connected to the connecting electrode RE through a hole in the second planarization layer 332. The bank 340 is positioned on the second planarization layer 332 and the pixel electrode PE. An opening in the bank 340 exposes a section of the pixel electrode PE to form a light-emitting surface. The opening in the bank 340 overlaps with a section of the pixel electrode PE. Bank 340 contains a material that includes a black pigment, or an organic material that includes a benzocyclobutene resin, a polyimide resin, an acrylic resin, a photosensitive polymer, or the like. However, aspects of the present disclosure are not limited to this. In an example where Bank 340 contains a material that includes a black pigment or a black dye, Bank 340 can be a black bank. In the example where Bank 340 contains a material that includes a black pigment or a black dye, the luminance of the display device can be further improved because light from the outside or light reflected from the outside can be blocked. The intermediate layer EL of the light-emitting element ED is arranged on a section of the pixel electrode PE and the bank 340. The common electrode CE is arranged on the intermediate layer EL and the bank 340. The encapsulation part is arranged on the light-emitting element portion and is located on the common electrode CE. The encapsulation part contains an encapsulation layer 200, which is arranged on the common electrode CE. The encapsulation layer 200 prevents moisture or oxygen from penetrating the light-emitting element ED. The encapsulation layer 200 can also prevent moisture or oxygen from penetrating an organic material contained in the intermediate layer EL of the light-emitting element ED. In one or more aspects, the encapsulation layer 200 can be in the form of a single-layer or a multi-layer stack, but aspects of the present disclosure are not limited to this. The encapsulation layer 200 contains a first encapsulation layer 341, a second encapsulation layer 342, and a third encapsulation layer 343; however, aspects of the present disclosure are not limited thereto. The first encapsulation layer 341 and the third encapsulation layer 343 contain an inorganic material, and the second encapsulation layer 342 contains an organic material. However, aspects of the present disclosure are not limited thereto. In one or more aspects, a touch sensor can be embedded in the display panel 110. In this implementation, the display panel 110 includes a touch sensor layer 210, which is arranged on the encapsulation layer 200 and contains the touch sensor. The touch sensor layer 210 contains several touch electrodes TE which serve as the touch sensor and contains at least one touch metal layer to form the several touch electrodes TE. For example, to form the multiple contact electrodes TE, the contact sensor layer 210 includes a first contact metal layer in which several first contact metals TM1 are arranged, and a second contact metal layer in which several second contact metals TM2 are arranged. In this implementation, the contact sensor layer 210 further includes a contact intermediate insulation layer 352, which is arranged between the first contact metal layer and the second contact metal layer. For example, one of the first contact metal layers and the second contact metal layer can be a sensor metal layer, and the other can be a bridge metal layer. The first contact metal layer is a bridge metal layer, and the second contact metal layer is a sensor metal layer. In this implementation, the multiple second contact metals TM2 arranged in the second contact metal layer are sensor metals that form the touch sensor, and the multiple first contact metals TM1 arranged in the first contact metal layer are bridge metals that electrically connect the multiple second contact metals TM2 that are the sensor metals. In one or more aspects, two or more second contact metals TM2 and at least one first contact metal TM1 form a first contact electrode TE1. In this implementation, the two or more second contact electrodes TE2 are electrically connected by at least one first contact metal TM1. In one or more aspects, the first contact metal layer is a sensor metal layer, and the second contact metal layer is a bridge metal layer. In this implementation, the multiple first contact metals TM1 arranged in the first contact metal layer are sensor metals that form the touch sensor, and the multiple second contact metals TM2 arranged in the second contact metal layer are bridge metals that electrically connect the multiple first contact metals TM1, which are the sensor metals. In one or more aspects, each of the first contact metal layer and the second contact metal layer is a sensor metal layer and a bridge metal layer. The first contact metal layer is a sensor metal layer and a bridge metal layer, and the second contact metal layer is a sensor metal layer and a bridge metal layer. In this implementation, the multiple first contact metals TM1 arranged in the first contact metal layer contain sensor metals and bridge metals, and the multiple second contact metals TM2 arranged in the second contact metal layer contain sensor metals and bridge metals. The touch sensor layer 210 further comprises a touch buffer layer 351, which is arranged on the encapsulation layer 200. The touch buffer layer 351 is arranged between the encapsulation layer 200 and the contact metal layer. The first contact metal layer is arranged on the touch buffer layer 351, and the contact intermediate insulating layer 352 is arranged on the first contact metal layer. The touch sensor layer 210 further includes a touch protection layer 353, which is arranged such that the touch protection layer 353 covers the contact metal layers. The touch protection layer 353 is arranged on the second contact metal layer. The contact buffer layer 351 is an inorganic layer containing an inorganic insulating material, or an organic layer containing an organic insulating material. The contact intermediate insulating layer 352 is an inorganic layer containing an inorganic insulating material, or an organic layer containing an organic insulating material. The contact protection layer 353 is an inorganic layer containing an inorganic insulating material, or an organic layer containing an organic insulating material. For example, at least one of the touch buffer layer 351 and the touch intermediate insulating layer 352 is arranged such that it extends from the display area DA to the non-display area NDA. The touch protection layer 353 is arranged such that it extends from the display area DA to the non-display area NDA. A touch guide wire TL electrically connects a touch electrode TE and a touch-sensitive control panel TP. The touch guide wire TL is formed by at least one of the first touch metal TM1 and the second touch metal TM2. The touch guide TL is formed by the first touch metal TM1. The touch guide TL is formed by the second touch metal TM2. The touch guide TL is formed by the first touch metal TM1 and the second touch metal TM2. In an example where a touch guide TL is formed by the first touch metal TM1 and the second touch metal TM2, the first touch metal TM1 and the second touch metal TM2 contained in the touch guide TL are electrically connected by a hole in the insulating layer 352. For example, a touch conductor guide cable (TL) contains several conductor sections, and each of these conductor sections can be either a single conductor section or a double conductor section. A single conductor section can be a conductor section with one signal path, and a double conductor section can be a conductor section with two signal paths connected in parallel. The touch guide TL runs along an inclined surface of the encapsulation layer 200, runs over an upper section of at least one dam (314-1 and / or 314-2) and reaches or touches a touch-sensitive control panel TP. The touch buffer layer 351 has an opening to expose at least one section of the touch-sensitive control panel TP. The touch guide cable TL is electrically connected to the touch-sensitive control panel TP through the opening in the touch buffer layer 351. The touch intermediate insulating layer 352 is arranged on a section of the touch guide cable TL and extends to a surface in which the touch-sensitive control panel TP is located. The touch protection layer 353 is arranged only in the display area DA or may extend to the non-display area NDA and be arranged on the touch guide cable TL. In one or more aspects, the touch protection layer 353 also extends to an upper section of the touch-sensitive control panel TP. Each of several contact electrodes TE can be a grid-type electrode configured to have a mesh and multiple openings. In this implementation, each of the several contact electrodes TE includes at least one second contact metal TM2, but aspects of the present disclosure are not limited thereto. The multiple contact electrodes TE include at least one first contact electrode TE1 and at least one second contact electrode TE2. In an example where the first contact metal layer is a bridge metal layer and the second contact metal layer is a sensor metal layer, two or more second contact metals TM2, contained within a first contact electrode TE1, which is the touch sensor, are electrically connected by at least one first contact metal TM1, which is the bridge metal. For example, two spaced-apart second contact metals TM2 are electrically connected by a first contact metal TM1 to form a first contact electrode TE1. The multiple first contact metals TM1 and the multiple second contact metals TM2 are arranged such that they do not overlap with the light-emitting element ED. The multiple first contact metals TM1 and the multiple second contact metals TM2 overlap with bank 340. According to these configurations, the display panel 110 can provide an advantage in improving the emission efficiency of the light-emitting element ED. The touch guide TL connects the touch-sensitive control panel TP, which is located in a contact surface PA of a second non-display surface NDA2, and the first touch electrode TE1, which is located in the display surface DA. In this implementation, the touch guide TL is arranged across the second non-display surface NDA2, a bending surface BA, and a first non-display surface NDA1. The touch conductor guide TL comprises a first conductor section TLa, a second conductor section TLb, and a third conductor section TLc. The touch conductor guide TL includes the first conductor section TLa and the second conductor section TLb, which are located in the first non-display area NDA1 and the second non-display area NDA2, respectively, and the third conductor section TLc, which is located in the bending area BA. The third conductor section TLc connects either two first conductor sections TLa or the first conductor section TLa and the second conductor section TLb. The first conductor section TLa of the contact conductor guide TL is a single conductor section and further contains a third contact metal layer in which a third contact metal TM3 is arranged. The first conductor section TLa of the contact conductor guide TL is arranged such that it runs along an inclined surface of the encapsulation layer 200 and further extends over at least one dam (314-1 and / or 314-2). The first conductor section TLa of the contact conductor guide TL is connected to the third conductor section TLc of the contact conductor guide TL by at least one of the first contact metal layer and the second contact metal layer. The second conductor section TLb of the contact conductor guide TL contains at least one of the first contact metal layer in which the first contact metal TM1 is arranged, and the second contact metal layer in which the second contact metal TM2 is arranged. The second conductor section TLb of the contact conductor guide TL can be formed by the second contact metal layer. Alternatively, the second conductor section TLb of the contact conductor guide TL can be formed by an electrical connection between the first and second contact metal layers. The second conductor section TLb of the touch conductor guide TL is electrically connected to the touch-sensitive control panel TP through a contact hole (an opening) through the second planarization layer 332, the touch buffer layer 351 and the touch intermediate layer insulation layer 352. The third conductor section TLc of the touch conductor guide line TL is connected to the second conductor section TLb of the touch conductor guide line TL. The third conductor section TLc of the touch conductor guide TL contains a metal layer that differs from the first to third touch metal layers, in which the first and second touch metals (TM1, TM3, and TM4) are arranged. The metal layer contained in the third conductor section TLc of the touch conductor guide TL is the same as a metal layer in which one or more electrodes or leads for display control are arranged. The metal layer contained in the third conductor section TLc of the touch conductor guide TL includes a metal layer in which the pixel electrode PE is arranged; however, aspects of the present disclosure are not limited to this. The touch-sensitive control panel TP is electrically connected to the second conductor section TLb of the touch guide line TL and contains a metal layer that is different from the first to third touch metal layers. The metal layer contained in the touch-sensitive control panel TP is the same as a metal layer in which one or more electrodes or lines for display control are arranged. The metal layer contained in the touch-sensitive control panel TP includes a metal layer in which the pixel electrode PE is arranged; however, aspects of the present disclosure are not limited thereto. In one or more aspects, the display panel 110 further includes a common voltage line VSSL to which a common voltage VSS is applied, and a connection pattern CP for connecting the common electrode CE and the common voltage line VSSL. The connection pattern CP contains a first connection pattern CP1 and a second connection pattern CP2. The first connection pattern CP1 connects the common electrode CE and the second connection pattern CP2 connects the first connection pattern CP1 and the first common voltage line VSSL, however, aspects of the present disclosure are not limited thereto. The first connection pattern CP1 contains the same material as the pixel electrode PE. The second connection pattern CP2 contains the same material as the connection electrode RE. Fig. 4 is an example plan view of the display board 110 according to aspects of the present disclosure. Referring to Fig. 4, in one or more exemplary embodiments the display panel 110 contains several subpixels SP. The subpixels SP are arranged in the display area DA for displaying images. Each of the subpixels SP contains a light-emitting element configured to emit red light R, green light G, or blue light B. In one or more aspects, the display device 100 may be a television, a surveillance device, or the like. In one or more aspects, the display device 100 may be a smartphone, a tablet, a portable electronic device, or the like. In one or more aspects, the display device 100 may be a vehicle display device, an electronic device for virtual reality (VR device), an electronic device for augmented reality (AR device), or the like. Figures 5, 6, 7 to 8 are exemplary cross-sectional views taken along line AB of Figure 4, according to embodiments of the present disclosure. For the sake of simplicity, the following description of features that are the same, substantially the same, or similar to those described with reference to Figure 3 is omitted. With reference to Fig. 5, in one or more exemplary embodiments the display panel 110 includes a substrate 111, a transistor part, a part of light-emitting elements and an encapsulation part, but aspects of the present disclosure are not limited thereto. Substrate 111 contains a stack or structure consisting of a single layer or multiple layers. In an example where substrate 111 contains a multilayer structure, it includes a first substrate 500, an intermediate substrate layer 501, and a second substrate 502. The intermediate substrate layer 501 is located between the first substrate 500 and the second substrate 502, with each of the first substrate, the intermediate substrate layer 501, and the second substrate 502 in direct contact to form the multilayer stack of substrate 111. For example, both the first substrate 500 and the second substrate 502 are polyimide (PI) layers, but aspects of the present disclosure are not limited to these. The intermediate substrate layer 501 is an inorganic insulating layer, but aspects of the present disclosure are not limited to this. If electrical charges are stored on the first substrate 500, which is a polyimide (PI) layer, the intermediate substrate layer 501, via the second substrate 502, which is also a polyimide (PI) layer, can block the charges from influencing transistors located on the second substrate 502. Thus, the intermediate substrate layer 501 can be either a shielding layer or an insulating layer. Furthermore, the intermediate substrate layer 501 can block moisture from migrating upwards through the first substrate 500. The intermediate substrate layer 501 can be in the form of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer stack or structure of silicon nitride (SiNx) and / or silicon oxide (SiOx), or in the form of bilayers of silicon dioxide (SiO2) and silicon nitride (SiNx); however, aspects of the present disclosure are not limited to these. The transistor section includes, but is not limited to, insulating layers (503, 504, 505, 506, 507, 508, 509 and 510) on substrate 111, thin-film transistors (TFT1, TFT2 and TFT3), a storage capacitor Cst and various electrodes or signal lines. The thin-film transistors (TFT1, TFT2 and TFT3) contained in the transistor section include a first thin-film transistor TFT1, a second thin-film transistor TFT2 and a third thin-film transistor TFT3, but are not limited to this. The first thin-film transistor TFT1 contains a first active layer ACT1, a first gate electrode G1, a first electrode E1a and a second electrode E1b. The first active layer ACT1 contains a first semiconductor material. The first semiconductor material may be an oxide semiconductor, amorphous silicon, polysilicon, low-temperature polysilicon (LTPS), or the like, but is not limited to these. The first thin-film transistor TFT1 may be a p-channel transistor or an n-channel transistor, but aspects of this disclosure are not limited to these. The first electrode E1a is a source electrode or a drain electrode, and the second electrode E1b is either the drain electrode or the source electrode. For the sake of simplicity, embodiments are described below in which the first electrode E1a is a first source electrode E1a and the second electrode E1b is a first drain electrode E1b; however, aspects of the present disclosure are not limited thereto. The second thin-film transistor TFT2 contains a second active layer ACT2, a second gate electrode G2, a third electrode E2a and a fourth electrode E2b. The second active layer ACT2 contains a second semiconductor material. This second semiconductor material may include, but is not limited to, oxide semiconductors, amorphous silicon, polysilicon, low-temperature polysilicon (LTPS), or the like. The second thin-film transistor TFT2 may be a p-channel transistor or an n-channel transistor, but aspects of this disclosure are not limited to these possibilities. The third electrode E2a is a source electrode or a drain electrode, and the fourth electrode E2b is either the drain electrode or the source electrode. For the sake of simplicity, embodiments are described below in which the third electrode E2a is a second source electrode E2a and the fourth electrode E2b is a second drain electrode E2b; however, aspects of the present disclosure are not limited to these embodiments. The third thin-film transistor TFT3 contains a third active layer ACT3, a third gate electrode G3, a fifth electrode E3a and a sixth electrode E3b. The third active layer ACT3 contains a third semiconductor material. This third semiconductor material may include, but is not limited to, oxide semiconductors, amorphous silicon, polysilicon, low-temperature polysilicon (LTPS), or the like. The third thin-film transistor TFT3 may be a p-channel transistor or an n-channel transistor, but aspects of this disclosure are not limited to these possibilities. The fifth electrode E3a is a source electrode or a drain electrode, and the sixth electrode E3b is either the drain electrode or the source electrode. For the sake of simplicity, embodiments are described below in which the fifth electrode E3a is a third source electrode E3a and the sixth electrode E3b is a third drain electrode E3b; however, aspects of the present disclosure are not limited to these embodiments. The types of respective semiconductor materials of the first active layer ACT1 of the first thin-film transistor TFT1, the second active layer ACT2 of the second thin-film transistor TFT2 and the third active layer ACT3 of the third thin-film transistor TFT3 are as follows. For example, each of the first active layer ACT1 of the first thin-film transistor TFT1, the second active layer ACT2 of the second thin-film transistor TFT2, and the third active layer ACT3 of the third thin-film transistor TFT3 contains an oxide semiconductor material; however, aspects of the present disclosure are not limited thereto. For example, each of the first active layer ACT1 of the first thin-film transistor TFT1, the second active layer ACT2 of the second thin-film transistor TFT2, and the third active layer ACT3 of the third thin-film transistor TFT3 contains a low-temperature polysilicon semiconductor material; however, aspects of the present disclosure are not limited thereto. For example, all transistors contained in each subpixel SP are implemented as the first thin-film transistor TFT1. For example, all transistors contained in each subpixel SP are implemented as the second thin-film transistor TFT2. For example, all transistors contained in each subpixel SP are implemented as the third thin-film transistor TFT3. One or more of the transistors contained in each subpixel SP are implemented as the first thin-film transistor TFT1, and the one or more remaining transistors are implemented as the second thin-film transistor TFT2 and the third thin-film transistor TFT3. For example, each subpixel SP contains at least one first thin-film transistor TFT1, at least one second thin-film transistor TFT2, and at least one third thin-film transistor TFT3. In the following examples, one or more of the transistors contained in each subpixel SP are implemented as the first thin-film transistor TFT1, and the one or more remaining transistors are implemented as the second thin-film transistor TFT2 and the third thin-film transistor TFT3. For example, in each subpixel SP, a drive transistor DT is implemented as the first thin-film transistor TFT1, and the one or more remaining transistors (e.g., a sampling transistor ST, an emission control transistor, and / or the like) are implemented as at least one of the second thin-film transistor TFT2 and the third thin-film transistor TFT3. The first thin-film transistor TFT1, connected to a first pixel electrode PE1 of a first light-emitting element ED1, is, depending on the configuration of a corresponding subpixel circuit SPC, either a driver transistor DT or a transistor other than the driver transistor DT. For example, in Fig. 5, the first thin-film transistor TFT1, connected to the first pixel electrode PE1 of the first light-emitting element ED1, is an emission control transistor connected between the driver transistor DT and the first light-emitting element ED1. The insulating layers (503, 504, 505, 506, 507, 508, 509, and 510) are arranged on the substrate 111 as follows. A first buffer layer is arranged on the substrate 111. The first buffer layer 503, 504 can be in the form of a single-layer or a multi-layer stack, but aspects of this disclosure are not limited thereto. If the first buffer layer 503, 504 is in the form of a multi-layer stack, the first buffer layer 503, 504 comprises a first lower buffer layer 503 and a first upper buffer layer 504, but aspects of this disclosure are not limited thereto. A first gate isolation layer 505 and a first isolation intermediate layer 506 are arranged on the first buffer layer 503, 504. The first gate isolation layer 505 is arranged on the third active layer ACT3 of the third thin-film transistor TFT3. The third gate electrode G3 of the third thin-film transistor TFT3 is also arranged on the first gate isolation layer 505, however, aspects of the present disclosure are not limited thereto. The first insulating layer 506 is arranged on the third gate electrode G3 of the third thin-film transistor TFT3. A metal layer in which the third gate electrode G3 of the third thin-film transistor TFT3 is arranged can be referred to as a first gate metal layer, however, aspects of the present disclosure are not limited thereto. The third active layer ACT3 of the third thin-film transistor TFT3 is arranged on the first buffer layer 503, 504. The third active layer ACT3 contains a channel region in which a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region; however, aspects of the present disclosure are not limited thereto. A second buffer layer 507, 508 is arranged on the first insulating intermediate layer 506. The second buffer layer can be in the form of a single-layer or a multi-layer stack, but aspects of the present disclosure are not limited to this. If the second buffer layer 507, 508 is in the form of a multi-layer stack, the second buffer layer comprises a second lower buffer layer 507 and a second upper buffer layer 508, but aspects of the present disclosure are not limited to this. A second gate isolation layer 509 and a second isolation intermediate layer 510 are arranged on the second buffer layer 507, 508. The second gate isolation layer 509 is arranged on the first active layer ACT1 of the first thin-film transistor TFT1 and the second active layer ACT2 of the second thin-film transistor TFT2. The first gate electrode G1 of the first thin-film transistor TFT1 and the second gate electrode G2 of the second thin-film transistor TFT2 are arranged on the second gate isolation layer 509, but aspects of the present disclosure are not limited thereto. The second insulating layer 510 is arranged on the first gate electrode G1 of the first thin-film transistor TFT1 and the second gate electrode G2 of the second thin-film transistor TFT2. The first gate electrode G1 of the first thin-film transistor TFT1 and the second gate electrode G2 of the second thin-film transistor TFT2 can be referred to as a second gate metal layer, however, aspects of the present disclosure are not limited to this. The first source electrode E1a and the first drain electrode E1b of the first thin-film transistor TFT1 are connected to the source junction area and the drain junction area of ​​the first active layer ACT1, respectively, by holes in the second intermediate insulation layer 510 and the second gate insulation layer 509. The second source electrode E2a and the second drain electrode E2b of the second thin-film transistor TFT2 are connected to the source junction area and the drain junction area of ​​the second active layer ACT2, respectively, by holes in the second intermediate insulation layer 510 and the second gate insulation layer 509. The third source electrode E3a and the third drain electrode E3b of the third thin-film transistor TFT3 are connected to the source junction area and the drain junction area of ​​the third active layer ACT3, respectively, by holes in the second insulating layer 510, the second gate insulating layer 509, the second buffer layer 507, 508, the first insulating layer 506 and the first gate insulating layer 505, however, aspects of the present disclosure are not limited thereto. The first source electrode E1a and the first drain electrode E1b of the first thin-film transistor TFT1, the second source electrode E2a and the second drain electrode E2b of the second thin-film transistor TFT2, and the third source electrode E3a and the third drain electrode E3b of the third thin-film transistor TFT3 contain a first source / drain metal and are arranged in a first source / drain metal layer. The storage capacitor Cst is formed by a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. In one or more aspects, the storage capacitor Cst is formed by three or more capacitor electrodes. The storage capacitor Cst can also be in the form of two or more capacitors connected in parallel. For example, each of the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 is arranged on different metal layers arranged in the display panel 110, but aspects of the present disclosure are not limited thereto. The first capacitor electrode CAPE1 contains the same first gate metal as the third gate electrode G3 of the third thin-film transistor TFT3, which is arranged on the first gate insulating layer 505, and is located in the first gate metal layer; however, aspects of the present disclosure are not limited thereto. The second capacitor electrode CAPE2 is located on the first insulating intermediate layer 506; however, aspects of the present disclosure are not limited thereto. The transistor portion further comprises a first shielding pattern BSM1, which is arranged on the substrate 111. The first shielding pattern BSM1 overlaps with the first active layer ACT1 of the first thin-film transistor TFT1. The first shielding pattern BSM1 is arranged beneath the first active layer ACT1 of the first thin-film transistor TFT1. The first shielding pattern BSM1 is arranged in a metal layer between the first insulating intermediate layer 506 and the second buffer layer 507, 508, or is arranged between the second lower buffer layer 507 and the second upper buffer layer 508. However, aspects of the present disclosure are not limited to these. The transistor portion further includes a second shielding pattern BSM2, which is arranged on substrate 111. The second shielding pattern BSM2 overlaps with the second active layer ACT2 of the second thin-film transistor TFT2. The second shielding pattern BSM2 is arranged beneath the second active layer ACT2 of the second thin-film transistor TFT2. The second shielding pattern BSM2 is arranged in a metal layer between the first gate insulating layer 505 and the first insulating intermediate layer 506. The second shielding pattern BSM2 is arranged in the same metal layer as the first capacitor CAPE1, but aspects of this disclosure are not limited thereto. The second shielding pattern BSM2 is arranged in the same first gate metal layer as the third gate electrode G3 of the third thin-film transistor TFT3, but aspects of this disclosure are not limited thereto. The transistor portion further includes a third shielding pattern BSM3, which is arranged on the substrate 111. The third shielding pattern BSM3 overlaps with the third active layer ACT3 of the third thin-film transistor TFT3. The third shielding pattern BSM3 is arranged beneath the third active layer ACT3 of the third thin-film transistor TFT3. The third shielding pattern BSM3 is arranged between the substrate 111 and the first buffer layer 503, 504, or between the first lower buffer layer 503 and the first upper buffer layer 504. However, aspects of the present disclosure are not limited to these. A planarization layer 520 is arranged on the first thin-film transistor TFT1, the second thin-film transistor TFT2, and the third thin-film transistor TFT3, and is located beneath the first light-emitting element ED1. The planarization layer 520 can be an organic insulating layer containing an organic insulating material; however, aspects of the present disclosure are not limited to this. Planarization layer 520 is in the form of a single layer. Planarization layer 520 contains two layers. Planarization layer 520 contains three or more layers; however, aspects of the present disclosure are not limited to these. The planarization layer 520, which contains three or more layers, includes a lower planarization layer 521, an intermediate planarization layer 522, and an upper planarization layer 523 in a sequential layer stack; however, aspects of the present disclosure are not limited thereto. For the sake of simplicity, the planarization layer 520 may be expressed as a first planarization layer 520 in the following description; however, aspects of the present disclosure are not limited thereto. The lower planarization layer 521 is arranged on the first source electrode E1a and the first drain electrode E1b of the first thin-film transistor TFT1, the second source electrode E2a and the second drain electrode E2b of the second thin-film transistor TFT2, and the third source electrode E3a and the third drain electrode E3b of the third thin-film transistor TFT3. The lower planarization layer 521 is arranged such that it covers all aspects of the first thin-film transistor TFT1, the second thin-film transistor TFT2, and the third thin-film transistor TFT3; however, aspects of this disclosure are not limited thereto. A first interconnecting electrode RE1 is arranged on the lower planarization layer 521. The first interconnecting electrode RE1 electrically connects the first source electrode E1a of the first thin-film transistor TFT1 and the first pixel electrode PE1 of the first light-emitting element ED1, however, aspects of the present disclosure are not limited thereto. The light-emitting element component contains the first light-emitting element ED1, which is located on the upper planarization layer 523. The first light-emitting element ED1 can also generally be formed on the first planarization layer 520. The first light-emitting element ED1 comprises a first pixel electrode PE1, a first intermediate layer EL1, and a common electrode CE1. A light-emitting area of ​​the first light-emitting element ED1 is formed by an area in which the first pixel electrode PE1, the first intermediate layer EL1, and the common electrode CE1 overlap and touch each other. The first pixel electrode PE1 is arranged on the upper planarization layer 523. The first pixel electrode PE1 is arranged on the first planarization layer 520. The first pixel electrode PE1 is electrically connected to the first connecting electrode RE1 through holes in the intermediate planarization layer 522 and the upper planarization layer 523; however, aspects of the present disclosure are not limited thereto. The first planarization layer 520 contains an opening H2. In embodiments where the first planarization layer 520 is a multilayer structure, the opening H2 can specifically be located in and through a section of the upper planarization layer 523. The first planarization layer 520 further contains a black bank 530 arranged in the opening H2. The black bank 530 exposes a section of the first pixel electrode PE1 to form a light-emitting area. The black bank 530 overlaps with a section of the first pixel electrode PE1. The black bank 530 contains a material that includes a black pigment, or an organic material that includes a benzocyclobutene resin, a polyimide resin, an acrylic resin, a photosensitive polymer, or the like. However, aspects of the present disclosure are not limited to this. The black bank 530 contains a material that includes a black pigment or a black dye, or the like. If the black bank 530 contains a material that includes a black pigment or a black dye, the luminance of the display device 100 can be further improved because light from the outside or reflected light from the outside can be blocked. However, aspects of the present disclosure are not limited to this. The black bank 530 includes, but is not limited to, a first black bank 531 and a second black bank 532. The first black bank 531 is located in the opening H2 of the first planarization layer 520 and has a groove 531-G that extends downwards from the upper surface of the first black bank 531, but aspects of the present disclosure are not limited to this. More precisely, the opening H2 through the upper planarization layer 523 has sloping sides, such that the first black back surface 531 has similarly sloping sides. The first black bank 531 includes an upper surface 531-U, which can be an upper or a top surface of the first black bank 531. The first black bank overlaps and is in direct contact with the upper planarization layer 523 on opposite sides of the opening H2.The groove 531-G in the upper surface 531-U of the first black bank 531 is in the form of a downwardly convex depression in the upper surface 531-U such that the first black bank 531 has a concave shape at the location of the groove 531-G. Thus, the upper surface 531-U of the first black bank 531 has a curved surface corresponding to the location of the groove 531-G. The ends of the curve in the upper surface 531-U may be aligned with or overlap the inclined side surfaces of the upper planarization layer 523. For example, an interface where the curved section of the upper surface 531-U meets a flat and a planar section of the upper surface 531-U (i.e., a location where the curved surface terminates) may be aligned with the lower end faces of the inclined side surfaces of the upper planarization layer 523. The second black bank 532 is located on the first planarization layer 520, and specifically directly on the upper planarization layer 523, wherein the planarization layer 520 is a multilayer structure. The second black bank 532 further contains a hole 532_H, but aspects of the present disclosure are not limited to this. The second black bank 532 overlaps and is in direct contact with at least one section of the first pixel electrode PE1 and a first connection pattern CP1, which are further described below. The second black bank 532 is spaced from the first black bank 531 by the first light-emitting element ED1, or the first light-emitting element ED1 is located between the black banks 531 and 532. For example, a non-black bank 540 is arranged on the first pixel electrode PE1 and the black bank 530, and in some embodiments is in direct contact with such features in a multilayer stack. The non-black bank 540 is a transparent bank in some embodiments, but aspects of the present disclosure are not limited to this. The non-black bank 540 overlaps the opening H2 of the first planarization layer 520 and fills the groove 531-G in the first black bank 531. The non-black bank 540 can be arranged on and in direct contact with the first intermediate layer EL1 of the first light-emitting element ED1. The non-black bank 540 includes a first groove TRC1 that corresponds to the groove 531-G of the first black bank 531, although aspects of the present disclosure are not limited thereto. In some embodiments, the first groove TRC1 is aligned with and corresponds to the groove 531-G of the first black bank 531. The first groove TRC1 provides the advantage in the indicator device 100 of reducing errors due to leakage current. In one embodiment, a spacer 533 is arranged on the non-black bank 540. The spacer 531 overlaps with the second black bank 532, but aspects of the present disclosure are not limited thereto. In another embodiment, the spacer 533 is positioned in direct contact with a top surface or upper surface of the non-black bank 540 above the second black bank 532, such that the spacer 533 is located between the first intermediate layer EL1 and the non-black bank 540 on the second black bank 532. The first intermediate layer EL1 of the first light-emitting element ED1 is arranged on a section of the first pixel electrode PE1 and the non-black bank 540, and the common electrode CE1 is arranged on the first intermediate layer EL1. However, aspects of the present disclosure are not limited thereto. In one or more aspects, the display panel 110 further comprises a common voltage line to which a common voltage is applied, and further comprises the first connection pattern CP1 for electrically connecting the common voltage line and the common electrode CE1. The first connection pattern CP1 overlaps with the hole 532_H of the second black bank 532 and is located on the first planarization layer 520 in the hole 532_H. Furthermore, in some embodiments, the first connection pattern CP1 comprises the same material as the first pixel electrode PE1. However, aspects of the present disclosure are not limited thereto. The encapsulation part is arranged on the light-emitting element portion and is located on the common electrode CE1. The encapsulation part contains an encapsulation layer 200, which is arranged on the common electrode CE1. The encapsulation layer 200 can prevent moisture or oxygen from penetrating the first light-emitting element ED1. The encapsulation layer 200 can prevent moisture or oxygen from penetrating an organic material contained in the first intermediate layer EL1 of the first light-emitting element ED1. The encapsulation layer 200 can be in the form of a single layer or comprise multiple layers; however, aspects of the present disclosure are not limited to this. The encapsulation layer 200 comprises a first encapsulation layer 550, a second encapsulation layer 551, and a third encapsulation layer 552; however, aspects of the present disclosure are not limited thereto. The first encapsulation layer 550 and the third encapsulation layer 552 comprise an inorganic encapsulation layer, and the second encapsulation layer 551 comprises an organic encapsulation layer; however, aspects of the present disclosure are not limited thereto. In one or more aspects, a touch sensor is embedded in the display panel 110. In this configuration, the display panel 110 includes a touch sensor layer 560, which is arranged on the encapsulation layer 200 and contains the touch sensor. The touch sensor layer 560 contains several touch electrodes that serve as the touch sensor and includes at least one touch metal layer for forming the multiple touch electrodes. For example, to form the multiple touch electrodes, the touch sensor layer 560 includes a first touch metal layer 561 in which at least one first touch metal TM1 is arranged, and a second touch metal layer 564 in which at least one second touch metal TM2 is arranged. In this implementation, the touch sensor layer 560 further includes a touch buffer layer 562 and a touch intermediate insulating layer 563, which are arranged between the first touch metal layer 561 and the second touch metal layer 564; however, aspects of the present disclosure are not limited thereto. For example, if the first contact metal layer 561 is a bridge metal layer and the second contact metal layer 564 is a sensor metal layer, then the second contact metals TM2, which serve as the contact sensor, are electrically connected by at least one first contact metal TM1, which is the bridge metal. The second contact metals TM2 are electrically connected to the at least one first contact metal TM1 to form a contact electrode TE. In one or more aspects, the display panel 110 further comprises a black matrix 570, which has at least one first opening 570_H1 on the touch sensor layer 560. At least one of the first touch metal TM1 and the second touch metal TM2 overlaps with the black matrix 570, but aspects of the present disclosure are not limited thereto. In one or more aspects, the display panel 110 further comprises a first color filter CF1, which is arranged on the black matrix 570 and overlaps with the first aperture 570_H1. The display panel 110 also comprises a top layer 580, which is arranged on the first color filter CF1. Unless the context otherwise requires, the layer stack of the display panel 110, illustrated in Figures 5 to 8, represents the actual layers of the stack such that different layers are arranged sequentially and / or in direct contact with one another, as shown in the accompanying drawings, even if not explicitly described herein. In scoreboards, a situation can arise where light emitted by the light-emitting element reaches the encapsulation layer and is totally reflected back into the scoreboard. The reflected light may then be absorbed by the black bank or flow into the transistor section instead of exiting the scoreboard as intended. This is illustrated in Fig. 5 by dashed arrows 534, which represent light reflected back into the scoreboard through the encapsulation section instead of exiting it. As a result, the light extraction efficiency may be reduced. Unless otherwise noted, the term "light extraction" means light generated by a light-emitting element that is extracted, directed, or caused to exit the scoreboard.Thus, the term "light extraction efficiency" refers to the percentage or amount of light that exits the scoreboard in relation to the total amount of light produced by the light-emitting element. A light extraction efficiency of 90% therefore means that 90% of the total light emitted by the light-emitting element exits the scoreboard, while the remaining 10% is reflected back into the scoreboard and / or absorbed within it. The concepts of the disclosure address this problem by providing a structure of the display panel 110 that can increase such a light extraction efficiency by causing light that is absorbed by the black bank 530 or flows into the interior of the transistor part to be extracted outside the display panel 110 or to be otherwise enabled to escape from the display panel 110, as further described in the following embodiments. With reference to Fig. 6 and with further reference to Fig. 5, in one or more exemplary embodiments the display panel 110 further comprises a second planarization layer 600 containing a first hole H1, such that the second planarization layer 600 has an inner surface surrounding the first hole H1 and is a first inclined surface S1. For the sake of brevity, the discussion of features of the display panel 110 of Fig. 6 that are the same, substantially the same, or similar to the features described with reference to Fig. 5 is omitted. The first pixel electrode PE1 of the first light-emitting element ED1 is arranged on the first planarization layer 520 in the first hole H1 and extends along the first inclined surface S1 to an upper surface of the second planarization layer 600. However, aspects of the present disclosure are not limited to this. The non-black bank 540 is arranged on the first pixel electrode PE1 and the second planarization layer 600. The non-black bank 540 is a transparent bank, however, aspects of the present disclosure are not limited to it. The non-black bank 540 contains a first trench TRC1 on one side, however, aspects of the present disclosure are not limited to it. The first trench TRC1 provides the benefit of reducing a fault due to a leakage current. The non-black bank 540 may also contain the spacer 533 on its other side, however, aspects of the present disclosure are not limited to this. The first intermediate layer EL1 of the first light-emitting element ED1 is arranged on a section of the first pixel electrode PE1 and the non-black bank 540, and the common electrode CE1 is arranged on the first intermediate layer EL1. However, aspects of the present disclosure are not limited thereto. In one or more aspects, the display panel 110 further comprises a common voltage line to which a common voltage is applied, and a first connection pattern CP1 for electrically connecting the common voltage line and the common electrode CE1. The first connection pattern CP1 is arranged on the second planarization layer 600 and comprises the same material as the first pixel electrode PE1, however, aspects of the present disclosure are not limited thereto. The second planarization layer 600 is positioned on and in direct contact with the upper planarization layer 523 and / or the first planarization layer 520. The first light-emitting element ED1 is formed in the hole H1 in the second planarization layer 600. Furthermore, the display panel 110 of Fig. 6 can omit the black bank 530 (i.e., the first and second black banks 531, 532) and instead include the second planarization layer 600. In one embodiment, the display panel 110 of Fig. 6 does not include a black bank or any black banks. Accordingly, the trench TRC1 runs over a section of the second planarization layer 600 instead of over the first black bank 531. In some embodiments, the second planarization layer 600 can have a varying thickness above the second planarization layer 600.For example, the second planarization layer 600 contains a stepped configuration with a protrusion 601 that increases the thickness of the second planarization layer 600 in at least some faces of the second planarization layer 600 relative to other faces. The protrusion 601 is formed around the first hole H1 such that the second planarization layer 600 has a face of increased thickness around the first hole H1 relative to any other faces, areas, or sections of the second planarization layer 600. The protrusion 601 and the entire stepped configuration of the second planarization layer 600 at the location of the first hole H1 increase the length of the first inclined surface S1 to aid in the extraction of additional light, as described below. In the display panel 110 of Fig. 6, light emitted by the first light-emitting element ED1 is reflected at the first inclined surface S1 of the second planarization layer 600 and caused to exit the display panel 110, as indicated by the dashed arrow 535. This improves the light extraction efficiency of the display device 100. However, a situation can still occur in which the first light reaching the encapsulation layer 200 is totally reflected and then flows into the interior of the transistor part, as described above, and this situation can reduce the light extraction efficiency of the display panel 100. Thus, the display panel 110 of Fig. 6 is an improvement over previous solutions; however, the disclosure provides additional solutions to further improve the light extraction efficiency. With reference to Fig. 7 and with further reference to Figs. 5 and 6, in one or more exemplary embodiments, the display panel 110 includes the second planarization layer 600. The second planarization layer 600 includes the first hole H1, described above, which has an inner surface comprising a first inclined surface S1, and a second hole H3, which is distinct from the first hole H1. Repeated features of Fig. 7 in relation to the description above have been omitted for simplicity. The first pixel electrode PE1 of the first light-emitting element ED1 is arranged on the first planarization layer 520 in the first hole H1 and extends along the first inclined surface S1 to an upper surface of the second planarization layer 600. However, aspects of the present disclosure are not limited to this. A black bank 530 is arranged in the second hole H3 and on the second planarization layer 600, but aspects of the present disclosure are not limited thereto. The black bank 530 contains a first black bank 531 and a second black bank 532, but aspects of the present disclosure are not limited thereto. In the display panel 110 of Fig. 7, the second planarization layer 600 contains the second hole H3, instead of the first planarization layer 520 containing the second hole H2. The second hole H3 of Fig. 7 is otherwise similar to the second hole H2 and is not described further. The first black bank 531 is located in the second hole H2 and is otherwise similar to the first black bank 531 described above. The second black bank 532 is located on the second planarization layer 600 and contains a hole 532_H, however, aspects of the present disclosure are not limited to it. The non-black bank 540 is arranged on the first black bank 531, the second black bank 532, and the first pixel electrode PE1; however, aspects of the present disclosure are not limited thereto. The non-black bank 540 may be a transparent bank; however, aspects of the present disclosure are not limited thereto. The non-black bank 540 contains a first groove TRC1, which overlaps with the second hole H3 and corresponds to the groove of the first black bank 531. The first groove TRC1 provides the advantage of reducing faults due to leakage current. A spacer 533 is arranged on the non-black bank 540. The spacer 533 overlaps with the second black bank 532, however, aspects of the present disclosure are not limited to this. The first intermediate layer EL1 of the first light-emitting element ED1 is arranged on a section of the first pixel electrode PE1 and the non-black bank 540, and the common electrode CE1 is arranged on the first intermediate layer EL1. However, aspects of the present disclosure are not limited thereto. As described above with reference to Fig. 6, light emitted by the first light-emitting element ED1 can be reflected at the first inclined surface S1 and caused to exit the display panel 110, thereby improving the light extraction efficiency. However, the display panel 110 of Fig. 7 includes the black bank 530 such that, instead of light entering the transistor section as described in Fig. 6, light reaching and being reflected by the encapsulation layer 200 is absorbed by the black bank 530, thus preventing optimization of the light extraction efficiency. Furthermore, the viewing angle characteristic may be reduced due to external light entering the display panel 110. Accordingly, Fig. 7 also provides a solution for improving the light extraction efficiency in an embodiment of the display panel 110 that includes the black bank 530. The present disclosure further provides embodiments of the display panel 110 wherein light absorbed by the black bank 530 or reaching the interior of the transistor section can be extracted outside the display panel 110, thereby increasing the light extraction efficiency of the display panel 110 and implementing an improved viewing angle characteristic. In other words, the following embodiments further optimize the light extraction efficiency while also improving viewing angle characteristics beyond the solutions described with reference to Figures 6 and 7. With reference to Fig. 8 and further reference to Figs. 5-7, in one or more exemplary embodiments, the second planarization layer 600 of the display panel 110 includes the first hole H1, which has an inner surface comprising a first inclined surface S1 and a second inclined surface S2, and the second hole H3, which is different from the first hole H1. Repeated features of Fig. 8 in relation to the description above have been omitted for the sake of simplicity. The second planarization layer 600 of Fig. 8 has a different structure and arrangement than the other planarization layers described here. The second planarization layer 600 includes the projection 601, which increases the thickness of a section of the second planarization layer 600 in a stepped configuration. However, the projection 601 is spaced from the first hole H1, instead of being located at the first hole H1 as described elsewhere. Thus, while the projection 601 still surrounds the first hole H1, it defines a first projection 602 and a second projection 603. The first projection 602 is a flat, planar surface of the second planarization layer 600 located between the projection 601 and the first hole H1. The second projection 603 corresponds to a top surface of the projection 601.Such an arrangement generates the first and second inclined surfaces S1, S2 of the second planarization layer 600, which define the first hole H1. The sidewalls of the second planarization layer 600 forming the first hole H1 therefore have a two-stage configuration, and the width of the first hole H1 varies across its length. Specifically, as a result of the projection 601 being spaced or offset from an interface between the first hole H1 and the second planarization layer 600 at the first light-emitting element ED1, a lower or bottom portion of the first hole H1 adjacent to the first light-emitting element ED1 has a width that is smaller than the width of the first hole H1 across the first projection 602.In other words, in one embodiment, the projection 601 has a trapezoidal cross-section that is offset from an edge of the second planarization layer 600, with a large part or principal portion of the first hole H1 passing through the second planarization layer 600 to create the two-stage configuration shown in Fig. 8. The benefits of the first and second inclined surfaces S1, S2 are further described below. The first pixel electrode PE1 of the first light-emitting element ED1 is arranged on the first planarization layer 520 in the first hole H1 and extends along the first inclined surface S1 and the second inclined surface S2 to an upper surface 600-U of the second planarization layer 600. However, aspects of the present disclosure are not limited to this. A first angle θ1 is formed by the first inclined surface S1 and a rear, bottom, or back surface 600-B of the second planarization layer 600, but aspects of this disclosure are not limited thereto. Furthermore, a second angle θ2 is formed by the second inclined surface S2 and the rear, bottom, or back surface 600-B of the second planarization layer 600, but aspects of this disclosure are not limited thereto. The first angle θ1 is preferably smaller than the second angle θ2 to provide the benefits described herein, but aspects of this disclosure are not limited thereto. In general, the angles θ1 and θ2 can be chosen to be equal or different from each other, such as the first angle θ1 being larger than the second angle θ2. A black bank 530 is located in the second hole H3 and on the second planarization layer 600, however, aspects of the present disclosure are not limited thereto. The black bank 530 includes, but is not limited to, a first black bank 531, a second black bank 532, and a third black bank 800. The first black bank 531 is located in the second hole H3 and has the groove that extends downwards from the upper surface of the first black bank 531, as described elsewhere. The second black bank 532 is arranged on the second planarization layer 600 and contains a hole 532_H corresponding to the first connection pattern CP1, but aspects of the present disclosure are not limited thereto. The third black bank 800 is located between the first inclined surface S1 and the second inclined surface S2, but aspects of the present disclosure are not limited thereto. Specifically, the third black bank 800 is located on the first projection 602 between the projection 601 and the first light-emitting element ED1, which is located in the first hole H1.Accordingly, the first projection 602 and the arrangement of the projection 601 also provide a flat support surface and / or a space for forming the third black bank 800, which provides the benefits described here. A non-black bank 540 may be located on the first black bank 531, the second black bank 532, the third black bank 800, and the first pixel electrode PE1; however, aspects of the present disclosure are not limited to these. The non-black bank 540 may be a transparent bank; however, aspects of the present disclosure are not limited to this. The non-black bank 540 contains a first trench TRC1 that overlaps with the second hole H3 and corresponds to the groove that is recessed from the upper surface of the first black bank 531; however, aspects of the present disclosure are not limited thereto. The first trench TRC1 provides the advantage of reducing a fault due to leakage current. A spacer 533 is arranged on the non-black bank 540. The spacer 533 overlaps with the second black bank 532, however, aspects of the present disclosure are not limited to this. The first intermediate layer EL1 of the first light-emitting element ED1 is arranged on a section of the first pixel electrode PE1 and the non-black bank 540, and the common electrode CE1 is arranged on the first intermediate layer EL1. However, aspects of the present disclosure are not limited thereto. In the configuration of the display panel 110 according to Fig. 8, light emitted by the first light-emitting element ED1 is reflected at the first inclined surface S1 and caused to exit the display panel 110, thereby improving the light extraction efficiency of the display panel 110, similar to the display panels 110 of Fig. 6 and Fig. 7 described above and as shown by arrow 535 in Fig. 8. Light emitted by the first light-emitting element ED1 can be totally reflected by a common electrode CE1, and specifically by the rear surface of the common electrode CE1. In such a situation, the light can be reflected at the first and / or the second inclined surface S1, S2 and caused to exit the display panel 110, as indicated by arrow 536. This can improve the light extraction efficiency of the display panel 110. Additionally, external light entering the display panel 110 can be absorbed by the third black bank 800. Alternatively, in a situation where external light entering the display panel 110 is reflected by the third black bank 800, the light can be absorbed by a black matrix 570. The absorption and / or reflection of light by the third black bank 800 is schematically represented by arrow 537 in Fig. 8. This can improve the reflection sensitivity and increase the viewing angle of the display panel 110.Accordingly, the offset of the projection 601 of the second planarization layer 600 from the first hole H1 forms the first projection 602, which enables the formation of an additional black bank, and two inclined surfaces to provide significant improvements in light extraction efficiency, reflection sensitivity and viewing angle characteristics. Fig. 9 is an example cross-sectional view of the display panel 110, taken along line AC of Fig. 4, according to aspects of the present disclosure. The concepts shown in Fig. 9 are discussed with continued reference to Figs. 5, 6, 7 to 8, and a repeated description is omitted. With reference to Fig. 8 and Fig. 9, in one or more exemplary embodiments the display panel 110 comprises a substrate 111, a planarization layer, a portion of light-emitting elements and an encapsulation part, but aspects of the present disclosure are not limited thereto. Substrate 111 is in the form of a single-layer or a multi-layer stack. In an example where substrate 111 contains a multi-layer stack, it comprises a first substrate 500, an intermediate substrate layer 501, and a second substrate 502. The intermediate substrate layer 501 can be located between the first substrate 500 and the second substrate 502. The planarization layer contains a first planarization layer 520 and a second planarization layer 600. The first planarization layer 520 contains, but is not limited to, a lower planarization layer 521, an intermediate planarization layer 522, and an upper planarization layer 523. The second planarization layer 600 can be similar to any of the second planarization layers 600 described here. In one or more aspects, insulating layers contained in the transistor part are arranged between the substrate 111 and the first planarization layer 520, however, aspects of the present disclosure are not limited to this. The portion of light-emitting elements comprises a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3, arranged on the first planarization layer 520. However, aspects of the present disclosure are not limited thereto. At least one of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 can emit light of a color different from that of the one or more remaining light-emitting elements; however, aspects of the present disclosure are not limited thereto. The first light-emitting element ED1 comprises a first pixel electrode PE1, a first intermediate layer EL1, and a common electrode CE1. A light-emitting surface of the first light-emitting element ED1 is formed by a surface in which the first pixel electrode PE1, the first intermediate layer EL1, and the common electrode CE1 overlap and touch each other; however, aspects of the present disclosure are not limited thereto. The second light-emitting element ED2 comprises a second pixel electrode PE2, a second intermediate layer EL2, and a common electrode CE2. A light-emitting surface of the second light-emitting element ED2 is formed by a surface in which the second pixel electrode PE2, the second intermediate layer EL2, and the common electrode CE2 overlap and touch each other; however, aspects of the present disclosure are not limited thereto. The third light-emitting element ED3 comprises a third pixel electrode PE3, a third intermediate layer EL3, and a common electrode CE3. A light-emitting surface of the third light-emitting element ED3 is formed by a surface in which the third pixel electrode PE3, the third intermediate layer EL3, and the common electrode CE3 overlap and touch each other; however, aspects of the present disclosure are not limited thereto. The first light-emitting element ED1 can emit a first light, but is not limited to this. The second light-emitting element ED2 can emit a second light that is different from the first light, but is not limited to this. The third light-emitting element ED2 can emit a third light that is different from the first and second lights, but is not limited to this. A first connecting electrode RE1 is arranged on the lower planarization layer 521. Although not shown in Fig. 9, in Figs. 5, 6, 7 to 8, the first connecting electrode RE1 electrically connects a first source electrode E1a of a first thin-film transistor TFT1 of the transistor part and the first pixel electrode PE1 of the first light-emitting element ED1; however, aspects of the present disclosure are not limited to this. The first pixel electrode PE1 can be electrically connected to the first connecting electrode RE1 through a hole in the intermediate planarization layer 522 and the upper planarization layer 523; however, aspects of the present disclosure are not limited to this. A second connecting electrode RE2 is arranged on the lower planarization layer 521. Although not shown in Fig. 9, the second connecting electrode RE2 electrically connects a source electrode of a thin-film transistor of the transistor part and the second pixel electrode PE2 of the second light-emitting element ED2; however, aspects of the present disclosure are not limited to this. The second pixel electrode PE2 is electrically connected to the second connecting electrode RE2 by holes in the intermediate planarization layer 522 and the upper planarization layer 523; however, aspects of the present disclosure are not limited to this. A third connecting electrode RE3 is arranged on the lower planarization layer 521. Although not shown in Fig. 9, the third connecting electrode RE3 electrically connects a source electrode of a thin-film transistor of the transistor part and the third pixel electrode PE3 of the third light-emitting element ED3; however, aspects of the present disclosure are not limited to this. The third pixel electrode PE3 is electrically connected to the third connecting electrode RE3 by holes in the intermediate planarization layer 522 and the upper planarization layer 523; however, aspects of the present disclosure are not limited to this. A black bank 530 is arranged on the second planarization layer 600, but aspects of the present disclosure are not limited to it. The black bank 530 contains a first black bank 531, a second black bank 532, and a third black bank 800, but is not limited to it. The encapsulation component is located on the light-emitting element component and is situated on the common electrode (CE1, CE2, and CE3). The encapsulation component contains an encapsulation layer 200, which is also located on the common electrode (CE1, CE2, and CE3). The encapsulation layer 200 prevents moisture or oxygen from penetrating the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3. The encapsulation layer 200 also prevents moisture or oxygen from penetrating any organic substance contained within the first intermediate layer EL1, the second intermediate layer EL2, and the third intermediate layer EL3 of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3.The encapsulation layer 200 can be in the form of a single layer or can contain several layers, however, aspects of the present disclosure are not limited thereto. In one or more aspects, a touch sensor layer 560 is arranged on the encapsulation layer 200 and contains a touch sensor. The touch sensor layer 560 contains several touch electrodes that serve as the touch sensor and includes at least one touch metal layer for forming the multiple touch electrodes. For example, to form the multiple touch electrodes, the touch sensor layer 560 includes a first touch metal layer 561 in which at least one first touch metal TM1 is arranged, and a second touch metal layer 564 in which at least one second touch metal TM2 is arranged. In this implementation, the touch sensor layer 560 may further include a touch buffer layer 562 and a touch intermediate insulating layer 563 arranged between the first touch metal layer 561 and the second touch metal layer 564, but aspects of the present disclosure are not limited thereto. In one or more aspects, a black matrix 570, having a first opening 570_H1, a second opening 570_H2, and a third opening 570_H3, is arranged on the touch sensor layer 560. At least one of the first touch metal TM1 and the second touch metal TM2 may overlap with the black matrix 570, but aspects of the present disclosure are not limited to this. In one or more aspects, color filters, comprising a first color filter CF1 overlapping the first aperture 570_H1, a second color filter CF2 overlapping the second aperture 570_H2, and a third color filter CF3 overlapping the third aperture 570_H3, are arranged on the black matrix 570, and a cover layer 580 is arranged on the color filters. The display panel 110 of Fig. 9 similarly includes the projection 601 of the second planarization layer 600, which is spaced from the edge of the second planarization layer 600 at the interface with the first hole H1, thus forming the first and second inclined surfaces S1, S2 shown in Fig. 8. Referring to Fig. 8 and Fig. 9, first light emitted by the first light-emitting element ED1 can be reflected at the first inclined surface S1 and caused to exit the display panel 110, thereby improving the light extraction efficiency of the display panel 110. Referring to Fig. 9, for example, external light entering the display panel 110 can be absorbed by the third black bank 800. In another example, if external light entering the display panel 110 is reflected by the third black bank 800, the light can be absorbed by the black matrix 570. This improves the reflection sensitivity and allows the viewing angle characteristic to be implemented. Referring to Fig. 9, in a situation where third light emitted by the third light-emitting element ED3 is totally reflected by a rear surface of the common electrode CE3, the third light can be reflected at the first and / or the second inclined surfaces S1, S2 and caused to exit the display panel 110, thereby improving the light extraction efficiency of the display panel 110. Fig. 10 is a top view of an exemplary light-emitting surface of the display panel 110 according to aspects of the present disclosure. Referring to Fig. 10, when a subpixel of the display panel is viewed from a top view, the third black bank 800 is arranged in a shape that surrounds at least one subpixel having multiple light-emitting surfaces. However, aspects of the present disclosure are not limited to this. The third black bank 800 is located within the first hole H1 on the first projection 602, which is shown in Fig. 8 and is arranged in the second planarization layer 600, and is arranged in a shape that surrounds an inner surface of the first hole H1. However, aspects of the present disclosure are not limited thereto. In another example, the third black bank 800 is located between the first inclined surface S1 and the second inclined surface S2 of Fig. 8, but aspects of the present disclosure are not limited thereto. For example, at least two light-emitting surfaces and one non-light-emitting surface NEA are arranged inside the third black bank 800, but aspects of the present disclosure are not limited thereto. The at least two light-emitting surfaces arranged inside the third black bank 800 correspond to a main light-emitting surface MEA and a surface corresponding to the first inclined surface S1, which serves as a light-reflecting surface, respectively, but aspects of the present disclosure are not limited thereto. In other words, one of the light-emitting surfaces is the main light-emitting surface MEA, which corresponds to the light-emitting element, and a second of the light-emitting surfaces, among other possible ones, is a light-reflecting surface corresponding to light reflected from the first inclined surface S1.The light reflected from the first inclined surface S1 is designed as a supplementary emitting surface SEA, with the supplementary surface inside the third black bank 800 being designated as SEA-I. The main light-emitting area MEA and the non-light-emitting area NEA overlap with at least one of the first aperture 570_H1, the second aperture 570_H2 and the third aperture 570_H3 of the black matrix 570 of Fig. 9, however, aspects of the present disclosure are not limited thereto. The main light-emitting area MEA can represent an area in which the first pixel electrode PE1, the first intermediate layer EL1, and the common electrode CE1 of the first light-emitting element ED1 overlap in the first hole H1 of Fig. 8; however, aspects of the present disclosure are not limited to this. The light-emitting area corresponding to the first inclined surface S1 can be formed by an area in which first light emitted by the first light-emitting element ED1 is reflected at the first inclined surface S1 of Fig. 8 and then caused to exit the display panel 110; however, aspects of the present disclosure are not limited to this. The one non-light-emitting area NEA contains a section of an area in which the first pixel electrode PE1 overlaps with the first planarization layer 520 except for the main light-emitting area MEA in the first hole H1 of Fig. 8, however, aspects of the present disclosure are not limited thereto. For example, at least one light-reflecting surface can be formed outside the third black bank 800. The at least one light-reflecting surface arranged outside the third black bank 800 can correspond to the second inclined surface S2 (i.e., light reflected from the second inclined surface S2) and be arranged in a shape surrounding the third black bank 800; however, aspects of the present disclosure are not limited to this. In another example, a light-emitting surface can be formed by a surface in which, while first light emitted by the first light-emitting element ED1 of Fig. 8 is totally internally reflected by the common electrode CE1, the first light is reflected from the rear surface of the common electrode CE1, and the reflected first light is again reflected at the second inclined surface S2 and caused to exit the display panel 110.However, aspects of the present disclosure are not limited to this. The light reflected from the second inclined surface S2 is generally shown to be an outer complementary emitting surface SEA-O outside the third black bank 800. A first side surface of the third black bank 800 is arranged such that it is spaced apart from the first black bank 531 by a first distance, and a second opposite side surface of the third black bank 800 is arranged such that it is spaced apart from the second black bank 532 by a second distance. However, aspects of the present disclosure are not limited thereto. A third light-reflecting surface is formed in respective areas located between the third black bank 800 and each of the first black bank 531 and the second black bank 532, spaced apart by the first distance and the second distance, respectively.Fig. 11 is a top view of an embodiment of several light-emitting surfaces of the display panel 110. The display panel 110 comprises a primary light-emitting surface 101 and a secondary light-emitting surface 103. The primary light-emitting surface 101 corresponds to light emitted through the hole 570_H1 by the first light-emitting element ED1. The secondary light-emitting surface 103 corresponds to light that is not absorbed by the black matrix 570, but rather passes through the black matrix 570, the first color filter CF1, and the top layer 580. In other words, the black matrix 570 does not need to completely absorb the light emitted by the first light-emitting element ED1, and at least a portion of the light emitted by the first light-emitting element ED1 will pass through the black matrix 570 to form a secondary light-emitting surface 103.The primary light-emitting surface 101 is larger than the secondary light-emitting surface 103. In some embodiments, the light emitted by the secondary light-emitting surface 103 is similar to the light emitted by the primary light-emitting surface 101. For example, the color of the light emitted by the secondary light-emitting surface 103 is the same as the color of the light emitted by the primary light-emitting surface 101. A color coordinate of visible light emitted by the primary light-emitting surface 101 may be the same or different from a color coordinate of the light emitted by the secondary light-emitting surface 103. Furthermore, due to the difference in size between the emitting surfaces 101 and 103, the amount of light emitted by each surface may differ. As shown in Fig. 11, the main light-emitting surface 101 is located centrally with respect to the secondary light-emitting surface 103 in the top view of the display panel 110. The secondary light-emitting surface 103 is concentric with respect to the main light-emitting surface 101. Furthermore, in some embodiments, the light-emitting surfaces 101 and 103 have a circular shape, but they can also be any other chosen shape, including, without limitation, rectangles and other shapes. The secondary light-emitting surface 103 is spaced apart from the main light-emitting surface 101 by an intermediate surface 105. The intermediate surface 105 can be a light-emitting surface or a non-light-emitting surface in various embodiments. For example, in the embodiments described above with respect to Fig. 10, the intermediate surface 105 is the non-emitting surface NEA. However, for the embodiments described above with respect to Fig.As described in section 5, the intermediate surface 105 is another light-emitting surface, such that the display panel 110 contains at least three light-emitting surfaces 101, 103, and 105. The intermediate surface 105 is concentric with the main light-emitting surface 101 and the secondary light-emitting surface 103 and is positioned between the main and secondary light-emitting surfaces 101 and 103. Thus, the main light-emitting surface 101, the intermediate surface 105, and the secondary light-emitting surface 103 are arranged sequentially and adjacent to each other. As shown in Fig. 11, the intermediate surface 105 separates the light-emitting main surface 101 from the light-emitting secondary surface 103. A width W1 of the intermediate surface 105 is preferably larger than a width W2 of the light-emitting secondary surface 103; however, this is not required, and the widths W1 and W2 can be equal, or the width W1 can be smaller than the width W2. The intermediate surface 105 extends from an outer boundary of the light-emitting main surface 101 to an inner boundary of the light-emitting secondary surface 103, corresponding to the width W1 shown in Fig. 11. The width W2 corresponds to the distance between an outer boundary of the light-emitting secondary surface 103 and the inner boundary of the light-emitting secondary surface 103. In embodiments where the width W1 is greater than the width W2, the width W1 can be greater than the width W2 by a factor ranging from 1% to 500% or more, including intermediate values.Thus, in some non-restrictive examples, the width W1 can be 7% or 127% of the width W2. In embodiments where the intermediate surface 105 emits light, the intermediate surface 105 can emit light with the same or different properties as the light-emitting primary and secondary surfaces 101, 103. For example, the color of light emitted by the intermediate surface 105 can be the same as that emitted by the primary and secondary surfaces 101, 103, but the light emitted by the intermediate surface 105 can have a different intensity or transmission, meaning that less light is emitted by the intermediate surface than by the primary and / or secondary surfaces 101, 103.The light emitted in the intermediate surface 105 originates from the first light-emitting element ED1, similar to the light-emitting main and secondary surfaces 101, 103, but has a different emission angle than the light emitted in the light-emitting main and secondary surfaces 101, 103, in order to provide the light emitted in the intermediate surface 105 with different properties. The examples, aspects and embodiments for the display device 100 and the display panel 110 described here can be described as follows. According to one aspect of the present disclosure, a display device can be provided comprising a substrate, a first planarization layer arranged on the substrate, a second planarization layer arranged on the first planarization layer and having a first hole that allows a first light-emitting element to be arranged, and an inner surface comprising a first inclined surface, a second inclined surface and a second hole different from the first hole, a first pixel electrode arranged on the first planarization layer in the first hole and extending along the first inclined surface and the second inclined surface to an upper surface of the second planarization layer, a first black bank located in the second hole, a second black bank located on the second planarization layer, a third black bank,which is located between the first inclined surface and the second inclined surface, a non-black bank located on the first black bank, the second black bank, the third black bank and the first pixel electrode, a first intermediate layer located on a section of the first pixel electrode and the non-black bank, and a common electrode located on the first intermediate layer. According to one aspect of the present disclosure, a display device comprises the following: a substrate having multiple layers; multiple TFT layers on the substrate; multiple planarization layers arranged on the TFT layers; a subpixel arranged on the multiple planarization layers and containing an anode, the subpixel being connected to the multiple TFT layers and having multiple light-emitting surfaces; and a black bank arranged on the multiple planarization layers and covering at least one section of the anode. According to one aspect of the present disclosure, a display device comprises the following: a substrate having multiple layers; multiple TFT layers on the substrate; multiple planarization layers arranged on the TFT layers; a subpixel arranged on the multiple planarization layers and connected to the multiple TFT layers, the subpixel having a light-emitting major surface, a light-emitting minor surface, and an intermediate surface between the light-emitting major surface and the light-emitting minor surface; and a black bank arranged on the multiple planarization layers. According to one aspect of the present disclosure, a display device comprises the following: a substrate; several thin-film transistors on the substrate; a planarization layer on the thin-film transistors; a subpixel having a light-emitting element arranged on the planarization layer, the light-emitting element comprising an anode connected to one of the several thin-film transistors, and the subpixel having several light-emitting surfaces; and a black bank arranged on the planarization layer covering at least one section of the anode. The display device according to one of these aspects may include one or more of the following features: The display device may further include an encapsulation layer arranged on the common electrode. The display device may further include a black matrix arranged on the encapsulation layer and having a first opening. The display device may further include a first color filter arranged on the black matrix and overlapping with the first opening. The display device may further comprise a first contact metal arranged on the encapsulation layer, a contact buffer layer arranged on the first contact metal, and a second contact metal arranged on the contact buffer layer and electrically connected to the first contact metal. At least one of the first contact metal and the second contact metal may overlap with the black matrix. A first angle can be defined by the first inclined surface and a back surface of the second planarization layer. A second angle can be defined by the second inclined surface and the back surface of the second planarization layer. The first angle can be smaller than the second angle. A non-black bank can be a transparent bank. The third black bank can be configured to absorb or reflect external light entering the display device. The second black bank may also contain at least one hole. The display device may further include a common voltage line to which a common voltage is applied. The display device may further include a first connection pattern that electrically connects the common electrode and the common voltage line. The first connection pattern may be arranged to overlap the hole of the second black bank. The first connection pattern may be arranged on the second planarization layer. The first connection pattern may contain or consist of the same material as the first pixel electrode. The first black bank may have a groove that extends downwards from an upper surface of the first black bank. The non-black bench may contain a first trench that overlaps with the second hole. The first trench may correspond to the groove. The display device may further include a spacer arranged on the non-black bank. The spacer may overlap with the second black bank. The first inclined surface can be configured to reflect a first light emitted by the first light-emitting element, causing the reflected first light to exit the display device. Since first light emitted by the first light-emitting element is totally reflected by the common electrode when the first light is reflected from a rear surface of the common electrode, the second inclined surface can be configured to reflect the first light and cause the reflected first light to exit the display device. According to one aspect, a display device can be provided comprising a substrate, a first planarization layer arranged on the substrate, a second planarization layer arranged on the first planarization layer and having a first hole that allows a first light-emitting element to be arranged, and an inner surface comprising a first inclined surface, a second inclined surface and a second hole different from the first hole, a first pixel electrode arranged on the first planarization layer in the first hole and extending along the first inclined surface and the second inclined surface to an upper surface of the second planarization layer, a bank arranged on the first pixel electrode and the second planarization layer, and a first intermediate layer arranged on a section of the first pixel electrode and the bank.and includes a common electrode located on the first intermediate layer. In one or more aspects, a first angle formed by the first inclined surface and the back surface of the second planarization layer may be smaller than a second angle formed by the second inclined surface and the back surface of the second planarization layer. The bank can contain a first black bank located in the second hole, a second black bank located on the second planarization layer, and a third black bank located between the first inclined surface and the second inclined surface. The bank can further contain a non-black bank arranged on top of the first black bank, the second black bank, the third black bank, and the first pixel electrode. The non-black bank can be a transparent bank. The display device may further include a common voltage line to which a common voltage is applied. The display device may further include a first connection pattern that electrically connects the common electrode and the common voltage line. The second black bank may further include at least one hole. The first connection pattern may be arranged to overlap with the hole of the second black bank. The first connection pattern may be arranged on the second planarization layer. The first connection pattern may be made of the same material as the first pixel electrode. The first black bank may have a groove that extends downwards from an upper surface of the first black bank. The non-black bank may contain a first trench that overlaps with the second hole and corresponds to the groove. The display device may further include an encapsulation layer arranged on the common electrode. The display device may further include a black matrix arranged on the encapsulation layer and having a first opening. The display device may further include a first color filter arranged on the black matrix and overlapping with the first opening. The display device may further comprise a first contact metal arranged on the encapsulation layer. The display device may further comprise a contact buffer layer arranged on the first contact metal. The display device may further comprise a second contact metal arranged on the contact buffer layer and electrically connected to the first contact metal. At least one of the first and second contact metals may overlap with the black matrix. According to one aspect of the present disclosure, a display device comprises the following: a substrate having multiple layers; multiple TFT layers on the substrate; multiple planarization layers arranged on the TFT layers; a subpixel arranged on the multiple planarization layers and containing an anode, the subpixel being connected to the multiple TFT layers and having multiple light-emitting surfaces; and a black bank arranged on the multiple planarization layers and covering at least one section of the anode. According to one aspect of the present disclosure, a display device comprises the following: a substrate having multiple layers; multiple TFT layers on the substrate; multiple planarization layers arranged on the TFT layers; a subpixel arranged on the multiple planarization layers and connected to the multiple TFT layers, the subpixel having a light-emitting major surface, a light-emitting minor surface, and an intermediate surface between the light-emitting major surface and the light-emitting minor surface; and a black bank arranged on the multiple planarization layers. According to one aspect of the present disclosure, a display device comprises the following: a substrate; several thin-film transistors on the substrate; a planarization layer on the thin-film transistors; a subpixel having a light-emitting element arranged on the planarization layer, the light-emitting element comprising an anode connected to one of the several thin-film transistors, and the subpixel having several light-emitting surfaces; and a black bank arranged on the planarization layer covering at least one section of the anode. The display device according to one of these aspects may include one or more of the following features: The substrate can have multiple layers. The planarization layer can be provided as multiple planarization layers. The black bank may have a hole corresponding to the anode. The black bank may expose at least one section of the anode, e.g., a section of the anode corresponding to one of the light-emitting surfaces. The substrate can have a display area and a non-display area. The non-display area can contain a contact area. The black bank can (also) be located in the contact area. The black bank can extend to an outer edge of the substrate in the non-display area. The contact surface may contain a source drain and the black bank may cover at least a section of the source drain. A dam can be arranged on the substrate in the non-display area. The dam can overlap with at least one anode, a first source drain, and a second source drain of the non-display area. The dam can contain multiple layers. One of these layers can be the black bank. The dam can be one of several dams that overlap with at least one of the anode, the first source drain, and the second source drain. The multiple light-emitting surfaces of the subpixel can contain at least one primary light-emitting surface, one intermediate surface, and one secondary light-emitting surface. The intermediate surface can be located between the primary light-emitting surface and the secondary light-emitting surface. The intermediate surface and the secondary light-emitting surface can be arranged concentrically around or with the primary light-emitting surface. The intermediate surface can be one of several light-emitting surfaces and / or can be configured to emit light. Alternatively, the intermediate surface can be a non-emitting surface, e.g., a surface configured not to emit light. The width of the intermediate surface can be greater than the width of the light-emitting secondary surface. Here, the width can refer to an extent parallel to a surface of the substrate or in a top view. The multiple light-emitting surfaces can be configured to emit the same color of light. The light-emitting element can be arranged on the substrate and / or on the planarization layer. The multiple light-emitting surfaces can be configured to emit light from the light-emitting element of the subpixel. An encapsulation layer can be arranged on top of the multiple planarization layers. A color filter (a color filter layer) can be arranged on the encapsulation layer. The display device may contain a black matrix. The black matrix may be positioned between the encapsulation layer and the color filter (color filter layer). The black matrix may have a hole corresponding to the light-emitting element. The color filter layer may be positioned within the hole. The hole in the black matrix can correspond to the main light-emitting surface of the multiple light-emitting surfaces. The intermediate surface and / or the secondary light-emitting surface can correspond to a location where the black matrix and the color filter layer overlap. The subpixel can contain an anode. The black bank can cover at least a section of the anode. The multiple TFT layers contain a first active layer and a second active layer. The thickness of the first active layer can be greater than the thickness of the second active layer. The first active layer can correspond to an LPTS transistor and / or the second active layer can correspond to an oxide transistor. The light-emitting element can contain several light-emitting layers arranged in a tandem structure. The planarization layer (or multiple planarization layers) may have a first inclined surface, a second inclined surface, and a projection between the first and second inclined surfaces. A hole may be provided above the planarization layer (or at least one of the multiple planarization layers) corresponding to the first and second inclined surfaces. A light-emitting element may be positioned on the substrate within the (first) hole. A bench may be provided on the projection between the first and second inclined surfaces. This means that a hole can be formed in the planarization layer or at least partially above the planarization layer. The hole can be defined by the first inclined surface and / or the second inclined surface. The first inclined surface can run from a bottom of the hole to the projection, and / or the second inclined surface can run from the projection to a top of the hole. The first inclined surface and the second inclined surface can be consecutive and point in a direction away from the substrate and perpendicular to the substrate. An angle between the first inclined surface and a back surface of the planarization layer (or a surface of the substrate) can be smaller than an angle between the second inclined surface and the back surface of the planarization layer (or a surface of the substrate). The second inclined surface can correspond to a projection of the planarization layer. The projection can be a section of the planarization layer with a greater thickness than other sections of the planarization layer. The first inclined surface can be a reflective surface. The first inclined surface can be configured to reflect light emitted by the light-emitting element and / or to cause a first reflected light to exit the display device. The second inclined surface can be a reflective surface. The second inclined surface can be configured to reflect light reflected by a rear surface of an electrode of the light-emitting element, causing a second reflected light to exit the display device. The bank can be configured to absorb or reflect external light entering the display device. A further hole may be provided at least partially through or within the planarization layer. The bank may include at least one first black bank located in the further hole, a second black bank arranged on the planarization layer, and a third black bank on the projection of the planarization layer between the first inclined surface and the second inclined surface. The projection can correspond to a flat and / or a planar surface of the planarization layer between the first inclined surface and the second inclined surface. The description above has been presented to enable those skilled in the art to understand and utilize the technical concept of this disclosure and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions of the described embodiments will be apparent to those skilled in the art, and the principles described herein can be applied to other embodiments and applications without departing from the scope of this disclosure. The description above and the accompanying drawings provide an example of the technical concept of this disclosure for illustrative purposes only. That is to say, it is intended that the disclosed embodiments illustrate the scope of the technical concept of this disclosure. These and further modifications may be made to the embodiments in light of the detailed description set forth above. In general, the terms used in the following claims are not to be interpreted as limiting the claims to the specific embodiments disclosed in the application and the claims themselves, but rather as encompassing all possible embodiments together with the full range of correspondences to which such claims are entitled. Accordingly, the claims are not limited by the disclosure. QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature KR 10-2024-0198990

[0001]

Claims

Display device comprising: a substrate (111) having a display area (DA) and a non-display area (NDA, NDA1, NDA2); several thin-film transistors (TFT1, TFT2) on the substrate (111); a planarization layer (520, 521, 522, 523) on the thin-film transistors (TFT1, TFT2); a subpixel (SP) having a light-emitting element (ED1, ED2, ED3) arranged on the planarization layer (520, 521, 522, 523), wherein the light-emitting element (ED1, ED2, ED3) includes an anode (PE1, PE2, PE3) connected to one of the several thin-film transistors (TFT1, TFT2), and the subpixel (SP) has several light-emitting surfaces (101, 103, 105); and a black bank (530, 531, 532, 800) arranged on the planarization layer (520, 521, 522, 523) covering at least one section of the anode (PE1, PE2, PE3). Display device according to claim 1, wherein the black bank (530, 531) has a hole (H1) corresponding to the anode (PE1, PE2, PE3). Display device according to claim 1 or 2, wherein the non-display area (NDA2) contains a contact area (PA) and the black bank (530, 531, 532) is arranged in the contact area (PA) and / or extends to an outer edge of the substrate (111) in the non-display area (NDA, NDA1, NDA2) and / or the contact area (PA) contains a source drain and the black bank (530, 531, 532) covers at least a section of the source drain. Display device according to one of the preceding claims, wherein the display device further comprises: a dam (314) arranged on the substrate (111) in the non-display area (NDA), wherein the dam (314) overlaps with at least one anode, a first source drain and a second source drain in the non-display area (NDA), wherein the dam (314) contains several layers and one layer of the several layers is the black bank. Display device according to claim 4, wherein the dam is one of several dams that overlap with the anode, the first source drain and the second source drain. Display device according to one of the preceding claims, wherein the multiple light-emitting surfaces of the subpixel comprise a light-emitting main surface (101) and a light-emitting secondary surface (103) and an intermediate surface (105) between the light-emitting main surface (101) and the light-emitting secondary surface (103). Display device according to claim 6, wherein the intermediate surface (105) is one of the several light-emitting surfaces and is configured to emit light, or the intermediate surface (105) is a non-emitting surface that is not configured to emit light. Display device according to claim 6, wherein a width of the intermediate surface (105) is greater than a width of the light-emitting secondary surface (103) and / or the intermediate surface (105) and the light-emitting secondary surface (103) are arranged concentrically with respect to the light-emitting main surface (101) and / or at least two of the multiple light-emitting surfaces (101, 103, 105) are configured to emit the same color of light; and / or the multiple light-emitting surfaces (101, 103, 105) are configured to emit light from the light-emitting element (ED1, ED2, ED3). Display device according to one of the preceding claims, further comprising: an encapsulation layer (200) on the planarization layer (520, 521, 522, 523); a color filter layer on the encapsulation layer (200) and a black matrix (570) between the encapsulation layer (200) and the color filter layer, wherein the black matrix (570) has a hole corresponding to the light-emitting element (ED1, ED2, ED3) and the color filter layer is arranged in the hole. Display device according to claim 9 in combination with claim 6, wherein the hole in the black matrix (570) corresponds to the main light-emitting surface (101) of the multiple light-emitting surfaces and the intermediate surface (105) and / or the secondary light-emitting surface (103) correspond to a location where the black matrix (570) and the color filter layer overlap. Display device comprising: a substrate (111) having a display area (DA) and a non-display area (NDA, NDA1, NDA2); several thin-film transistors (TFT1, TFT2) on the substrate (111); a planarization layer (520, 521, 522, 523) arranged on the thin-film transistors (TFT1, TFT2); a subpixel (SP) having a light-emitting element (ED1, ED2, ED3), wherein the subpixel (SP) has a main light-emitting area (101), a secondary light-emitting area (103), and an intermediate area (105) between the main light-emitting area (101) and the secondary light-emitting area (103); and a black bank (530, 531, 532, 800) that is located on the planarization layer (520, 521, 522, 523, 600). Display device according to claim 11, wherein the light-emitting element (ED1, ED2, ED3) contains an anode (PE1, PE2, PE3) and the black bank (530, 531, 532, 800) covers at least one section of the anode (PE1, PE2, PE3). Display device according to claim 11, wherein the multiple thin-film transistors (TFT1, TFT2) comprise a first active layer (ACT1) and a second active layer (ACT2) and the thickness of the first active layer (ACT1) is greater than the thickness of the second active layer (ACT2) and / or the first active layer (ACT1) corresponds to an LPTS transistor and / or the second active layer (ACT2) corresponds to an oxide transistor and / or the multiple thin-film transistors (TFT1, TFT2) comprise at least one of an LPTS transistor and one of an oxide transistor. Display device according to claim 11, 12 or 13, wherein the light-emitting element (ED1, ED2, ED3) contains several light-emitting layers arranged in a tandem structure. Display device according to claim 11, 12, 13 or 14, wherein the planarization layer (600) has a first inclined surface (S1), a second inclined surface (S2) and a projection (602) between the first inclined surface (S1) and the second inclined surface (S2); the planarization layer (600) has a hole (H1) defined by the first inclined surface (S1) and the second inclined surface (S2); the light-emitting element (ED1, ED2, ED3) is arranged in the hole (H1) and a bank (800) is arranged on the projection (602) of the planarization layer (600). Display device according to claim 15, wherein an angle between the first inclined surface (S1) and a back surface (600-B) of the planarization layer (600) is smaller than an angle between the second inclined surface (S2) and the back surface (600-B) of the planarization layer (600). Display device according to claim 15 or 16, wherein the first inclined surface (S1) and / or the second inclined surface (S2) correspond to a projection (601) of the planarization layer (600) and the projection (601) is a section of the planarization layer (600) with a greater thickness than any section of the planarization layer (600). Display device according to claim 15, 16 or 17, wherein the first inclined surface (S1) is configured to reflect light emitted by the light-emitting element and / or to cause a first reflected light to exit the display device; and / or the second inclined surface (S2) is configured to reflect light reflected by a rear surface of an electrode of the light-emitting element and / or to cause a second reflected light to exit the display device; and / or the bank is configured to absorb or reflect external light entering the display device. Display device according to claim 15, 16, 17 or 18, further comprising: a further hole (H3) in the planarization layer (600), wherein the bank includes a first black bank (531) located in the further hole (H3), a second black bank (532) arranged on the planarization layer (600), and a third black bank (800) on the projection (602) of the planarization layer (600) between the first inclined surface (S1) and the second inclined surface (S2). Display device according to claim 15, 16, 17, 18 or 19, wherein the projection (602) corresponds to a flat and / or planar surface of the planarization layer (600) connecting the first inclined surface (S1) and the second inclined surface (S2), and / or the projection (602) is a surface of the planarization layer (600) that is parallel to the substrate (111).

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